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82 lines
1.1 KiB
Systemverilog
82 lines
1.1 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4-Stream FIFO testbench
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*/
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module test_taxi_uart #
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(
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/* verilator lint_off WIDTHTRUNC */
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parameter DATA_W = 8
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/* verilator lint_on WIDTHTRUNC */
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)
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();
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logic clk;
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logic rst;
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taxi_axis_if #(.DATA_W(DATA_W)) s_axis_tx();
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taxi_axis_if #(.DATA_W(DATA_W)) m_axis_rx();
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logic rxd;
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logic txd;
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logic tx_busy;
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logic rx_busy;
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logic rx_overrun_error;
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logic rx_frame_error;
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logic [15:0] prescale;
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taxi_uart #(
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.DATA_W(DATA_W)
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)
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uut (
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.clk(clk),
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.rst(rst),
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/*
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* AXI4-Stream input (sink)
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*/
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.s_axis_tx(s_axis_tx),
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/*
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* AXI4-Stream output (source)
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*/
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.m_axis_rx(m_axis_rx),
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/*
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* UART interface
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*/
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.rxd(rxd),
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.txd(txd),
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/*
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* Status
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*/
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.tx_busy(tx_busy),
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.rx_busy(rx_busy),
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.rx_overrun_error(rx_overrun_error),
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.rx_frame_error(rx_frame_error),
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/*
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* Configuration
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*/
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.prescale(prescale)
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);
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endmodule
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`resetall
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