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83 lines
1.7 KiB
Systemverilog
83 lines
1.7 KiB
Systemverilog
// SPDX-License-Identifier: MIT
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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interface taxi_axis_if #(
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// Width of AXI stream interfaces in bits
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parameter DATA_W = 8,
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// tkeep signal width (bytes per cycle)
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parameter KEEP_W = ((DATA_W+7)/8),
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// Use tkeep signal
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parameter logic KEEP_EN = KEEP_W > 1,
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// Use tstrb signal
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parameter logic STRB_EN = 1'b0,
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// Use tlast signal
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parameter logic LAST_EN = 1'b1,
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// Use tid signal
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parameter logic ID_EN = 0,
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// tid signal width
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parameter ID_W = 8,
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// Use tdest signal
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parameter logic DEST_EN = 0,
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// tdest signal width
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parameter DEST_W = 8,
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// Use tuser signal
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parameter logic USER_EN = 0,
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// tuser signal width
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parameter USER_W = 1
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)
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();
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logic [DATA_W-1:0] tdata;
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logic [KEEP_W-1:0] tkeep;
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logic [KEEP_W-1:0] tstrb;
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logic [ID_W-1:0] tid;
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logic [DEST_W-1:0] tdest;
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logic [USER_W-1:0] tuser;
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logic tlast;
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logic tvalid;
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logic tready;
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modport src (
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output tdata,
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output tkeep,
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output tstrb,
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output tid,
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output tdest,
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output tuser,
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output tlast,
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output tvalid,
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input tready
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);
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modport snk (
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input tdata,
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input tkeep,
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input tstrb,
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input tid,
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input tdest,
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input tuser,
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input tlast,
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input tvalid,
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output tready
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);
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modport mon (
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input tdata,
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input tkeep,
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input tstrb,
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input tid,
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input tdest,
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input tuser,
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input tlast,
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input tvalid,
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input tready
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);
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endinterface
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