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223 lines
7.9 KiB
Systemverilog
223 lines
7.9 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2021-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4-Stream pipeline FIFO
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*/
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module taxi_axis_pipeline_fifo #
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(
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// Number of registers in pipeline
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parameter LENGTH = 2
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* AXI4-Stream input (sink)
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*/
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taxi_axis_if.snk s_axis,
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/*
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* AXI4-Stream output (source)
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*/
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taxi_axis_if.src m_axis
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);
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// extract parameters
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localparam DATA_W = s_axis.DATA_W;
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localparam logic KEEP_EN = s_axis.KEEP_EN && m_axis.KEEP_EN;
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localparam KEEP_W = s_axis.KEEP_W;
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localparam logic STRB_EN = s_axis.STRB_EN && m_axis.STRB_EN;
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localparam logic LAST_EN = s_axis.LAST_EN && m_axis.LAST_EN;
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localparam logic ID_EN = s_axis.ID_EN && m_axis.ID_EN;
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localparam ID_W = s_axis.ID_W;
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localparam logic DEST_EN = s_axis.DEST_EN && m_axis.DEST_EN;
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localparam DEST_W = s_axis.DEST_W;
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localparam logic USER_EN = s_axis.USER_EN && m_axis.USER_EN;
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localparam USER_W = s_axis.USER_W;
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// check configuration
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if (m_axis.DATA_W != DATA_W)
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$fatal(0, "Error: Interface DATA_W parameter mismatch (instance %m)");
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if (KEEP_EN && m_axis.KEEP_W != KEEP_W)
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$fatal(0, "Error: Interface KEEP_W parameter mismatch (instance %m)");
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localparam FIFO_AW = LENGTH < 2 ? 3 : $clog2(LENGTH*4+1);
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taxi_axis_if #(.DATA_W(DATA_W), .KEEP_W(KEEP_W), .ID_W(ID_W), .DEST_W(DEST_W), .USER_W(USER_W)) axis_pipe[LENGTH+1]();
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for (genvar n = 0; n < LENGTH; n = n + 1) begin : stage
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(* shreg_extract = "no" *)
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logic [DATA_W-1:0] axis_tdata_reg = 0;
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(* shreg_extract = "no" *)
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logic [KEEP_W-1:0] axis_tkeep_reg = 0;
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(* shreg_extract = "no" *)
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logic axis_tvalid_reg = 0;
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(* shreg_extract = "no" *)
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logic axis_tready_reg = 0;
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(* shreg_extract = "no" *)
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logic axis_tlast_reg = 0;
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(* shreg_extract = "no" *)
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logic [ID_W-1:0] axis_tid_reg = 0;
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(* shreg_extract = "no" *)
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logic [DEST_W-1:0] axis_tdest_reg = 0;
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(* shreg_extract = "no" *)
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logic [USER_W-1:0] axis_tuser_reg = 0;
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assign axis_pipe[n+1].tdata = axis_tdata_reg;
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assign axis_pipe[n+1].tkeep = axis_tkeep_reg;
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assign axis_pipe[n+1].tvalid = axis_tvalid_reg;
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assign axis_pipe[n+1].tlast = axis_tlast_reg;
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assign axis_pipe[n+1].tid = axis_tid_reg;
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assign axis_pipe[n+1].tdest = axis_tdest_reg;
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assign axis_pipe[n+1].tuser = axis_tuser_reg;
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assign axis_pipe[n].tready = axis_tready_reg;
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always_ff @(posedge clk) begin
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axis_tdata_reg <= axis_pipe[n].tdata;
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axis_tkeep_reg <= axis_pipe[n].tkeep;
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axis_tvalid_reg <= axis_pipe[n].tvalid;
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axis_tlast_reg <= axis_pipe[n].tlast;
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axis_tid_reg <= axis_pipe[n].tid;
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axis_tdest_reg <= axis_pipe[n].tdest;
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axis_tuser_reg <= axis_pipe[n].tuser;
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axis_tready_reg <= axis_pipe[n+1].tready;
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if (rst) begin
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axis_tvalid_reg <= 1'b0;
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axis_tready_reg <= 1'b0;
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end
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end
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end
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if (LENGTH > 0) begin : fifo
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assign axis_pipe[0].tdata = s_axis.tdata;
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assign axis_pipe[0].tkeep = s_axis.tkeep;
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assign axis_pipe[0].tvalid = s_axis.tvalid & s_axis.tready;
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assign axis_pipe[0].tlast = s_axis.tlast;
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assign axis_pipe[0].tid = s_axis.tid;
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assign axis_pipe[0].tdest = s_axis.tdest;
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assign axis_pipe[0].tuser = s_axis.tuser;
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assign s_axis.tready = axis_pipe[0].tready;
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wire [DATA_W-1:0] m_axis_tdata_int = axis_pipe[LENGTH].tdata;
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wire [KEEP_W-1:0] m_axis_tkeep_int = axis_pipe[LENGTH].tkeep;
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wire m_axis_tvalid_int = axis_pipe[LENGTH].tvalid;
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wire m_axis_tready_int;
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wire m_axis_tlast_int = axis_pipe[LENGTH].tlast;
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wire [ID_W-1:0] m_axis_tid_int = axis_pipe[LENGTH].tid;
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wire [DEST_W-1:0] m_axis_tdest_int = axis_pipe[LENGTH].tdest;
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wire [USER_W-1:0] m_axis_tuser_int = axis_pipe[LENGTH].tuser;
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assign axis_pipe[LENGTH].tready = m_axis_tready_int;
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// output datapath logic
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logic [DATA_W-1:0] m_axis_tdata_reg = '0;
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logic [KEEP_W-1:0] m_axis_tkeep_reg = '0;
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logic m_axis_tvalid_reg = 1'b0;
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logic m_axis_tlast_reg = 1'b0;
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logic [ID_W-1:0] m_axis_tid_reg = '0;
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logic [DEST_W-1:0] m_axis_tdest_reg = '0;
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logic [USER_W-1:0] m_axis_tuser_reg = '0;
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logic [FIFO_AW+1-1:0] out_fifo_wr_ptr_reg = 0;
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logic [FIFO_AW+1-1:0] out_fifo_rd_ptr_reg = 0;
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logic out_fifo_half_full_reg = 1'b0;
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wire out_fifo_full = out_fifo_wr_ptr_reg == (out_fifo_rd_ptr_reg ^ {1'b1, {FIFO_AW{1'b0}}});
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wire out_fifo_empty = out_fifo_wr_ptr_reg == out_fifo_rd_ptr_reg;
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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logic [DATA_W-1:0] out_fifo_tdata[2**FIFO_AW-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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logic [KEEP_W-1:0] out_fifo_tkeep[2**FIFO_AW-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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logic out_fifo_tlast[2**FIFO_AW-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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logic [ID_W-1:0] out_fifo_tid[2**FIFO_AW-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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logic [DEST_W-1:0] out_fifo_tdest[2**FIFO_AW-1:0];
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(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
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logic [USER_W-1:0] out_fifo_tuser[2**FIFO_AW-1:0];
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assign m_axis_tready_int = !out_fifo_half_full_reg;
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assign m_axis.tdata = m_axis_tdata_reg;
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assign m_axis.tkeep = KEEP_EN ? m_axis_tkeep_reg : '1;
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assign m_axis.tvalid = m_axis_tvalid_reg;
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assign m_axis.tlast = LAST_EN ? m_axis_tlast_reg : 1'b1;
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assign m_axis.tid = ID_EN ? m_axis_tid_reg : '0;
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assign m_axis.tdest = DEST_EN ? m_axis_tdest_reg : '0;
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assign m_axis.tuser = USER_EN ? m_axis_tuser_reg : '0;
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always_ff @(posedge clk) begin
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m_axis_tvalid_reg <= m_axis_tvalid_reg && !m_axis.tready;
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out_fifo_half_full_reg <= $unsigned(out_fifo_wr_ptr_reg - out_fifo_rd_ptr_reg) >= 2**(FIFO_AW-1);
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if (!out_fifo_full && m_axis_tvalid_int) begin
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out_fifo_tdata[out_fifo_wr_ptr_reg[FIFO_AW-1:0]] <= m_axis_tdata_int;
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out_fifo_tkeep[out_fifo_wr_ptr_reg[FIFO_AW-1:0]] <= m_axis_tkeep_int;
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out_fifo_tlast[out_fifo_wr_ptr_reg[FIFO_AW-1:0]] <= m_axis_tlast_int;
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out_fifo_tid[out_fifo_wr_ptr_reg[FIFO_AW-1:0]] <= m_axis_tid_int;
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out_fifo_tdest[out_fifo_wr_ptr_reg[FIFO_AW-1:0]] <= m_axis_tdest_int;
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out_fifo_tuser[out_fifo_wr_ptr_reg[FIFO_AW-1:0]] <= m_axis_tuser_int;
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out_fifo_wr_ptr_reg <= out_fifo_wr_ptr_reg + 1;
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end
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if (!out_fifo_empty && (!m_axis_tvalid_reg || m_axis.tready)) begin
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m_axis_tdata_reg <= out_fifo_tdata[out_fifo_rd_ptr_reg[FIFO_AW-1:0]];
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m_axis_tkeep_reg <= out_fifo_tkeep[out_fifo_rd_ptr_reg[FIFO_AW-1:0]];
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m_axis_tvalid_reg <= 1'b1;
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m_axis_tlast_reg <= out_fifo_tlast[out_fifo_rd_ptr_reg[FIFO_AW-1:0]];
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m_axis_tid_reg <= out_fifo_tid[out_fifo_rd_ptr_reg[FIFO_AW-1:0]];
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m_axis_tdest_reg <= out_fifo_tdest[out_fifo_rd_ptr_reg[FIFO_AW-1:0]];
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m_axis_tuser_reg <= out_fifo_tuser[out_fifo_rd_ptr_reg[FIFO_AW-1:0]];
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out_fifo_rd_ptr_reg <= out_fifo_rd_ptr_reg + 1;
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end
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if (rst) begin
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out_fifo_wr_ptr_reg <= 0;
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out_fifo_rd_ptr_reg <= 0;
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m_axis_tvalid_reg <= 1'b0;
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end
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end
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end else begin
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// bypass
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assign m_axis.tdata = s_axis.tdata;
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assign m_axis.tkeep = KEEP_EN ? s_axis.tkeep : '1;
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assign m_axis.tvalid = s_axis.tvalid;
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assign m_axis.tlast = LAST_EN ? s_axis.tlast : 1'b1;
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assign m_axis.tid = ID_EN ? s_axis.tid : '0;
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assign m_axis.tdest = DEST_EN ? s_axis.tdest : '0;
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assign m_axis.tuser = USER_EN ? s_axis.tuser : '0;
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assign s_axis.tready = m_axis.tready;
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end
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endmodule
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`resetall
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