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84 lines
1.4 KiB
Systemverilog
84 lines
1.4 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4-Stream multiplexer testbench
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*/
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module test_taxi_axis_mux #
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(
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/* verilator lint_off WIDTHTRUNC */
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parameter S_COUNT = 4,
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parameter DATA_W = 8,
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parameter logic KEEP_EN = (DATA_W>8),
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parameter KEEP_W = ((DATA_W+7)/8),
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parameter logic STRB_EN = 1'b0,
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parameter logic LAST_EN = 1'b1,
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parameter logic ID_EN = 1'b0,
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parameter ID_W = 8,
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parameter logic DEST_EN = 1'b0,
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parameter DEST_W = 8,
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parameter logic USER_EN = 1'b1,
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parameter USER_W = 1
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/* verilator lint_on WIDTHTRUNC */
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)
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();
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logic clk;
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logic rst;
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taxi_axis_if #(
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.DATA_W(DATA_W),
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.KEEP_EN(KEEP_EN),
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.KEEP_W(KEEP_W),
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.STRB_EN(STRB_EN),
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.LAST_EN(LAST_EN),
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.ID_EN(ID_EN),
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.ID_W(ID_W),
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.DEST_EN(DEST_EN),
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.DEST_W(DEST_W),
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.USER_EN(USER_EN),
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.USER_W(USER_W)
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) s_axis[S_COUNT](), m_axis();
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logic enable;
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logic [$clog2(S_COUNT)-1:0] select;
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taxi_axis_mux #(
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.S_COUNT(S_COUNT)
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)
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uut (
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.clk(clk),
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.rst(rst),
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/*
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* AXI4-Stream input (sink)
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*/
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.s_axis(s_axis),
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/*
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* AXI4-Stream output (source)
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*/
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.m_axis(m_axis),
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/*
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* Control
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*/
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.enable(enable),
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.select(select)
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);
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endmodule
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`resetall
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