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https://github.com/fpganinja/taxi.git
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248 lines
6.5 KiB
Systemverilog
248 lines
6.5 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2018-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* 10G Ethernet PHY RX IF
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*/
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module taxi_eth_phy_10g_rx_if #
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(
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parameter DATA_W = 64,
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parameter HDR_W = 2,
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parameter logic BIT_REVERSE = 1'b0,
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parameter logic SCRAMBLER_DISABLE = 1'b0,
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parameter logic PRBS31_EN = 1'b0,
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parameter SERDES_PIPELINE = 0,
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parameter BITSLIP_HIGH_CYCLES = 1,
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parameter BITSLIP_LOW_CYCLES = 7,
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parameter COUNT_125US = 125000/6.4
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)
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(
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input wire logic clk,
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input wire logic rst,
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/*
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* 10GBASE-R encoded interface
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*/
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output wire logic [DATA_W-1:0] encoded_rx_data,
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output wire logic [HDR_W-1:0] encoded_rx_hdr,
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/*
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* SERDES interface
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*/
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input wire logic [DATA_W-1:0] serdes_rx_data,
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input wire logic [HDR_W-1:0] serdes_rx_hdr,
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output wire logic serdes_rx_bitslip,
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output wire logic serdes_rx_reset_req,
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/*
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* Status
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*/
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input wire logic rx_bad_block,
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input wire logic rx_sequence_error,
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output wire logic [6:0] rx_error_count,
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output wire logic rx_block_lock,
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output wire logic rx_high_ber,
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output wire logic rx_status,
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/*
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* Configuration
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*/
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input wire logic cfg_rx_prbs31_enable
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);
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// check configuration
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if (DATA_W != 64)
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$fatal(0, "Error: Interface width must be 64");
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if (HDR_W != 2)
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$fatal(0, "Error: HDR_W must be 2");
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wire [DATA_W-1:0] serdes_rx_data_rev, serdes_rx_data_int;
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wire [HDR_W-1:0] serdes_rx_hdr_rev, serdes_rx_hdr_int;
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if (BIT_REVERSE) begin
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for (genvar n = 0; n < DATA_W; n = n + 1) begin
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assign serdes_rx_data_rev[n] = serdes_rx_data[DATA_W-n-1];
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end
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for (genvar n = 0; n < HDR_W; n = n + 1) begin
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assign serdes_rx_hdr_rev[n] = serdes_rx_hdr[HDR_W-n-1];
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end
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end else begin
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assign serdes_rx_data_rev = serdes_rx_data;
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assign serdes_rx_hdr_rev = serdes_rx_hdr;
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end
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if (SERDES_PIPELINE > 0) begin
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(* srl_style = "register" *)
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logic [DATA_W-1:0] serdes_rx_data_pipe_reg[SERDES_PIPELINE-1:0];
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(* srl_style = "register" *)
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logic [HDR_W-1:0] serdes_rx_hdr_pipe_reg[SERDES_PIPELINE-1:0];
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for (genvar n = 0; n < SERDES_PIPELINE; n = n + 1) begin
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initial begin
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serdes_rx_data_pipe_reg[n] = '0;
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serdes_rx_hdr_pipe_reg[n] = '0;
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end
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always @(posedge clk) begin
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serdes_rx_data_pipe_reg[n] <= n == 0 ? serdes_rx_data_rev : serdes_rx_data_pipe_reg[n-1];
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serdes_rx_hdr_pipe_reg[n] <= n == 0 ? serdes_rx_hdr_rev : serdes_rx_hdr_pipe_reg[n-1];
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end
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end
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assign serdes_rx_data_int = serdes_rx_data_pipe_reg[SERDES_PIPELINE-1];
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assign serdes_rx_hdr_int = serdes_rx_hdr_pipe_reg[SERDES_PIPELINE-1];
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end else begin
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assign serdes_rx_data_int = serdes_rx_data_rev;
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assign serdes_rx_hdr_int = serdes_rx_hdr_rev;
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end
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wire [DATA_W-1:0] descrambled_rx_data;
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logic [DATA_W-1:0] encoded_rx_data_reg = '0;
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logic [HDR_W-1:0] encoded_rx_hdr_reg = '0;
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logic [57:0] scrambler_state_reg = {58{1'b1}};
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wire [57:0] scrambler_state;
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logic [30:0] prbs31_state_reg = 31'h7fffffff;
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wire [30:0] prbs31_state;
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wire [DATA_W+HDR_W-1:0] prbs31_data;
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logic [DATA_W+HDR_W-1:0] prbs31_data_reg = '0;
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logic [6:0] rx_error_count_reg = '0;
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logic [5:0] rx_error_count_1_reg = '0;
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logic [5:0] rx_error_count_2_reg = '0;
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logic [5:0] rx_error_count_1_temp;
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logic [5:0] rx_error_count_2_temp;
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taxi_lfsr #(
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.LFSR_W(58),
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.LFSR_POLY(58'h8000000001),
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.LFSR_GALOIS(0),
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.LFSR_FEED_FORWARD(1),
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.REVERSE(1),
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.DATA_W(DATA_W)
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)
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descrambler_inst (
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.data_in(serdes_rx_data_int),
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.state_in(scrambler_state_reg),
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.data_out(descrambled_rx_data),
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.state_out(scrambler_state)
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);
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taxi_lfsr #(
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.LFSR_W(31),
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.LFSR_POLY(31'h10000001),
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.LFSR_GALOIS(0),
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.LFSR_FEED_FORWARD(1),
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.REVERSE(1),
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.DATA_W(DATA_W+HDR_W)
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)
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prbs31_check_inst (
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.data_in(~{serdes_rx_data_int, serdes_rx_hdr_int}),
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.state_in(prbs31_state_reg),
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.data_out(prbs31_data),
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.state_out(prbs31_state)
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);
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always_comb begin
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rx_error_count_1_temp = '0;
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rx_error_count_2_temp = '0;
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for (integer i = 0; i < DATA_W+HDR_W; i = i + 1) begin
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if (i[0]) begin
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rx_error_count_1_temp = rx_error_count_1_temp + 6'(prbs31_data_reg[i]);
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end else begin
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rx_error_count_2_temp = rx_error_count_2_temp + 6'(prbs31_data_reg[i]);
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end
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end
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end
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always_ff @(posedge clk) begin
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scrambler_state_reg <= scrambler_state;
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encoded_rx_data_reg <= SCRAMBLER_DISABLE ? serdes_rx_data_int : descrambled_rx_data;
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encoded_rx_hdr_reg <= serdes_rx_hdr_int;
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if (PRBS31_EN) begin
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if (cfg_rx_prbs31_enable) begin
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prbs31_state_reg <= prbs31_state;
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prbs31_data_reg <= prbs31_data;
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end else begin
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prbs31_data_reg <= '0;
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end
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rx_error_count_1_reg <= rx_error_count_1_temp;
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rx_error_count_2_reg <= rx_error_count_2_temp;
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rx_error_count_reg <= rx_error_count_1_reg + rx_error_count_2_reg;
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end else begin
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rx_error_count_reg <= '0;
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end
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end
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assign encoded_rx_data = encoded_rx_data_reg;
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assign encoded_rx_hdr = encoded_rx_hdr_reg;
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assign rx_error_count = rx_error_count_reg;
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wire serdes_rx_bitslip_int;
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wire serdes_rx_reset_req_int;
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assign serdes_rx_bitslip = serdes_rx_bitslip_int && !(PRBS31_EN && cfg_rx_prbs31_enable);
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assign serdes_rx_reset_req = serdes_rx_reset_req_int && !(PRBS31_EN && cfg_rx_prbs31_enable);
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taxi_eth_phy_10g_rx_frame_sync #(
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.HDR_W(HDR_W),
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.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
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.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES)
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)
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eth_phy_10g_rx_frame_sync_inst (
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.clk(clk),
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.rst(rst),
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.serdes_rx_hdr(serdes_rx_hdr_int),
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.serdes_rx_bitslip(serdes_rx_bitslip_int),
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.rx_block_lock(rx_block_lock)
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);
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taxi_eth_phy_10g_rx_ber_mon #(
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.HDR_W(HDR_W),
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.COUNT_125US(COUNT_125US)
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)
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eth_phy_10g_rx_ber_mon_inst (
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.clk(clk),
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.rst(rst),
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.serdes_rx_hdr(serdes_rx_hdr_int),
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.rx_high_ber(rx_high_ber)
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);
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taxi_eth_phy_10g_rx_watchdog #(
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.HDR_W(HDR_W),
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.COUNT_125US(COUNT_125US)
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)
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eth_phy_10g_rx_watchdog_inst (
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.clk(clk),
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.rst(rst),
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.serdes_rx_hdr(serdes_rx_hdr_int),
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.serdes_rx_reset_req(serdes_rx_reset_req_int),
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.rx_bad_block(rx_bad_block),
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.rx_sequence_error(rx_sequence_error),
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.rx_block_lock(rx_block_lock),
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.rx_high_ber(rx_high_ber),
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.rx_status(rx_status)
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);
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endmodule
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`resetall
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