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79 lines
1.1 KiB
Systemverilog
79 lines
1.1 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Statistics collector testbench
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*/
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module test_taxi_stats_collect #
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(
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/* verilator lint_off WIDTHTRUNC */
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parameter CNT = 8,
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parameter INC_W = 8,
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parameter ID_BASE = 0,
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parameter UPDATE_PERIOD = 128,
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parameter STAT_INC_W = 16,
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parameter STAT_ID_W = $clog2(CNT)
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/* verilator lint_on WIDTHTRUNC */
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)
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();
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logic clk;
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logic rst;
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logic [INC_W-1:0] stat_inc[CNT];
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logic [0:0] stat_valid[CNT];
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taxi_axis_if #(
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.DATA_W(STAT_INC_W),
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.KEEP_EN(0),
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.KEEP_W(1),
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.ID_EN(1),
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.ID_W(STAT_ID_W)
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) m_axis_stat();
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logic gate;
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logic update;
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taxi_stats_collect #(
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.CNT(CNT),
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.INC_W(INC_W),
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.ID_BASE(ID_BASE),
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.UPDATE_PERIOD(UPDATE_PERIOD)
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)
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uut (
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.clk(clk),
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.rst(rst),
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/*
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* Increment inputs
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*/
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.stat_inc(stat_inc),
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.stat_valid(stat_valid),
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/*
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* Statistics increment output
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*/
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.m_axis_stat(m_axis_stat),
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/*
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* Control inputs
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*/
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.gate(gate),
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.update(update)
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);
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endmodule
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`resetall
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