mirror of
https://github.com/fpganinja/taxi.git
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909 lines
30 KiB
Systemverilog
909 lines
30 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* Transceiver and MAC/PHY wrapper for UltraScale/UltraScale+
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*/
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module taxi_eth_mac_25g_us_ch #
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(
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parameter logic SIM = 1'b0,
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parameter string VENDOR = "XILINX",
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parameter string FAMILY = "virtexuplus",
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parameter logic HAS_COMMON = 1'b1,
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// GT type
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parameter string GT_TYPE = "GTY",
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// GT parameters
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parameter logic GT_TX_POLARITY = 1'b0,
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parameter logic GT_RX_POLARITY = 1'b0,
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// MAC/PHY parameters
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parameter logic PADDING_EN = 1'b1,
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parameter logic DIC_EN = 1'b1,
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parameter MIN_FRAME_LEN = 64,
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parameter logic PTP_TS_EN = 1'b0,
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parameter logic PTP_TS_FMT_TOD = 1'b1,
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parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
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parameter logic PRBS31_EN = 1'b0,
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parameter TX_SERDES_PIPELINE = 1,
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parameter RX_SERDES_PIPELINE = 1,
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parameter BITSLIP_HIGH_CYCLES = 0,
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parameter BITSLIP_LOW_CYCLES = 7,
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parameter COUNT_125US = 125000/6.4,
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parameter logic STAT_EN = 1'b0,
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parameter STAT_TX_LEVEL = 1,
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parameter STAT_RX_LEVEL = 1,
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parameter STAT_ID_BASE = 0,
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parameter STAT_UPDATE_PERIOD = 1024,
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parameter logic STAT_STR_EN = 1'b0,
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parameter logic [8*8-1:0] STAT_PREFIX_STR = "MAC"
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)
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(
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input wire logic xcvr_ctrl_clk,
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input wire logic xcvr_ctrl_rst,
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/*
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* Common
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*/
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output wire logic xcvr_gtpowergood_out,
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/*
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* PLL out
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*/
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input wire logic xcvr_gtrefclk00_in,
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output wire logic xcvr_qpll0lock_out,
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output wire logic xcvr_qpll0clk_out,
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output wire logic xcvr_qpll0refclk_out,
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/*
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* PLL in
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*/
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input wire logic xcvr_qpll0lock_in,
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output wire logic xcvr_qpll0reset_out,
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input wire logic xcvr_qpll0clk_in,
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input wire logic xcvr_qpll0refclk_in,
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/*
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* Serial data
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*/
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output wire logic xcvr_txp,
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output wire logic xcvr_txn,
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input wire logic xcvr_rxp,
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input wire logic xcvr_rxn,
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/*
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* MAC clocks
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*/
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output wire logic rx_clk,
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input wire logic rx_rst_in,
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output wire logic rx_rst_out,
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output wire logic tx_clk,
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input wire logic tx_rst_in,
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output wire logic tx_rst_out,
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input wire logic ptp_sample_clk,
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/*
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* Transmit interface (AXI stream)
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*/
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taxi_axis_if.snk s_axis_tx,
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taxi_axis_if.src m_axis_tx_cpl,
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/*
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* Receive interface (AXI stream)
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*/
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taxi_axis_if.src m_axis_rx,
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/*
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* PTP clock
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*/
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input wire logic [PTP_TS_W-1:0] tx_ptp_ts = '0,
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input wire logic tx_ptp_ts_step = 1'b0,
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input wire logic [PTP_TS_W-1:0] rx_ptp_ts = '0,
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input wire logic rx_ptp_ts_step = 1'b0,
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/*
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* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
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*/
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input wire logic tx_lfc_req = 1'b0,
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input wire logic tx_lfc_resend = 1'b0,
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input wire logic rx_lfc_en = 1'b0,
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output wire logic rx_lfc_req,
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input wire logic rx_lfc_ack = 1'b0,
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/*
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* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
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*/
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input wire logic [7:0] tx_pfc_req = '0,
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input wire logic tx_pfc_resend = 1'b0,
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input wire logic [7:0] rx_pfc_en = '0,
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output wire logic [7:0] rx_pfc_req,
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input wire logic [7:0] rx_pfc_ack = '0,
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/*
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* Pause interface
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*/
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input wire logic tx_lfc_pause_en = 1'b0,
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input wire logic tx_pause_req = 1'b0,
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output wire logic tx_pause_ack,
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/*
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* Statistics
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*/
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input wire logic stat_clk,
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input wire logic stat_rst,
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taxi_axis_if.src m_axis_stat,
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/*
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* Status
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*/
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output wire logic [1:0] tx_start_packet,
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output wire logic [3:0] stat_tx_byte,
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output wire logic [15:0] stat_tx_pkt_len,
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output wire logic stat_tx_pkt_ucast,
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output wire logic stat_tx_pkt_mcast,
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output wire logic stat_tx_pkt_bcast,
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output wire logic stat_tx_pkt_vlan,
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output wire logic stat_tx_pkt_good,
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output wire logic stat_tx_pkt_bad,
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output wire logic stat_tx_err_oversize,
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output wire logic stat_tx_err_user,
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output wire logic stat_tx_err_underflow,
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output wire logic [1:0] rx_start_packet,
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output wire logic [6:0] rx_error_count,
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output wire logic rx_block_lock,
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output wire logic rx_high_ber,
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output wire logic rx_status,
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output wire logic [3:0] stat_rx_byte,
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output wire logic [15:0] stat_rx_pkt_len,
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output wire logic stat_rx_pkt_fragment,
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output wire logic stat_rx_pkt_jabber,
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output wire logic stat_rx_pkt_ucast,
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output wire logic stat_rx_pkt_mcast,
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output wire logic stat_rx_pkt_bcast,
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output wire logic stat_rx_pkt_vlan,
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output wire logic stat_rx_pkt_good,
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output wire logic stat_rx_pkt_bad,
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output wire logic stat_rx_err_oversize,
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output wire logic stat_rx_err_bad_fcs,
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output wire logic stat_rx_err_bad_block,
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output wire logic stat_rx_err_framing,
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output wire logic stat_rx_err_preamble,
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input wire logic stat_rx_fifo_drop = 1'b0,
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output wire logic stat_tx_mcf,
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output wire logic stat_rx_mcf,
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output wire logic stat_tx_lfc_pkt,
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output wire logic stat_tx_lfc_xon,
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output wire logic stat_tx_lfc_xoff,
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output wire logic stat_tx_lfc_paused,
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output wire logic stat_tx_pfc_pkt,
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output wire logic [7:0] stat_tx_pfc_xon,
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output wire logic [7:0] stat_tx_pfc_xoff,
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output wire logic [7:0] stat_tx_pfc_paused,
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output wire logic stat_rx_lfc_pkt,
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output wire logic stat_rx_lfc_xon,
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output wire logic stat_rx_lfc_xoff,
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output wire logic stat_rx_lfc_paused,
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output wire logic stat_rx_pfc_pkt,
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output wire logic [7:0] stat_rx_pfc_xon,
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output wire logic [7:0] stat_rx_pfc_xoff,
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output wire logic [7:0] stat_rx_pfc_paused,
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/*
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* Configuration
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*/
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input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518,
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input wire logic [7:0] cfg_tx_ifg = 8'd12,
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input wire logic cfg_tx_enable = 1'b1,
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input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518,
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input wire logic cfg_rx_enable = 1'b1,
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input wire logic cfg_tx_prbs31_enable = 1'b0,
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input wire logic cfg_rx_prbs31_enable = 1'b0,
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input wire logic [47:0] cfg_mcf_rx_eth_dst_mcast = 48'h01_80_C2_00_00_01,
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input wire logic cfg_mcf_rx_check_eth_dst_mcast = 1'b1,
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input wire logic [47:0] cfg_mcf_rx_eth_dst_ucast = 48'd0,
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input wire logic cfg_mcf_rx_check_eth_dst_ucast = 1'b0,
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input wire logic [47:0] cfg_mcf_rx_eth_src = 48'd0,
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input wire logic cfg_mcf_rx_check_eth_src = 1'b0,
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input wire logic [15:0] cfg_mcf_rx_eth_type = 16'h8808,
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input wire logic [15:0] cfg_mcf_rx_opcode_lfc = 16'h0001,
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input wire logic cfg_mcf_rx_check_opcode_lfc = 1'b1,
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input wire logic [15:0] cfg_mcf_rx_opcode_pfc = 16'h0101,
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input wire logic cfg_mcf_rx_check_opcode_pfc = 1'b1,
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input wire logic cfg_mcf_rx_forward = 1'b0,
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input wire logic cfg_mcf_rx_enable = 1'b0,
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input wire logic [47:0] cfg_tx_lfc_eth_dst = 48'h01_80_C2_00_00_01,
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input wire logic [47:0] cfg_tx_lfc_eth_src = 48'h80_23_31_43_54_4C,
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input wire logic [15:0] cfg_tx_lfc_eth_type = 16'h8808,
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input wire logic [15:0] cfg_tx_lfc_opcode = 16'h0001,
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input wire logic cfg_tx_lfc_en = 1'b0,
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input wire logic [15:0] cfg_tx_lfc_quanta = 16'hffff,
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input wire logic [15:0] cfg_tx_lfc_refresh = 16'h7fff,
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input wire logic [47:0] cfg_tx_pfc_eth_dst = 48'h01_80_C2_00_00_01,
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input wire logic [47:0] cfg_tx_pfc_eth_src = 48'h80_23_31_43_54_4C,
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input wire logic [15:0] cfg_tx_pfc_eth_type = 16'h8808,
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input wire logic [15:0] cfg_tx_pfc_opcode = 16'h0101,
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input wire logic cfg_tx_pfc_en = 1'b0,
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input wire logic [15:0] cfg_tx_pfc_quanta[8] = '{8{16'hffff}},
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input wire logic [15:0] cfg_tx_pfc_refresh[8] = '{8{16'h7fff}},
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input wire logic [15:0] cfg_rx_lfc_opcode = 16'h0001,
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input wire logic cfg_rx_lfc_en = 1'b0,
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input wire logic [15:0] cfg_rx_pfc_opcode = 16'h0101,
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input wire logic cfg_rx_pfc_en = 1'b0
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);
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localparam GT_USP = FAMILY == "kintexuplus" || FAMILY == "virtexuplus" || FAMILY == "virtexuplusHBM"
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|| FAMILY == "virtexuplus58G" || FAMILY == "zynquplus" || FAMILY == "zynquplusRFSOC";
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localparam DATA_W = 64;
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localparam HDR_W = 2;
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wire rx_reset_req;
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wire gt_reset_tx_datapath = tx_rst_in;
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wire gt_reset_rx_datapath = rx_rst_in || rx_reset_req;
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wire gt_reset_tx_done;
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wire gt_reset_rx_done;
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wire [5:0] gt_txheader;
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wire [63:0] gt_txdata;
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wire gt_rxgearboxslip;
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wire [5:0] gt_rxheader;
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wire [1:0] gt_rxheadervalid;
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wire [63:0] gt_rxdata;
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wire [1:0] gt_rxdatavalid;
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if (SIM) begin : xcvr
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// simulation (no GT core)
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assign xcvr_gtpowergood_out = 1'b1;
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assign xcvr_qpll0lock_out = 1'b1;
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assign xcvr_qpll0clk_out = 1'b0;
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assign xcvr_qpll0refclk_out = 1'b0;
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assign gt_reset_tx_done = !xcvr_ctrl_rst;
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assign gt_reset_rx_done = !xcvr_ctrl_rst;
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end else if (HAS_COMMON && GT_TYPE == "GTY" && GT_USP) begin : xcvr
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// UltraScale+ GTY (with common)
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taxi_eth_mac_25g_us_gty_full
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taxi_eth_mac_25g_us_gty_full_inst (
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// Common
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.gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk),
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.gtwiz_reset_all_in(xcvr_ctrl_rst),
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.gtpowergood_out(xcvr_gtpowergood_out),
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// PLL
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.gtrefclk00_in(xcvr_gtrefclk00_in),
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.qpll0lock_out(xcvr_qpll0lock_out),
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.qpll0outclk_out(xcvr_qpll0clk_out),
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.qpll0outrefclk_out(xcvr_qpll0refclk_out),
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// Serial data
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.gtytxp_out(xcvr_txp),
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.gtytxn_out(xcvr_txn),
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.gtyrxp_in(xcvr_rxp),
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.gtyrxn_in(xcvr_rxn),
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// Transmit
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.gtwiz_userclk_tx_reset_in(1'b0),
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.gtwiz_userclk_tx_srcclk_out(),
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.gtwiz_userclk_tx_usrclk_out(),
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.gtwiz_userclk_tx_usrclk2_out(tx_clk),
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.gtwiz_userclk_tx_active_out(),
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.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
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.gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath),
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.gtwiz_reset_tx_done_out(gt_reset_tx_done),
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.txpmaresetdone_out(),
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.txprgdivresetdone_out(),
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.txpolarity_in(GT_TX_POLARITY),
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.gtwiz_userdata_tx_in(gt_txdata),
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.txheader_in(gt_txheader),
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.txsequence_in(7'b0),
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// Receive
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.gtwiz_userclk_rx_reset_in(1'b0),
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.gtwiz_userclk_rx_srcclk_out(),
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.gtwiz_userclk_rx_usrclk_out(),
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.gtwiz_userclk_rx_usrclk2_out(rx_clk),
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.gtwiz_userclk_rx_active_out(),
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.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
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.gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath),
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.gtwiz_reset_rx_cdr_stable_out(),
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.gtwiz_reset_rx_done_out(gt_reset_rx_done),
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.rxpmaresetdone_out(),
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.rxprgdivresetdone_out(),
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.rxpolarity_in(GT_RX_POLARITY),
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.rxgearboxslip_in(gt_rxgearboxslip),
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.gtwiz_userdata_rx_out(gt_rxdata),
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.rxdatavalid_out(gt_rxdatavalid),
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.rxheader_out(gt_rxheader),
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.rxheadervalid_out(gt_rxheadervalid),
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.rxstartofseq_out()
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);
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assign xcvr_qpll0reset_out = 1'b0;
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end else if (HAS_COMMON && GT_TYPE == "GTH" && GT_USP) begin : xcvr
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// UltraScale+ GTH (with common)
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taxi_eth_mac_25g_us_gth_full
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taxi_eth_mac_25g_us_gth_full_inst (
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// Common
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.gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk),
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.gtwiz_reset_all_in(xcvr_ctrl_rst),
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.gtpowergood_out(xcvr_gtpowergood_out),
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// PLL
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.gtrefclk00_in(xcvr_gtrefclk00_in),
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.qpll0lock_out(xcvr_qpll0lock_out),
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.qpll0outclk_out(xcvr_qpll0clk_out),
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.qpll0outrefclk_out(xcvr_qpll0refclk_out),
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// Serial data
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.gthtxp_out(xcvr_txp),
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.gthtxn_out(xcvr_txn),
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.gthrxp_in(xcvr_rxp),
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.gthrxn_in(xcvr_rxn),
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// Transmit
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.gtwiz_userclk_tx_reset_in(1'b0),
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.gtwiz_userclk_tx_srcclk_out(),
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.gtwiz_userclk_tx_usrclk_out(),
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.gtwiz_userclk_tx_usrclk2_out(tx_clk),
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.gtwiz_userclk_tx_active_out(),
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.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
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.gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath),
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.gtwiz_reset_tx_done_out(gt_reset_tx_done),
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.txpmaresetdone_out(),
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.txprgdivresetdone_out(),
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.txpolarity_in(GT_TX_POLARITY),
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.gtwiz_userdata_tx_in(gt_txdata),
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.txheader_in(gt_txheader),
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.txsequence_in(7'b0),
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// Receive
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.gtwiz_userclk_rx_reset_in(1'b0),
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.gtwiz_userclk_rx_srcclk_out(),
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.gtwiz_userclk_rx_usrclk_out(),
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.gtwiz_userclk_rx_usrclk2_out(rx_clk),
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.gtwiz_userclk_rx_active_out(),
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.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
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.gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath),
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.gtwiz_reset_rx_cdr_stable_out(),
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.gtwiz_reset_rx_done_out(gt_reset_rx_done),
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.rxpmaresetdone_out(),
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.rxprgdivresetdone_out(),
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.rxpolarity_in(GT_RX_POLARITY),
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.rxgearboxslip_in(gt_rxgearboxslip),
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.gtwiz_userdata_rx_out(gt_rxdata),
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.rxdatavalid_out(gt_rxdatavalid),
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.rxheader_out(gt_rxheader),
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.rxheadervalid_out(gt_rxheadervalid),
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.rxstartofseq_out()
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);
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assign xcvr_qpll0reset_out = 1'b0;
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end else if (HAS_COMMON && GT_TYPE == "GTY" && !GT_USP) begin : xcvr
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// UltraScale GTY (with common)
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taxi_eth_mac_25g_us_gty_full
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taxi_eth_mac_25g_us_gty_full_inst (
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// Common
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.gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk),
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.gtwiz_reset_all_in(xcvr_ctrl_rst),
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.gtpowergood_out(xcvr_gtpowergood_out),
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// PLL
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.gtrefclk00_in(xcvr_gtrefclk00_in),
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.qpll0lock_out(xcvr_qpll0lock_out),
|
|
.qpll0outclk_out(xcvr_qpll0clk_out),
|
|
.qpll0outrefclk_out(xcvr_qpll0refclk_out),
|
|
|
|
// Serial data
|
|
.gtytxp_out(xcvr_txp),
|
|
.gtytxn_out(xcvr_txn),
|
|
.gtyrxp_in(xcvr_rxp),
|
|
.gtyrxn_in(xcvr_rxn),
|
|
|
|
// Transmit
|
|
.gtwiz_userclk_tx_reset_in(1'b0),
|
|
.gtwiz_userclk_tx_srcclk_out(),
|
|
.gtwiz_userclk_tx_usrclk_out(),
|
|
.gtwiz_userclk_tx_usrclk2_out(tx_clk),
|
|
.gtwiz_userclk_tx_active_out(),
|
|
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
|
|
.gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath),
|
|
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
|
|
.txpmaresetdone_out(),
|
|
.txprgdivresetdone_out(),
|
|
|
|
.txpolarity_in(GT_TX_POLARITY),
|
|
|
|
.gtwiz_userdata_tx_in(gt_txdata),
|
|
.txheader_in(gt_txheader),
|
|
.txsequence_in(7'b0),
|
|
|
|
// Receive
|
|
.gtwiz_userclk_rx_reset_in(1'b0),
|
|
.gtwiz_userclk_rx_srcclk_out(),
|
|
.gtwiz_userclk_rx_usrclk_out(),
|
|
.gtwiz_userclk_rx_usrclk2_out(rx_clk),
|
|
.gtwiz_userclk_rx_active_out(),
|
|
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
|
|
.gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath),
|
|
.gtwiz_reset_rx_cdr_stable_out(),
|
|
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
|
|
.rxpmaresetdone_out(),
|
|
.rxprgdivresetdone_out(),
|
|
|
|
.rxpolarity_in(GT_RX_POLARITY),
|
|
|
|
.rxgearboxslip_in(gt_rxgearboxslip),
|
|
.gtwiz_userdata_rx_out(gt_rxdata),
|
|
.rxdatavalid_out(gt_rxdatavalid),
|
|
.rxheader_out(gt_rxheader),
|
|
.rxheadervalid_out(gt_rxheadervalid),
|
|
.rxstartofseq_out()
|
|
);
|
|
|
|
assign xcvr_qpll0reset_out = 1'b0;
|
|
|
|
end else if (HAS_COMMON && GT_TYPE == "GTH" && !GT_USP) begin : xcvr
|
|
// UltraScale GTH (with common)
|
|
|
|
taxi_eth_mac_25g_us_gth_full
|
|
taxi_eth_mac_25g_us_gth_full_inst (
|
|
// Common
|
|
.gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk),
|
|
.gtwiz_reset_all_in(xcvr_ctrl_rst),
|
|
.gtpowergood_out(xcvr_gtpowergood_out),
|
|
|
|
// PLL
|
|
.gtrefclk00_in(xcvr_gtrefclk00_in),
|
|
.qpll0lock_out(xcvr_qpll0lock_out),
|
|
.qpll0outclk_out(xcvr_qpll0clk_out),
|
|
.qpll0outrefclk_out(xcvr_qpll0refclk_out),
|
|
|
|
// Serial data
|
|
.gthtxp_out(xcvr_txp),
|
|
.gthtxn_out(xcvr_txn),
|
|
.gthrxp_in(xcvr_rxp),
|
|
.gthrxn_in(xcvr_rxn),
|
|
|
|
// Transmit
|
|
.gtwiz_userclk_tx_reset_in(1'b0),
|
|
.gtwiz_userclk_tx_srcclk_out(),
|
|
.gtwiz_userclk_tx_usrclk_out(),
|
|
.gtwiz_userclk_tx_usrclk2_out(tx_clk),
|
|
.gtwiz_userclk_tx_active_out(),
|
|
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
|
|
.gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath),
|
|
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
|
|
.txpmaresetdone_out(),
|
|
.txprgdivresetdone_out(),
|
|
|
|
.txpolarity_in(GT_TX_POLARITY),
|
|
|
|
.gtwiz_userdata_tx_in(gt_txdata),
|
|
.txheader_in(gt_txheader),
|
|
.txsequence_in(7'b0),
|
|
|
|
// Receive
|
|
.gtwiz_userclk_rx_reset_in(1'b0),
|
|
.gtwiz_userclk_rx_srcclk_out(),
|
|
.gtwiz_userclk_rx_usrclk_out(),
|
|
.gtwiz_userclk_rx_usrclk2_out(rx_clk),
|
|
.gtwiz_userclk_rx_active_out(),
|
|
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
|
|
.gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath),
|
|
.gtwiz_reset_rx_cdr_stable_out(),
|
|
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
|
|
.rxpmaresetdone_out(),
|
|
.rxprgdivresetdone_out(),
|
|
|
|
.rxpolarity_in(GT_RX_POLARITY),
|
|
|
|
.rxgearboxslip_in(gt_rxgearboxslip),
|
|
.gtwiz_userdata_rx_out(gt_rxdata),
|
|
.rxdatavalid_out(gt_rxdatavalid),
|
|
.rxheader_out(gt_rxheader),
|
|
.rxheadervalid_out(gt_rxheadervalid),
|
|
.rxstartofseq_out()
|
|
);
|
|
|
|
assign xcvr_qpll0reset_out = 1'b0;
|
|
|
|
end else if (!HAS_COMMON && GT_TYPE == "GTY") begin : xcvr
|
|
// UltraScale/UltraScale+ GTY (channel only)
|
|
|
|
taxi_eth_mac_25g_us_gty_channel
|
|
taxi_eth_mac_25g_us_gty_channel_inst (
|
|
// Common
|
|
.gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk),
|
|
.gtwiz_reset_all_in(xcvr_ctrl_rst),
|
|
.gtpowergood_out(xcvr_gtpowergood_out),
|
|
|
|
// PLL
|
|
.gtwiz_reset_qpll0lock_in(xcvr_qpll0lock_in),
|
|
.gtwiz_reset_qpll0reset_out(xcvr_qpll0reset_out),
|
|
.qpll0clk_in(xcvr_qpll0clk_in),
|
|
.qpll0refclk_in(xcvr_qpll0refclk_in),
|
|
.qpll1clk_in(1'b0),
|
|
.qpll1refclk_in(1'b0),
|
|
|
|
// Serial data
|
|
.gtytxp_out(xcvr_txp),
|
|
.gtytxn_out(xcvr_txn),
|
|
.gtyrxp_in(xcvr_rxp),
|
|
.gtyrxn_in(xcvr_rxn),
|
|
|
|
// Transmit
|
|
.gtwiz_userclk_tx_reset_in(1'b0),
|
|
.gtwiz_userclk_tx_srcclk_out(),
|
|
.gtwiz_userclk_tx_usrclk_out(),
|
|
.gtwiz_userclk_tx_usrclk2_out(tx_clk),
|
|
.gtwiz_userclk_tx_active_out(),
|
|
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
|
|
.gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath),
|
|
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
|
|
.txpmaresetdone_out(),
|
|
.txprgdivresetdone_out(),
|
|
|
|
.txpolarity_in(GT_TX_POLARITY),
|
|
|
|
.gtwiz_userdata_tx_in(gt_txdata),
|
|
.txheader_in(gt_txheader),
|
|
.txsequence_in(7'b0),
|
|
|
|
// Receive
|
|
.gtwiz_userclk_rx_reset_in(1'b0),
|
|
.gtwiz_userclk_rx_srcclk_out(),
|
|
.gtwiz_userclk_rx_usrclk_out(),
|
|
.gtwiz_userclk_rx_usrclk2_out(rx_clk),
|
|
.gtwiz_userclk_rx_active_out(),
|
|
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
|
|
.gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath),
|
|
.gtwiz_reset_rx_cdr_stable_out(),
|
|
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
|
|
.rxpmaresetdone_out(),
|
|
.rxprgdivresetdone_out(),
|
|
|
|
.rxpolarity_in(GT_RX_POLARITY),
|
|
|
|
.rxgearboxslip_in(gt_rxgearboxslip),
|
|
.gtwiz_userdata_rx_out(gt_rxdata),
|
|
.rxdatavalid_out(gt_rxdatavalid),
|
|
.rxheader_out(gt_rxheader),
|
|
.rxheadervalid_out(gt_rxheadervalid),
|
|
.rxstartofseq_out()
|
|
);
|
|
|
|
assign xcvr_qpll0lock_out = 1'b0;
|
|
assign xcvr_qpll0clk_out = 1'b0;
|
|
assign xcvr_qpll0refclk_out = 1'b0;
|
|
|
|
end else if (!HAS_COMMON && GT_TYPE == "GTH") begin : xcvr
|
|
// UltraScale/UltraScale+ GTY (channel only)
|
|
|
|
taxi_eth_mac_25g_us_gth_channel
|
|
taxi_eth_mac_25g_us_gth_channel_inst (
|
|
// Common
|
|
.gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk),
|
|
.gtwiz_reset_all_in(xcvr_ctrl_rst),
|
|
.gtpowergood_out(xcvr_gtpowergood_out),
|
|
|
|
// PLL
|
|
.gtwiz_reset_qpll0lock_in(xcvr_qpll0lock_in),
|
|
.gtwiz_reset_qpll0reset_out(xcvr_qpll0reset_out),
|
|
.qpll0clk_in(xcvr_qpll0clk_in),
|
|
.qpll0refclk_in(xcvr_qpll0refclk_in),
|
|
.qpll1clk_in(1'b0),
|
|
.qpll1refclk_in(1'b0),
|
|
|
|
// Serial data
|
|
.gthtxp_out(xcvr_txp),
|
|
.gthtxn_out(xcvr_txn),
|
|
.gthrxp_in(xcvr_rxp),
|
|
.gthrxn_in(xcvr_rxn),
|
|
|
|
// Transmit
|
|
.gtwiz_userclk_tx_reset_in(1'b0),
|
|
.gtwiz_userclk_tx_srcclk_out(),
|
|
.gtwiz_userclk_tx_usrclk_out(),
|
|
.gtwiz_userclk_tx_usrclk2_out(tx_clk),
|
|
.gtwiz_userclk_tx_active_out(),
|
|
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
|
|
.gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath),
|
|
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
|
|
.txpmaresetdone_out(),
|
|
.txprgdivresetdone_out(),
|
|
|
|
.txpolarity_in(GT_TX_POLARITY),
|
|
|
|
.gtwiz_userdata_tx_in(gt_txdata),
|
|
.txheader_in(gt_txheader),
|
|
.txsequence_in(7'b0),
|
|
|
|
// Receive
|
|
.gtwiz_userclk_rx_reset_in(1'b0),
|
|
.gtwiz_userclk_rx_srcclk_out(),
|
|
.gtwiz_userclk_rx_usrclk_out(),
|
|
.gtwiz_userclk_rx_usrclk2_out(rx_clk),
|
|
.gtwiz_userclk_rx_active_out(),
|
|
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
|
|
.gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath),
|
|
.gtwiz_reset_rx_cdr_stable_out(),
|
|
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
|
|
.rxpmaresetdone_out(),
|
|
.rxprgdivresetdone_out(),
|
|
|
|
.rxpolarity_in(GT_RX_POLARITY),
|
|
|
|
.rxgearboxslip_in(gt_rxgearboxslip),
|
|
.gtwiz_userdata_rx_out(gt_rxdata),
|
|
.rxdatavalid_out(gt_rxdatavalid),
|
|
.rxheader_out(gt_rxheader),
|
|
.rxheadervalid_out(gt_rxheadervalid),
|
|
.rxstartofseq_out()
|
|
);
|
|
|
|
assign xcvr_qpll0lock_out = 1'b0;
|
|
assign xcvr_qpll0clk_out = 1'b0;
|
|
assign xcvr_qpll0refclk_out = 1'b0;
|
|
|
|
end else begin
|
|
|
|
$fatal(0, "Error: invalid configuration (%m)");
|
|
|
|
end
|
|
|
|
taxi_sync_reset #(
|
|
.N(4)
|
|
)
|
|
tx_reset_sync_inst (
|
|
.clk(tx_clk),
|
|
.rst(!gt_reset_tx_done || tx_rst_in),
|
|
.out(tx_rst_out)
|
|
);
|
|
|
|
taxi_sync_reset #(
|
|
.N(4)
|
|
)
|
|
rx_reset_sync_inst (
|
|
.clk(rx_clk),
|
|
.rst(!gt_reset_rx_done || rx_rst_in),
|
|
.out(rx_rst_out)
|
|
);
|
|
|
|
wire [DATA_W-1:0] serdes_tx_data;
|
|
wire [HDR_W-1:0] serdes_tx_hdr;
|
|
wire [DATA_W-1:0] serdes_rx_data;
|
|
wire [HDR_W-1:0] serdes_rx_hdr;
|
|
wire serdes_rx_bitslip;
|
|
|
|
assign gt_txdata = serdes_tx_data;
|
|
assign gt_txheader = {4'd0, serdes_tx_hdr};
|
|
assign gt_rxgearboxslip = serdes_rx_bitslip;
|
|
|
|
if (!SIM) begin
|
|
assign serdes_rx_data = gt_rxdata;
|
|
assign serdes_rx_hdr = gt_rxheader[1:0];
|
|
end
|
|
|
|
taxi_eth_mac_phy_10g #(
|
|
.DATA_W(DATA_W),
|
|
.HDR_W(HDR_W),
|
|
.PADDING_EN(PADDING_EN),
|
|
.DIC_EN(DIC_EN),
|
|
.MIN_FRAME_LEN(MIN_FRAME_LEN),
|
|
.PTP_TS_EN(PTP_TS_EN),
|
|
.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
|
|
.PTP_TS_W(PTP_TS_W),
|
|
.BIT_REVERSE(1'b1),
|
|
.SCRAMBLER_DISABLE(1'b0),
|
|
.PRBS31_EN(PRBS31_EN),
|
|
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
|
|
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
|
|
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
|
|
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
|
|
.COUNT_125US(COUNT_125US),
|
|
.STAT_EN(STAT_EN),
|
|
.STAT_TX_LEVEL(STAT_TX_LEVEL),
|
|
.STAT_RX_LEVEL(STAT_RX_LEVEL),
|
|
.STAT_ID_BASE(STAT_ID_BASE),
|
|
.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD),
|
|
.STAT_STR_EN(STAT_STR_EN),
|
|
.STAT_PREFIX_STR(STAT_PREFIX_STR)
|
|
)
|
|
eth_mac_phy_10g_inst (
|
|
.tx_clk(tx_clk),
|
|
.tx_rst(tx_rst_out),
|
|
.rx_clk(rx_clk),
|
|
.rx_rst(rx_rst_out),
|
|
|
|
/*
|
|
* Transmit interface (AXI stream)
|
|
*/
|
|
.s_axis_tx(s_axis_tx),
|
|
.m_axis_tx_cpl(m_axis_tx_cpl),
|
|
|
|
/*
|
|
* Receive interface (AXI stream)
|
|
*/
|
|
.m_axis_rx(m_axis_rx),
|
|
|
|
/*
|
|
* Serdes interface
|
|
*/
|
|
.serdes_tx_data(serdes_tx_data),
|
|
.serdes_tx_hdr(serdes_tx_hdr),
|
|
.serdes_rx_data(serdes_rx_data),
|
|
.serdes_rx_hdr(serdes_rx_hdr),
|
|
.serdes_rx_bitslip(serdes_rx_bitslip),
|
|
.serdes_rx_reset_req(rx_reset_req),
|
|
|
|
/*
|
|
* PTP
|
|
*/
|
|
.tx_ptp_ts(tx_ptp_ts),
|
|
.rx_ptp_ts(rx_ptp_ts),
|
|
|
|
/*
|
|
* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
|
|
*/
|
|
.tx_lfc_req(tx_lfc_req),
|
|
.tx_lfc_resend(tx_lfc_resend),
|
|
.rx_lfc_en(rx_lfc_en),
|
|
.rx_lfc_req(rx_lfc_req),
|
|
.rx_lfc_ack(rx_lfc_ack),
|
|
|
|
/*
|
|
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
|
|
*/
|
|
.tx_pfc_req(tx_pfc_req),
|
|
.tx_pfc_resend(tx_pfc_resend),
|
|
.rx_pfc_en(rx_pfc_en),
|
|
.rx_pfc_req(rx_pfc_req),
|
|
.rx_pfc_ack(rx_pfc_ack),
|
|
|
|
/*
|
|
* Pause interface
|
|
*/
|
|
.tx_lfc_pause_en(tx_lfc_pause_en),
|
|
.tx_pause_req(tx_pause_req),
|
|
.tx_pause_ack(tx_pause_ack),
|
|
|
|
/*
|
|
* Statistics
|
|
*/
|
|
.stat_clk(stat_clk),
|
|
.stat_rst(stat_rst),
|
|
.m_axis_stat(m_axis_stat),
|
|
|
|
/*
|
|
* Status
|
|
*/
|
|
.tx_start_packet(tx_start_packet),
|
|
.stat_tx_byte(stat_tx_byte),
|
|
.stat_tx_pkt_len(stat_tx_pkt_len),
|
|
.stat_tx_pkt_ucast(stat_tx_pkt_ucast),
|
|
.stat_tx_pkt_mcast(stat_tx_pkt_mcast),
|
|
.stat_tx_pkt_bcast(stat_tx_pkt_bcast),
|
|
.stat_tx_pkt_vlan(stat_tx_pkt_vlan),
|
|
.stat_tx_pkt_good(stat_tx_pkt_good),
|
|
.stat_tx_pkt_bad(stat_tx_pkt_bad),
|
|
.stat_tx_err_oversize(stat_tx_err_oversize),
|
|
.stat_tx_err_user(stat_tx_err_user),
|
|
.stat_tx_err_underflow(stat_tx_err_underflow),
|
|
.rx_start_packet(rx_start_packet),
|
|
.rx_error_count(rx_error_count),
|
|
.rx_block_lock(rx_block_lock),
|
|
.rx_high_ber(rx_high_ber),
|
|
.rx_status(rx_status),
|
|
.stat_rx_byte(stat_rx_byte),
|
|
.stat_rx_pkt_len(stat_rx_pkt_len),
|
|
.stat_rx_pkt_fragment(stat_rx_pkt_fragment),
|
|
.stat_rx_pkt_jabber(stat_rx_pkt_jabber),
|
|
.stat_rx_pkt_ucast(stat_rx_pkt_ucast),
|
|
.stat_rx_pkt_mcast(stat_rx_pkt_mcast),
|
|
.stat_rx_pkt_bcast(stat_rx_pkt_bcast),
|
|
.stat_rx_pkt_vlan(stat_rx_pkt_vlan),
|
|
.stat_rx_pkt_good(stat_rx_pkt_good),
|
|
.stat_rx_pkt_bad(stat_rx_pkt_bad),
|
|
.stat_rx_err_oversize(stat_rx_err_oversize),
|
|
.stat_rx_err_bad_fcs(stat_rx_err_bad_fcs),
|
|
.stat_rx_err_bad_block(stat_rx_err_bad_block),
|
|
.stat_rx_err_framing(stat_rx_err_framing),
|
|
.stat_rx_err_preamble(stat_rx_err_preamble),
|
|
.stat_rx_fifo_drop(stat_rx_fifo_drop),
|
|
.stat_tx_mcf(stat_tx_mcf),
|
|
.stat_rx_mcf(stat_rx_mcf),
|
|
.stat_tx_lfc_pkt(stat_tx_lfc_pkt),
|
|
.stat_tx_lfc_xon(stat_tx_lfc_xon),
|
|
.stat_tx_lfc_xoff(stat_tx_lfc_xoff),
|
|
.stat_tx_lfc_paused(stat_tx_lfc_paused),
|
|
.stat_tx_pfc_pkt(stat_tx_pfc_pkt),
|
|
.stat_tx_pfc_xon(stat_tx_pfc_xon),
|
|
.stat_tx_pfc_xoff(stat_tx_pfc_xoff),
|
|
.stat_tx_pfc_paused(stat_tx_pfc_paused),
|
|
.stat_rx_lfc_pkt(stat_rx_lfc_pkt),
|
|
.stat_rx_lfc_xon(stat_rx_lfc_xon),
|
|
.stat_rx_lfc_xoff(stat_rx_lfc_xoff),
|
|
.stat_rx_lfc_paused(stat_rx_lfc_paused),
|
|
.stat_rx_pfc_pkt(stat_rx_pfc_pkt),
|
|
.stat_rx_pfc_xon(stat_rx_pfc_xon),
|
|
.stat_rx_pfc_xoff(stat_rx_pfc_xoff),
|
|
.stat_rx_pfc_paused(stat_rx_pfc_paused),
|
|
|
|
/*
|
|
* Configuration
|
|
*/
|
|
.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
|
|
.cfg_tx_ifg(cfg_tx_ifg),
|
|
.cfg_tx_enable(cfg_tx_enable),
|
|
.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
|
|
.cfg_rx_enable(cfg_rx_enable),
|
|
.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable),
|
|
.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable),
|
|
.cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
|
|
.cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),
|
|
.cfg_mcf_rx_eth_dst_ucast(cfg_mcf_rx_eth_dst_ucast),
|
|
.cfg_mcf_rx_check_eth_dst_ucast(cfg_mcf_rx_check_eth_dst_ucast),
|
|
.cfg_mcf_rx_eth_src(cfg_mcf_rx_eth_src),
|
|
.cfg_mcf_rx_check_eth_src(cfg_mcf_rx_check_eth_src),
|
|
.cfg_mcf_rx_eth_type(cfg_mcf_rx_eth_type),
|
|
.cfg_mcf_rx_opcode_lfc(cfg_mcf_rx_opcode_lfc),
|
|
.cfg_mcf_rx_check_opcode_lfc(cfg_mcf_rx_check_opcode_lfc),
|
|
.cfg_mcf_rx_opcode_pfc(cfg_mcf_rx_opcode_pfc),
|
|
.cfg_mcf_rx_check_opcode_pfc(cfg_mcf_rx_check_opcode_pfc),
|
|
.cfg_mcf_rx_forward(cfg_mcf_rx_forward),
|
|
.cfg_mcf_rx_enable(cfg_mcf_rx_enable),
|
|
.cfg_tx_lfc_eth_dst(cfg_tx_lfc_eth_dst),
|
|
.cfg_tx_lfc_eth_src(cfg_tx_lfc_eth_src),
|
|
.cfg_tx_lfc_eth_type(cfg_tx_lfc_eth_type),
|
|
.cfg_tx_lfc_opcode(cfg_tx_lfc_opcode),
|
|
.cfg_tx_lfc_en(cfg_tx_lfc_en),
|
|
.cfg_tx_lfc_quanta(cfg_tx_lfc_quanta),
|
|
.cfg_tx_lfc_refresh(cfg_tx_lfc_refresh),
|
|
.cfg_tx_pfc_eth_dst(cfg_tx_pfc_eth_dst),
|
|
.cfg_tx_pfc_eth_src(cfg_tx_pfc_eth_src),
|
|
.cfg_tx_pfc_eth_type(cfg_tx_pfc_eth_type),
|
|
.cfg_tx_pfc_opcode(cfg_tx_pfc_opcode),
|
|
.cfg_tx_pfc_en(cfg_tx_pfc_en),
|
|
.cfg_tx_pfc_quanta(cfg_tx_pfc_quanta),
|
|
.cfg_tx_pfc_refresh(cfg_tx_pfc_refresh),
|
|
.cfg_rx_lfc_opcode(cfg_rx_lfc_opcode),
|
|
.cfg_rx_lfc_en(cfg_rx_lfc_en),
|
|
.cfg_rx_pfc_opcode(cfg_rx_pfc_opcode),
|
|
.cfg_rx_pfc_en(cfg_rx_pfc_en)
|
|
);
|
|
|
|
endmodule
|
|
|
|
`resetall
|