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44 lines
1.8 KiB
Tcl
44 lines
1.8 KiB
Tcl
# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2014-2026 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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# XDC constraints for the Xilinx VCU108 board
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# part: xcvu095-ffva2104-2-e
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# General configuration
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set_property CFGBVS GND [current_design]
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set_property CONFIG_VOLTAGE 1.8 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
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set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1 [current_design]
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set_property CONFIG_MODE BPI16 [current_design]
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set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
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# System clocks
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# 300 MHz
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#set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_p]
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#set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_n]
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#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p]
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#set_property -dict {LOC G22 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_p]
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#set_property -dict {LOC G21 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_n]
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#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p]
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# 125 MHz
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set_property -dict {LOC BC9 IOSTANDARD LVDS} [get_ports clk_125mhz_p]
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set_property -dict {LOC BC8 IOSTANDARD LVDS} [get_ports clk_125mhz_n]
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create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
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# 90 MHz
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#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz]
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#create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz]
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# User SMA clock J34/J35
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#set_property -dict {LOC AR14 IOSTANDARD LVDS} [get_ports user_sma_clk_p]
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#set_property -dict {LOC AT14 IOSTANDARD LVDS} [get_ports user_sma_clk_n]
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#create_clock -period 8.000 -name user_sma_clk [get_ports user_sma_clk_p]
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