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36 lines
1.5 KiB
Tcl
36 lines
1.5 KiB
Tcl
# SPDX-License-Identifier: MIT
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#
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# Copyright (c) 2014-2026 FPGA Ninja, LLC
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#
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# Authors:
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# - Alex Forencich
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#
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# XDC constraints for the Xilinx VCU108 board
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# part: xcvu095-ffva2104-2-e
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# Gigabit Ethernet SGMII PHY
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set_property -dict {LOC AR24 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_rx_p]
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set_property -dict {LOC AT24 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_rx_n]
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set_property -dict {LOC AR23 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_tx_p]
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set_property -dict {LOC AR22 IOSTANDARD DIFF_HSTL_I_18} [get_ports phy_sgmii_tx_n]
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set_property -dict {LOC AT22 IOSTANDARD LVDS_25} [get_ports phy_sgmii_clk_p]
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set_property -dict {LOC AU22 IOSTANDARD LVDS_25} [get_ports phy_sgmii_clk_n]
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set_property -dict {LOC AU21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_reset_n]
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set_property -dict {LOC AT21 IOSTANDARD LVCMOS18} [get_ports phy_int_n]
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#set_property -dict {LOC AV24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdio]
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#set_property -dict {LOC AV21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdc]
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# 625 MHz ref clock from SGMII PHY
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#create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p]
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set_false_path -to [get_ports {phy_reset_n}]
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set_output_delay 0 [get_ports {phy_reset_n}]
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set_false_path -from [get_ports {phy_int_n}]
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set_input_delay 0 [get_ports {phy_int_n}]
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#set_false_path -to [get_ports {phy_mdio phy_mdc}]
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#set_output_delay 0 [get_ports {phy_mdio phy_mdc}]
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#set_false_path -from [get_ports {phy_mdio}]
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#set_input_delay 0 [get_ports {phy_mdio}]
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