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55 lines
882 B
Systemverilog
55 lines
882 B
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* XFCP switch testbench
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*/
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module test_taxi_xfcp_switch #
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(
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/* verilator lint_off WIDTHTRUNC */
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parameter PORTS = 4
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/* verilator lint_on WIDTHTRUNC */
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)
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();
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logic clk;
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logic rst;
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taxi_axis_if #(.DATA_W(8), .LAST_EN(1), .USER_EN(1), .USER_W(1)) xfcp_usp_ds(), xfcp_usp_us();
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taxi_axis_if #(.DATA_W(8), .LAST_EN(1), .USER_EN(1), .USER_W(1)) xfcp_dsp_ds[PORTS](), xfcp_dsp_us[PORTS]();
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taxi_xfcp_switch #(
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.PORTS(PORTS)
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)
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uut (
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.clk(clk),
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.rst(rst),
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/*
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* XFCP upstream port
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*/
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.xfcp_usp_ds(xfcp_usp_ds),
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.xfcp_usp_us(xfcp_usp_us),
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/*
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* XFCP downstream ports
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*/
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.xfcp_dsp_ds(xfcp_dsp_ds),
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.xfcp_dsp_us(xfcp_dsp_us)
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);
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endmodule
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`resetall
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