This website requires JavaScript.
Explore
Help
Register
Sign In
bslathi19
/
taxi
Watch
1
Star
0
Fork
0
You've already forked taxi
mirror of
https://github.com/fpganinja/taxi.git
synced
2025-12-13 10:38:39 -08:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Files
ee4d0da13e6a648d2793198a90eeecd0e548439d
taxi
/
example
/
Alveo
/
fpga
/
rtl
History
Alex Forencich
ebeadee172
lss: Implement fractional baud rate generation for UART
...
Signed-off-by: Alex Forencich <
alex@alexforencich.com
>
2025-03-11 23:49:39 -07:00
..
fpga_au45n.sv
example/Alveo: Add example design for Xilinx Alveo series
2025-02-25 11:34:26 -08:00
fpga_au50.sv
example/Alveo: Add example design for Xilinx Alveo series
2025-02-25 11:34:26 -08:00
fpga_au55.sv
example/Alveo: Add example design for Xilinx Alveo series
2025-02-25 11:34:26 -08:00
fpga_au200.sv
example/Alveo: Add example design for Xilinx Alveo series
2025-02-25 11:34:26 -08:00
fpga_au280.sv
example/Alveo: Add example design for Xilinx Alveo series
2025-02-25 11:34:26 -08:00
fpga_core.sv
lss: Implement fractional baud rate generation for UART
2025-03-11 23:49:39 -07:00
fpga_x3522.sv
example/Alveo: Add example design for Xilinx Alveo series
2025-02-25 11:34:26 -08:00
