mirror of
https://github.com/fpganinja/taxi.git
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600 lines
16 KiB
Systemverilog
600 lines
16 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2019-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* 10G Ethernet MAC/PHY combination with TX and RX FIFOs
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*/
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module taxi_eth_mac_phy_10g_fifo #
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(
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parameter DATA_W = 64,
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parameter HDR_W = (DATA_W/32),
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parameter logic PADDING_EN = 1'b1,
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parameter logic DIC_EN = 1'b1,
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parameter MIN_FRAME_LEN = 64,
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parameter logic PTP_TS_EN = 1'b0,
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parameter logic PTP_TS_FMT_TOD = 1'b1,
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parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
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parameter logic BIT_REVERSE = 1'b0,
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parameter logic SCRAMBLER_DISABLE = 1'b0,
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parameter logic PRBS31_EN = 1'b0,
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parameter TX_SERDES_PIPELINE = 0,
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parameter RX_SERDES_PIPELINE = 0,
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parameter BITSLIP_HIGH_CYCLES = 0,
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parameter BITSLIP_LOW_CYCLES = 7,
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parameter COUNT_125US = 125000/6.4,
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parameter logic STAT_EN = 1'b0,
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parameter STAT_TX_LEVEL = 1,
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parameter STAT_RX_LEVEL = 1,
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parameter STAT_ID_BASE = 0,
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parameter STAT_UPDATE_PERIOD = 1024,
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parameter TX_FIFO_DEPTH = 4096,
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parameter TX_FIFO_RAM_PIPELINE = 1,
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parameter logic TX_FRAME_FIFO = 1'b1,
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parameter logic TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO,
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parameter logic TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME,
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parameter logic TX_DROP_WHEN_FULL = 1'b0,
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parameter TX_CPL_FIFO_DEPTH = 64,
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parameter RX_FIFO_DEPTH = 4096,
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parameter RX_FIFO_RAM_PIPELINE = 1,
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parameter logic RX_FRAME_FIFO = 1'b1,
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parameter logic RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO,
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parameter logic RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME,
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parameter logic RX_DROP_WHEN_FULL = RX_DROP_OVERSIZE_FRAME
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)
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(
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input wire logic rx_clk,
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input wire logic rx_rst,
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input wire logic tx_clk,
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input wire logic tx_rst,
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input wire logic logic_clk,
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input wire logic logic_rst,
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input wire logic ptp_sample_clk,
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/*
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* Transmit interface (AXI stream)
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*/
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taxi_axis_if.snk s_axis_tx,
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taxi_axis_if.src m_axis_tx_cpl,
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/*
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* Receive interface (AXI stream)
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*/
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taxi_axis_if.src m_axis_rx,
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/*
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* SERDES interface
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*/
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output wire logic [DATA_W-1:0] serdes_tx_data,
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output wire logic [HDR_W-1:0] serdes_tx_hdr,
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input wire logic [DATA_W-1:0] serdes_rx_data,
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input wire logic [HDR_W-1:0] serdes_rx_hdr,
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output wire logic serdes_rx_bitslip,
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output wire logic serdes_rx_reset_req,
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/*
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* PTP clock
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*/
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input wire logic [PTP_TS_W-1:0] ptp_ts = '0,
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input wire logic ptp_ts_step = 1'b0,
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/*
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* Statistics
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*/
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input wire logic stat_clk,
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input wire logic stat_rst,
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taxi_axis_if.src m_axis_stat,
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/*
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* Status
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*/
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output wire logic tx_error_underflow,
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output wire logic tx_fifo_overflow,
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output wire logic tx_fifo_bad_frame,
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output wire logic tx_fifo_good_frame,
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output wire logic rx_error_bad_frame,
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output wire logic rx_error_bad_fcs,
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output wire logic rx_bad_block,
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output wire logic rx_sequence_error,
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output wire logic rx_block_lock,
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output wire logic rx_high_ber,
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output wire logic rx_status,
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output wire logic rx_fifo_overflow,
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output wire logic rx_fifo_bad_frame,
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output wire logic rx_fifo_good_frame,
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/*
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* Configuration
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*/
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input wire logic [15:0] cfg_tx_max_pkt_len = 16'd1518,
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input wire logic [7:0] cfg_tx_ifg = 8'd12,
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input wire logic cfg_tx_enable = 1'b1,
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input wire logic [15:0] cfg_rx_max_pkt_len = 16'd1518,
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input wire logic cfg_rx_enable = 1'b1,
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input wire logic cfg_tx_prbs31_enable = 1'b0,
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input wire logic cfg_rx_prbs31_enable = 1'b0
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);
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localparam KEEP_W = DATA_W/8;
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localparam TX_USER_W = 1;
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localparam RX_USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
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localparam TX_TAG_W = s_axis_tx.ID_W;
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taxi_axis_if #(.DATA_W(DATA_W), .KEEP_W(KEEP_W), .USER_EN(1), .USER_W(TX_USER_W), .ID_EN(1), .ID_W(TX_TAG_W)) axis_tx_int();
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taxi_axis_if #(.DATA_W(PTP_TS_W), .KEEP_W(1), .ID_EN(1), .ID_W(TX_TAG_W)) axis_tx_cpl_int();
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taxi_axis_if #(.DATA_W(DATA_W), .KEEP_W(KEEP_W), .USER_EN(1), .USER_W(RX_USER_W)) axis_rx_int();
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wire [PTP_TS_W-1:0] tx_ptp_ts;
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wire [PTP_TS_W-1:0] rx_ptp_ts;
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wire tx_ptp_locked;
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wire rx_ptp_locked;
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// synchronize MAC status signals into logic clock domain
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wire tx_error_underflow_int;
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reg [0:0] tx_sync_reg_1 = '0;
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reg [0:0] tx_sync_reg_2 = '0;
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reg [0:0] tx_sync_reg_3 = '0;
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reg [0:0] tx_sync_reg_4 = '0;
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assign tx_error_underflow = tx_sync_reg_3[0] ^ tx_sync_reg_4[0];
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always @(posedge tx_clk or posedge tx_rst) begin
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if (tx_rst) begin
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tx_sync_reg_1 <= '0;
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end else begin
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tx_sync_reg_1 <= tx_sync_reg_1 ^ {tx_error_underflow_int};
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end
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end
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always @(posedge logic_clk or posedge logic_rst) begin
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if (logic_rst) begin
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tx_sync_reg_2 <= '0;
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tx_sync_reg_3 <= '0;
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tx_sync_reg_4 <= '0;
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end else begin
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tx_sync_reg_2 <= tx_sync_reg_1;
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tx_sync_reg_3 <= tx_sync_reg_2;
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tx_sync_reg_4 <= tx_sync_reg_3;
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end
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end
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wire rx_error_bad_frame_int;
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wire rx_error_bad_fcs_int;
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wire rx_bad_block_int;
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wire rx_sequence_error_int;
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wire rx_block_lock_int;
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wire rx_high_ber_int;
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wire rx_status_int;
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reg [6:0] rx_sync_reg_1 = '0;
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reg [6:0] rx_sync_reg_2 = '0;
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reg [6:0] rx_sync_reg_3 = '0;
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reg [6:0] rx_sync_reg_4 = '0;
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assign rx_error_bad_frame = rx_sync_reg_3[0] ^ rx_sync_reg_4[0];
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assign rx_error_bad_fcs = rx_sync_reg_3[1] ^ rx_sync_reg_4[1];
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assign rx_bad_block = rx_sync_reg_3[2] ^ rx_sync_reg_4[2];
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assign rx_sequence_error = rx_sync_reg_3[3] ^ rx_sync_reg_4[3];
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assign rx_block_lock = rx_sync_reg_4[4];
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assign rx_high_ber = rx_sync_reg_4[5];
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assign rx_status = rx_sync_reg_4[6];
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always @(posedge rx_clk or posedge rx_rst) begin
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if (rx_rst) begin
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rx_sync_reg_1 <= '0;
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end else begin
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rx_sync_reg_1[0] <= rx_sync_reg_1[0] ^ rx_error_bad_frame_int;
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rx_sync_reg_1[1] <= rx_sync_reg_1[1] ^ rx_error_bad_fcs_int;
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rx_sync_reg_1[2] <= rx_sync_reg_1[2] ^ rx_bad_block_int;
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rx_sync_reg_1[3] <= rx_sync_reg_1[3] ^ rx_sequence_error_int;
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rx_sync_reg_1[4] <= rx_block_lock_int;
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rx_sync_reg_1[5] <= rx_high_ber_int;
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rx_sync_reg_1[6] <= rx_status_int;
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end
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end
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always @(posedge logic_clk or posedge logic_rst) begin
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if (logic_rst) begin
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rx_sync_reg_2 <= '0;
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rx_sync_reg_3 <= '0;
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rx_sync_reg_4 <= '0;
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end else begin
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rx_sync_reg_2 <= rx_sync_reg_1;
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rx_sync_reg_3 <= rx_sync_reg_2;
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rx_sync_reg_4 <= rx_sync_reg_3;
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end
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end
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// PTP timestamping
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if (PTP_TS_EN) begin : ptp
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taxi_ptp_clock_cdc #(
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.TS_W(PTP_TS_W),
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.NS_W(6)
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)
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tx_ptp_cdc (
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.input_clk(logic_clk),
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.input_rst(logic_rst),
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.output_clk(tx_clk),
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.output_rst(tx_rst),
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.sample_clk(ptp_sample_clk),
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.input_ts(ptp_ts),
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.input_ts_step(ptp_ts_step),
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.output_ts(tx_ptp_ts),
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.output_ts_step(),
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.output_pps(),
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.output_pps_str(),
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.locked(tx_ptp_locked)
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);
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taxi_ptp_clock_cdc #(
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.TS_W(PTP_TS_W),
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.NS_W(6)
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)
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rx_ptp_cdc (
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.input_clk(logic_clk),
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.input_rst(logic_rst),
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.output_clk(rx_clk),
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.output_rst(rx_rst),
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.sample_clk(ptp_sample_clk),
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.input_ts(ptp_ts),
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.input_ts_step(ptp_ts_step),
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.output_ts(rx_ptp_ts),
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.output_ts_step(),
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.output_pps(),
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.output_pps_str(),
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.locked(rx_ptp_locked)
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);
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end else begin
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assign tx_ptp_ts = '0;
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assign rx_ptp_ts = '0;
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assign tx_ptp_locked = 1'b0;
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assign rx_ptp_locked = 1'b0;
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end
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wire stat_rx_fifo_drop;
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taxi_eth_mac_phy_10g #(
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.DATA_W(DATA_W),
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.HDR_W(HDR_W),
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.PADDING_EN(PADDING_EN),
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.DIC_EN(DIC_EN),
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.MIN_FRAME_LEN(MIN_FRAME_LEN),
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.PTP_TS_EN(PTP_TS_EN),
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.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
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.PTP_TS_W(PTP_TS_W),
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.BIT_REVERSE(BIT_REVERSE),
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.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
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.PRBS31_EN(PRBS31_EN),
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.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
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.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
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.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
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.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
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.COUNT_125US(COUNT_125US),
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.STAT_EN(STAT_EN),
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.STAT_TX_LEVEL(STAT_TX_LEVEL),
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.STAT_RX_LEVEL(STAT_RX_LEVEL),
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.STAT_ID_BASE(STAT_ID_BASE),
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.STAT_UPDATE_PERIOD(STAT_UPDATE_PERIOD)
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)
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eth_mac_phy_10g_inst (
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.tx_clk(tx_clk),
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.tx_rst(tx_rst),
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.rx_clk(rx_clk),
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.rx_rst(rx_rst),
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/*
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* Transmit interface (AXI stream)
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*/
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.s_axis_tx(axis_tx_int),
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.m_axis_tx_cpl(axis_tx_cpl_int),
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/*
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* Receive interface (AXI stream)
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*/
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.m_axis_rx(axis_rx_int),
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/*
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* Serdes interface
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*/
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.serdes_tx_data(serdes_tx_data),
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.serdes_tx_hdr(serdes_tx_hdr),
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.serdes_rx_data(serdes_rx_data),
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.serdes_rx_hdr(serdes_rx_hdr),
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.serdes_rx_bitslip(serdes_rx_bitslip),
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.serdes_rx_reset_req(serdes_rx_reset_req),
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/*
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* PTP
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*/
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.tx_ptp_ts(tx_ptp_ts),
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.rx_ptp_ts(rx_ptp_ts),
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/*
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* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
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*/
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.tx_lfc_req(0),
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.tx_lfc_resend(0),
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.rx_lfc_en(0),
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.rx_lfc_req(),
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.rx_lfc_ack(0),
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/*
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* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
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*/
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.tx_pfc_req(0),
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.tx_pfc_resend(0),
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.rx_pfc_en(0),
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.rx_pfc_req(),
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.rx_pfc_ack(0),
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/*
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* Pause interface
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*/
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.tx_lfc_pause_en(0),
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.tx_pause_req(0),
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.tx_pause_ack(),
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/*
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* Statistics
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*/
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.stat_clk(stat_clk),
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.stat_rst(stat_rst),
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.m_axis_stat(m_axis_stat),
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/*
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* Status
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*/
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.tx_start_packet(),
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.stat_tx_byte(),
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.stat_tx_pkt_len(),
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.stat_tx_pkt_ucast(),
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.stat_tx_pkt_mcast(),
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.stat_tx_pkt_bcast(),
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.stat_tx_pkt_vlan(),
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.stat_tx_pkt_good(),
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.stat_tx_pkt_bad(),
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.stat_tx_err_oversize(),
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.stat_tx_err_user(),
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.stat_tx_err_underflow(tx_error_underflow_int),
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.rx_start_packet(),
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.rx_error_count(),
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.rx_block_lock(rx_block_lock_int),
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.rx_high_ber(rx_high_ber_int),
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.rx_status(rx_status_int),
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.stat_rx_byte(),
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.stat_rx_pkt_len(),
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.stat_rx_pkt_fragment(),
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.stat_rx_pkt_jabber(),
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.stat_rx_pkt_ucast(),
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.stat_rx_pkt_mcast(),
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.stat_rx_pkt_bcast(),
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.stat_rx_pkt_vlan(),
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.stat_rx_pkt_good(),
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.stat_rx_pkt_bad(rx_error_bad_frame_int),
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.stat_rx_err_oversize(),
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.stat_rx_err_bad_fcs(rx_error_bad_fcs_int),
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.stat_rx_err_bad_block(rx_bad_block_int),
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.stat_rx_err_framing(rx_sequence_error_int),
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.stat_rx_err_preamble(),
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.stat_rx_fifo_drop(stat_rx_fifo_drop),
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.stat_tx_mcf(),
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.stat_rx_mcf(),
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.stat_tx_lfc_pkt(),
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.stat_tx_lfc_xon(),
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.stat_tx_lfc_xoff(),
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.stat_tx_lfc_paused(),
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.stat_tx_pfc_pkt(),
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.stat_tx_pfc_xon(),
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.stat_tx_pfc_xoff(),
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.stat_tx_pfc_paused(),
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.stat_rx_lfc_pkt(),
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.stat_rx_lfc_xon(),
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.stat_rx_lfc_xoff(),
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.stat_rx_lfc_paused(),
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.stat_rx_pfc_pkt(),
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.stat_rx_pfc_xon(),
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.stat_rx_pfc_xoff(),
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.stat_rx_pfc_paused(),
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/*
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* Configuration
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*/
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.cfg_tx_max_pkt_len(cfg_tx_max_pkt_len),
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.cfg_tx_ifg(cfg_tx_ifg),
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.cfg_tx_enable(cfg_tx_enable),
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.cfg_rx_max_pkt_len(cfg_rx_max_pkt_len),
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.cfg_rx_enable(cfg_rx_enable),
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.cfg_tx_prbs31_enable(cfg_tx_prbs31_enable),
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.cfg_rx_prbs31_enable(cfg_rx_prbs31_enable),
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.cfg_mcf_rx_eth_dst_mcast('0),
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.cfg_mcf_rx_check_eth_dst_mcast('0),
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.cfg_mcf_rx_eth_dst_ucast('0),
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.cfg_mcf_rx_check_eth_dst_ucast('0),
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.cfg_mcf_rx_eth_src('0),
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.cfg_mcf_rx_check_eth_src('0),
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.cfg_mcf_rx_eth_type('0),
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.cfg_mcf_rx_opcode_lfc('0),
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.cfg_mcf_rx_check_opcode_lfc('0),
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.cfg_mcf_rx_opcode_pfc('0),
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.cfg_mcf_rx_check_opcode_pfc('0),
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.cfg_mcf_rx_forward('0),
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.cfg_mcf_rx_enable('0),
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.cfg_tx_lfc_eth_dst('0),
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.cfg_tx_lfc_eth_src('0),
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.cfg_tx_lfc_eth_type('0),
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.cfg_tx_lfc_opcode('0),
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.cfg_tx_lfc_en('0),
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.cfg_tx_lfc_quanta('0),
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.cfg_tx_lfc_refresh('0),
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.cfg_tx_pfc_eth_dst('0),
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.cfg_tx_pfc_eth_src('0),
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.cfg_tx_pfc_eth_type('0),
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.cfg_tx_pfc_opcode('0),
|
|
.cfg_tx_pfc_en('0),
|
|
.cfg_tx_pfc_quanta('{8{'0}}),
|
|
.cfg_tx_pfc_refresh('{8{'0}}),
|
|
.cfg_rx_lfc_opcode('0),
|
|
.cfg_rx_lfc_en('0),
|
|
.cfg_rx_pfc_opcode('0),
|
|
.cfg_rx_pfc_en('0)
|
|
);
|
|
|
|
taxi_axis_async_fifo_adapter #(
|
|
.DEPTH(TX_FIFO_DEPTH),
|
|
.RAM_PIPELINE(TX_FIFO_RAM_PIPELINE),
|
|
.FRAME_FIFO(TX_FRAME_FIFO),
|
|
.USER_BAD_FRAME_VALUE(1'b1),
|
|
.USER_BAD_FRAME_MASK(1'b1),
|
|
.DROP_OVERSIZE_FRAME(TX_DROP_OVERSIZE_FRAME),
|
|
.DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
|
|
.DROP_WHEN_FULL(TX_DROP_WHEN_FULL)
|
|
)
|
|
tx_fifo (
|
|
/*
|
|
* AXI4-Stream input (sink)
|
|
*/
|
|
.s_clk(logic_clk),
|
|
.s_rst(logic_rst),
|
|
.s_axis(s_axis_tx),
|
|
|
|
/*
|
|
* AXI4-Stream output (source)
|
|
*/
|
|
.m_clk(tx_clk),
|
|
.m_rst(tx_rst),
|
|
.m_axis(axis_tx_int),
|
|
|
|
/*
|
|
* Pause
|
|
*/
|
|
.s_pause_req(1'b0),
|
|
.s_pause_ack(),
|
|
.m_pause_req(1'b0),
|
|
.m_pause_ack(),
|
|
|
|
/*
|
|
* Status
|
|
*/
|
|
.s_status_depth(),
|
|
.s_status_depth_commit(),
|
|
.s_status_overflow(tx_fifo_overflow),
|
|
.s_status_bad_frame(tx_fifo_bad_frame),
|
|
.s_status_good_frame(tx_fifo_good_frame),
|
|
.m_status_depth(),
|
|
.m_status_depth_commit(),
|
|
.m_status_overflow(),
|
|
.m_status_bad_frame(),
|
|
.m_status_good_frame()
|
|
);
|
|
|
|
taxi_axis_async_fifo #(
|
|
.DEPTH(TX_CPL_FIFO_DEPTH),
|
|
.FRAME_FIFO(1'b0)
|
|
)
|
|
tx_cpl_fifo (
|
|
/*
|
|
* AXI4-Stream input (sink)
|
|
*/
|
|
.s_clk(tx_clk),
|
|
.s_rst(tx_rst),
|
|
.s_axis(axis_tx_cpl_int),
|
|
|
|
/*
|
|
* AXI4-Stream output (source)
|
|
*/
|
|
.m_clk(logic_clk),
|
|
.m_rst(logic_rst),
|
|
.m_axis(m_axis_tx_cpl),
|
|
|
|
/*
|
|
* Pause
|
|
*/
|
|
.s_pause_req(1'b0),
|
|
.s_pause_ack(),
|
|
.m_pause_req(1'b0),
|
|
.m_pause_ack(),
|
|
|
|
/*
|
|
* Status
|
|
*/
|
|
.s_status_depth(),
|
|
.s_status_depth_commit(),
|
|
.s_status_overflow(),
|
|
.s_status_bad_frame(),
|
|
.s_status_good_frame(),
|
|
.m_status_depth(),
|
|
.m_status_depth_commit(),
|
|
.m_status_overflow(),
|
|
.m_status_bad_frame(),
|
|
.m_status_good_frame()
|
|
);
|
|
|
|
taxi_axis_async_fifo_adapter #(
|
|
.DEPTH(RX_FIFO_DEPTH),
|
|
.RAM_PIPELINE(RX_FIFO_RAM_PIPELINE),
|
|
.FRAME_FIFO(RX_FRAME_FIFO),
|
|
.USER_BAD_FRAME_VALUE(1'b1),
|
|
.USER_BAD_FRAME_MASK(1'b1),
|
|
.DROP_OVERSIZE_FRAME(RX_DROP_OVERSIZE_FRAME),
|
|
.DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
|
|
.DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
|
|
)
|
|
rx_fifo (
|
|
/*
|
|
* AXI4-Stream input (sink)
|
|
*/
|
|
.s_clk(rx_clk),
|
|
.s_rst(rx_rst),
|
|
.s_axis(axis_rx_int),
|
|
|
|
/*
|
|
* AXI4-Stream output (source)
|
|
*/
|
|
.m_clk(logic_clk),
|
|
.m_rst(logic_rst),
|
|
.m_axis(m_axis_rx),
|
|
|
|
/*
|
|
* Pause
|
|
*/
|
|
.s_pause_req(1'b0),
|
|
.s_pause_ack(),
|
|
.m_pause_req(1'b0),
|
|
.m_pause_ack(),
|
|
|
|
/*
|
|
* Status
|
|
*/
|
|
.s_status_depth(),
|
|
.s_status_depth_commit(),
|
|
.s_status_overflow(stat_rx_fifo_drop),
|
|
.s_status_bad_frame(),
|
|
.s_status_good_frame(),
|
|
.m_status_depth(),
|
|
.m_status_depth_commit(),
|
|
.m_status_overflow(rx_fifo_overflow),
|
|
.m_status_bad_frame(rx_fifo_bad_frame),
|
|
.m_status_good_frame(rx_fifo_good_frame)
|
|
);
|
|
|
|
endmodule
|
|
|
|
`resetall
|