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https://github.com/fpganinja/taxi.git
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671 lines
19 KiB
Systemverilog
671 lines
19 KiB
Systemverilog
// SPDX-License-Identifier: CERN-OHL-S-2.0
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/*
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Copyright (c) 2015-2025 FPGA Ninja, LLC
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Authors:
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- Alex Forencich
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*/
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* 10G Ethernet MAC
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*/
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module taxi_eth_mac_10g #
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(
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parameter DATA_W = 64,
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parameter CTRL_W = (DATA_W/8),
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parameter logic PADDING_EN = 1'b1,
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parameter logic DIC_EN = 1'b1,
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parameter MIN_FRAME_LEN = 64,
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parameter logic PTP_TS_EN = 1'b0,
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parameter logic PTP_TS_FMT_TOD = 1'b1,
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parameter PTP_TS_W = PTP_TS_FMT_TOD ? 96 : 64,
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parameter logic PFC_EN = 1'b0,
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parameter logic PAUSE_EN = PFC_EN
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)
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(
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input wire logic rx_clk,
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input wire logic rx_rst,
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input wire logic tx_clk,
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input wire logic tx_rst,
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/*
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* Transmit interface (AXI stream)
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*/
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taxi_axis_if.snk s_axis_tx,
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taxi_axis_if.src m_axis_tx_cpl,
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/*
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* Receive interface (AXI stream)
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*/
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taxi_axis_if.src m_axis_rx,
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/*
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* XGMII interface
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*/
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input wire logic [DATA_W-1:0] xgmii_rxd,
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input wire logic [CTRL_W-1:0] xgmii_rxc,
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output wire logic [DATA_W-1:0] xgmii_txd,
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output wire logic [CTRL_W-1:0] xgmii_txc,
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/*
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* PTP
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*/
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input wire logic [PTP_TS_W-1:0] tx_ptp_ts = '0,
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input wire logic [PTP_TS_W-1:0] rx_ptp_ts = '0,
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/*
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* Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE)
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*/
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input wire logic tx_lfc_req = 1'b0,
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input wire logic tx_lfc_resend = 1'b0,
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input wire logic rx_lfc_en = 1'b0,
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output wire logic rx_lfc_req,
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input wire logic rx_lfc_ack = 1'b0,
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/*
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* Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC)
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*/
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input wire logic [7:0] tx_pfc_req = '0,
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input wire logic tx_pfc_resend = 1'b0,
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input wire logic [7:0] rx_pfc_en = '0,
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output wire logic [7:0] rx_pfc_req,
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input wire logic [7:0] rx_pfc_ack = '0,
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/*
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* Pause interface
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*/
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input wire logic tx_lfc_pause_en = 1'b0,
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input wire logic tx_pause_req = 1'b0,
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output wire logic tx_pause_ack,
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/*
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* Status
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*/
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output wire logic [1:0] tx_start_packet,
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output wire logic tx_error_underflow,
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output wire logic [1:0] rx_start_packet,
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output wire logic rx_error_bad_frame,
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output wire logic rx_error_bad_fcs,
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output wire logic stat_tx_mcf,
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output wire logic stat_rx_mcf,
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output wire logic stat_tx_lfc_pkt,
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output wire logic stat_tx_lfc_xon,
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output wire logic stat_tx_lfc_xoff,
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output wire logic stat_tx_lfc_paused,
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output wire logic stat_tx_pfc_pkt,
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output wire logic [7:0] stat_tx_pfc_xon,
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output wire logic [7:0] stat_tx_pfc_xoff,
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output wire logic [7:0] stat_tx_pfc_paused,
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output wire logic stat_rx_lfc_pkt,
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output wire logic stat_rx_lfc_xon,
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output wire logic stat_rx_lfc_xoff,
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output wire logic stat_rx_lfc_paused,
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output wire logic stat_rx_pfc_pkt,
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output wire logic [7:0] stat_rx_pfc_xon,
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output wire logic [7:0] stat_rx_pfc_xoff,
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output wire logic [7:0] stat_rx_pfc_paused,
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/*
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* Configuration
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*/
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input wire logic [7:0] cfg_ifg = 8'd12,
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input wire logic cfg_tx_enable = 1'b1,
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input wire logic cfg_rx_enable = 1'b1,
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input wire logic [47:0] cfg_mcf_rx_eth_dst_mcast = 48'h01_80_C2_00_00_01,
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input wire logic cfg_mcf_rx_check_eth_dst_mcast = 1'b1,
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input wire logic [47:0] cfg_mcf_rx_eth_dst_ucast = 48'd0,
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input wire logic cfg_mcf_rx_check_eth_dst_ucast = 1'b0,
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input wire logic [47:0] cfg_mcf_rx_eth_src = 48'd0,
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input wire logic cfg_mcf_rx_check_eth_src = 1'b0,
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input wire logic [15:0] cfg_mcf_rx_eth_type = 16'h8808,
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input wire logic [15:0] cfg_mcf_rx_opcode_lfc = 16'h0001,
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input wire logic cfg_mcf_rx_check_opcode_lfc = 1'b1,
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input wire logic [15:0] cfg_mcf_rx_opcode_pfc = 16'h0101,
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input wire logic cfg_mcf_rx_check_opcode_pfc = 1'b1,
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input wire logic cfg_mcf_rx_forward = 1'b0,
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input wire logic cfg_mcf_rx_enable = 1'b0,
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input wire logic [47:0] cfg_tx_lfc_eth_dst = 48'h01_80_C2_00_00_01,
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input wire logic [47:0] cfg_tx_lfc_eth_src = 48'h80_23_31_43_54_4C,
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input wire logic [15:0] cfg_tx_lfc_eth_type = 16'h8808,
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input wire logic [15:0] cfg_tx_lfc_opcode = 16'h0001,
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input wire logic cfg_tx_lfc_en = 1'b0,
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input wire logic [15:0] cfg_tx_lfc_quanta = 16'hffff,
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input wire logic [15:0] cfg_tx_lfc_refresh = 16'h7fff,
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input wire logic [47:0] cfg_tx_pfc_eth_dst = 48'h01_80_C2_00_00_01,
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input wire logic [47:0] cfg_tx_pfc_eth_src = 48'h80_23_31_43_54_4C,
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input wire logic [15:0] cfg_tx_pfc_eth_type = 16'h8808,
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input wire logic [15:0] cfg_tx_pfc_opcode = 16'h0101,
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input wire logic cfg_tx_pfc_en = 1'b0,
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input wire logic [7:0][15:0] cfg_tx_pfc_quanta = '{8{16'hffff}},
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input wire logic [7:0][15:0] cfg_tx_pfc_refresh = '{8{16'h7fff}},
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input wire logic [15:0] cfg_rx_lfc_opcode = 16'h0001,
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input wire logic cfg_rx_lfc_en = 1'b0,
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input wire logic [15:0] cfg_rx_pfc_opcode = 16'h0101,
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input wire logic cfg_rx_pfc_en = 1'b0
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);
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localparam KEEP_W = s_axis_tx.KEEP_W;
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localparam TX_USER_W = 1;
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localparam RX_USER_W = (PTP_TS_EN ? PTP_TS_W : 0) + 1;
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localparam TX_TAG_W = s_axis_tx.ID_W;
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localparam MAC_CTRL_EN = PAUSE_EN || PFC_EN;
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localparam TX_USER_W_INT = (MAC_CTRL_EN ? 1 : 0) + TX_USER_W;
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// check configuration
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if (DATA_W != 32 && DATA_W != 64)
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$fatal(0, "Error: Interface width must be 32 or 64 (instance %m)");
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if (KEEP_W*8 != DATA_W || CTRL_W*8 != DATA_W)
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$fatal(0, "Error: Interface requires byte (8-bit) granularity (instance %m)");
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taxi_axis_if #(.DATA_W(DATA_W), .KEEP_W(KEEP_W), .USER_EN(1), .USER_W(TX_USER_W_INT), .ID_EN(1), .ID_W(TX_TAG_W)) axis_tx_int();
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taxi_axis_if #(.DATA_W(DATA_W), .KEEP_W(KEEP_W), .USER_EN(1), .USER_W(RX_USER_W)) axis_rx_int();
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if (DATA_W == 64) begin
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taxi_axis_xgmii_rx_64 #(
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.DATA_W(DATA_W),
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.CTRL_W(CTRL_W),
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.PTP_TS_EN(PTP_TS_EN),
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.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
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.PTP_TS_W(PTP_TS_W)
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)
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axis_xgmii_rx_inst (
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.clk(rx_clk),
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.rst(rx_rst),
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/*
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* XGMII input
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*/
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.xgmii_rxd(xgmii_rxd),
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.xgmii_rxc(xgmii_rxc),
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/*
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* Receive interface (AXI stream)
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*/
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.m_axis_rx(axis_rx_int),
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/*
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* PTP
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*/
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.ptp_ts(rx_ptp_ts),
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/*
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* Configuration
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*/
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.cfg_rx_enable(cfg_rx_enable),
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/*
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* Status
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*/
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.start_packet(rx_start_packet),
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.error_bad_frame(rx_error_bad_frame),
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.error_bad_fcs(rx_error_bad_fcs)
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);
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taxi_axis_xgmii_tx_64 #(
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.DATA_W(DATA_W),
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.CTRL_W(CTRL_W),
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.PADDING_EN(PADDING_EN),
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.DIC_EN(DIC_EN),
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.MIN_FRAME_LEN(MIN_FRAME_LEN),
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.PTP_TS_EN(PTP_TS_EN),
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.PTP_TS_FMT_TOD(PTP_TS_FMT_TOD),
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.PTP_TS_W(PTP_TS_W),
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.TX_CPL_CTRL_IN_TUSER(MAC_CTRL_EN)
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)
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axis_xgmii_tx_inst (
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.clk(tx_clk),
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.rst(tx_rst),
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/*
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* Transmit interface (AXI stream)
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*/
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.s_axis_tx(axis_tx_int),
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.m_axis_tx_cpl(m_axis_tx_cpl),
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/*
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* XGMII output
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*/
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.xgmii_txd(xgmii_txd),
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.xgmii_txc(xgmii_txc),
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/*
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* PTP
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*/
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.ptp_ts(tx_ptp_ts),
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/*
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* Configuration
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*/
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.cfg_ifg(cfg_ifg),
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.cfg_tx_enable(cfg_tx_enable),
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/*
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* Status
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*/
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.start_packet(tx_start_packet),
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.error_underflow(tx_error_underflow)
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);
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end else if (DATA_W == 32) begin
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taxi_axis_xgmii_rx_32 #(
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.DATA_W(DATA_W),
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.CTRL_W(CTRL_W),
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.PTP_TS_EN(PTP_TS_EN),
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.PTP_TS_W(PTP_TS_W)
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)
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axis_xgmii_rx_inst (
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.clk(rx_clk),
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.rst(rx_rst),
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/*
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* XGMII input
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*/
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.xgmii_rxd(xgmii_rxd),
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.xgmii_rxc(xgmii_rxc),
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/*
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* Receive interface (AXI stream)
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*/
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.m_axis_rx(axis_rx_int),
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/*
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* PTP
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*/
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.ptp_ts(rx_ptp_ts),
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/*
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* Configuration
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*/
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.cfg_rx_enable(cfg_rx_enable),
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/*
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* Status
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*/
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.start_packet(rx_start_packet[0]),
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.error_bad_frame(rx_error_bad_frame),
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.error_bad_fcs(rx_error_bad_fcs)
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);
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assign rx_start_packet[1] = 1'b0;
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taxi_axis_xgmii_tx_32 #(
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.DATA_W(DATA_W),
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.CTRL_W(CTRL_W),
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.PADDING_EN(PADDING_EN),
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.DIC_EN(DIC_EN),
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.MIN_FRAME_LEN(MIN_FRAME_LEN),
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.PTP_TS_EN(PTP_TS_EN),
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.PTP_TS_W(PTP_TS_W),
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.TX_CPL_CTRL_IN_TUSER(MAC_CTRL_EN)
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)
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axis_xgmii_tx_inst (
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.clk(tx_clk),
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.rst(tx_rst),
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/*
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* Transmit interface (AXI stream)
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*/
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.s_axis_tx(axis_tx_int),
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.m_axis_tx_cpl(m_axis_tx_cpl),
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/*
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* XGMII output
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*/
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.xgmii_txd(xgmii_txd),
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.xgmii_txc(xgmii_txc),
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/*
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* PTP
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*/
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.ptp_ts(tx_ptp_ts),
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/*
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* Configuration
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*/
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.cfg_ifg(cfg_ifg),
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.cfg_tx_enable(cfg_tx_enable),
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/*
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* Status
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*/
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.start_packet(tx_start_packet[0]),
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.error_underflow(tx_error_underflow)
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);
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assign tx_start_packet[1] = 1'b0;
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end else begin
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$fatal(0, "Invalid DATA_W selection (instance %m)");
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end
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if (MAC_CTRL_EN) begin : mac_ctrl
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localparam MCF_PARAMS_SIZE = PFC_EN ? 18 : 2;
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wire tx_mcf_valid;
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wire tx_mcf_ready;
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wire [47:0] tx_mcf_eth_dst;
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wire [47:0] tx_mcf_eth_src;
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wire [15:0] tx_mcf_eth_type;
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wire [15:0] tx_mcf_opcode;
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wire [MCF_PARAMS_SIZE*8-1:0] tx_mcf_params;
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wire rx_mcf_valid;
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wire [47:0] rx_mcf_eth_dst;
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wire [47:0] rx_mcf_eth_src;
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wire [15:0] rx_mcf_eth_type;
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wire [15:0] rx_mcf_opcode;
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wire [MCF_PARAMS_SIZE*8-1:0] rx_mcf_params;
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// terminate LFC pause requests from RX internally on TX side
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wire tx_pause_req_int;
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wire rx_lfc_ack_int;
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wire rx_lfc_req_sync;
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taxi_sync_signal #(
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.WIDTH(1),
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.N(2)
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)
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rx_lfc_req_sync_inst (
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.clk(tx_clk),
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.in(rx_lfc_req),
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.out(rx_lfc_req_sync)
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);
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wire tx_pause_ack_sync;
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taxi_sync_signal #(
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.WIDTH(1),
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.N(2)
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)
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tx_pause_ack_sync_inst (
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.clk(rx_clk),
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.in(tx_lfc_pause_en && tx_pause_ack),
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.out(tx_pause_ack_sync)
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);
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assign tx_pause_req_int = tx_pause_req || (tx_lfc_pause_en && rx_lfc_req_sync);
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assign rx_lfc_ack_int = rx_lfc_ack || tx_pause_ack_sync;
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taxi_mac_ctrl_tx #(
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.ID_W(s_axis_tx.ID_W),
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.DEST_W(s_axis_tx.DEST_W),
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.USER_W(TX_USER_W_INT),
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.MCF_PARAMS_SIZE(MCF_PARAMS_SIZE)
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)
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mac_ctrl_tx_inst (
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.clk(tx_clk),
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.rst(tx_rst),
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/*
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* AXI stream input
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*/
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.s_axis(s_axis_tx),
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/*
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* AXI stream output
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*/
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.m_axis(axis_tx_int),
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/*
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* MAC control frame interface
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*/
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.mcf_valid(tx_mcf_valid),
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.mcf_ready(tx_mcf_ready),
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.mcf_eth_dst(tx_mcf_eth_dst),
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.mcf_eth_src(tx_mcf_eth_src),
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.mcf_eth_type(tx_mcf_eth_type),
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.mcf_opcode(tx_mcf_opcode),
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.mcf_params(tx_mcf_params),
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.mcf_id('0),
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.mcf_dest('0),
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.mcf_user(2'b10),
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/*
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* Pause interface
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*/
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.tx_pause_req(tx_pause_req_int),
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.tx_pause_ack(tx_pause_ack),
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/*
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* Status
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*/
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.stat_tx_mcf(stat_tx_mcf)
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);
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taxi_mac_ctrl_rx #(
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.USER_W(RX_USER_W),
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.USE_READY(0),
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.MCF_PARAMS_SIZE(MCF_PARAMS_SIZE)
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)
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mac_ctrl_rx_inst (
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.clk(rx_clk),
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.rst(rx_rst),
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/*
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* AXI stream input
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*/
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.s_axis(axis_rx_int),
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/*
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* AXI stream output
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*/
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.m_axis(m_axis_rx),
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/*
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* MAC control frame interface
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*/
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.mcf_valid(rx_mcf_valid),
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.mcf_eth_dst(rx_mcf_eth_dst),
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.mcf_eth_src(rx_mcf_eth_src),
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.mcf_eth_type(rx_mcf_eth_type),
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.mcf_opcode(rx_mcf_opcode),
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.mcf_params(rx_mcf_params),
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.mcf_id(),
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.mcf_dest(),
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.mcf_user(),
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/*
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* Configuration
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*/
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.cfg_mcf_rx_eth_dst_mcast(cfg_mcf_rx_eth_dst_mcast),
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.cfg_mcf_rx_check_eth_dst_mcast(cfg_mcf_rx_check_eth_dst_mcast),
|
|
.cfg_mcf_rx_eth_dst_ucast(cfg_mcf_rx_eth_dst_ucast),
|
|
.cfg_mcf_rx_check_eth_dst_ucast(cfg_mcf_rx_check_eth_dst_ucast),
|
|
.cfg_mcf_rx_eth_src(cfg_mcf_rx_eth_src),
|
|
.cfg_mcf_rx_check_eth_src(cfg_mcf_rx_check_eth_src),
|
|
.cfg_mcf_rx_eth_type(cfg_mcf_rx_eth_type),
|
|
.cfg_mcf_rx_opcode_lfc(cfg_mcf_rx_opcode_lfc),
|
|
.cfg_mcf_rx_check_opcode_lfc(cfg_mcf_rx_check_opcode_lfc),
|
|
.cfg_mcf_rx_opcode_pfc(cfg_mcf_rx_opcode_pfc),
|
|
.cfg_mcf_rx_check_opcode_pfc(cfg_mcf_rx_check_opcode_pfc && PFC_EN),
|
|
.cfg_mcf_rx_forward(cfg_mcf_rx_forward),
|
|
.cfg_mcf_rx_enable(cfg_mcf_rx_enable),
|
|
|
|
/*
|
|
* Status
|
|
*/
|
|
.stat_rx_mcf(stat_rx_mcf)
|
|
);
|
|
|
|
taxi_mac_pause_ctrl_tx #(
|
|
.MCF_PARAMS_SIZE(MCF_PARAMS_SIZE),
|
|
.PFC_EN(PFC_EN)
|
|
)
|
|
mac_pause_ctrl_tx_inst (
|
|
.clk(tx_clk),
|
|
.rst(tx_rst),
|
|
|
|
/*
|
|
* MAC control frame interface
|
|
*/
|
|
.mcf_valid(tx_mcf_valid),
|
|
.mcf_ready(tx_mcf_ready),
|
|
.mcf_eth_dst(tx_mcf_eth_dst),
|
|
.mcf_eth_src(tx_mcf_eth_src),
|
|
.mcf_eth_type(tx_mcf_eth_type),
|
|
.mcf_opcode(tx_mcf_opcode),
|
|
.mcf_params(tx_mcf_params),
|
|
|
|
/*
|
|
* Pause (IEEE 802.3 annex 31B)
|
|
*/
|
|
.tx_lfc_req(tx_lfc_req),
|
|
.tx_lfc_resend(tx_lfc_resend),
|
|
|
|
/*
|
|
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D)
|
|
*/
|
|
.tx_pfc_req(tx_pfc_req),
|
|
.tx_pfc_resend(tx_pfc_resend),
|
|
|
|
/*
|
|
* Configuration
|
|
*/
|
|
.cfg_tx_lfc_eth_dst(cfg_tx_lfc_eth_dst),
|
|
.cfg_tx_lfc_eth_src(cfg_tx_lfc_eth_src),
|
|
.cfg_tx_lfc_eth_type(cfg_tx_lfc_eth_type),
|
|
.cfg_tx_lfc_opcode(cfg_tx_lfc_opcode),
|
|
.cfg_tx_lfc_en(cfg_tx_lfc_en),
|
|
.cfg_tx_lfc_quanta(cfg_tx_lfc_quanta),
|
|
.cfg_tx_lfc_refresh(cfg_tx_lfc_refresh),
|
|
.cfg_tx_pfc_eth_dst(cfg_tx_pfc_eth_dst),
|
|
.cfg_tx_pfc_eth_src(cfg_tx_pfc_eth_src),
|
|
.cfg_tx_pfc_eth_type(cfg_tx_pfc_eth_type),
|
|
.cfg_tx_pfc_opcode(cfg_tx_pfc_opcode),
|
|
.cfg_tx_pfc_en(cfg_tx_pfc_en),
|
|
.cfg_tx_pfc_quanta(cfg_tx_pfc_quanta),
|
|
.cfg_tx_pfc_refresh(cfg_tx_pfc_refresh),
|
|
.cfg_quanta_step(10'((DATA_W*256)/512)),
|
|
.cfg_quanta_clk_en(1'b1),
|
|
|
|
/*
|
|
* Status
|
|
*/
|
|
.stat_tx_lfc_pkt(stat_tx_lfc_pkt),
|
|
.stat_tx_lfc_xon(stat_tx_lfc_xon),
|
|
.stat_tx_lfc_xoff(stat_tx_lfc_xoff),
|
|
.stat_tx_lfc_paused(stat_tx_lfc_paused),
|
|
.stat_tx_pfc_pkt(stat_tx_pfc_pkt),
|
|
.stat_tx_pfc_xon(stat_tx_pfc_xon),
|
|
.stat_tx_pfc_xoff(stat_tx_pfc_xoff),
|
|
.stat_tx_pfc_paused(stat_tx_pfc_paused)
|
|
);
|
|
|
|
taxi_mac_pause_ctrl_rx #(
|
|
.MCF_PARAMS_SIZE(18),
|
|
.PFC_EN(PFC_EN)
|
|
)
|
|
mac_pause_ctrl_rx_inst (
|
|
.clk(rx_clk),
|
|
.rst(rx_rst),
|
|
|
|
/*
|
|
* MAC control frame interface
|
|
*/
|
|
.mcf_valid(rx_mcf_valid),
|
|
.mcf_eth_dst(rx_mcf_eth_dst),
|
|
.mcf_eth_src(rx_mcf_eth_src),
|
|
.mcf_eth_type(rx_mcf_eth_type),
|
|
.mcf_opcode(rx_mcf_opcode),
|
|
.mcf_params(rx_mcf_params),
|
|
|
|
/*
|
|
* Pause (IEEE 802.3 annex 31B)
|
|
*/
|
|
.rx_lfc_en(rx_lfc_en),
|
|
.rx_lfc_req(rx_lfc_req),
|
|
.rx_lfc_ack(rx_lfc_ack_int),
|
|
|
|
/*
|
|
* Priority Flow Control (PFC) (IEEE 802.3 annex 31D)
|
|
*/
|
|
.rx_pfc_en(rx_pfc_en),
|
|
.rx_pfc_req(rx_pfc_req),
|
|
.rx_pfc_ack(rx_pfc_ack),
|
|
|
|
/*
|
|
* Configuration
|
|
*/
|
|
.cfg_rx_lfc_opcode(cfg_rx_lfc_opcode),
|
|
.cfg_rx_lfc_en(cfg_rx_lfc_en),
|
|
.cfg_rx_pfc_opcode(cfg_rx_pfc_opcode),
|
|
.cfg_rx_pfc_en(cfg_rx_pfc_en),
|
|
.cfg_quanta_step(10'((DATA_W*256)/512)),
|
|
.cfg_quanta_clk_en(1'b1),
|
|
|
|
/*
|
|
* Status
|
|
*/
|
|
.stat_rx_lfc_pkt(stat_rx_lfc_pkt),
|
|
.stat_rx_lfc_xon(stat_rx_lfc_xon),
|
|
.stat_rx_lfc_xoff(stat_rx_lfc_xoff),
|
|
.stat_rx_lfc_paused(stat_rx_lfc_paused),
|
|
.stat_rx_pfc_pkt(stat_rx_pfc_pkt),
|
|
.stat_rx_pfc_xon(stat_rx_pfc_xon),
|
|
.stat_rx_pfc_xoff(stat_rx_pfc_xoff),
|
|
.stat_rx_pfc_paused(stat_rx_pfc_paused)
|
|
);
|
|
|
|
end else begin
|
|
|
|
assign axis_tx_int.tdata = s_axis_tx.tdata;
|
|
assign axis_tx_int.tkeep = s_axis_tx.tkeep;
|
|
assign axis_tx_int.tvalid = s_axis_tx.tvalid;
|
|
assign s_axis_tx.tready = axis_tx_int.tready;
|
|
assign axis_tx_int.tlast = s_axis_tx.tlast;
|
|
assign axis_tx_int.tid = s_axis_tx.tid;
|
|
assign axis_tx_int.tdest = s_axis_tx.tdest;
|
|
assign axis_tx_int.tuser = s_axis_tx.tuser;
|
|
|
|
assign m_axis_rx.tdata = axis_rx_int.tdata;
|
|
assign m_axis_rx.tkeep = axis_rx_int.tkeep;
|
|
assign m_axis_rx.tvalid = axis_rx_int.tvalid;
|
|
assign m_axis_rx.tlast = axis_rx_int.tlast;
|
|
assign m_axis_rx.tid = axis_rx_int.tid;
|
|
assign m_axis_rx.tdest = axis_rx_int.tdest;
|
|
assign m_axis_rx.tuser = axis_rx_int.tuser;
|
|
|
|
assign rx_lfc_req = '0;
|
|
assign rx_pfc_req = '0;
|
|
assign tx_pause_ack = '0;
|
|
|
|
assign stat_tx_mcf = '0;
|
|
assign stat_rx_mcf = '0;
|
|
assign stat_tx_lfc_pkt = '0;
|
|
assign stat_tx_lfc_xon = '0;
|
|
assign stat_tx_lfc_xoff = '0;
|
|
assign stat_tx_lfc_paused = '0;
|
|
assign stat_tx_pfc_pkt = '0;
|
|
assign stat_tx_pfc_xon = '0;
|
|
assign stat_tx_pfc_xoff = '0;
|
|
assign stat_tx_pfc_paused = '0;
|
|
assign stat_rx_lfc_pkt = '0;
|
|
assign stat_rx_lfc_xon = '0;
|
|
assign stat_rx_lfc_xoff = '0;
|
|
assign stat_rx_lfc_paused = '0;
|
|
assign stat_rx_pfc_pkt = '0;
|
|
assign stat_rx_pfc_xon = '0;
|
|
assign stat_rx_pfc_xoff = '0;
|
|
assign stat_rx_pfc_paused = '0;
|
|
|
|
end
|
|
|
|
endmodule
|
|
|
|
`resetall
|