Support hard memories in FIFOs

Right now the FIFOs are designed for FPGAs, which relies on inferring block rams. If we want to tape these out, then they should use hard sram macros instead of ff ram.

The interface for the sram is pretty simple, clock, chip select, addr, and data. The interface changes a little bit depending on if you have a rw port or a single direction port, but it just means you lose the write enable bit and the data in bits, for example.

The major difference is that instead of writing to the ram in the clocked blocks, we need to have the signals be set in a comb block, and the ram itself is clocked. Otherwise, the ram will be 1 cycle behind. This might involve rewriting the FIFOs, but that shouldn't be too complicated.

Bonus points if we use the FPGA primitives for RAM too.