From 151643b2ade0f42408a36a6d5f02ae9c924a4f16 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Sun, 24 May 2026 17:13:20 -0700 Subject: [PATCH] Get it working more --- ...ication_wrapper_cache_miss_handler_test.py | 103 ++++++++++++++++++ .../application_wrapper_cache_miss_handler.sv | 31 ++++-- .../cache/application_wrapper_cache_pkg.sv | 2 +- 3 files changed, 126 insertions(+), 10 deletions(-) diff --git a/sim/application_wrapper/cache/application_wrapper_cache_miss_handler_test.py b/sim/application_wrapper/cache/application_wrapper_cache_miss_handler_test.py index bbdffbf..023cc5f 100644 --- a/sim/application_wrapper/cache/application_wrapper_cache_miss_handler_test.py +++ b/sim/application_wrapper/cache/application_wrapper_cache_miss_handler_test.py @@ -122,6 +122,8 @@ async def test_sanity(dut): cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start()) cocotb.start_soon(handle_cache_arrays(dut)) + dut.i_cpu_we.value = 0 + dut.i_rst.value = Immediate(1) for _ in range(10): await RisingEdge(dut.i_clk) @@ -158,6 +160,8 @@ async def test_clean_eviction(dut): cocotb.start_soon(handle_writeback(dut)) cocotb.start_soon(handle_bus_interface(dut)) + dut.i_cpu_we.value = 0 + dut.i_rst.value = Immediate(1) for _ in range(10): await RisingEdge(dut.i_clk) @@ -198,6 +202,8 @@ async def test_eviction(dut): cocotb.start_soon(handle_writeback(dut)) cocotb.start_soon(handle_bus_interface(dut)) + dut.i_cpu_we.value = 0 + dut.i_rst.value = Immediate(1) for _ in range(10): await RisingEdge(dut.i_clk) @@ -238,6 +244,8 @@ async def test_request_ownership(dut): cocotb.start_soon(handle_writeback(dut)) cocotb.start_soon(handle_bus_interface(dut)) + dut.i_cpu_we.value = 0 + dut.i_rst.value = Immediate(1) for _ in range(10): await RisingEdge(dut.i_clk) @@ -280,6 +288,7 @@ async def test_way_read_thrash(dut): cocotb.start_soon(handle_writeback(dut)) cocotb.start_soon(handle_bus_interface(dut)) + dut.i_cpu_we.value = 0 dut.i_rst.value = Immediate(1) for _ in range(10): await RisingEdge(dut.i_clk) @@ -297,3 +306,97 @@ async def test_way_read_thrash(dut): await RisingEdge(dut.i_clk) await Timer(1, "us") + + +@cocotb.test +async def test_write_waw(dut): + cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start()) + cocotb.start_soon(handle_cache_arrays(dut)) + cocotb.start_soon(handle_lru_arrays(dut)) + cocotb.start_soon(handle_writeback(dut)) + cocotb.start_soon(handle_bus_interface(dut)) + + dut.i_rst.value = Immediate(1) + for _ in range(10): + await RisingEdge(dut.i_clk) + dut.i_rst.value = 0 + + await RisingEdge(dut.o_rdy) + + INDEX = 7 + TAG = 0xabcd + + + # unused tag + dut.i_cpu_tag.value = 0xffff + dut.i_rdy.value = 1 + + dut.i_cpu_we.value = 1 + dut.i_cpu_index.value = INDEX + dut.i_cpu_offset.value = 1 + dut.i_cpu_data.value = 0xaa + await RisingEdge(dut.i_clk) + dut.i_cpu_tag.value = TAG + + while not dut.o_rdy.value: + await RisingEdge(dut.i_clk) + + dut.i_cpu_we.value = 1 + dut.i_cpu_index.value = INDEX + dut.i_cpu_offset.value = 2 + dut.i_cpu_data.value = 0x55 + await RisingEdge(dut.i_clk) + dut.i_cpu_tag.value = TAG + + while not dut.o_rdy.value: + await RisingEdge(dut.i_clk) + + dut.i_cpu_we.value = 0 + + await Timer(1, "us") + +@cocotb.test +async def test_write_raw(dut): + cocotb.start_soon(Clock(dut.i_clk, CLK_PERIOD, unit="ns").start()) + cocotb.start_soon(handle_cache_arrays(dut)) + cocotb.start_soon(handle_lru_arrays(dut)) + cocotb.start_soon(handle_writeback(dut)) + cocotb.start_soon(handle_bus_interface(dut)) + + dut.i_rst.value = Immediate(1) + for _ in range(10): + await RisingEdge(dut.i_clk) + dut.i_rst.value = 0 + + await RisingEdge(dut.o_rdy) + + INDEX = 7 + TAG = 0xabcd + + + # unused tag + dut.i_cpu_tag.value = 0xffff + dut.i_rdy.value = 1 + + dut.i_cpu_we.value = 1 + dut.i_cpu_index.value = INDEX + dut.i_cpu_offset.value = 1 + dut.i_cpu_data.value = 0x41 + await RisingEdge(dut.i_clk) + dut.i_cpu_tag.value = TAG + + while not dut.o_rdy.value: + await RisingEdge(dut.i_clk) + + dut.i_cpu_we.value = 0 + dut.i_cpu_index.value = INDEX + dut.i_cpu_offset.value = 1 + await RisingEdge(dut.i_clk) + dut.i_cpu_tag.value = TAG + + while not dut.o_rdy.value: + await RisingEdge(dut.i_clk) + + dut.i_cpu_we.value = 0 + + await Timer(1, "us") \ No newline at end of file diff --git a/src/application_wrapper/cache/application_wrapper_cache_miss_handler.sv b/src/application_wrapper/cache/application_wrapper_cache_miss_handler.sv index 72fcfdd..a9b749b 100644 --- a/src/application_wrapper/cache/application_wrapper_cache_miss_handler.sv +++ b/src/application_wrapper/cache/application_wrapper_cache_miss_handler.sv @@ -90,6 +90,7 @@ logic [INDEX_W-1:0] cpu_index_new, cpu_index_new_next; logic [OFFSET_W-1:0] cpu_offset_new, cpu_offset_new_next; logic [$clog2(NUM_WAYS)-1:0] cpu_way_new, cpu_way_new_next; logic [7:0] cpu_data_new, cpu_data_new_next; +logic cpu_we_new, cpu_we_new_next; logic previous_was_valid, previous_was_valid_next; @@ -117,6 +118,7 @@ always_ff @(posedge i_clk) begin cpu_tag_new <= cpu_tag_new_next; cpu_way_new <= cpu_way_new_next; cpu_data_new <= cpu_data_new_next; + cpu_we_new <= cpu_we_new_next; clear_index <= clear_index_next; cpu_we_d1 <= i_cpu_we; @@ -165,6 +167,7 @@ always_comb begin cpu_tag_new_next = cpu_tag_new; cpu_way_new_next = cpu_way_new; cpu_data_new_next = cpu_data_new; + cpu_we_new_next = cpu_we_new; read_req_addr_next = read_req_addr; @@ -284,6 +287,9 @@ always_comb begin end else begin o_rdy = '0; state_next = CHECK_VICTIM; + + cpu_data_new_next = cpu_i_data_d1; + cpu_we_new_next = cpu_we_d1; end end @@ -391,26 +397,33 @@ always_comb begin // This state can be put into WAIT_WRITEBACK_ACK and CHECK_VICTIM o_memory_addr = read_req_addr; o_memory_valid = '1; - // if the cache hit was a write, we should read unique, so we can be - // sure that we are given EXCLUSIVE and can set it to MODIFIED right away - o_memory_cmd = CACHE_CMD_READ; + + if (cpu_we_new) begin + o_memory_cmd = CACHE_CMD_READ_UNIQUE; + end else begin + o_memory_cmd = CACHE_CMD_READ; + end state_next = WAIT_MEMORY; end WAIT_MEMORY: begin - // need to handle if this was a write miss if (i_memory_done) begin o_write_valid = (1 << cpu_way_new); o_write_data = i_memory_data; o_write_index = cpu_index_new; - if (i_memory_resp == CACHE_RSP_SHARED) begin - o_write_meta = {MESI_SHARED, cpu_tag_new}; - end else if (i_memory_resp == CACHE_RSP_EXCLUSIVE) begin - o_write_meta = {MESI_EXCLUSIVE, cpu_tag_new}; + if (cpu_we_new) begin + o_write_data[cpu_offset_new*8 +: CPU_W] = cpu_data_new; + o_write_meta = {MESI_MODIFIED, cpu_tag_new}; + end else begin + if (i_memory_resp == CACHE_RSP_SHARED) begin + o_write_meta = {MESI_SHARED, cpu_tag_new}; + end else if (i_memory_resp == CACHE_RSP_EXCLUSIVE) begin + o_write_meta = {MESI_EXCLUSIVE, cpu_tag_new}; + end + o_cpu_data = i_memory_data[cpu_offset_new*8 +: CPU_W]; end o_rdy = '1; - o_cpu_data = i_memory_data[cpu_offset_new*8 +: CPU_W]; // update lru // start by copying the read data, then change the bits diff --git a/src/application_wrapper/cache/application_wrapper_cache_pkg.sv b/src/application_wrapper/cache/application_wrapper_cache_pkg.sv index c6ce66d..b823568 100644 --- a/src/application_wrapper/cache/application_wrapper_cache_pkg.sv +++ b/src/application_wrapper/cache/application_wrapper_cache_pkg.sv @@ -13,7 +13,7 @@ package application_wrapper_cache_pkg; typedef enum logic [2:0] { CACHE_CMD_NONE, CACHE_CMD_READ, - CAHCE_CMD_READ_UNIQUE, + CACHE_CMD_READ_UNIQUE, CACHE_CMD_WRITE, CACHE_CMD_CLEAN_UNIQUE, CACHE_CMD_EVICT