From 2338d4c720089ae13d74467275b2f879faf02426 Mon Sep 17 00:00:00 2001 From: Byron Lathi Date: Tue, 28 Apr 2026 22:17:42 -0700 Subject: [PATCH] Add some more tests --- sim/verilog6502_32bit_test.py | 81 ++++++++++++++++++++++++++++++++++- 1 file changed, 80 insertions(+), 1 deletion(-) diff --git a/sim/verilog6502_32bit_test.py b/sim/verilog6502_32bit_test.py index 375acca..86cb441 100644 --- a/sim/verilog6502_32bit_test.py +++ b/sim/verilog6502_32bit_test.py @@ -2,10 +2,13 @@ import cocotb from cocotb.handle import Immediate from cocotb.clock import Clock -from cocotb.triggers import Timer, RisingEdge +from cocotb.triggers import Timer, RisingEdge, FallingEdge from collections import defaultdict +import struct +import random + CLK_PERIOD = 5 memory = defaultdict(int) @@ -471,3 +474,79 @@ async def test_indirect_indexed(dut): ] await check_instruction_sequence(dut, expected_cpu_outputs) + +@cocotb.test +async def test_adc(dut): + cocotb.start_soon(Clock(dut.clk, CLK_PERIOD, unit="ns").start()) + cocotb.start_soon(handle_memory(dut)) + + write_dword(0xfffffff4, 0x200) + + + def zp_indirect(): + value = random.randint(0,255) + address = random.randint(0x300, 0xffffffff) + + address_le = struct.pack("