From 6c47ce12a5c27638f76e0cec6abe852cb5ea101e Mon Sep 17 00:00:00 2001
From: Byron Lathi <byron@byronlathi.com>
Date: Fri, 8 May 2026 22:07:13 -0700
Subject: [PATCH] Update assembly tests

---
 sim/asm_source/jsr_test.s         | 23 +++++++++++++-
 sim/asm_source/lda_test.s         | 53 +++++++++++++++++++++++++++++++
 sim/verilog6502_32bit_asm_test.py | 19 ++++++++---
 3 files changed, 89 insertions(+), 6 deletions(-)

diff --git a/sim/asm_source/jsr_test.s b/sim/asm_source/jsr_test.s
index 98d4ca1..ceb5b92 100644
--- a/sim/asm_source/jsr_test.s
+++ b/sim/asm_source/jsr_test.s
@@ -1,5 +1,9 @@
 .export vec_reset, vec_irq, vec_nmi
 
+.ZEROPAGE
+
+result: .res 1
+
 .segment "CODE"
 
 vec_nmi:
@@ -8,4 +12,21 @@ vec_irq:
 
 
 jsr_test:
-    bra jsr_test
\ No newline at end of file
+    lda #$ff
+    sta result
+    ldx #$ff
+    txs
+    jsr function_1
+    lda #$01
+    sta result
+    wai
+
+function_2:
+    pha
+    pla
+    rts
+
+function_1:
+    jsr function_2
+    rts
+
diff --git a/sim/asm_source/lda_test.s b/sim/asm_source/lda_test.s
index ebd994e..94faf1d 100644
--- a/sim/asm_source/lda_test.s
+++ b/sim/asm_source/lda_test.s
@@ -2,11 +2,15 @@
 
 .ZEROPAGE
 
+result: .res 1
+
 zp0: .res 1
 zp1: .res 4
 zp2: .res 8
 zp3: .res 4
 
+good_count: .res 1
+
 .CODE
 
 data1:  .byte 1
@@ -55,14 +59,63 @@ prepare_test:
     lda #.TOPBYTE(data5-2)
     sta zp3+3
 
+    stz good_count
+
 lda_test:
+@test1:
     lda zp0         ; data 1
+    cmp #$1
+    bne @test2
+    inc good_count
+
+@test2:
     lda (zp1)       ; data 2
+    cmp #$2
+    bne @test3
+    inc good_count
+
+@test3:
     lda data3       ; data 3
+    cmp #$3
+    bne @test4
+    inc good_count
+
+@test4:
     ldx #$4
     ldy #$2
     lda (zp2,x)     ; data 4
+    cmp #$4
+    bne @test5
+    inc good_count
+
+@test5:
     lda (zp3),y     ; data 5
+    cmp #$5
+    bne @test6
+    inc good_count
+
+@test6:
     lda data6,x     ; data 6
+    cmp #$6
+    bne @test7
+    inc good_count
+
+@test7:
     lda data7,y     ; data 7
+    cmp #$7
+    bne @done
+    inc good_count
+
+@done:
+    lda good_count
+    cmp #$7
+    bne @fail
+
+    lda #$1
+    sta result
+    wai
+
+@fail:
+    lda #$ff
+    sta result
     wai
\ No newline at end of file
diff --git a/sim/verilog6502_32bit_asm_test.py b/sim/verilog6502_32bit_asm_test.py
index 28bfaf7..f47a83d 100644
--- a/sim/verilog6502_32bit_asm_test.py
+++ b/sim/verilog6502_32bit_asm_test.py
@@ -2,7 +2,7 @@ import cocotb
 from cocotb.handle import Immediate
 
 from cocotb.clock import Clock
-from cocotb.triggers import Timer, RisingEdge, FallingEdge
+from cocotb.triggers import Timer, RisingEdge, FallingEdge, with_timeout
 
 from collections import defaultdict
 
@@ -39,8 +39,7 @@ async def handle_memory(dut):
         if we:
             memory[addr] = int(dut.DO.value)
 
-@cocotb.test
-async def test_lda(dut):
+async def do_asm_test(dut, filename):
     cocotb.start_soon(Clock(dut.clk, CLK_PERIOD, unit="ns").start())
     cocotb.start_soon(handle_memory(dut))
 
@@ -48,7 +47,7 @@ async def test_lda(dut):
 
     base_addr = 0xfffff000
 
-    with open(f"{path}/asm_source/lda_test", "rb") as file:
+    with open(f"{path}/asm_source/{filename}", "rb") as file:
         for i, val in enumerate(file.read()):
             write_byte(base_addr+i, val)
 
@@ -59,4 +58,14 @@ async def test_lda(dut):
         await RisingEdge(dut.clk)
     dut.reset.value = 0
 
-    await FallingEdge(dut.RDY_O)
\ No newline at end of file
+    await with_timeout(FallingEdge(dut.RDY_O), 10, "us")
+
+    assert memory[0] == 1
+
+@cocotb.test
+async def test_lda(dut):
+    await do_asm_test(dut, "lda_test")
+
+@cocotb.test
+async def test_jsr(dut):
+    await do_asm_test(dut, "jsr_test")
\ No newline at end of file