diff --git a/sim/verilog6502_32bit_test.py b/sim/verilog6502_32bit_test.py
index 66859bf..ee06ad9 100644
--- a/sim/verilog6502_32bit_test.py
+++ b/sim/verilog6502_32bit_test.py
@@ -534,7 +534,6 @@ async def test_jsr(dut):
         (0x1234567c, False, None),  # Updating PC before jump
         (0x00000208, False, None),  # WAI
         (0x00000209, False, None),  # second wai
-        (0x0000020a, False, None),  # third wai
     ]
 
     await check_instruction_sequence(dut, expected_cpu_outputs)
@@ -604,6 +603,48 @@ async def test_rti(dut):
 
     await check_instruction_sequence(dut, expected_cpu_outputs)
 
+@cocotb.test
+async def test_irq(dut):
+    cocotb.start_soon(Clock(dut.clk, CLK_PERIOD, unit="ns").start())
+    cocotb.start_soon(handle_memory(dut))
+
+    write_dword(0xfffffff4, 0x200)
+    write_dword(0xfffffffc, 0x300)
+
+    # @0x200
+    # cli
+    # wai
+    # wai
+    # 0x300
+    # rti
+
+    write_bytes(0x200, [0x58, 0xcb, 0xcb])
+    write_bytes(0x300, [0x40])
+
+    dut.RDY.value = Immediate(1)
+
+    dut.reset.value = Immediate(1)
+    for _ in range(10):
+        await RisingEdge(dut.clk)
+    dut.reset.value = 0
+
+    await FallingEdge(dut.RDY_O)
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+    dut.IRQ.value = 1
+
+    while True:
+        await RisingEdge(dut.clk)
+        if int(dut.state.value) == 0x08:
+            break
+
+    dut.IRQ.value = 0
+
+    await Timer(300, "ns")
+
+    assert int(dut.RDY_O.value) == 0
 
 @cocotb.test
 async def test_adc(dut):
diff --git a/src/cpu_65c02.v b/src/cpu_65c02.v
index e371654..7816a93 100644
--- a/src/cpu_65c02.v
+++ b/src/cpu_65c02.v
@@ -434,6 +434,8 @@ always @*
     case( state )
         DECODE:         if( (~I & IRQ) | NMI_edge ) begin
                             PC_inc = 0;
+                        end else if (IR == 8'b1100_1011) begin
+                            PC_inc = 0;
                         end else begin
                             PC_inc = 1;
                         end