bslathi19/verilog6502
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Byron Lathi
2026-04-18 18:50:18 -07:00
commit db61ca2d74
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requirements.txt Normal file
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peakrdl
rtl-manifest
cocotb
cocotb-bus
cocotbext-axi>=0.1.30
cocotbext-eth>=0.1.24
pytest
fpga-sim>=0.5.4
build_fpga
git+https://github.com/arnavsacheti/PeakRDL-BusDecoder.git
peakrdl-python-regmap>=0.0.5
taxi-peakrdl-extensions