Files
verilog6502/sim/embedded_wrapper/verilog6502_32bit_asm.yaml
2026-05-09 16:03:57 -07:00

9 lines
180 B
YAML

tests:
- name: "cpu_65c02"
toplevel: "cpu_65c02"
modules:
- "verilog6502_32bit_asm_test"
sources: "../sources.list"
waves: True
defines:
SIM: "hi"