Files
verilog6502/sim/verilog6502_wrapper.yaml
2026-04-18 18:50:18 -07:00

9 lines
198 B
YAML

tests:
- name: "verilog6502_wrapper"
toplevel: "verilog6502_wrapper_tb"
modules:
- "verilog6502_wrapper_test"
sources: "sources.list"
waves: True
defines:
SIM: "hi"