Files
verilog6502/sim/embedded_wrapper/asm_source/jsr_test.s
2026-05-09 16:03:57 -07:00

33 lines
304 B
ArmAsm

.export vec_reset, vec_irq, vec_nmi
.ZEROPAGE
result: .res 1
.segment "CODE"
vec_nmi:
vec_reset:
vec_irq:
jsr_test:
lda #$ff
sta result
ldx #$ff
txs
jsr function_1
lda #$01
sta result
wai
function_2:
pha
pla
rts
function_1:
jsr function_2
rts