Files
verilog6502/src/embedded_wrapper/regs/verilog6502_io_regs_pkg.sv
2026-05-09 16:03:57 -07:00

63 lines
1.8 KiB
Systemverilog

// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
// https://github.com/SystemRDL/PeakRDL-regblock
package verilog6502_io_regs_pkg;
localparam VERILOG6502_IO_REGS_DATA_WIDTH = 32;
localparam VERILOG6502_IO_REGS_MIN_ADDR_WIDTH = 12;
localparam VERILOG6502_IO_REGS_SIZE = 'h1000;
typedef struct {
logic value;
} verilog6502_io_regs__core_ctrl__reset__out_t;
typedef struct {
logic value;
} verilog6502_io_regs__core_ctrl__rdy__out_t;
typedef struct {
verilog6502_io_regs__core_ctrl__reset__out_t reset;
verilog6502_io_regs__core_ctrl__rdy__out_t rdy;
} verilog6502_io_regs__core_ctrl__out_t;
typedef struct {
logic value;
} verilog6502_io_regs__core_status__rdy_o__out_t;
typedef struct {
verilog6502_io_regs__core_status__rdy_o__out_t rdy_o;
} verilog6502_io_regs__core_status__out_t;
typedef struct {
logic [31:0] value;
} verilog6502_io_regs__nmi__nmi__out_t;
typedef struct {
verilog6502_io_regs__nmi__nmi__out_t nmi;
} verilog6502_io_regs__nmi__out_t;
typedef struct {
logic [31:0] value;
} verilog6502_io_regs__rst__reset__out_t;
typedef struct {
verilog6502_io_regs__rst__reset__out_t reset;
} verilog6502_io_regs__rst__out_t;
typedef struct {
logic [31:0] value;
} verilog6502_io_regs__brk__brk__out_t;
typedef struct {
verilog6502_io_regs__brk__brk__out_t brk;
} verilog6502_io_regs__brk__out_t;
typedef struct {
verilog6502_io_regs__core_ctrl__out_t core_ctrl;
verilog6502_io_regs__core_status__out_t core_status;
verilog6502_io_regs__nmi__out_t nmi;
verilog6502_io_regs__rst__out_t rst;
verilog6502_io_regs__brk__out_t brk;
} verilog6502_io_regs__out_t;
endpackage