Files
verilog6502/sim/asm_source/lda_test.s
2026-05-08 09:54:14 -07:00

68 lines
1.0 KiB
ArmAsm

.export vec_reset, vec_irq, vec_nmi
.ZEROPAGE
zp0: .res 1
zp1: .res 4
zp2: .res 8
zp3: .res 4
.CODE
data1: .byte 1
data2: .byte 2
data3: .byte 3
data4: .byte 4
data5: .byte 5
data6: .res 4
.byte 6
data7: .res 2
.byte 7
vec_nmi:
vec_reset:
vec_irq:
prepare_test:
lda data1
sta zp0
lda #.LOBYTE(data2)
sta zp1
lda #.HIBYTE(data2)
sta zp1+1
lda #.BANKBYTE(data2)
sta zp1+2
lda #.TOPBYTE(data2)
sta zp1+3
lda #.LOBYTE(data4)
sta zp2+4
lda #.HIBYTE(data4)
sta zp2+5
lda #.BANKBYTE(data4)
sta zp2+6
lda #.TOPBYTE(data4)
sta zp2+7
lda #.LOBYTE(data5-2)
sta zp3
lda #.HIBYTE(data5-2)
sta zp3+1
lda #.BANKBYTE(data5-2)
sta zp3+2
lda #.TOPBYTE(data5-2)
sta zp3+3
lda_test:
lda zp0 ; data 1
lda (zp1) ; data 2
lda data3 ; data 3
ldx #$4
ldy #$2
lda (zp2,x) ; data 4
lda (zp3),y ; data 5
lda data6,x ; data 6
lda data7,y ; data 7
wai