31 lines
755 B
Systemverilog
31 lines
755 B
Systemverilog
module application_wrapper_cache_lru #(
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// This should be NUM_WAYS - 1
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parameter LRU_W = 3,
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parameter NUM_SETS = 64,
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localparam INDEX_W = $clog2(NUM_SETS)
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) (
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input logic i_clk,
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input logic [INDEX_W-1:0] i_read_index,
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input logic i_read_valid,
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output logic [LRU_W-1:0] o_read_data,
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input logic [INDEX_W-1:0] i_write_index,
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input logic i_write_valid,
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input logic [LRU_W-1:0] i_write_data
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);
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logic [LRU_W-1:0] lru_array [NUM_SETS];
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always @(posedge i_clk) begin
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if (i_write_valid) begin
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lru_array[i_write_index] = i_write_data;
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end
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if (i_read_valid) begin
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o_read_data = lru_array[i_read_index];
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end
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end
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endmodule |