diff --git a/.gitignore b/.gitignore index 49616fa..0dbb4e9 100644 --- a/.gitignore +++ b/.gitignore @@ -6,4 +6,7 @@ __pycache__/ # Simulations -sim_build/ \ No newline at end of file +sim_build/ + +outflow/ +work*/ \ No newline at end of file diff --git a/.gitmodules b/.gitmodules index 8187f1b..e21be67 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,6 +1,9 @@ [submodule "src/common/crypto"] path = src/common/crypto url = ../../bslathi19/crypto.git -[submodule "src/common/taxi"] - path = src/common/taxi - url = ../../bslathi19/taxi.git +[submodule "src/common/fifo"] + path = src/common/fifo + url = https://github.com/olofk/fifo.git +[submodule "src/common/taxi-bsl"] + path = src/common/taxi-bsl + url = ../../bslathi19/taxi-bsl.git diff --git a/Ti375C529_devkit/.lock b/Ti375C529_devkit/.lock new file mode 100644 index 0000000..9518eff --- /dev/null +++ b/Ti375C529_devkit/.lock @@ -0,0 +1 @@ +4176154 diff --git a/Ti375C529_devkit/EfxSapphireHpSoc_bootloader/default_bootloader.hex b/Ti375C529_devkit/EfxSapphireHpSoc_bootloader/default_bootloader.hex new file mode 100644 index 0000000..85ba367 --- /dev/null +++ b/Ti375C529_devkit/EfxSapphireHpSoc_bootloader/default_bootloader.hex @@ -0,0 +1,50 @@ +:02000004F90001 +:1000000097110000938181AC23A00182732540F1F8 +:1000100015C503A5018275DD0F0020020F10000039 +:1000200083A7C181014581450146828723AEA18016 +:100030000F001001054523A0A182828013818192C7 +:1000400013850181938501811386C18163FAC500FF +:100050008322050023A0550011059105E3EAC5FEA2 +:100060001385C181938581826377B50023200500C4 +:0E0070001105E36DB5FEDD2A192001A0828086 +:10007E00B70701E81307E01098C7B70701E81D4757 +:10008E00D8C771A8B70603E8416791067D179C4251 +:10009E00F98FF5DF856793870780370703E81CC361 +:1000AE008280B70603E8416791067D179C42F98F5F +:1000BE00F5DF13070020B70703E898C3370703E8F7 +:1000CE0011071C43C183F5DFB70703E88843137597 +:1000DE00F50F8280B70603E8416791067D179C42B3 +:1000EE00F98FF5DF13650510B70703E888C3828023 +:1000FE00B7C7B0F8E11794439386A60F984333879A +:10010E00E640E35D07FEB70603E8416791067D17FB +:10011E00130600109C42F98FE39EC7FE82804111A8 +:10012E0006C622C426C2B70703E823A40700094760 +:10013E00B70703E898D39546B70703E8D4D3B707B4 +:10014E0003E898D71D47B70703E8D8D755371D3FA3 +:10015E00B70603E8416791067D179C42F98FF5DFDC +:10016E00856793870788370703E81CC31305B00A12 +:10017E009537093FB53FB7C7B0F8E11794431967F4 +:10018E001307871ABA9698433387E640E35D07FE56 +:10019E00B70603E8416791067D179C42F98FF5DF9C +:1001AE00856793870788370703E81CC31305F00993 +:1001BE001537C53DB7C7B0F8E11794434967130724 +:1001CE00874F2A84BA9698433387E640E35D07FE4D +:1001DE00553D393FB70603E8416791067D179C42AE +:1001EE00F98FF5DF856793870788370703E81CC308 +:1001FE009307D009130590026304F4001305900EC3 +:10020E00D13D4935F535B70603E8416791067D17AF +:10021E009C42F98FF5DF856793870788370703E8D8 +:10022E001CC32D45453D130500046D3501455D3557 +:10023E0001454D350145793D0564B70402009535FC +:10024E00A2872380A7000504E31B94FE253D0565C8 +:10025E00F9332244B24092448567410182874111AD +:10026E0022C44AC097070000938747061704000070 +:10027E001304C40506C626C233898740638B8700E4 +:10028E001359294081441C40850411048297E3ECE4 +:10029E0024FF9707000093876703170400001304D9 +:1002AE00E4023389874013592940638987008144CA +:1002BE001C40850411048297E3EC24FFB2402244D3 +:0802CE009244024941018280C3 +:0C02D6000000000000000000000000001C +:04000005F9000000FE +:00000001FF diff --git a/Ti375C529_devkit/Ti375C529_devkit.isf b/Ti375C529_devkit/Ti375C529_devkit.isf new file mode 100644 index 0000000..f47d39d --- /dev/null +++ b/Ti375C529_devkit/Ti375C529_devkit.isf @@ -0,0 +1,285 @@ +# Efinity Interface Configuration +# Version: 2026.1.132 +# Date: 2026-08-08 20:48 +# +# Copyright (C) 2013 - 2026 Efinix Inc. All rights reserved. +# +# Device: Ti375C529 +# Package: 529-ball FBGA (final) +# Project: Ti375C529_devkit +# Configuration mode: active (x1) +# Timing Model: C4 (final) + + +# Device setting +design.set_device_property("2A","DYNAMIC_VOLTAGE","0","IOBANK") +design.set_mode_sel_name("2A","2A_MODE_SEL","2A") +design.set_device_property("2A","VOLTAGE","1.8","IOBANK") +design.set_device_property("2B","DYNAMIC_VOLTAGE","0","IOBANK") +design.set_mode_sel_name("2B","2B_MODE_SEL","2B") +design.set_device_property("2B","VOLTAGE","1.8","IOBANK") +design.set_device_property("2C","DYNAMIC_VOLTAGE","0","IOBANK") +design.set_mode_sel_name("2C","2C_MODE_SEL","2C") +design.set_device_property("2C","VOLTAGE","1.8","IOBANK") +design.set_device_property("2D","DYNAMIC_VOLTAGE","0","IOBANK") +design.set_mode_sel_name("2D","2D_MODE_SEL","2D") +design.set_device_property("2D","VOLTAGE","1.8","IOBANK") +design.set_device_property("2E","DYNAMIC_VOLTAGE","0","IOBANK") +design.set_mode_sel_name("2E","2E_MODE_SEL","2E") +design.set_device_property("2E","VOLTAGE","1.8","IOBANK") +design.set_device_property("4A_4B","DYNAMIC_VOLTAGE","0","IOBANK") +design.set_mode_sel_name("4A_4B","4A_4B_MODE_SEL","4A_4B") +design.set_device_property("4A_4B","VOLTAGE","1.8","IOBANK") +design.set_device_property("4C","DYNAMIC_VOLTAGE","0","IOBANK") +design.set_mode_sel_name("4C","4C_MODE_SEL","4C") +design.set_device_property("4C","VOLTAGE","1.8","IOBANK") +design.set_device_property("4D","DYNAMIC_VOLTAGE","0","IOBANK") +design.set_mode_sel_name("4D","4D_MODE_SEL","4D") +design.set_device_property("4D","VOLTAGE","1.8","IOBANK") +design.set_device_property("BL2_BL3","DYNAMIC_VOLTAGE","0","IOBANK") +design.set_mode_sel_name("BL2_BL3","BL2_BL3_MODE_SEL","BL2_BL3") +design.set_device_property("BL2_BL3","VOLTAGE","3.3","IOBANK") +design.set_device_property("BR0","DYNAMIC_VOLTAGE","0","IOBANK") +design.set_mode_sel_name("BR0","BR0_MODE_SEL","BR0") +design.set_device_property("BR0","VOLTAGE","3.3","IOBANK") +design.set_device_property("BR3_BR4","DYNAMIC_VOLTAGE","0","IOBANK") +design.set_mode_sel_name("BR3_BR4","BR3_BR4_MODE_SEL","BR3_BR4") +design.set_device_property("BR3_BR4","VOLTAGE","3.3","IOBANK") +design.set_device_property("TL1_TL5","DYNAMIC_VOLTAGE","0","IOBANK") +design.set_mode_sel_name("TL1_TL5","TL1_TL5_MODE_SEL","TL1_TL5") +design.set_device_property("TL1_TL5","VOLTAGE","3.3","IOBANK") +design.set_device_property("TR0","DYNAMIC_VOLTAGE","0","IOBANK") +design.set_mode_sel_name("TR0","TR0_MODE_SEL","TR0") +design.set_device_property("TR0","VOLTAGE","3.3","IOBANK") +design.set_device_property("TR1","DYNAMIC_VOLTAGE","0","IOBANK") +design.set_mode_sel_name("TR1","TR1_MODE_SEL","TR1") +design.set_device_property("TR1","VOLTAGE","3.3","IOBANK") +design.set_device_property("TR2","DYNAMIC_VOLTAGE","0","IOBANK") +design.set_mode_sel_name("TR2","TR2_MODE_SEL","TR2") +design.set_device_property("TR2","VOLTAGE","3.3","IOBANK") +design.set_device_property("seu","ENA_DETECT","0","SEU") +design.set_device_property("cfg","CBSEL_PIN","cfg_CBSEL","RU") +design.set_device_property("cfg","CLK_PIN","","RU") +design.set_device_property("cfg","CONFIG_PIN","cfg_CONFIG","RU") +design.set_device_property("cfg","ENA_PIN","cfg_ENA","RU") +design.set_device_property("cfg","ERROR_PIN","cfg_ERROR","RU") +design.set_device_property("cfg","INVERT_CLK_EN","0","RU") +design.set_device_property("cfg","RECONFIG_EN","0","RU") +design.set_device_property("cfg","REMOTE_UPDATE_RETRIES","3","RU") +design.set_device_property("Bottom","CORE0_PIN","","CLKMUX") +design.set_device_property("Bottom","CORE1_PIN","","CLKMUX") +design.set_device_property("Bottom","CORE2_PIN","","CLKMUX") +design.set_device_property("Bottom","CORE3_PIN","","CLKMUX") +design.set_device_property("Bottom","DYN_MUX0_EN","0","CLKMUX") +design.set_device_property("Bottom","DYN_MUX7_EN","0","CLKMUX") +design.set_device_property("Left","CORE0_PIN","","CLKMUX") +design.set_device_property("Left","CORE1_PIN","","CLKMUX") +design.set_device_property("Left","CORE2_PIN","","CLKMUX") +design.set_device_property("Left","CORE3_PIN","","CLKMUX") +design.set_device_property("Left","DYN_MUX0_EN","0","CLKMUX") +design.set_device_property("Left","DYN_MUX7_EN","0","CLKMUX") +design.set_device_property("Right","CORE0_PIN","","CLKMUX") +design.set_device_property("Right","CORE1_PIN","","CLKMUX") +design.set_device_property("Right","CORE2_PIN","","CLKMUX") +design.set_device_property("Right","CORE3_PIN","","CLKMUX") +design.set_device_property("Right","DYN_MUX0_EN","0","CLKMUX") +design.set_device_property("Right","DYN_MUX7_EN","0","CLKMUX") +design.set_device_property("Top","CORE0_PIN","","CLKMUX") +design.set_device_property("Top","CORE1_PIN","","CLKMUX") +design.set_device_property("Top","CORE2_PIN","","CLKMUX") +design.set_device_property("Top","CORE3_PIN","","CLKMUX") +design.set_device_property("Top","DYN_MUX0_EN","0","CLKMUX") +design.set_device_property("Top","DYN_MUX7_EN","0","CLKMUX") +design.set_gpio_unused_state("INPUT_WEAK_PULLUP") + +# Create instance +design.create_block("soc_jtag_inst1","JTAG") +design.create_block("qcrv32_inst1","SOC") + +# Set property, non-defaults +design.set_property("soc_jtag_inst1","NAME","soc_jtag_inst1","JTAG") +design.set_property("soc_jtag_inst1","RESOURCE","JTAG_USER1","JTAG") +design.set_property("soc_jtag_inst1","CAPTURE","ut_jtagCtrl_capture","JTAG") +design.set_property("soc_jtag_inst1","DRCK","","JTAG") +design.set_property("soc_jtag_inst1","RESET","ut_jtagCtrl_reset","JTAG") +design.set_property("soc_jtag_inst1","RUNTEST","","JTAG") +design.set_property("soc_jtag_inst1","SEL","ut_jtagCtrl_enable","JTAG") +design.set_property("soc_jtag_inst1","SHIFT","ut_jtagCtrl_shift","JTAG") +design.set_property("soc_jtag_inst1","TCK","jtagCtrl_tck","JTAG") +design.set_property("soc_jtag_inst1","TDI","ut_jtagCtrl_tdi","JTAG") +design.set_property("soc_jtag_inst1","TMS","","JTAG") +design.set_property("soc_jtag_inst1","UPDATE","ut_jtagCtrl_update","JTAG") +design.set_property("soc_jtag_inst1","TDO","ut_jtagCtrl_tdo","JTAG") +design.set_property("qcrv32_inst1","AXIAINTERRUPT_PIN","axiAInterrupt","SOC") +design.set_property("qcrv32_inst1","AXIA_ARADDR_PIN","axiA_araddr","SOC") +design.set_property("qcrv32_inst1","AXIA_ARBURST_PIN","axiA_arburst","SOC") +design.set_property("qcrv32_inst1","AXIA_ARCACHE_PIN","axiA_arcache","SOC") +design.set_property("qcrv32_inst1","AXIA_ARLEN_PIN","axiA_arlen","SOC") +design.set_property("qcrv32_inst1","AXIA_ARLOCK_PIN","axiA_arlock","SOC") +design.set_property("qcrv32_inst1","AXIA_ARPROT_PIN","axiA_arprot","SOC") +design.set_property("qcrv32_inst1","AXIA_ARQOS_PIN","axiA_arqos","SOC") +design.set_property("qcrv32_inst1","AXIA_ARREADY_PIN","axiA_arready","SOC") +design.set_property("qcrv32_inst1","AXIA_ARREGION_PIN","axiA_arregion","SOC") +design.set_property("qcrv32_inst1","AXIA_ARSIZE_PIN","axiA_arsize","SOC") +design.set_property("qcrv32_inst1","AXIA_ARVALID_PIN","axiA_arvalid","SOC") +design.set_property("qcrv32_inst1","AXIA_AWADDR_PIN","axiA_awaddr","SOC") +design.set_property("qcrv32_inst1","AXIA_AWBURST_PIN","axiA_awburst","SOC") +design.set_property("qcrv32_inst1","AXIA_AWCACHE_PIN","axiA_awcache","SOC") +design.set_property("qcrv32_inst1","AXIA_AWLEN_PIN","axiA_awlen","SOC") +design.set_property("qcrv32_inst1","AXIA_AWLOCK_PIN","axiA_awlock","SOC") +design.set_property("qcrv32_inst1","AXIA_AWPROT_PIN","axiA_awprot","SOC") +design.set_property("qcrv32_inst1","AXIA_AWQOS_PIN","axiA_awqos","SOC") +design.set_property("qcrv32_inst1","AXIA_AWREADY_PIN","axiA_awready","SOC") +design.set_property("qcrv32_inst1","AXIA_AWREGION_PIN","axiA_awregion","SOC") +design.set_property("qcrv32_inst1","AXIA_AWSIZE_PIN","axiA_awsize","SOC") +design.set_property("qcrv32_inst1","AXIA_AWVALID_PIN","axiA_awvalid","SOC") +design.set_property("qcrv32_inst1","AXIA_BREADY_PIN","axiA_bready","SOC") +design.set_property("qcrv32_inst1","AXIA_BRESP_PIN","axiA_bresp","SOC") +design.set_property("qcrv32_inst1","AXIA_BVALID_PIN","axiA_bvalid","SOC") +design.set_property("qcrv32_inst1","AXIA_RDATA_PIN","axiA_rdata","SOC") +design.set_property("qcrv32_inst1","AXIA_RLAST_PIN","axiA_rlast","SOC") +design.set_property("qcrv32_inst1","AXIA_RREADY_PIN","axiA_rready","SOC") +design.set_property("qcrv32_inst1","AXIA_RRESP_PIN","axiA_rresp","SOC") +design.set_property("qcrv32_inst1","AXIA_RVALID_PIN","axiA_rvalid","SOC") +design.set_property("qcrv32_inst1","AXIA_WDATA_PIN","axiA_wdata","SOC") +design.set_property("qcrv32_inst1","AXIA_WLAST_PIN","axiA_wlast","SOC") +design.set_property("qcrv32_inst1","AXIA_WREADY_PIN","axiA_wready","SOC") +design.set_property("qcrv32_inst1","AXIA_WSTRB_PIN","axiA_wstrb","SOC") +design.set_property("qcrv32_inst1","AXIA_WVALID_PIN","axiA_wvalid","SOC") +design.set_property("qcrv32_inst1","AXI_MASTER_EN","1","SOC") +design.set_property("qcrv32_inst1","AXI_SLAVE_EN","1","SOC") +design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_CMD_READY_PIN","cpu0_customInstruction_cmd_ready","SOC") +design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_CMD_VALID_PIN","cpu0_customInstruction_cmd_valid","SOC") +design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_FUNCTION_ID_PIN","cpu0_customInstruction_function_id","SOC") +design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_INPUTS_0_PIN","cpu0_customInstruction_inputs_0","SOC") +design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_INPUTS_1_PIN","cpu0_customInstruction_inputs_1","SOC") +design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_OUTPUTS_0_PIN","cpu0_customInstruction_outputs_0","SOC") +design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_RSP_READY_PIN","cpu0_customInstruction_rsp_ready","SOC") +design.set_property("qcrv32_inst1","CPU0_CUSTOMINSTRUCTION_RSP_VALID_PIN","cpu0_customInstruction_rsp_valid","SOC") +design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_CMD_READY_PIN","cpu1_customInstruction_cmd_ready","SOC") +design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_CMD_VALID_PIN","cpu1_customInstruction_cmd_valid","SOC") +design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_FUNCTION_ID_PIN","cpu1_customInstruction_function_id","SOC") +design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_INPUTS_0_PIN","cpu1_customInstruction_inputs_0","SOC") +design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_INPUTS_1_PIN","cpu1_customInstruction_inputs_1","SOC") +design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_OUTPUTS_0_PIN","cpu1_customInstruction_outputs_0","SOC") +design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_RSP_READY_PIN","cpu1_customInstruction_rsp_ready","SOC") +design.set_property("qcrv32_inst1","CPU1_CUSTOMINSTRUCTION_RSP_VALID_PIN","cpu1_customInstruction_rsp_valid","SOC") +design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_CMD_READY_PIN","cpu2_customInstruction_cmd_ready","SOC") +design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_CMD_VALID_PIN","cpu2_customInstruction_cmd_valid","SOC") +design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_FUNCTION_ID_PIN","cpu2_customInstruction_function_id","SOC") +design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_INPUTS_0_PIN","cpu2_customInstruction_inputs_0","SOC") +design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_INPUTS_1_PIN","cpu2_customInstruction_inputs_1","SOC") +design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_OUTPUTS_0_PIN","cpu2_customInstruction_outputs_0","SOC") +design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_RSP_READY_PIN","cpu2_customInstruction_rsp_ready","SOC") +design.set_property("qcrv32_inst1","CPU2_CUSTOMINSTRUCTION_RSP_VALID_PIN","cpu2_customInstruction_rsp_valid","SOC") +design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_CMD_READY_PIN","cpu3_customInstruction_cmd_ready","SOC") +design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_CMD_VALID_PIN","cpu3_customInstruction_cmd_valid","SOC") +design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_FUNCTION_ID_PIN","cpu3_customInstruction_function_id","SOC") +design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_INPUTS_0_PIN","cpu3_customInstruction_inputs_0","SOC") +design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_INPUTS_1_PIN","cpu3_customInstruction_inputs_1","SOC") +design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_OUTPUTS_0_PIN","cpu3_customInstruction_outputs_0","SOC") +design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_RSP_READY_PIN","cpu3_customInstruction_rsp_ready","SOC") +design.set_property("qcrv32_inst1","CPU3_CUSTOMINSTRUCTION_RSP_VALID_PIN","cpu3_customInstruction_rsp_valid","SOC") +design.set_property("qcrv32_inst1","CUSTOM_INSTRUCTION_0_EN","1","SOC") +design.set_property("qcrv32_inst1","CUSTOM_INSTRUCTION_1_EN","1","SOC") +design.set_property("qcrv32_inst1","CUSTOM_INSTRUCTION_2_EN","1","SOC") +design.set_property("qcrv32_inst1","CUSTOM_INSTRUCTION_3_EN","1","SOC") +design.set_property("qcrv32_inst1","IO_ASYNCRESET_PIN","io_asyncReset","SOC") +design.set_property("qcrv32_inst1","IO_CFUCLK_INVERT_EN","0","SOC") +design.set_property("qcrv32_inst1","IO_CFUCLK_PIN","io_cfuClk","SOC") +design.set_property("qcrv32_inst1","IO_CFURESET_PIN","io_cfuReset","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_ADDR_PIN","io_ddrMasters_0_ar_payload_addr","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_BURST_PIN","io_ddrMasters_0_ar_payload_burst","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_CACHE_PIN","io_ddrMasters_0_ar_payload_cache","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_ID_PIN","io_ddrMasters_0_ar_payload_id","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_LEN_PIN","io_ddrMasters_0_ar_payload_len","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_LOCK_PIN","io_ddrMasters_0_ar_payload_lock","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_PROT_PIN","io_ddrMasters_0_ar_payload_prot","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_QOS_PIN","io_ddrMasters_0_ar_payload_qos","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_REGION_PIN","io_ddrMasters_0_ar_payload_region","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_PAYLOAD_SIZE_PIN","io_ddrMasters_0_ar_payload_size","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_READY_PIN","io_ddrMasters_0_ar_ready","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AR_VALID_PIN","io_ddrMasters_0_ar_valid","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_ADDR_PIN","io_ddrMasters_0_aw_payload_addr","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_ALLSTRB_PIN","io_ddrMasters_0_aw_payload_allStrb","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_BURST_PIN","io_ddrMasters_0_aw_payload_burst","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_CACHE_PIN","io_ddrMasters_0_aw_payload_cache","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_ID_PIN","io_ddrMasters_0_aw_payload_id","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_LEN_PIN","io_ddrMasters_0_aw_payload_len","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_LOCK_PIN","io_ddrMasters_0_aw_payload_lock","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_PROT_PIN","io_ddrMasters_0_aw_payload_prot","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_QOS_PIN","io_ddrMasters_0_aw_payload_qos","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_REGION_PIN","io_ddrMasters_0_aw_payload_region","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_PAYLOAD_SIZE_PIN","io_ddrMasters_0_aw_payload_size","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_READY_PIN","io_ddrMasters_0_aw_ready","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_AW_VALID_PIN","io_ddrMasters_0_aw_valid","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_B_PAYLOAD_ID_PIN","io_ddrMasters_0_b_payload_id","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_B_PAYLOAD_RESP_PIN","io_ddrMasters_0_b_payload_resp","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_B_READY_PIN","io_ddrMasters_0_b_ready","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_B_VALID_PIN","io_ddrMasters_0_b_valid","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_CLK_INVERT_EN","0","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_CLK_PIN","io_ddrMasters_0_clk","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_RESET_PIN","io_ddrMasters_0_reset","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_R_PAYLOAD_DATA_PIN","io_ddrMasters_0_r_payload_data","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_R_PAYLOAD_ID_PIN","io_ddrMasters_0_r_payload_id","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_R_PAYLOAD_LAST_PIN","io_ddrMasters_0_r_payload_last","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_R_PAYLOAD_RESP_PIN","io_ddrMasters_0_r_payload_resp","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_R_READY_PIN","io_ddrMasters_0_r_ready","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_R_VALID_PIN","io_ddrMasters_0_r_valid","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_W_PAYLOAD_DATA_PIN","io_ddrMasters_0_w_payload_data","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_W_PAYLOAD_LAST_PIN","io_ddrMasters_0_w_payload_last","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_W_PAYLOAD_STRB_PIN","io_ddrMasters_0_w_payload_strb","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_W_READY_PIN","io_ddrMasters_0_w_ready","SOC") +design.set_property("qcrv32_inst1","IO_DDRMASTERS_0_W_VALID_PIN","io_ddrMasters_0_w_valid","SOC") +design.set_property("qcrv32_inst1","IO_JTAG_TCK_INVERT_EN","0","SOC") +design.set_property("qcrv32_inst1","IO_JTAG_TCK_PIN","","SOC") +design.set_property("qcrv32_inst1","IO_JTAG_TDI_PIN","","SOC") +design.set_property("qcrv32_inst1","IO_JTAG_TDO_PIN","","SOC") +design.set_property("qcrv32_inst1","IO_JTAG_TMS_PIN","","SOC") +design.set_property("qcrv32_inst1","IO_PERIPHERALCLK_INVERT_EN","0","SOC") +design.set_property("qcrv32_inst1","IO_PERIPHERALCLK_PIN","io_peripheralClk","SOC") +design.set_property("qcrv32_inst1","IO_PERIPHERALRESET_PIN","io_peripheralReset","SOC") +design.set_property("qcrv32_inst1","IO_SYSTEMRESET_PIN","io_systemReset","SOC") +design.set_property("qcrv32_inst1","JTAGCTRL_CAPTURE_PIN","jtagCtrl_capture","SOC") +design.set_property("qcrv32_inst1","JTAGCTRL_ENABLE_PIN","jtagCtrl_enable","SOC") +design.set_property("qcrv32_inst1","JTAGCTRL_RESET_PIN","jtagCtrl_reset","SOC") +design.set_property("qcrv32_inst1","JTAGCTRL_SHIFT_PIN","jtagCtrl_shift","SOC") +design.set_property("qcrv32_inst1","JTAGCTRL_TCK_INVERT_EN","0","SOC") +design.set_property("qcrv32_inst1","JTAGCTRL_TCK_PIN","jtagCtrl_tck","SOC") +design.set_property("qcrv32_inst1","JTAGCTRL_TDI_PIN","jtagCtrl_tdi","SOC") +design.set_property("qcrv32_inst1","JTAGCTRL_TDO_PIN","jtagCtrl_tdo","SOC") +design.set_property("qcrv32_inst1","JTAGCTRL_UPDATE_PIN","jtagCtrl_update","SOC") +design.set_property("qcrv32_inst1","JTAG_TYPE","FPGA","SOC") +design.set_property("qcrv32_inst1","MEM_CLK_SOURCE","Clock 0","SOC") +design.set_property("qcrv32_inst1","OCR_FILE_PATH","EfxSapphireHpSoc_bootloader/default_bootloader.hex","SOC") +design.set_property("qcrv32_inst1","PIPELINE_SOC_AXI_MEM_INTERFACE_EN","0","SOC") +design.set_property("qcrv32_inst1","SYS_CLK_SOURCE","Clock 0","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTA_PIN","userInterruptA","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTB_PIN","userInterruptB","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTC_PIN","userInterruptC","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTD_PIN","userInterruptD","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTE_PIN","userInterruptE","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTF_PIN","userInterruptF","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTG_PIN","userInterruptG","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTH_PIN","userInterruptH","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTI_PIN","userInterruptI","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTJ_PIN","","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTK_PIN","","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTL_PIN","","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTM_PIN","","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTN_PIN","","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTO_PIN","","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTP_PIN","","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTQ_PIN","","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTR_PIN","","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTS_PIN","","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTT_PIN","","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTU_PIN","","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTV_PIN","","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTW_PIN","","SOC") +design.set_property("qcrv32_inst1","USERINTERRUPTX_PIN","","SOC") +design.set_property("qcrv32_inst1","WRITEBUFFER_SOC_AXI_INTERFACE_EN","0","SOC") + +# Set resource assignment +design.assign_resource("soc_jtag_inst1","JTAG_USER1","JTAG") +design.assign_resource("qcrv32_inst1","SOC_0","SOC") diff --git a/Ti375C529_devkit/Ti375C529_devkit.peri.xml b/Ti375C529_devkit/Ti375C529_devkit.peri.xml new file mode 100644 index 0000000..7e3cac2 --- /dev/null +++ b/Ti375C529_devkit/Ti375C529_devkit.peri.xml @@ -0,0 +1,853 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Ti375C529_devkit/Ti375C529_devkit.xml b/Ti375C529_devkit/Ti375C529_devkit.xml new file mode 100644 index 0000000..287b280 --- /dev/null +++ b/Ti375C529_devkit/Ti375C529_devkit.xml @@ -0,0 +1,156 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Ti375C529_devkit/constraints.sdc b/Ti375C529_devkit/constraints.sdc new file mode 100644 index 0000000..7e3647b --- /dev/null +++ b/Ti375C529_devkit/constraints.sdc @@ -0,0 +1,369 @@ + +# Auto-generated by Interface Designer +# +# WARNING: Any manual changes made to this file will be lost when generating constraints. + +# Efinity Interface Designer SDC +# Version: 2024.M.98 +# Date: 2024-04-13 10:16 + +# Copyright (C) 2013 - 2024 Efinix Inc. All rights reserved. + +# Device: Ti375C529 +# Project: Ti375C529_devkit +# Timing Model: C4 (preliminary) +# NOTE: The timing data is not final + +# PLL Constraints +################# +create_clock -period 10.0000 io_sysFbClk +create_clock -period 5.0000 io_peripheralClk +create_clock -period 4.0000 io_ddrMasters_0_clk +create_clock -period 8.0000 io_cfuClk +create_clock -period 10.0000 sd_base_clk +create_clock -period 8.0000 rgmii_rxc +create_clock -waveform {2.0000 6.0000} -period 8.0000 io_tseClk_90 +create_clock -period 8.0000 io_tseClk + +set_clock_groups -exclusive -group {rgmii_rxc io_tseClk_90 io_tseClk} -group {sd_base_clk} -group {io_cfuClk} -group {io_peripheralClk} -group {io_ddrMasters_0_clk} + +# GPIO Constraints +#################### +set_output_delay -clock sd_base_clk -reference_pin [get_ports {sd_base_clk~CLKOUT~347~2}] -max 0.079 [get_ports {sd_clk_hi}] +set_output_delay -clock sd_base_clk -reference_pin [get_ports {sd_base_clk~CLKOUT~347~2}] -min -0.045 [get_ports {sd_clk_hi}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {io_gpio_sw_n}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {io_gpio_sw_n}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {system_uart_0_io_rxd}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {system_uart_0_io_rxd}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_uart_0_io_txd}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_uart_0_io_txd}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_read[1]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_read[1]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_write[1]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_write[1]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_writeEnable[1]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_writeEnable[1]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_read[2]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_read[2]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_write[2]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_write[2]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_writeEnable[2]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_writeEnable[2]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {system_i2c_0_io_scl_read}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {system_i2c_0_io_scl_read}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_i2c_0_io_scl_write}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_i2c_0_io_scl_write}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_i2c_0_io_scl_writeEnable}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_i2c_0_io_scl_writeEnable}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {system_i2c_0_io_sda_read}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {system_i2c_0_io_sda_read}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_i2c_0_io_sda_write}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_i2c_0_io_sda_write}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_i2c_0_io_sda_writeEnable}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_i2c_0_io_sda_writeEnable}] + +# JTAG Constraints +#################### +create_clock -period 100 [get_ports {jtagCtrl_tck}] +set_output_delay -clock jtagCtrl_tck -max 0.117 [get_ports {ut_jtagCtrl_tdo}] +set_output_delay -clock jtagCtrl_tck -min -0.075 [get_ports {ut_jtagCtrl_tdo}] +set_input_delay -clock_fall -clock jtagCtrl_tck -max 0.280 [get_ports {ut_jtagCtrl_capture}] +set_input_delay -clock_fall -clock jtagCtrl_tck -min 0.187 [get_ports {ut_jtagCtrl_capture}] +set_input_delay -clock_fall -clock jtagCtrl_tck -max 0.280 [get_ports {ut_jtagCtrl_reset}] +set_input_delay -clock_fall -clock jtagCtrl_tck -min 0.187 [get_ports {ut_jtagCtrl_reset}] +set_input_delay -clock_fall -clock jtagCtrl_tck -max 0.243 [get_ports {ut_jtagCtrl_enable}] +set_input_delay -clock_fall -clock jtagCtrl_tck -min 0.162 [get_ports {ut_jtagCtrl_enable}] +set_input_delay -clock_fall -clock jtagCtrl_tck -max 0.280 [get_ports {ut_jtagCtrl_update}] +set_input_delay -clock_fall -clock jtagCtrl_tck -min 0.187 [get_ports {ut_jtagCtrl_update}] +set_input_delay -clock_fall -clock jtagCtrl_tck -max 0.337 [get_ports {ut_jtagCtrl_shift}] +set_input_delay -clock_fall -clock jtagCtrl_tck -min 0.225 [get_ports {ut_jtagCtrl_shift}] +# JTAG Constraints (extra... not used by current Efinity debug tools) +# Create separate clock groups for JTAG clocks. Remove DRCK clock from the list below if it is not defined. +# set_clock_groups -asynchronous -group {jtagCtrl_tck} + +# HSIO GPIO Constraints +######################### +set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~391~964}] -max 0.414 [get_ports {rgmii_rx_ctl_LO rgmii_rx_ctl_HI}] +set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~391~964}] -min 0.276 [get_ports {rgmii_rx_ctl_LO rgmii_rx_ctl_HI}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {rgmii_rxc_phy}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {rgmii_rxc_phy}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {rgmii_rxc_slow}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {rgmii_rxc_slow}] +set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~395~964}] -max 0.414 [get_ports {rgmii_rxd_LO[0] rgmii_rxd_HI[0]}] +set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~395~964}] -min 0.276 [get_ports {rgmii_rxd_LO[0] rgmii_rxd_HI[0]}] +set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~397~964}] -max 0.414 [get_ports {rgmii_rxd_LO[1] rgmii_rxd_HI[1]}] +set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~397~964}] -min 0.276 [get_ports {rgmii_rxd_LO[1] rgmii_rxd_HI[1]}] +set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~408~964}] -max 0.414 [get_ports {rgmii_rxd_LO[2] rgmii_rxd_HI[2]}] +set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~408~964}] -min 0.276 [get_ports {rgmii_rxd_LO[2] rgmii_rxd_HI[2]}] +set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~412~963}] -max 0.414 [get_ports {rgmii_rxd_LO[3] rgmii_rxd_HI[3]}] +set_input_delay -clock rgmii_rxc -reference_pin [get_ports {rgmii_rxc~CLKOUT~412~963}] -min 0.276 [get_ports {rgmii_rxd_LO[3] rgmii_rxd_HI[3]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {sd_cd_n}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {sd_cd_n}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {io_ddrMasters_memCheck_pass}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {io_ddrMasters_memCheck_pass}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {phy_mdc}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {phy_mdc}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~352~963}] -max 0.263 [get_ports {rgmii_tx_ctl_LO rgmii_tx_ctl_HI}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~352~963}] -min -0.140 [get_ports {rgmii_tx_ctl_LO rgmii_tx_ctl_HI}] +set_output_delay -clock io_tseClk_90 -reference_pin [get_ports {io_tseClk_90~CLKOUT~359~964}] -max 0.263 [get_ports {rgmii_txc_LO rgmii_txc_HI}] +set_output_delay -clock io_tseClk_90 -reference_pin [get_ports {io_tseClk_90~CLKOUT~359~964}] -min -0.140 [get_ports {rgmii_txc_LO rgmii_txc_HI}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~358~963}] -max 0.263 [get_ports {rgmii_txd_LO[0] rgmii_txd_HI[0]}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~358~963}] -min -0.140 [get_ports {rgmii_txd_LO[0] rgmii_txd_HI[0]}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~364~963}] -max 0.263 [get_ports {rgmii_txd_LO[1] rgmii_txd_HI[1]}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~364~963}] -min -0.140 [get_ports {rgmii_txd_LO[1] rgmii_txd_HI[1]}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~365~964}] -max 0.263 [get_ports {rgmii_txd_LO[2] rgmii_txd_HI[2]}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~365~964}] -min -0.140 [get_ports {rgmii_txd_LO[2] rgmii_txd_HI[2]}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~376~964}] -max 0.263 [get_ports {rgmii_txd_LO[3] rgmii_txd_HI[3]}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~376~964}] -min -0.140 [get_ports {rgmii_txd_LO[3] rgmii_txd_HI[3]}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~418~2}] -max 0.263 [get_ports {system_spi_0_io_sclk_write}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~418~2}] -min -0.140 [get_ports {system_spi_0_io_sclk_write}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~407~2}] -max 0.263 [get_ports {system_spi_0_io_ss[0]}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~407~2}] -min -0.140 [get_ports {system_spi_0_io_ss[0]}] +set_input_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~381~964}] -max 0.414 [get_ports {phy_mdi}] +set_input_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~381~964}] -min 0.276 [get_ports {phy_mdi}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~384~964}] -max 0.263 [get_ports {phy_mdo}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~384~964}] -min -0.140 [get_ports {phy_mdo}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~384~964}] -max 0.263 [get_ports {phy_mdo_en}] +set_output_delay -clock io_tseClk -reference_pin [get_ports {io_tseClk~CLKOUT~384~964}] -min -0.140 [get_ports {phy_mdo_en}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_read[0]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_read[0]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_write[0]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_write[0]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_writeEnable[0]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_writeEnable[0]}] +# set_input_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_read[3]}] +# set_input_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_read[3]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_write[3]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_write[3]}] +# set_output_delay -clock [-reference_pin ] -max [get_ports {system_gpio_0_io_writeEnable[3]}] +# set_output_delay -clock [-reference_pin ] -min [get_ports {system_gpio_0_io_writeEnable[3]}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~418~1}] -max 0.414 [get_ports {system_spi_0_io_data_0_read}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~418~1}] -min 0.276 [get_ports {system_spi_0_io_data_0_read}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~422~2}] -max 0.263 [get_ports {system_spi_0_io_data_0_write}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~422~2}] -min -0.140 [get_ports {system_spi_0_io_data_0_write}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~422~2}] -max 0.263 [get_ports {system_spi_0_io_data_0_writeEnable}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~422~2}] -min -0.140 [get_ports {system_spi_0_io_data_0_writeEnable}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~425~1}] -max 0.414 [get_ports {system_spi_0_io_data_1_read}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~425~1}] -min 0.276 [get_ports {system_spi_0_io_data_1_read}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~420~1}] -max 0.263 [get_ports {system_spi_0_io_data_1_write}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~420~1}] -min -0.140 [get_ports {system_spi_0_io_data_1_write}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~420~1}] -max 0.263 [get_ports {system_spi_0_io_data_1_writeEnable}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~420~1}] -min -0.140 [get_ports {system_spi_0_io_data_1_writeEnable}] + +# QCRV32 Constraints +####################### +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.701 [get_ports {io_ddrMasters_0_reset}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.340 [get_ports {io_ddrMasters_0_reset}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.196 [get_ports {io_ddrMasters_0_ar_payload_addr[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.071 [get_ports {io_ddrMasters_0_ar_payload_addr[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.217 [get_ports {io_ddrMasters_0_ar_payload_burst[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.034 [get_ports {io_ddrMasters_0_ar_payload_burst[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.222 [get_ports {io_ddrMasters_0_ar_payload_cache[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.020 [get_ports {io_ddrMasters_0_ar_payload_cache[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.247 [get_ports {io_ddrMasters_0_ar_payload_id[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.038 [get_ports {io_ddrMasters_0_ar_payload_id[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.251 [get_ports {io_ddrMasters_0_ar_payload_len[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.008 [get_ports {io_ddrMasters_0_ar_payload_len[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.226 [get_ports {io_ddrMasters_0_ar_payload_lock}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.054 [get_ports {io_ddrMasters_0_ar_payload_lock}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.265 [get_ports {io_ddrMasters_0_ar_payload_prot[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.006 [get_ports {io_ddrMasters_0_ar_payload_prot[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.191 [get_ports {io_ddrMasters_0_ar_payload_qos[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.013 [get_ports {io_ddrMasters_0_ar_payload_qos[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.259 [get_ports {io_ddrMasters_0_ar_payload_region[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.018 [get_ports {io_ddrMasters_0_ar_payload_region[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.219 [get_ports {io_ddrMasters_0_ar_payload_size[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.007 [get_ports {io_ddrMasters_0_ar_payload_size[*]}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 1.064 [get_ports {io_ddrMasters_0_ar_ready}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.544 [get_ports {io_ddrMasters_0_ar_ready}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.025 [get_ports {io_ddrMasters_0_ar_valid}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.051 [get_ports {io_ddrMasters_0_ar_valid}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 1.031 [get_ports {io_ddrMasters_0_r_payload_data[*]}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.347 [get_ports {io_ddrMasters_0_r_payload_data[*]}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.844 [get_ports {io_ddrMasters_0_r_payload_last}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.387 [get_ports {io_ddrMasters_0_r_payload_last}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.426 [get_ports {io_ddrMasters_0_r_ready}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.095 [get_ports {io_ddrMasters_0_r_ready}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.965 [get_ports {io_ddrMasters_0_r_valid}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.508 [get_ports {io_ddrMasters_0_r_valid}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.372 [get_ports {io_ddrMasters_0_aw_payload_addr[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.005 [get_ports {io_ddrMasters_0_aw_payload_addr[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.296 [get_ports {io_ddrMasters_0_aw_payload_allStrb}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.016 [get_ports {io_ddrMasters_0_aw_payload_allStrb}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.217 [get_ports {io_ddrMasters_0_aw_payload_burst[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.002 [get_ports {io_ddrMasters_0_aw_payload_burst[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.217 [get_ports {io_ddrMasters_0_aw_payload_cache[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.027 [get_ports {io_ddrMasters_0_aw_payload_cache[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.238 [get_ports {io_ddrMasters_0_aw_payload_id[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.001 [get_ports {io_ddrMasters_0_aw_payload_id[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.280 [get_ports {io_ddrMasters_0_aw_payload_len[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.003 [get_ports {io_ddrMasters_0_aw_payload_len[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.205 [get_ports {io_ddrMasters_0_aw_payload_lock}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.022 [get_ports {io_ddrMasters_0_aw_payload_lock}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.178 [get_ports {io_ddrMasters_0_aw_payload_prot[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.039 [get_ports {io_ddrMasters_0_aw_payload_prot[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.243 [get_ports {io_ddrMasters_0_aw_payload_qos[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.053 [get_ports {io_ddrMasters_0_aw_payload_qos[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.253 [get_ports {io_ddrMasters_0_aw_payload_region[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.008 [get_ports {io_ddrMasters_0_aw_payload_region[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.263 [get_ports {io_ddrMasters_0_aw_payload_size[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.007 [get_ports {io_ddrMasters_0_aw_payload_size[*]}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 1.213 [get_ports {io_ddrMasters_0_aw_ready}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.610 [get_ports {io_ddrMasters_0_aw_ready}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.294 [get_ports {io_ddrMasters_0_aw_valid}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.058 [get_ports {io_ddrMasters_0_aw_valid}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.289 [get_ports {io_ddrMasters_0_w_payload_data[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.105 [get_ports {io_ddrMasters_0_w_payload_data[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.042 [get_ports {io_ddrMasters_0_w_payload_last}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.053 [get_ports {io_ddrMasters_0_w_payload_last}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.130 [get_ports {io_ddrMasters_0_w_payload_strb[*]}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.070 [get_ports {io_ddrMasters_0_w_payload_strb[*]}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 1.193 [get_ports {io_ddrMasters_0_w_ready}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.616 [get_ports {io_ddrMasters_0_w_ready}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.118 [get_ports {io_ddrMasters_0_w_valid}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.038 [get_ports {io_ddrMasters_0_w_valid}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.196 [get_ports {io_ddrMasters_0_b_ready}] +set_output_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min -0.012 [get_ports {io_ddrMasters_0_b_ready}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -max 0.991 [get_ports {io_ddrMasters_0_b_valid}] +set_input_delay -clock io_ddrMasters_0_clk -reference_pin [get_ports {io_ddrMasters_0_clk~CLKOUT~38~2}] -min 0.514 [get_ports {io_ddrMasters_0_b_valid}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.766 [get_ports {axiAInterrupt}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.322 [get_ports {axiAInterrupt}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 1.089 [get_ports {axiA_araddr[*]}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.425 [get_ports {axiA_araddr[*]}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 1.134 [get_ports {axiA_arlen[*]}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.484 [get_ports {axiA_arlen[*]}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.285 [get_ports {axiA_arready}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.074 [get_ports {axiA_arready}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.824 [get_ports {axiA_arvalid}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.444 [get_ports {axiA_arvalid}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.660 [get_ports {axiA_rdata[*]}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.018 [get_ports {axiA_rdata[*]}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.384 [get_ports {axiA_rlast}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.068 [get_ports {axiA_rlast}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 1.305 [get_ports {axiA_rready}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.647 [get_ports {axiA_rready}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.460 [get_ports {axiA_rresp[*]}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.113 [get_ports {axiA_rresp[*]}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.344 [get_ports {axiA_rvalid}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.071 [get_ports {axiA_rvalid}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.710 [get_ports {axiA_awaddr[*]}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.344 [get_ports {axiA_awaddr[*]}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.753 [get_ports {axiA_awlen[*]}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.363 [get_ports {axiA_awlen[*]}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.156 [get_ports {axiA_awready}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min -0.017 [get_ports {axiA_awready}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.674 [get_ports {axiA_awvalid}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.354 [get_ports {axiA_awvalid}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 1.000 [get_ports {axiA_wdata[*]}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.373 [get_ports {axiA_wdata[*]}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.933 [get_ports {axiA_wlast}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.494 [get_ports {axiA_wlast}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.155 [get_ports {axiA_wready}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min -0.018 [get_ports {axiA_wready}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 1.021 [get_ports {axiA_wstrb[*]}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.491 [get_ports {axiA_wstrb[*]}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.799 [get_ports {axiA_wvalid}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.414 [get_ports {axiA_wvalid}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.944 [get_ports {axiA_bready}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.494 [get_ports {axiA_bready}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.315 [get_ports {axiA_bresp[*]}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.064 [get_ports {axiA_bresp[*]}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.251 [get_ports {axiA_bvalid}] +set_output_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.052 [get_ports {axiA_bvalid}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -max 0.730 [get_ports {io_peripheralReset}] +set_input_delay -clock io_peripheralClk -reference_pin [get_ports {io_peripheralClk~CLKOUT~42~2}] -min 0.386 [get_ports {io_peripheralReset}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.777 [get_ports {cpu0_customInstruction_cmd_ready}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.246 [get_ports {cpu0_customInstruction_cmd_ready}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.488 [get_ports {cpu0_customInstruction_cmd_valid}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.776 [get_ports {cpu0_customInstruction_cmd_valid}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.500 [get_ports {cpu0_customInstruction_function_id[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.637 [get_ports {cpu0_customInstruction_function_id[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.545 [get_ports {cpu0_customInstruction_inputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.612 [get_ports {cpu0_customInstruction_inputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.428 [get_ports {cpu0_customInstruction_inputs_1[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.625 [get_ports {cpu0_customInstruction_inputs_1[*]}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.844 [get_ports {cpu0_customInstruction_outputs_0[*]}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.147 [get_ports {cpu0_customInstruction_outputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.401 [get_ports {cpu0_customInstruction_rsp_ready}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.746 [get_ports {cpu0_customInstruction_rsp_ready}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.864 [get_ports {cpu0_customInstruction_rsp_valid}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.251 [get_ports {cpu0_customInstruction_rsp_valid}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.947 [get_ports {cpu1_customInstruction_cmd_ready}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.300 [get_ports {cpu1_customInstruction_cmd_ready}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.580 [get_ports {cpu1_customInstruction_cmd_valid}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.804 [get_ports {cpu1_customInstruction_cmd_valid}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.849 [get_ports {cpu1_customInstruction_function_id[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.720 [get_ports {cpu1_customInstruction_function_id[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.956 [get_ports {cpu1_customInstruction_inputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.752 [get_ports {cpu1_customInstruction_inputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.810 [get_ports {cpu1_customInstruction_inputs_1[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.748 [get_ports {cpu1_customInstruction_inputs_1[*]}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.052 [get_ports {cpu1_customInstruction_outputs_0[*]}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.169 [get_ports {cpu1_customInstruction_outputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.643 [get_ports {cpu1_customInstruction_rsp_ready}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.869 [get_ports {cpu1_customInstruction_rsp_ready}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.800 [get_ports {cpu1_customInstruction_rsp_valid}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.278 [get_ports {cpu1_customInstruction_rsp_valid}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.863 [get_ports {cpu2_customInstruction_cmd_ready}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.325 [get_ports {cpu2_customInstruction_cmd_ready}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.757 [get_ports {cpu2_customInstruction_cmd_valid}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.841 [get_ports {cpu2_customInstruction_cmd_valid}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.667 [get_ports {cpu2_customInstruction_function_id[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.801 [get_ports {cpu2_customInstruction_function_id[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.848 [get_ports {cpu2_customInstruction_inputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.750 [get_ports {cpu2_customInstruction_inputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.750 [get_ports {cpu2_customInstruction_inputs_1[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.762 [get_ports {cpu2_customInstruction_inputs_1[*]}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.950 [get_ports {cpu2_customInstruction_outputs_0[*]}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.234 [get_ports {cpu2_customInstruction_outputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.745 [get_ports {cpu2_customInstruction_rsp_ready}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.931 [get_ports {cpu2_customInstruction_rsp_ready}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.726 [get_ports {cpu2_customInstruction_rsp_valid}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.277 [get_ports {cpu2_customInstruction_rsp_valid}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.730 [get_ports {cpu3_customInstruction_cmd_ready}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.297 [get_ports {cpu3_customInstruction_cmd_ready}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.529 [get_ports {cpu3_customInstruction_cmd_valid}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.830 [get_ports {cpu3_customInstruction_cmd_valid}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.677 [get_ports {cpu3_customInstruction_function_id[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.788 [get_ports {cpu3_customInstruction_function_id[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.677 [get_ports {cpu3_customInstruction_inputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.770 [get_ports {cpu3_customInstruction_inputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.741 [get_ports {cpu3_customInstruction_inputs_1[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.769 [get_ports {cpu3_customInstruction_inputs_1[*]}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.074 [get_ports {cpu3_customInstruction_outputs_0[*]}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.200 [get_ports {cpu3_customInstruction_outputs_0[*]}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 1.685 [get_ports {cpu3_customInstruction_rsp_ready}] +set_input_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.913 [get_ports {cpu3_customInstruction_rsp_ready}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -max 0.756 [get_ports {cpu3_customInstruction_rsp_valid}] +set_output_delay -clock io_cfuClk -reference_pin [get_ports {io_cfuClk~CLKOUT~3~1}] -min 0.319 [get_ports {cpu3_customInstruction_rsp_valid}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 1.058 [get_ports {jtagCtrl_capture}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.420 [get_ports {jtagCtrl_capture}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 1.423 [get_ports {jtagCtrl_enable}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.374 [get_ports {jtagCtrl_enable}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 1.313 [get_ports {jtagCtrl_reset}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.436 [get_ports {jtagCtrl_reset}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 1.379 [get_ports {jtagCtrl_shift}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.399 [get_ports {jtagCtrl_shift}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 0.687 [get_ports {jtagCtrl_tdi}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.304 [get_ports {jtagCtrl_tdi}] +set_input_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 2.055 [get_ports {jtagCtrl_tdo}] +set_input_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.906 [get_ports {jtagCtrl_tdo}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -max 1.351 [get_ports {jtagCtrl_update}] +set_output_delay -clock jtagCtrl_tck -reference_pin [get_ports {jtagCtrl_tck~CLKOUT~44~1}] -min 0.425 [get_ports {jtagCtrl_update}] + +# Clock Latency Constraints +############################ +# set_clock_latency -source -setup [get_ports {io_sysFbClk}] +# set_clock_latency -source -hold [get_ports {io_sysFbClk}] +# set_clock_latency -source -setup [get_ports {io_systemClk}] +# set_clock_latency -source -hold [get_ports {io_systemClk}] +# set_clock_latency -source -setup [get_ports {io_memoryClk}] +# set_clock_latency -source -hold [get_ports {io_memoryClk}] +# set_clock_latency -source -setup [get_ports {io_memFbClk}] +# set_clock_latency -source -hold [get_ports {io_memFbClk}] +# set_clock_latency -source -setup [get_ports {io_peripheralClk}] +# set_clock_latency -source -hold [get_ports {io_peripheralClk}] +# set_clock_latency -source -setup [get_ports {io_ddrMasters_0_clk}] +# set_clock_latency -source -hold [get_ports {io_ddrMasters_0_clk}] +# set_clock_latency -source -setup [get_ports {io_cfuClk}] +# set_clock_latency -source -hold [get_ports {io_cfuClk}] diff --git a/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb.v b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb.v new file mode 100644 index 0000000..7b89235 --- /dev/null +++ b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb.v @@ -0,0 +1,8650 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2026.1.132 +// IP Version: 1.23.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2026 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _be6ad777990c4e5089d0b11c63cc2698 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module EfxSapphireHpSoc_slb +( + input io_peripheralClk, + input io_peripheralReset, + output io_asyncReset, + input io_gpio_sw_n, + input pll_peripheral_locked, + input pll_system_locked, + output jtagCtrl_capture, + output jtagCtrl_enable, + output jtagCtrl_reset, + output jtagCtrl_shift, + output jtagCtrl_tdi, + input jtagCtrl_tdo, + output jtagCtrl_update, + input ut_jtagCtrl_capture, + input ut_jtagCtrl_enable, + input ut_jtagCtrl_reset, + input ut_jtagCtrl_shift, + input ut_jtagCtrl_tdi, + output ut_jtagCtrl_tdo, + input ut_jtagCtrl_update, + input system_spi_0_io_data_0_read, + output system_spi_0_io_data_0_write, + output system_spi_0_io_data_0_writeEnable, + input system_spi_0_io_data_1_read, + output system_spi_0_io_data_1_write, + output system_spi_0_io_data_1_writeEnable, + input system_spi_0_io_data_2_read, + output system_spi_0_io_data_2_write, + output system_spi_0_io_data_2_writeEnable, + input system_spi_0_io_data_3_read, + output system_spi_0_io_data_3_write, + output system_spi_0_io_data_3_writeEnable, + output system_spi_0_io_sclk_write, + output [3:0] system_spi_0_io_ss, + input system_uart_0_io_rxd, + output system_uart_0_io_txd, + input system_i2c_0_io_scl_read, + output system_i2c_0_io_scl_write, + input system_i2c_0_io_sda_read, + input [3:0] system_gpio_0_io_read, + output [3:0] system_gpio_0_io_write, + output [3:0] system_gpio_0_io_writeEnable, + input cfg_done, + output cfg_start, + output cfg_sel, + output cfg_reset, + output axiAInterrupt, + input [31:0] axiA_awaddr, + input [7:0] axiA_awlen, + input [2:0] axiA_awsize, + input [1:0] axiA_awburst, + input axiA_awlock, + input [3:0] axiA_awcache, + input [2:0] axiA_awprot, + input [3:0] axiA_awqos, + input [3:0] axiA_awregion, + input axiA_awvalid, + output axiA_awready, + input [31:0] axiA_wdata, + input [3:0] axiA_wstrb, + input axiA_wvalid, + input axiA_wlast, + output axiA_wready, + output [1:0] axiA_bresp, + output axiA_bvalid, + input axiA_bready, + input [31:0] axiA_araddr, + input [7:0] axiA_arlen, + input [2:0] axiA_arsize, + input [1:0] axiA_arburst, + input axiA_arlock, + input [3:0] axiA_arcache, + input [2:0] axiA_arprot, + input [3:0] axiA_arqos, + input [3:0] axiA_arregion, + input axiA_arvalid, + output axiA_arready, + output [31:0] axiA_rdata, + output [1:0] axiA_rresp, + output axiA_rlast, + output axiA_rvalid, + input axiA_rready, + output userInterruptA, + output userInterruptB, + output userInterruptC, + output userInterruptD, + output userInterruptE, + output userInterruptF, + output [31:0] io_apbSlave_0_PADDR, + output io_apbSlave_0_PENABLE, + input [31:0] io_apbSlave_0_PRDATA, + input io_apbSlave_0_PREADY, + output io_apbSlave_0_PSEL, + input io_apbSlave_0_PSLVERROR, + output [31:0] io_apbSlave_0_PWDATA, + output io_apbSlave_0_PWRITE, + output system_i2c_0_io_sda_write, + output system_i2c_0_io_sda_writeEnable, + output system_i2c_0_io_scl_writeEnable, + output system_watchdog_hardPanic_reset +); +`IP_MODULE_NAME(Axi4Peripheral_wrapper) +#( + .PERI_FREQ (200) +) +u_Axi4Peripheral_wrapper +( + .io_peripheralClk ( io_peripheralClk ), + .io_peripheralReset ( io_peripheralReset ), + .io_asyncReset ( io_asyncReset ), + .io_gpio_sw_n ( io_gpio_sw_n ), + .pll_peripheral_locked ( pll_peripheral_locked ), + .pll_system_locked ( pll_system_locked ), + .jtagCtrl_capture ( jtagCtrl_capture ), + .jtagCtrl_enable ( jtagCtrl_enable ), + .jtagCtrl_reset ( jtagCtrl_reset ), + .jtagCtrl_shift ( jtagCtrl_shift ), + .jtagCtrl_tdi ( jtagCtrl_tdi ), + .jtagCtrl_tdo ( jtagCtrl_tdo ), + .jtagCtrl_update ( jtagCtrl_update ), + .ut_jtagCtrl_capture ( ut_jtagCtrl_capture ), + .ut_jtagCtrl_enable ( ut_jtagCtrl_enable ), + .ut_jtagCtrl_reset ( ut_jtagCtrl_reset ), + .ut_jtagCtrl_shift ( ut_jtagCtrl_shift ), + .ut_jtagCtrl_tdi ( ut_jtagCtrl_tdi ), + .ut_jtagCtrl_tdo ( ut_jtagCtrl_tdo ), + .ut_jtagCtrl_update ( ut_jtagCtrl_update ), + .system_spi_0_io_data_0_read ( system_spi_0_io_data_0_read ), + .system_spi_0_io_data_0_write ( system_spi_0_io_data_0_write ), + .system_spi_0_io_data_0_writeEnable ( system_spi_0_io_data_0_writeEnable ), + .system_spi_0_io_data_1_read ( system_spi_0_io_data_1_read ), + .system_spi_0_io_data_1_write ( system_spi_0_io_data_1_write ), + .system_spi_0_io_data_1_writeEnable ( system_spi_0_io_data_1_writeEnable ), + .system_spi_0_io_data_2_read ( system_spi_0_io_data_2_read ), + .system_spi_0_io_data_2_write ( system_spi_0_io_data_2_write ), + .system_spi_0_io_data_2_writeEnable ( system_spi_0_io_data_2_writeEnable ), + .system_spi_0_io_data_3_read ( system_spi_0_io_data_3_read ), + .system_spi_0_io_data_3_write ( system_spi_0_io_data_3_write ), + .system_spi_0_io_data_3_writeEnable ( system_spi_0_io_data_3_writeEnable ), + .system_spi_0_io_sclk_write ( system_spi_0_io_sclk_write ), + .system_spi_0_io_ss ( system_spi_0_io_ss ), + .system_uart_0_io_rxd ( system_uart_0_io_rxd ), + .system_uart_0_io_txd ( system_uart_0_io_txd ), + .system_i2c_0_io_scl_read ( system_i2c_0_io_scl_read ), + .system_i2c_0_io_scl_write ( system_i2c_0_io_scl_write ), + .system_i2c_0_io_sda_read ( system_i2c_0_io_sda_read ), + .system_gpio_0_io_read ( system_gpio_0_io_read ), + .system_gpio_0_io_write ( system_gpio_0_io_write ), + .system_gpio_0_io_writeEnable ( system_gpio_0_io_writeEnable ), + .cfg_done ( cfg_done ), + .cfg_start ( cfg_start ), + .cfg_sel ( cfg_sel ), + .cfg_reset ( cfg_reset ), + .axiAInterrupt ( axiAInterrupt ), + .axiA_awaddr ( axiA_awaddr ), + .axiA_awlen ( axiA_awlen ), + .axiA_awsize ( axiA_awsize ), + .axiA_awburst ( axiA_awburst ), + .axiA_awlock ( axiA_awlock ), + .axiA_awcache ( axiA_awcache ), + .axiA_awprot ( axiA_awprot ), + .axiA_awqos ( axiA_awqos ), + .axiA_awregion ( axiA_awregion ), + .axiA_awvalid ( axiA_awvalid ), + .axiA_awready ( axiA_awready ), + .axiA_wdata ( axiA_wdata ), + .axiA_wstrb ( axiA_wstrb ), + .axiA_wvalid ( axiA_wvalid ), + .axiA_wlast ( axiA_wlast ), + .axiA_wready ( axiA_wready ), + .axiA_bresp ( axiA_bresp ), + .axiA_bvalid ( axiA_bvalid ), + .axiA_bready ( axiA_bready ), + .axiA_araddr ( axiA_araddr ), + .axiA_arlen ( axiA_arlen ), + .axiA_arsize ( axiA_arsize ), + .axiA_arburst ( axiA_arburst ), + .axiA_arlock ( axiA_arlock ), + .axiA_arcache ( axiA_arcache ), + .axiA_arprot ( axiA_arprot ), + .axiA_arqos ( axiA_arqos ), + .axiA_arregion ( axiA_arregion ), + .axiA_arvalid ( axiA_arvalid ), + .axiA_arready ( axiA_arready ), + .axiA_rdata ( axiA_rdata ), + .axiA_rresp ( axiA_rresp ), + .axiA_rlast ( axiA_rlast ), + .axiA_rvalid ( axiA_rvalid ), + .axiA_rready ( axiA_rready ), + .userInterruptA ( userInterruptA ), + .userInterruptB ( userInterruptB ), + .userInterruptC ( userInterruptC ), + .userInterruptD ( userInterruptD ), + .userInterruptE ( userInterruptE ), + .userInterruptF ( userInterruptF ), + .io_apbSlave_0_PADDR ( io_apbSlave_0_PADDR ), + .io_apbSlave_0_PENABLE ( io_apbSlave_0_PENABLE ), + .io_apbSlave_0_PRDATA ( io_apbSlave_0_PRDATA ), + .io_apbSlave_0_PREADY ( io_apbSlave_0_PREADY ), + .io_apbSlave_0_PSEL ( io_apbSlave_0_PSEL ), + .io_apbSlave_0_PSLVERROR ( io_apbSlave_0_PSLVERROR ), + .io_apbSlave_0_PWDATA ( io_apbSlave_0_PWDATA ), + .io_apbSlave_0_PWRITE ( io_apbSlave_0_PWRITE ), + .system_i2c_0_io_sda_write ( system_i2c_0_io_sda_write ), + .system_i2c_0_io_sda_writeEnable ( system_i2c_0_io_sda_writeEnable ), + .system_i2c_0_io_scl_writeEnable ( system_i2c_0_io_scl_writeEnable ), + .system_watchdog_hardPanic_reset ( system_watchdog_hardPanic_reset ) +); +endmodule + +module `IP_MODULE_NAME(Axi4Peripheral_wrapper) #( +parameter PERI_FREQ=250 +)( +input [3:0] system_gpio_0_io_read, +output [3:0] system_gpio_0_io_write, +output [3:0] system_gpio_0_io_writeEnable, +output system_i2c_0_io_sda_writeEnable, +output system_i2c_0_io_sda_write, +input system_i2c_0_io_sda_read, +output system_i2c_0_io_scl_writeEnable, +output system_i2c_0_io_scl_write, +input system_i2c_0_io_scl_read, +output system_watchdog_hardPanic_reset, +output userInterruptF, +output system_spi_0_io_sclk_write, +output system_spi_0_io_data_0_writeEnable, +input system_spi_0_io_data_0_read, +output system_spi_0_io_data_0_write, +output system_spi_0_io_data_1_writeEnable, +input system_spi_0_io_data_1_read, +output system_spi_0_io_data_1_write, +output system_spi_0_io_data_2_writeEnable, +input system_spi_0_io_data_2_read, +output system_spi_0_io_data_2_write, +output system_spi_0_io_data_3_writeEnable, +input system_spi_0_io_data_3_read, +output system_spi_0_io_data_3_write, +output [3:0] system_spi_0_io_ss, +output userInterruptD, +output [15:0] io_apbSlave_0_PADDR, +output io_apbSlave_0_PSEL, +output io_apbSlave_0_PENABLE, +input io_apbSlave_0_PREADY, +output io_apbSlave_0_PWRITE, +output [31:0] io_apbSlave_0_PWDATA, +input [31:0] io_apbSlave_0_PRDATA, +input io_apbSlave_0_PSLVERROR, +output userInterruptC, +output jtagCtrl_tdi, +input jtagCtrl_tdo, +output jtagCtrl_enable, +output jtagCtrl_capture, +output jtagCtrl_shift, +output jtagCtrl_update, +output jtagCtrl_reset, +input ut_jtagCtrl_tdi, +output ut_jtagCtrl_tdo, +input ut_jtagCtrl_enable, +input ut_jtagCtrl_capture, +input ut_jtagCtrl_shift, +input ut_jtagCtrl_update, +input ut_jtagCtrl_reset, +output system_uart_0_io_txd, +input system_uart_0_io_rxd, +output userInterruptB, +output userInterruptA, +output userInterruptE, +input [31:0] axiA_awaddr, +input [7:0] axiA_awlen, +input [2:0] axiA_awsize, +input [1:0] axiA_awburst, +input axiA_awlock, +input [3:0] axiA_awcache, +input [2:0] axiA_awprot, +input [3:0] axiA_awqos, +input [3:0] axiA_awregion, +input axiA_awvalid, +output axiA_awready, +input [31:0] axiA_wdata, +input [3:0] axiA_wstrb, +input axiA_wvalid, +input axiA_wlast, +output axiA_wready, +output [1:0] axiA_bresp, +output axiA_bvalid, +input axiA_bready, +input [31:0] axiA_araddr, +input [7:0] axiA_arlen, +input [2:0] axiA_arsize, +input [1:0] axiA_arburst, +input axiA_arlock, +input [3:0] axiA_arcache, +input [2:0] axiA_arprot, +input [3:0] axiA_arqos, +input [3:0] axiA_arregion, +input axiA_arvalid, +output axiA_arready, +output [31:0] axiA_rdata, +output [1:0] axiA_rresp, +output axiA_rlast, +output axiA_rvalid, +input axiA_rready, +output axiAInterrupt, +input cfg_done, +output cfg_start, +output cfg_sel, +output cfg_reset, +input io_peripheralClk, +input io_peripheralReset, +output io_asyncReset, +input io_gpio_sw_n, +input pll_peripheral_locked, +input pll_system_locked +); + +wire flag_ok; +wire system_watchdog_softPanic_interrupt; +wire system_i2c_0_io_interrupt; +wire system_spi_0_io_interrupt; +wire system_uart_0_io_interrupt; +wire system_gpio_0_io_interrupt_0; +wire system_gpio_0_io_interrupt_1; + + +`IP_MODULE_NAME(lppdr4_init) u_lppdr4_init ( +.io_peripheralClk (io_peripheralClk), +.io_peripheralReset (io_peripheralReset), +.io_gpio_sw_n (io_gpio_sw_n), +.flag_ok (flag_ok), +.cfg_done (cfg_done), +.cfg_start (cfg_start), +.cfg_sel (cfg_sel), +.cfg_reset (cfg_reset) +); + +assign io_asyncReset = ~(io_gpio_sw_n & + pll_peripheral_locked & + pll_system_locked & + flag_ok); + +assign userInterruptA = system_uart_0_io_interrupt; +assign userInterruptB = system_spi_0_io_interrupt; +assign userInterruptC = system_i2c_0_io_interrupt; +assign userInterruptD = system_gpio_0_io_interrupt_0; +assign userInterruptE = system_gpio_0_io_interrupt_1; +assign userInterruptF = system_watchdog_softPanic_interrupt; + +assign jtagCtrl_capture = ut_jtagCtrl_capture; +assign jtagCtrl_enable = ut_jtagCtrl_enable; +assign jtagCtrl_reset = ut_jtagCtrl_reset; +assign jtagCtrl_shift = ut_jtagCtrl_shift; +assign jtagCtrl_tdi = ut_jtagCtrl_tdi; +assign jtagCtrl_update = ut_jtagCtrl_update; +assign ut_jtagCtrl_tdo = jtagCtrl_tdo; + + +assign system_i2c_0_io_sda_writeEnable=!system_i2c_0_io_sda_write; +assign system_i2c_0_io_scl_writeEnable=!system_i2c_0_io_scl_write; + + +//axi4 bridge to various I/O +Axi4PeripheralTop_be6ad777990c4e5089d0b11c63cc2698 u_Axi4PeripheralTop( +.io_apbSlave_0_PADDR(io_apbSlave_0_PADDR), +.io_apbSlave_0_PSEL(io_apbSlave_0_PSEL), +.io_apbSlave_0_PENABLE(io_apbSlave_0_PENABLE), +.io_apbSlave_0_PREADY(io_apbSlave_0_PREADY), +.io_apbSlave_0_PWRITE(io_apbSlave_0_PWRITE), +.io_apbSlave_0_PWDATA(io_apbSlave_0_PWDATA), +.io_apbSlave_0_PRDATA(io_apbSlave_0_PRDATA), +.io_apbSlave_0_PSLVERROR(io_apbSlave_0_PSLVERROR), +.system_i2c_0_io_interrupt(system_i2c_0_io_interrupt), +.system_i2c_0_io_sda_write(system_i2c_0_io_sda_write), +.system_i2c_0_io_sda_read(system_i2c_0_io_sda_read), +.system_i2c_0_io_scl_write(system_i2c_0_io_scl_write), +.system_i2c_0_io_scl_read(system_i2c_0_io_scl_read), +.system_gpio_0_io_interrupts_0(system_gpio_0_io_interrupt_0), +.system_gpio_0_io_interrupts_1(system_gpio_0_io_interrupt_1), +.system_gpio_0_io_read(system_gpio_0_io_read), +.system_gpio_0_io_write(system_gpio_0_io_write), +.system_gpio_0_io_writeEnable(system_gpio_0_io_writeEnable), +.system_spi_0_io_interrupt(system_spi_0_io_interrupt), +.system_spi_0_io_sclk_write(system_spi_0_io_sclk_write), +.system_spi_0_io_data_0_writeEnable(system_spi_0_io_data_0_writeEnable), +.system_spi_0_io_data_0_read(system_spi_0_io_data_0_read), +.system_spi_0_io_data_0_write(system_spi_0_io_data_0_write), +.system_spi_0_io_data_1_writeEnable(system_spi_0_io_data_1_writeEnable), +.system_spi_0_io_data_1_read(system_spi_0_io_data_1_read), +.system_spi_0_io_data_1_write(system_spi_0_io_data_1_write), +.system_spi_0_io_data_2_writeEnable(system_spi_0_io_data_2_writeEnable), +.system_spi_0_io_data_2_read(system_spi_0_io_data_2_read), +.system_spi_0_io_data_2_write(system_spi_0_io_data_2_write), +.system_spi_0_io_data_3_writeEnable(system_spi_0_io_data_3_writeEnable), +.system_spi_0_io_data_3_read(system_spi_0_io_data_3_read), +.system_spi_0_io_data_3_write(system_spi_0_io_data_3_write), +.system_spi_0_io_ss(system_spi_0_io_ss), +.system_uart_0_io_interrupt(system_uart_0_io_interrupt), +.system_uart_0_io_txd(system_uart_0_io_txd), +.system_uart_0_io_rxd(system_uart_0_io_rxd), +.system_watchdog_hardPanic_reset(system_watchdog_hardPanic_reset), +.system_watchdog_logic_panics_0(system_watchdog_softPanic_interrupt), +.axi_awvalid(axiA_awvalid), +.axi_awready(axiA_awready), +.axi_awaddr(axiA_awaddr[23:0]), +.axi_awlen(axiA_awlen), +.axi_awsize(axiA_awsize), +.axi_awcache(axiA_awcache), +.axi_awprot(axiA_awprot), +.axi_wvalid(axiA_wvalid), +.axi_wready(axiA_wready), +.axi_wdata(axiA_wdata), +.axi_wstrb(axiA_wstrb), +.axi_wlast(axiA_wlast), +.axi_bvalid(axiA_bvalid), +.axi_bready(axiA_bready), +.axi_bresp(axiA_bresp), +.axi_arvalid(axiA_arvalid), +.axi_arready(axiA_arready), +.axi_araddr(axiA_araddr[23:0]), +.axi_arlen(axiA_arlen), +.axi_arsize(axiA_arsize), +.axi_arcache(axiA_arcache), +.axi_arprot(axiA_arprot), +.axi_rvalid(axiA_rvalid), +.axi_rready(axiA_rready), +.axi_rdata(axiA_rdata), +.axi_rresp(axiA_rresp), +.axi_rlast(axiA_rlast), +.clk(io_peripheralClk), +.reset(io_peripheralReset) +); +assign axiAInterrupt = 1'b0; + +endmodule + + +module `IP_MODULE_NAME(lppdr4_init) ( + input io_peripheralClk, + input io_peripheralReset, + input io_gpio_sw_n, + output reg flag_ok, + input cfg_done, + output cfg_start, + output cfg_sel, + output cfg_reset +); + +localparam [1:0] IDLE = 2'b00, + CFG_START = 2'b01, + CFG_DONE = 2'b11; + +reg [1:0] cfg_st, + cfg_next; +reg [7:0] cfg_count; +wire cfg_ok; +reg [1:0] buf_reset; +wire dmReset; + +always@(posedge io_peripheralClk) +begin + buf_reset[1] <= io_peripheralReset; + buf_reset[0] <= buf_reset[1]; +end + +assign dmReset = (~buf_reset[0] & buf_reset[1]); + +always@(posedge io_peripheralClk or negedge io_gpio_sw_n) +begin + if(!io_gpio_sw_n) + flag_ok <= 1'b0; + else + begin + if(cfg_st == CFG_DONE) + flag_ok <= 1'b1; + else + flag_ok <= flag_ok; + end +end + +always@(posedge io_peripheralClk or negedge io_gpio_sw_n) +begin + if(!io_gpio_sw_n || dmReset) + cfg_st <= IDLE; + else + cfg_st <= cfg_next; +end + +always@(*) +begin + cfg_next = cfg_st; + case(cfg_st) + IDLE: + begin + if(cfg_count == 'hff) + cfg_next = CFG_START; + else + cfg_next = IDLE; + end + CFG_START: + begin + if(cfg_done) + cfg_next = CFG_DONE; + else + cfg_next = CFG_START; + end + CFG_DONE: + cfg_next = CFG_DONE; + default: + cfg_next = IDLE; + endcase +end + +assign cfg_start = (cfg_st != IDLE); +assign cfg_ok = (cfg_st == CFG_DONE); +assign cfg_reset = (cfg_st == IDLE); +assign cfg_sel = 1'b0; + +always@(posedge io_peripheralClk) +begin + if(cfg_st == IDLE) + cfg_count <= cfg_count + 1'b1; + else + cfg_count <= 'h0; +end + +endmodule + + +// Generator : SpinalHDL dev git head : a69f4b9a329be784802c37cd8038b7dc9aec3094 +// Component : Axi4PeripheralTop_be6ad777990c4e5089d0b11c63cc2698 + +`timescale 1ns/1ps + +module Axi4PeripheralTop_be6ad777990c4e5089d0b11c63cc2698 ( + input wire axi_awvalid, + output wire axi_awready, + input wire [23:0] axi_awaddr, + input wire [7:0] axi_awlen, + input wire [2:0] axi_awsize, + input wire [3:0] axi_awcache, + input wire [2:0] axi_awprot, + input wire axi_wvalid, + output wire axi_wready, + input wire [31:0] axi_wdata, + input wire [3:0] axi_wstrb, + input wire axi_wlast, + output wire axi_bvalid, + input wire axi_bready, + output wire [1:0] axi_bresp, + input wire axi_arvalid, + output wire axi_arready, + input wire [23:0] axi_araddr, + input wire [7:0] axi_arlen, + input wire [2:0] axi_arsize, + input wire [3:0] axi_arcache, + input wire [2:0] axi_arprot, + output wire axi_rvalid, + input wire axi_rready, + output wire [31:0] axi_rdata, + output wire [1:0] axi_rresp, + output wire axi_rlast, + output wire system_uart_0_io_txd, + input wire system_uart_0_io_rxd, + output wire system_i2c_0_io_sda_write, + input wire system_i2c_0_io_sda_read, + output wire system_i2c_0_io_scl_write, + input wire system_i2c_0_io_scl_read, + input wire [3:0] system_gpio_0_io_read, + output wire [3:0] system_gpio_0_io_write, + output wire [3:0] system_gpio_0_io_writeEnable, + output wire [15:0] io_apbSlave_0_PADDR, + output wire [0:0] io_apbSlave_0_PSEL, + output wire io_apbSlave_0_PENABLE, + input wire io_apbSlave_0_PREADY, + output wire io_apbSlave_0_PWRITE, + output wire [31:0] io_apbSlave_0_PWDATA, + input wire [31:0] io_apbSlave_0_PRDATA, + input wire io_apbSlave_0_PSLVERROR, + output wire system_uart_0_io_interrupt, + output wire system_spi_0_io_interrupt, + output wire [0:0] system_spi_0_io_sclk_write, + output wire system_spi_0_io_data_0_writeEnable, + input wire [0:0] system_spi_0_io_data_0_read, + output wire [0:0] system_spi_0_io_data_0_write, + output wire system_spi_0_io_data_1_writeEnable, + input wire [0:0] system_spi_0_io_data_1_read, + output wire [0:0] system_spi_0_io_data_1_write, + output wire system_spi_0_io_data_2_writeEnable, + input wire [0:0] system_spi_0_io_data_2_read, + output wire [0:0] system_spi_0_io_data_2_write, + output wire system_spi_0_io_data_3_writeEnable, + input wire [0:0] system_spi_0_io_data_3_read, + output wire [0:0] system_spi_0_io_data_3_write, + output wire [3:0] system_spi_0_io_ss, + output wire system_i2c_0_io_interrupt, + output wire system_gpio_0_io_interrupts_0, + output wire system_gpio_0_io_interrupts_1, + output wire system_watchdog_logic_panics_0, + output wire system_watchdog_hardPanic_reset, + input wire clk, + input wire reset +); + + wire streamArbiter_io_inputs_0_ready; + wire streamArbiter_io_inputs_1_ready; + wire streamArbiter_io_output_valid; + wire [23:0] streamArbiter_io_output_payload_addr; + wire [7:0] streamArbiter_io_output_payload_len; + wire [2:0] streamArbiter_io_output_payload_size; + wire [3:0] streamArbiter_io_output_payload_cache; + wire [2:0] streamArbiter_io_output_payload_prot; + wire [0:0] streamArbiter_io_chosen; + wire [1:0] streamArbiter_io_chosenOH; + wire axiToBmb_io_axi_arw_ready; + wire axiToBmb_io_axi_w_ready; + wire axiToBmb_io_axi_b_valid; + wire [1:0] axiToBmb_io_axi_b_payload_resp; + wire axiToBmb_io_axi_r_valid; + wire [31:0] axiToBmb_io_axi_r_payload_data; + wire [1:0] axiToBmb_io_axi_r_payload_resp; + wire axiToBmb_io_axi_r_payload_last; + wire axiToBmb_io_bmb_cmd_valid; + wire axiToBmb_io_bmb_cmd_payload_last; + wire [0:0] axiToBmb_io_bmb_cmd_payload_fragment_source; + wire [0:0] axiToBmb_io_bmb_cmd_payload_fragment_opcode; + wire [23:0] axiToBmb_io_bmb_cmd_payload_fragment_address; + wire [9:0] axiToBmb_io_bmb_cmd_payload_fragment_length; + wire [31:0] axiToBmb_io_bmb_cmd_payload_fragment_data; + wire [3:0] axiToBmb_io_bmb_cmd_payload_fragment_mask; + wire axiToBmb_io_bmb_rsp_ready; + wire bmbHandle_decoder_io_input_cmd_ready; + wire bmbHandle_decoder_io_input_rsp_valid; + wire bmbHandle_decoder_io_input_rsp_payload_last; + wire [0:0] bmbHandle_decoder_io_input_rsp_payload_fragment_source; + wire [0:0] bmbHandle_decoder_io_input_rsp_payload_fragment_opcode; + wire [31:0] bmbHandle_decoder_io_input_rsp_payload_fragment_data; + wire bmbHandle_decoder_io_outputs_0_cmd_valid; + wire bmbHandle_decoder_io_outputs_0_cmd_payload_last; + wire [0:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_source; + wire [0:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_opcode; + wire [23:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_address; + wire [9:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_length; + wire [31:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_data; + wire [3:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_mask; + wire bmbHandle_decoder_io_outputs_0_rsp_ready; + wire bmbHandle_unburstify_io_input_cmd_ready; + wire bmbHandle_unburstify_io_input_rsp_valid; + wire bmbHandle_unburstify_io_input_rsp_payload_last; + wire [0:0] bmbHandle_unburstify_io_input_rsp_payload_fragment_source; + wire [0:0] bmbHandle_unburstify_io_input_rsp_payload_fragment_opcode; + wire [31:0] bmbHandle_unburstify_io_input_rsp_payload_fragment_data; + wire bmbHandle_unburstify_io_output_cmd_valid; + wire bmbHandle_unburstify_io_output_cmd_payload_last; + wire [0:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_opcode; + wire [23:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_address; + wire [1:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_length; + wire [31:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_data; + wire [3:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_mask; + wire [2:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_context; + wire bmbHandle_unburstify_io_output_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_input_cmd_ready; + wire bmbPeripheral_bmb_decoder_io_input_rsp_valid; + wire bmbPeripheral_bmb_decoder_io_input_rsp_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode; + wire [31:0] bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data; + wire [2:0] bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_outputs_5_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_5_rsp_ready; + wire system_uart_0_io_logic_io_bus_cmd_ready; + wire system_uart_0_io_logic_io_bus_rsp_valid; + wire system_uart_0_io_logic_io_bus_rsp_payload_last; + wire [0:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode; + wire [31:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_data; + wire [2:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_context; + wire system_uart_0_io_logic_io_uart_txd; + wire system_uart_0_io_logic_system_uart_0_io_interrupt_source; + wire system_spi_0_io_logic_io_ctrl_cmd_ready; + wire system_spi_0_io_logic_io_ctrl_rsp_valid; + wire system_spi_0_io_logic_io_ctrl_rsp_payload_last; + wire [0:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; + wire [31:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data; + wire [2:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context; + wire [0:0] system_spi_0_io_logic_io_spi_sclk_write; + wire [3:0] system_spi_0_io_logic_io_spi_ss; + wire [0:0] system_spi_0_io_logic_io_spi_data_0_write; + wire system_spi_0_io_logic_io_spi_data_0_writeEnable; + wire [0:0] system_spi_0_io_logic_io_spi_data_1_write; + wire system_spi_0_io_logic_io_spi_data_1_writeEnable; + wire [0:0] system_spi_0_io_logic_io_spi_data_2_write; + wire system_spi_0_io_logic_io_spi_data_2_writeEnable; + wire [0:0] system_spi_0_io_logic_io_spi_data_3_write; + wire system_spi_0_io_logic_io_spi_data_3_writeEnable; + wire system_spi_0_io_logic_system_spi_0_io_interrupt_source; + wire system_i2c_0_io_logic_io_ctrl_cmd_ready; + wire system_i2c_0_io_logic_io_ctrl_rsp_valid; + wire system_i2c_0_io_logic_io_ctrl_rsp_payload_last; + wire [0:0] system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; + wire [31:0] system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_data; + wire [2:0] system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_context; + wire system_i2c_0_io_logic_io_i2c_scl_write; + wire system_i2c_0_io_logic_io_i2c_sda_write; + wire system_i2c_0_io_logic_system_i2c_0_io_interrupt_source; + wire [3:0] system_gpio_0_io_logic_io_gpio_write; + wire [3:0] system_gpio_0_io_logic_io_gpio_writeEnable; + wire system_gpio_0_io_logic_io_bus_cmd_ready; + wire system_gpio_0_io_logic_io_bus_rsp_valid; + wire system_gpio_0_io_logic_io_bus_rsp_payload_last; + wire [0:0] system_gpio_0_io_logic_io_bus_rsp_payload_fragment_opcode; + wire [31:0] system_gpio_0_io_logic_io_bus_rsp_payload_fragment_data; + wire [2:0] system_gpio_0_io_logic_io_bus_rsp_payload_fragment_context; + wire [3:0] system_gpio_0_io_logic_io_interrupt; + wire system_watchdog_logic_logic_io_bus_cmd_ready; + wire system_watchdog_logic_logic_io_bus_rsp_valid; + wire system_watchdog_logic_logic_io_bus_rsp_payload_last; + wire [0:0] system_watchdog_logic_logic_io_bus_rsp_payload_fragment_opcode; + wire [31:0] system_watchdog_logic_logic_io_bus_rsp_payload_fragment_data; + wire [2:0] system_watchdog_logic_logic_io_bus_rsp_payload_fragment_context; + wire [1:0] system_watchdog_logic_logic_io_panics; + wire io_apbSlave_0_logic_io_input_cmd_ready; + wire io_apbSlave_0_logic_io_input_rsp_valid; + wire io_apbSlave_0_logic_io_input_rsp_payload_last; + wire [0:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode; + wire [31:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_data; + wire [2:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_context; + wire [15:0] io_apbSlave_0_logic_io_output_PADDR; + wire [0:0] io_apbSlave_0_logic_io_output_PSEL; + wire io_apbSlave_0_logic_io_output_PENABLE; + wire io_apbSlave_0_logic_io_output_PWRITE; + wire [31:0] io_apbSlave_0_logic_io_output_PWDATA; + wire _zz_axiShared_b_ready; + wire _zz_axiShared_r_ready; + wire axi_aw_halfPipe_valid; + wire axi_aw_halfPipe_ready; + wire [23:0] axi_aw_halfPipe_payload_addr; + wire [7:0] axi_aw_halfPipe_payload_len; + wire [2:0] axi_aw_halfPipe_payload_size; + wire [3:0] axi_aw_halfPipe_payload_cache; + wire [2:0] axi_aw_halfPipe_payload_prot; + reg axi_aw_rValid; + wire axi_aw_halfPipe_fire; + reg [23:0] axi_aw_rData_addr; + reg [7:0] axi_aw_rData_len; + reg [2:0] axi_aw_rData_size; + reg [3:0] axi_aw_rData_cache; + reg [2:0] axi_aw_rData_prot; + wire axi_w_halfPipe_valid; + wire axi_w_halfPipe_ready; + wire [31:0] axi_w_halfPipe_payload_data; + wire [3:0] axi_w_halfPipe_payload_strb; + wire axi_w_halfPipe_payload_last; + reg axi_w_rValid; + wire axi_w_halfPipe_fire; + reg [31:0] axi_w_rData_data; + reg [3:0] axi_w_rData_strb; + reg axi_w_rData_last; + wire _zz_axi_bvalid; + reg _zz_axi_bvalid_1; + reg [1:0] _zz_axi_bresp; + wire axi_ar_halfPipe_valid; + wire axi_ar_halfPipe_ready; + wire [23:0] axi_ar_halfPipe_payload_addr; + wire [7:0] axi_ar_halfPipe_payload_len; + wire [2:0] axi_ar_halfPipe_payload_size; + wire [3:0] axi_ar_halfPipe_payload_cache; + wire [2:0] axi_ar_halfPipe_payload_prot; + reg axi_ar_rValid; + wire axi_ar_halfPipe_fire; + reg [23:0] axi_ar_rData_addr; + reg [7:0] axi_ar_rData_len; + reg [2:0] axi_ar_rData_size; + reg [3:0] axi_ar_rData_cache; + reg [2:0] axi_ar_rData_prot; + wire _zz_axi_rvalid; + reg _zz_axi_rvalid_1; + reg [31:0] _zz_axi_rdata; + reg [1:0] _zz_axi_rresp; + reg _zz_axi_rlast; + wire axiShared_arw_valid; + wire axiShared_arw_ready; + wire [23:0] axiShared_arw_payload_addr; + wire [7:0] axiShared_arw_payload_len; + wire [2:0] axiShared_arw_payload_size; + wire [3:0] axiShared_arw_payload_cache; + wire [2:0] axiShared_arw_payload_prot; + wire axiShared_arw_payload_write; + wire axiShared_w_valid; + wire axiShared_w_ready; + wire [31:0] axiShared_w_payload_data; + wire [3:0] axiShared_w_payload_strb; + wire axiShared_w_payload_last; + wire axiShared_b_valid; + wire axiShared_b_ready; + wire [1:0] axiShared_b_payload_resp; + wire axiShared_r_valid; + wire axiShared_r_ready; + wire [31:0] axiShared_r_payload_data; + wire [1:0] axiShared_r_payload_resp; + wire axiShared_r_payload_last; + wire bmbPeripheral_bmb_cmd_valid; + wire bmbPeripheral_bmb_cmd_ready; + wire bmbPeripheral_bmb_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_rsp_valid; + wire bmbPeripheral_bmb_rsp_ready; + wire bmbPeripheral_bmb_rsp_payload_last; + wire [0:0] bmbPeripheral_bmb_rsp_payload_fragment_opcode; + wire [31:0] bmbPeripheral_bmb_rsp_payload_fragment_data; + wire [2:0] bmbPeripheral_bmb_rsp_payload_fragment_context; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_gpio_0_io_interrupts_0_source; + wire system_gpio_0_io_interrupts_1_source; + wire system_gpio_0_io_interrupts_2; + wire system_gpio_0_io_interrupts_3; + wire system_watchdog_logic_panics_0_source; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire _zz_io_bus_rsp_ready; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last; + wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode; + wire [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address; + wire [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length; + wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data; + wire [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context; + reg system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire; + reg system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + reg [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + reg [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + reg [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + reg [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + reg [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + wire _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + reg _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + reg _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + reg [0:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + reg [31:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + reg [2:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last; + wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode; + wire [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address; + wire [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length; + wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data; + wire [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context; + reg system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire; + reg system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + reg [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + reg [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + reg [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + reg [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + reg [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [7:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last; + wire [0:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode; + wire [7:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address; + wire [1:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length; + wire [31:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data; + wire [2:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context; + reg system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire; + reg system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + reg [0:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + reg [7:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + reg [1:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + reg [31:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + reg [2:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [7:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [7:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [15:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire bmbPeripheral_bmb_withoutMask_cmd_valid; + wire bmbPeripheral_bmb_withoutMask_cmd_ready; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_withoutMask_rsp_valid; + wire bmbPeripheral_bmb_withoutMask_rsp_ready; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context; + wire bmbPeripheral_bmb_withoutMask_cmd_valid_1; + wire bmbPeripheral_bmb_withoutMask_cmd_ready_1; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_1; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1; + wire bmbPeripheral_bmb_withoutMask_rsp_valid_1; + wire bmbPeripheral_bmb_withoutMask_rsp_ready_1; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_1; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1; + wire bmbPeripheral_bmb_withoutMask_cmd_valid_2; + wire bmbPeripheral_bmb_withoutMask_cmd_ready_2; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_2; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2; + wire bmbPeripheral_bmb_withoutMask_rsp_valid_2; + wire bmbPeripheral_bmb_withoutMask_rsp_ready_2; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_2; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2; + wire bmbPeripheral_bmb_withoutMask_cmd_valid_3; + wire bmbPeripheral_bmb_withoutMask_cmd_ready_3; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_3; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3; + wire bmbPeripheral_bmb_withoutMask_rsp_valid_3; + wire bmbPeripheral_bmb_withoutMask_rsp_ready_3; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_3; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3; + wire bmbPeripheral_bmb_withoutMask_cmd_valid_4; + wire bmbPeripheral_bmb_withoutMask_cmd_ready_4; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_4; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4; + wire bmbPeripheral_bmb_withoutMask_rsp_valid_4; + wire bmbPeripheral_bmb_withoutMask_rsp_ready_4; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_4; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4; + wire bmbPeripheral_bmb_withoutMask_cmd_valid_5; + wire bmbPeripheral_bmb_withoutMask_cmd_ready_5; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_5; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_5; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_5; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_5; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_5; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_5; + wire bmbPeripheral_bmb_withoutMask_rsp_valid_5; + wire bmbPeripheral_bmb_withoutMask_rsp_ready_5; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_5; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_5; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_5; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_5; + + Axi4PeripheralStreamArbiter_be6ad777990c4e5089d0b11c63cc2698 streamArbiter ( + .io_inputs_0_valid (axi_ar_halfPipe_valid ), //i + .io_inputs_0_ready (streamArbiter_io_inputs_0_ready ), //o + .io_inputs_0_payload_addr (axi_ar_halfPipe_payload_addr[23:0] ), //i + .io_inputs_0_payload_len (axi_ar_halfPipe_payload_len[7:0] ), //i + .io_inputs_0_payload_size (axi_ar_halfPipe_payload_size[2:0] ), //i + .io_inputs_0_payload_cache (axi_ar_halfPipe_payload_cache[3:0] ), //i + .io_inputs_0_payload_prot (axi_ar_halfPipe_payload_prot[2:0] ), //i + .io_inputs_1_valid (axi_aw_halfPipe_valid ), //i + .io_inputs_1_ready (streamArbiter_io_inputs_1_ready ), //o + .io_inputs_1_payload_addr (axi_aw_halfPipe_payload_addr[23:0] ), //i + .io_inputs_1_payload_len (axi_aw_halfPipe_payload_len[7:0] ), //i + .io_inputs_1_payload_size (axi_aw_halfPipe_payload_size[2:0] ), //i + .io_inputs_1_payload_cache (axi_aw_halfPipe_payload_cache[3:0] ), //i + .io_inputs_1_payload_prot (axi_aw_halfPipe_payload_prot[2:0] ), //i + .io_output_valid (streamArbiter_io_output_valid ), //o + .io_output_ready (axiShared_arw_ready ), //i + .io_output_payload_addr (streamArbiter_io_output_payload_addr[23:0]), //o + .io_output_payload_len (streamArbiter_io_output_payload_len[7:0] ), //o + .io_output_payload_size (streamArbiter_io_output_payload_size[2:0] ), //o + .io_output_payload_cache (streamArbiter_io_output_payload_cache[3:0]), //o + .io_output_payload_prot (streamArbiter_io_output_payload_prot[2:0] ), //o + .io_chosen (streamArbiter_io_chosen ), //o + .io_chosenOH (streamArbiter_io_chosenOH[1:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralAxi4SharedToBmb_be6ad777990c4e5089d0b11c63cc2698 axiToBmb ( + .io_axi_arw_valid (axiShared_arw_valid ), //i + .io_axi_arw_ready (axiToBmb_io_axi_arw_ready ), //o + .io_axi_arw_payload_addr (axiShared_arw_payload_addr[23:0] ), //i + .io_axi_arw_payload_len (axiShared_arw_payload_len[7:0] ), //i + .io_axi_arw_payload_size (axiShared_arw_payload_size[2:0] ), //i + .io_axi_arw_payload_cache (axiShared_arw_payload_cache[3:0] ), //i + .io_axi_arw_payload_prot (axiShared_arw_payload_prot[2:0] ), //i + .io_axi_arw_payload_write (axiShared_arw_payload_write ), //i + .io_axi_w_valid (axiShared_w_valid ), //i + .io_axi_w_ready (axiToBmb_io_axi_w_ready ), //o + .io_axi_w_payload_data (axiShared_w_payload_data[31:0] ), //i + .io_axi_w_payload_strb (axiShared_w_payload_strb[3:0] ), //i + .io_axi_w_payload_last (axiShared_w_payload_last ), //i + .io_axi_b_valid (axiToBmb_io_axi_b_valid ), //o + .io_axi_b_ready (axiShared_b_ready ), //i + .io_axi_b_payload_resp (axiToBmb_io_axi_b_payload_resp[1:0] ), //o + .io_axi_r_valid (axiToBmb_io_axi_r_valid ), //o + .io_axi_r_ready (axiShared_r_ready ), //i + .io_axi_r_payload_data (axiToBmb_io_axi_r_payload_data[31:0] ), //o + .io_axi_r_payload_resp (axiToBmb_io_axi_r_payload_resp[1:0] ), //o + .io_axi_r_payload_last (axiToBmb_io_axi_r_payload_last ), //o + .io_bmb_cmd_valid (axiToBmb_io_bmb_cmd_valid ), //o + .io_bmb_cmd_ready (bmbHandle_decoder_io_input_cmd_ready ), //i + .io_bmb_cmd_payload_last (axiToBmb_io_bmb_cmd_payload_last ), //o + .io_bmb_cmd_payload_fragment_source (axiToBmb_io_bmb_cmd_payload_fragment_source ), //o + .io_bmb_cmd_payload_fragment_opcode (axiToBmb_io_bmb_cmd_payload_fragment_opcode ), //o + .io_bmb_cmd_payload_fragment_address (axiToBmb_io_bmb_cmd_payload_fragment_address[23:0] ), //o + .io_bmb_cmd_payload_fragment_length (axiToBmb_io_bmb_cmd_payload_fragment_length[9:0] ), //o + .io_bmb_cmd_payload_fragment_data (axiToBmb_io_bmb_cmd_payload_fragment_data[31:0] ), //o + .io_bmb_cmd_payload_fragment_mask (axiToBmb_io_bmb_cmd_payload_fragment_mask[3:0] ), //o + .io_bmb_rsp_valid (bmbHandle_decoder_io_input_rsp_valid ), //i + .io_bmb_rsp_ready (axiToBmb_io_bmb_rsp_ready ), //o + .io_bmb_rsp_payload_last (bmbHandle_decoder_io_input_rsp_payload_last ), //i + .io_bmb_rsp_payload_fragment_source (bmbHandle_decoder_io_input_rsp_payload_fragment_source ), //i + .io_bmb_rsp_payload_fragment_opcode (bmbHandle_decoder_io_input_rsp_payload_fragment_opcode ), //i + .io_bmb_rsp_payload_fragment_data (bmbHandle_decoder_io_input_rsp_payload_fragment_data[31:0]) //i + ); + Axi4PeripheralBmbDecoder_be6ad777990c4e5089d0b11c63cc2698 bmbHandle_decoder ( + .io_input_cmd_valid (axiToBmb_io_bmb_cmd_valid ), //i + .io_input_cmd_ready (bmbHandle_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (axiToBmb_io_bmb_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (axiToBmb_io_bmb_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (axiToBmb_io_bmb_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (axiToBmb_io_bmb_cmd_payload_fragment_address[23:0] ), //i + .io_input_cmd_payload_fragment_length (axiToBmb_io_bmb_cmd_payload_fragment_length[9:0] ), //i + .io_input_cmd_payload_fragment_data (axiToBmb_io_bmb_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (axiToBmb_io_bmb_cmd_payload_fragment_mask[3:0] ), //i + .io_input_rsp_valid (bmbHandle_decoder_io_input_rsp_valid ), //o + .io_input_rsp_ready (axiToBmb_io_bmb_rsp_ready ), //i + .io_input_rsp_payload_last (bmbHandle_decoder_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (bmbHandle_decoder_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (bmbHandle_decoder_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (bmbHandle_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_valid (bmbHandle_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (bmbHandle_unburstify_io_input_cmd_ready ), //i + .io_outputs_0_cmd_payload_last (bmbHandle_decoder_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_source (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_source ), //o + .io_outputs_0_cmd_payload_fragment_opcode (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_address[23:0]), //o + .io_outputs_0_cmd_payload_fragment_length (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_length[9:0] ), //o + .io_outputs_0_cmd_payload_fragment_data (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_mask (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_0_rsp_valid (bmbHandle_unburstify_io_input_rsp_valid ), //i + .io_outputs_0_rsp_ready (bmbHandle_decoder_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (bmbHandle_unburstify_io_input_rsp_payload_last ), //i + .io_outputs_0_rsp_payload_fragment_source (bmbHandle_unburstify_io_input_rsp_payload_fragment_source ), //i + .io_outputs_0_rsp_payload_fragment_opcode (bmbHandle_unburstify_io_input_rsp_payload_fragment_opcode ), //i + .io_outputs_0_rsp_payload_fragment_data (bmbHandle_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbUnburstify_be6ad777990c4e5089d0b11c63cc2698 bmbHandle_unburstify ( + .io_input_cmd_valid (bmbHandle_decoder_io_outputs_0_cmd_valid ), //i + .io_input_cmd_ready (bmbHandle_unburstify_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (bmbHandle_decoder_io_outputs_0_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_address[23:0] ), //i + .io_input_cmd_payload_fragment_length (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_length[9:0] ), //i + .io_input_cmd_payload_fragment_data (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //i + .io_input_rsp_valid (bmbHandle_unburstify_io_input_rsp_valid ), //o + .io_input_rsp_ready (bmbHandle_decoder_io_outputs_0_rsp_ready ), //i + .io_input_rsp_payload_last (bmbHandle_unburstify_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (bmbHandle_unburstify_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (bmbHandle_unburstify_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (bmbHandle_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_output_cmd_valid (bmbHandle_unburstify_io_output_cmd_valid ), //o + .io_output_cmd_ready (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i + .io_output_cmd_payload_last (bmbHandle_unburstify_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (bmbHandle_unburstify_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (bmbHandle_unburstify_io_output_cmd_payload_fragment_address[23:0] ), //o + .io_output_cmd_payload_fragment_length (bmbHandle_unburstify_io_output_cmd_payload_fragment_length[1:0] ), //o + .io_output_cmd_payload_fragment_data (bmbHandle_unburstify_io_output_cmd_payload_fragment_data[31:0] ), //o + .io_output_cmd_payload_fragment_mask (bmbHandle_unburstify_io_output_cmd_payload_fragment_mask[3:0] ), //o + .io_output_cmd_payload_fragment_context (bmbHandle_unburstify_io_output_cmd_payload_fragment_context[2:0] ), //o + .io_output_rsp_valid (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i + .io_output_rsp_ready (bmbHandle_unburstify_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0] ), //i + .io_output_rsp_payload_fragment_context (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context[2:0]), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbDecoder_1_be6ad777990c4e5089d0b11c63cc2698 bmbPeripheral_bmb_decoder ( + .io_input_cmd_valid (bmbPeripheral_bmb_cmd_valid ), //i + .io_input_cmd_ready (bmbPeripheral_bmb_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (bmbPeripheral_bmb_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (bmbPeripheral_bmb_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (bmbPeripheral_bmb_cmd_payload_fragment_address[23:0] ), //i + .io_input_cmd_payload_fragment_length (bmbPeripheral_bmb_cmd_payload_fragment_length[1:0] ), //i + .io_input_cmd_payload_fragment_data (bmbPeripheral_bmb_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (bmbPeripheral_bmb_cmd_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (bmbPeripheral_bmb_cmd_payload_fragment_context[2:0] ), //i + .io_input_rsp_valid (bmbPeripheral_bmb_decoder_io_input_rsp_valid ), //o + .io_input_rsp_ready (bmbPeripheral_bmb_rsp_ready ), //i + .io_input_rsp_payload_last (bmbPeripheral_bmb_decoder_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context[2:0] ), //o + .io_outputs_0_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready ), //i + .io_outputs_0_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[23:0]), //o + .io_outputs_0_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_0_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_0_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_0_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid ), //i + .io_outputs_0_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last ), //i + .io_outputs_0_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode ), //i + .io_outputs_0_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data[31:0] ), //i + .io_outputs_0_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context[2:0] ), //i + .io_outputs_1_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid ), //o + .io_outputs_1_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_1 ), //i + .io_outputs_1_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last ), //o + .io_outputs_1_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //o + .io_outputs_1_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[23:0]), //o + .io_outputs_1_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_1_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_1_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_1_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_1_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_1 ), //i + .io_outputs_1_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready ), //o + .io_outputs_1_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 ), //i + .io_outputs_1_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 ), //i + .io_outputs_1_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1[31:0] ), //i + .io_outputs_1_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1[2:0] ), //i + .io_outputs_2_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid ), //o + .io_outputs_2_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_2 ), //i + .io_outputs_2_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last ), //o + .io_outputs_2_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode ), //o + .io_outputs_2_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address[23:0]), //o + .io_outputs_2_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_2_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_2_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_2_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_2_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_2 ), //i + .io_outputs_2_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready ), //o + .io_outputs_2_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 ), //i + .io_outputs_2_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 ), //i + .io_outputs_2_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2[31:0] ), //i + .io_outputs_2_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2[2:0] ), //i + .io_outputs_3_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid ), //o + .io_outputs_3_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_3 ), //i + .io_outputs_3_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last ), //o + .io_outputs_3_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode ), //o + .io_outputs_3_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address[23:0]), //o + .io_outputs_3_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_3_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_3_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_3_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_3_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_3 ), //i + .io_outputs_3_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready ), //o + .io_outputs_3_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 ), //i + .io_outputs_3_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 ), //i + .io_outputs_3_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3[31:0] ), //i + .io_outputs_3_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3[2:0] ), //i + .io_outputs_4_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid ), //o + .io_outputs_4_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_4 ), //i + .io_outputs_4_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last ), //o + .io_outputs_4_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode ), //o + .io_outputs_4_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address[23:0]), //o + .io_outputs_4_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_4_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_4_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_4_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_4_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_4 ), //i + .io_outputs_4_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready ), //o + .io_outputs_4_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 ), //i + .io_outputs_4_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 ), //i + .io_outputs_4_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4[31:0] ), //i + .io_outputs_4_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4[2:0] ), //i + .io_outputs_5_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_valid ), //o + .io_outputs_5_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_5 ), //i + .io_outputs_5_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_last ), //o + .io_outputs_5_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_opcode ), //o + .io_outputs_5_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_address[23:0]), //o + .io_outputs_5_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_5_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_5_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_5_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_5_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_5 ), //i + .io_outputs_5_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_5_rsp_ready ), //o + .io_outputs_5_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_5 ), //i + .io_outputs_5_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_5 ), //i + .io_outputs_5_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_5[31:0] ), //i + .io_outputs_5_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_5[2:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbUartCtrl_be6ad777990c4e5089d0b11c63cc2698 system_uart_0_io_logic ( + .io_bus_cmd_valid (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i + .io_bus_cmd_ready (system_uart_0_io_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[5:0]), //i + .io_bus_cmd_payload_fragment_length (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_context (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[2:0]), //i + .io_bus_rsp_valid (system_uart_0_io_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (_zz_io_bus_rsp_ready ), //i + .io_bus_rsp_payload_last (system_uart_0_io_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_uart_0_io_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_uart_0_io_logic_io_bus_rsp_payload_fragment_context[2:0] ), //o + .io_uart_txd (system_uart_0_io_logic_io_uart_txd ), //o + .io_uart_rxd (system_uart_0_io_rxd ), //i + .system_uart_0_io_interrupt_source (system_uart_0_io_logic_system_uart_0_io_interrupt_source ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbSpiXdrMasterCtrl_be6ad777990c4e5089d0b11c63cc2698 system_spi_0_io_logic ( + .io_ctrl_cmd_valid (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i + .io_ctrl_cmd_ready (system_spi_0_io_logic_io_ctrl_cmd_ready ), //o + .io_ctrl_cmd_payload_last (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i + .io_ctrl_cmd_payload_fragment_opcode (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i + .io_ctrl_cmd_payload_fragment_address (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[11:0]), //i + .io_ctrl_cmd_payload_fragment_length (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i + .io_ctrl_cmd_payload_fragment_data (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i + .io_ctrl_cmd_payload_fragment_context (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[2:0] ), //i + .io_ctrl_rsp_valid (system_spi_0_io_logic_io_ctrl_rsp_valid ), //o + .io_ctrl_rsp_ready (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_ctrl_rsp_payload_last (system_spi_0_io_logic_io_ctrl_rsp_payload_last ), //o + .io_ctrl_rsp_payload_fragment_opcode (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode ), //o + .io_ctrl_rsp_payload_fragment_data (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data[31:0] ), //o + .io_ctrl_rsp_payload_fragment_context (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context[2:0] ), //o + .io_spi_sclk_write (system_spi_0_io_logic_io_spi_sclk_write ), //o + .io_spi_data_0_writeEnable (system_spi_0_io_logic_io_spi_data_0_writeEnable ), //o + .io_spi_data_0_read (system_spi_0_io_data_0_read ), //i + .io_spi_data_0_write (system_spi_0_io_logic_io_spi_data_0_write ), //o + .io_spi_data_1_writeEnable (system_spi_0_io_logic_io_spi_data_1_writeEnable ), //o + .io_spi_data_1_read (system_spi_0_io_data_1_read ), //i + .io_spi_data_1_write (system_spi_0_io_logic_io_spi_data_1_write ), //o + .io_spi_data_2_writeEnable (system_spi_0_io_logic_io_spi_data_2_writeEnable ), //o + .io_spi_data_2_read (system_spi_0_io_data_2_read ), //i + .io_spi_data_2_write (system_spi_0_io_logic_io_spi_data_2_write ), //o + .io_spi_data_3_writeEnable (system_spi_0_io_logic_io_spi_data_3_writeEnable ), //o + .io_spi_data_3_read (system_spi_0_io_data_3_read ), //i + .io_spi_data_3_write (system_spi_0_io_logic_io_spi_data_3_write ), //o + .io_spi_ss (system_spi_0_io_logic_io_spi_ss[3:0] ), //o + .system_spi_0_io_interrupt_source (system_spi_0_io_logic_system_spi_0_io_interrupt_source ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbI2cCtrl_be6ad777990c4e5089d0b11c63cc2698 system_i2c_0_io_logic ( + .io_ctrl_cmd_valid (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i + .io_ctrl_cmd_ready (system_i2c_0_io_logic_io_ctrl_cmd_ready ), //o + .io_ctrl_cmd_payload_last (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i + .io_ctrl_cmd_payload_fragment_opcode (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i + .io_ctrl_cmd_payload_fragment_address (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[7:0]), //i + .io_ctrl_cmd_payload_fragment_length (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i + .io_ctrl_cmd_payload_fragment_data (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i + .io_ctrl_cmd_payload_fragment_context (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[2:0]), //i + .io_ctrl_rsp_valid (system_i2c_0_io_logic_io_ctrl_rsp_valid ), //o + .io_ctrl_rsp_ready (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_ctrl_rsp_payload_last (system_i2c_0_io_logic_io_ctrl_rsp_payload_last ), //o + .io_ctrl_rsp_payload_fragment_opcode (system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_opcode ), //o + .io_ctrl_rsp_payload_fragment_data (system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_data[31:0] ), //o + .io_ctrl_rsp_payload_fragment_context (system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_context[2:0] ), //o + .io_i2c_sda_write (system_i2c_0_io_logic_io_i2c_sda_write ), //o + .io_i2c_sda_read (system_i2c_0_io_sda_read ), //i + .io_i2c_scl_write (system_i2c_0_io_logic_io_i2c_scl_write ), //o + .io_i2c_scl_read (system_i2c_0_io_scl_read ), //i + .system_i2c_0_io_interrupt_source (system_i2c_0_io_logic_system_i2c_0_io_interrupt_source ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbGpio2_be6ad777990c4e5089d0b11c63cc2698 system_gpio_0_io_logic ( + .io_gpio_read (system_gpio_0_io_read[3:0] ), //i + .io_gpio_write (system_gpio_0_io_logic_io_gpio_write[3:0] ), //o + .io_gpio_writeEnable (system_gpio_0_io_logic_io_gpio_writeEnable[3:0] ), //o + .io_bus_cmd_valid (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i + .io_bus_cmd_ready (system_gpio_0_io_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[7:0]), //i + .io_bus_cmd_payload_fragment_length (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_context (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[2:0]), //i + .io_bus_rsp_valid (system_gpio_0_io_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_bus_rsp_payload_last (system_gpio_0_io_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_gpio_0_io_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_gpio_0_io_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_gpio_0_io_logic_io_bus_rsp_payload_fragment_context[2:0] ), //o + .io_interrupt (system_gpio_0_io_logic_io_interrupt[3:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbWatchdog_be6ad777990c4e5089d0b11c63cc2698 system_watchdog_logic_logic ( + .io_bus_cmd_valid (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i + .io_bus_cmd_ready (system_watchdog_logic_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[7:0]), //i + .io_bus_cmd_payload_fragment_length (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_context (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[2:0]), //i + .io_bus_rsp_valid (system_watchdog_logic_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_bus_rsp_payload_last (system_watchdog_logic_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_watchdog_logic_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_watchdog_logic_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_watchdog_logic_logic_io_bus_rsp_payload_fragment_context[2:0] ), //o + .io_panics (system_watchdog_logic_logic_io_panics[1:0] ), //o + .io_heartBeat (1'b0 ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbToApb3Bridge_be6ad777990c4e5089d0b11c63cc2698 io_apbSlave_0_logic ( + .io_input_cmd_valid (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i + .io_input_cmd_ready (io_apbSlave_0_logic_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[15:0]), //i + .io_input_cmd_payload_fragment_length (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i + .io_input_cmd_payload_fragment_data (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_context (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[2:0] ), //i + .io_input_rsp_valid (io_apbSlave_0_logic_io_input_rsp_valid ), //o + .io_input_rsp_ready (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_input_rsp_payload_last (io_apbSlave_0_logic_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (io_apbSlave_0_logic_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (io_apbSlave_0_logic_io_input_rsp_payload_fragment_context[2:0] ), //o + .io_output_PADDR (io_apbSlave_0_logic_io_output_PADDR[15:0] ), //o + .io_output_PSEL (io_apbSlave_0_logic_io_output_PSEL ), //o + .io_output_PENABLE (io_apbSlave_0_logic_io_output_PENABLE ), //o + .io_output_PREADY (io_apbSlave_0_PREADY ), //i + .io_output_PWRITE (io_apbSlave_0_logic_io_output_PWRITE ), //o + .io_output_PWDATA (io_apbSlave_0_logic_io_output_PWDATA[31:0] ), //o + .io_output_PRDATA (io_apbSlave_0_PRDATA[31:0] ), //i + .io_output_PSLVERROR (io_apbSlave_0_PSLVERROR ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign axi_aw_halfPipe_fire = (axi_aw_halfPipe_valid && axi_aw_halfPipe_ready); + assign axi_awready = (! axi_aw_rValid); + assign axi_aw_halfPipe_valid = axi_aw_rValid; + assign axi_aw_halfPipe_payload_addr = axi_aw_rData_addr; + assign axi_aw_halfPipe_payload_len = axi_aw_rData_len; + assign axi_aw_halfPipe_payload_size = axi_aw_rData_size; + assign axi_aw_halfPipe_payload_cache = axi_aw_rData_cache; + assign axi_aw_halfPipe_payload_prot = axi_aw_rData_prot; + assign axi_aw_halfPipe_ready = streamArbiter_io_inputs_1_ready; + assign axi_w_halfPipe_fire = (axi_w_halfPipe_valid && axi_w_halfPipe_ready); + assign axi_wready = (! axi_w_rValid); + assign axi_w_halfPipe_valid = axi_w_rValid; + assign axi_w_halfPipe_payload_data = axi_w_rData_data; + assign axi_w_halfPipe_payload_strb = axi_w_rData_strb; + assign axi_w_halfPipe_payload_last = axi_w_rData_last; + assign axi_w_halfPipe_ready = axiShared_w_ready; + assign _zz_axiShared_b_ready = (! _zz_axi_bvalid_1); + assign _zz_axi_bvalid = _zz_axi_bvalid_1; + assign axi_bvalid = _zz_axi_bvalid; + assign axi_bresp = _zz_axi_bresp; + assign axi_ar_halfPipe_fire = (axi_ar_halfPipe_valid && axi_ar_halfPipe_ready); + assign axi_arready = (! axi_ar_rValid); + assign axi_ar_halfPipe_valid = axi_ar_rValid; + assign axi_ar_halfPipe_payload_addr = axi_ar_rData_addr; + assign axi_ar_halfPipe_payload_len = axi_ar_rData_len; + assign axi_ar_halfPipe_payload_size = axi_ar_rData_size; + assign axi_ar_halfPipe_payload_cache = axi_ar_rData_cache; + assign axi_ar_halfPipe_payload_prot = axi_ar_rData_prot; + assign axi_ar_halfPipe_ready = streamArbiter_io_inputs_0_ready; + assign _zz_axiShared_r_ready = (! _zz_axi_rvalid_1); + assign _zz_axi_rvalid = _zz_axi_rvalid_1; + assign axi_rvalid = _zz_axi_rvalid; + assign axi_rdata = _zz_axi_rdata; + assign axi_rresp = _zz_axi_rresp; + assign axi_rlast = _zz_axi_rlast; + assign axiShared_arw_valid = streamArbiter_io_output_valid; + assign axiShared_arw_payload_addr = streamArbiter_io_output_payload_addr; + assign axiShared_arw_payload_len = streamArbiter_io_output_payload_len; + assign axiShared_arw_payload_size = streamArbiter_io_output_payload_size; + assign axiShared_arw_payload_cache = streamArbiter_io_output_payload_cache; + assign axiShared_arw_payload_prot = streamArbiter_io_output_payload_prot; + assign axiShared_arw_payload_write = streamArbiter_io_chosenOH[1]; + assign axiShared_w_valid = axi_w_halfPipe_valid; + assign axiShared_w_payload_data = axi_w_halfPipe_payload_data; + assign axiShared_w_payload_strb = axi_w_halfPipe_payload_strb; + assign axiShared_w_payload_last = axi_w_halfPipe_payload_last; + assign axiShared_b_ready = _zz_axiShared_b_ready; + assign axiShared_r_ready = _zz_axiShared_r_ready; + assign axiShared_arw_ready = axiToBmb_io_axi_arw_ready; + assign axiShared_w_ready = axiToBmb_io_axi_w_ready; + assign axiShared_b_valid = axiToBmb_io_axi_b_valid; + assign axiShared_b_payload_resp = axiToBmb_io_axi_b_payload_resp; + assign axiShared_r_valid = axiToBmb_io_axi_r_valid; + assign axiShared_r_payload_data = axiToBmb_io_axi_r_payload_data; + assign axiShared_r_payload_last = axiToBmb_io_axi_r_payload_last; + assign axiShared_r_payload_resp = axiToBmb_io_axi_r_payload_resp; + assign bmbPeripheral_bmb_cmd_valid = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = bmbPeripheral_bmb_cmd_ready; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = bmbPeripheral_bmb_rsp_valid; + assign bmbPeripheral_bmb_rsp_ready = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign bmbPeripheral_bmb_cmd_payload_last = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = bmbPeripheral_bmb_rsp_payload_last; + assign bmbPeripheral_bmb_cmd_payload_fragment_opcode = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_cmd_payload_fragment_address = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_cmd_payload_fragment_length = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_cmd_payload_fragment_data = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_cmd_payload_fragment_mask = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign bmbPeripheral_bmb_cmd_payload_fragment_context = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = bmbPeripheral_bmb_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = bmbPeripheral_bmb_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = bmbPeripheral_bmb_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbHandle_unburstify_io_output_cmd_valid; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbHandle_unburstify_io_output_rsp_ready; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbHandle_unburstify_io_output_cmd_payload_last; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbHandle_unburstify_io_output_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbHandle_unburstify_io_output_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbHandle_unburstify_io_output_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbHandle_unburstify_io_output_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = bmbHandle_unburstify_io_output_cmd_payload_fragment_mask; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbHandle_unburstify_io_output_cmd_payload_fragment_context; + assign bmbPeripheral_bmb_cmd_ready = bmbPeripheral_bmb_decoder_io_input_cmd_ready; + assign bmbPeripheral_bmb_rsp_valid = bmbPeripheral_bmb_decoder_io_input_rsp_valid; + assign bmbPeripheral_bmb_rsp_payload_last = bmbPeripheral_bmb_decoder_io_input_rsp_payload_last; + assign bmbPeripheral_bmb_rsp_payload_fragment_opcode = bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_rsp_payload_fragment_data = bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_rsp_payload_fragment_context = bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context; + assign system_uart_0_io_txd = system_uart_0_io_logic_io_uart_txd; + assign system_i2c_0_io_sda_write = system_i2c_0_io_logic_io_i2c_sda_write; + assign system_i2c_0_io_scl_write = system_i2c_0_io_logic_io_i2c_scl_write; + assign system_gpio_0_io_write = system_gpio_0_io_logic_io_gpio_write; + assign system_gpio_0_io_writeEnable = system_gpio_0_io_logic_io_gpio_writeEnable; + assign system_gpio_0_io_interrupts_0_source = system_gpio_0_io_logic_io_interrupt[0]; + assign system_gpio_0_io_interrupts_1_source = system_gpio_0_io_logic_io_interrupt[1]; + assign system_gpio_0_io_interrupts_2 = system_gpio_0_io_logic_io_interrupt[2]; + assign system_gpio_0_io_interrupts_3 = system_gpio_0_io_logic_io_interrupt[3]; + assign system_watchdog_logic_panics_0_source = system_watchdog_logic_logic_io_panics[0]; + assign io_apbSlave_0_PADDR = io_apbSlave_0_logic_io_output_PADDR; + assign io_apbSlave_0_PSEL = io_apbSlave_0_logic_io_output_PSEL; + assign io_apbSlave_0_PENABLE = io_apbSlave_0_logic_io_output_PENABLE; + assign io_apbSlave_0_PWRITE = io_apbSlave_0_logic_io_output_PWRITE; + assign io_apbSlave_0_PWDATA = io_apbSlave_0_logic_io_output_PWDATA; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_uart_0_io_logic_io_bus_cmd_ready; + assign _zz_io_bus_rsp_ready = (! _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1); + assign _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_uart_0_io_interrupt = system_uart_0_io_logic_system_uart_0_io_interrupt_source; + assign system_spi_0_io_interrupt = system_spi_0_io_logic_system_spi_0_io_interrupt_source; + assign system_spi_0_io_sclk_write = system_spi_0_io_logic_io_spi_sclk_write; + assign system_spi_0_io_data_0_writeEnable = system_spi_0_io_logic_io_spi_data_0_writeEnable; + assign system_spi_0_io_data_0_write = system_spi_0_io_logic_io_spi_data_0_write; + assign system_spi_0_io_data_1_writeEnable = system_spi_0_io_logic_io_spi_data_1_writeEnable; + assign system_spi_0_io_data_1_write = system_spi_0_io_logic_io_spi_data_1_write; + assign system_spi_0_io_data_2_writeEnable = system_spi_0_io_logic_io_spi_data_2_writeEnable; + assign system_spi_0_io_data_2_write = system_spi_0_io_logic_io_spi_data_2_write; + assign system_spi_0_io_data_3_writeEnable = system_spi_0_io_logic_io_spi_data_3_writeEnable; + assign system_spi_0_io_data_3_write = system_spi_0_io_logic_io_spi_data_3_write; + assign system_spi_0_io_ss = system_spi_0_io_logic_io_spi_ss; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_spi_0_io_logic_io_ctrl_cmd_ready; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_spi_0_io_logic_io_ctrl_rsp_valid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_spi_0_io_logic_io_ctrl_rsp_payload_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_i2c_0_io_logic_io_ctrl_cmd_ready; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_i2c_0_io_logic_io_ctrl_rsp_valid; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_i2c_0_io_logic_io_ctrl_rsp_payload_last; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_data; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_context; + assign system_i2c_0_io_interrupt = system_i2c_0_io_logic_system_i2c_0_io_interrupt_source; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_gpio_0_io_logic_io_bus_cmd_ready; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_gpio_0_io_logic_io_bus_rsp_valid; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_gpio_0_io_logic_io_bus_rsp_payload_last; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_gpio_0_io_logic_io_bus_rsp_payload_fragment_opcode; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_gpio_0_io_logic_io_bus_rsp_payload_fragment_data; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_gpio_0_io_logic_io_bus_rsp_payload_fragment_context; + assign system_gpio_0_io_interrupts_0 = system_gpio_0_io_interrupts_0_source; + assign system_gpio_0_io_interrupts_1 = system_gpio_0_io_interrupts_1_source; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_watchdog_logic_logic_io_bus_cmd_ready; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_watchdog_logic_logic_io_bus_rsp_valid; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_watchdog_logic_logic_io_bus_rsp_payload_last; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_watchdog_logic_logic_io_bus_rsp_payload_fragment_opcode; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_watchdog_logic_logic_io_bus_rsp_payload_fragment_data; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_watchdog_logic_logic_io_bus_rsp_payload_fragment_context; + assign system_watchdog_logic_panics_0 = system_watchdog_logic_panics_0_source; + assign system_watchdog_hardPanic_reset = system_watchdog_logic_logic_io_panics[1]; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = io_apbSlave_0_logic_io_input_cmd_ready; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = io_apbSlave_0_logic_io_input_rsp_valid; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = io_apbSlave_0_logic_io_input_rsp_payload_last; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = io_apbSlave_0_logic_io_input_rsp_payload_fragment_data; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = io_apbSlave_0_logic_io_input_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready = bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_cmd_ready = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address[5:0]; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready_1 = bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_1; + assign bmbPeripheral_bmb_withoutMask_cmd_ready_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_1; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_1; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1[11:0]; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready_2 = bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_2; + assign bmbPeripheral_bmb_withoutMask_cmd_ready_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_2; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_2; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2[7:0]; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready_3 = bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_3; + assign bmbPeripheral_bmb_withoutMask_cmd_ready_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_3; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_3; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3[7:0]; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready_4 = bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_4; + assign bmbPeripheral_bmb_withoutMask_cmd_ready_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_4; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_4; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4[7:0]; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready_5 = bmbPeripheral_bmb_decoder_io_outputs_5_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_context; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_5; + assign bmbPeripheral_bmb_withoutMask_cmd_ready_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_5; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_5; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_5; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_5[15:0]; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_5; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_5; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_5; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + always @(posedge clk) begin + if(reset) begin + axi_aw_rValid <= 1'b0; + axi_w_rValid <= 1'b0; + _zz_axi_bvalid_1 <= 1'b0; + axi_ar_rValid <= 1'b0; + _zz_axi_rvalid_1 <= 1'b0; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end else begin + if(axi_awvalid) begin + axi_aw_rValid <= 1'b1; + end + if(axi_aw_halfPipe_fire) begin + axi_aw_rValid <= 1'b0; + end + if(axi_wvalid) begin + axi_w_rValid <= 1'b1; + end + if(axi_w_halfPipe_fire) begin + axi_w_rValid <= 1'b0; + end + if(axiShared_b_valid) begin + _zz_axi_bvalid_1 <= 1'b1; + end + if((_zz_axi_bvalid && axi_bready)) begin + _zz_axi_bvalid_1 <= 1'b0; + end + if(axi_arvalid) begin + axi_ar_rValid <= 1'b1; + end + if(axi_ar_halfPipe_fire) begin + axi_ar_rValid <= 1'b0; + end + if(axiShared_r_valid) begin + _zz_axi_rvalid_1 <= 1'b1; + end + if((_zz_axi_rvalid && axi_rready)) begin + _zz_axi_rvalid_1 <= 1'b0; + end + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + if(system_uart_0_io_logic_io_bus_rsp_valid) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b1; + end + if((_zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready)) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + if(system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + end + end + + always @(posedge clk) begin + if(axi_awready) begin + axi_aw_rData_addr <= axi_awaddr; + axi_aw_rData_len <= axi_awlen; + axi_aw_rData_size <= axi_awsize; + axi_aw_rData_cache <= axi_awcache; + axi_aw_rData_prot <= axi_awprot; + end + if(axi_wready) begin + axi_w_rData_data <= axi_wdata; + axi_w_rData_strb <= axi_wstrb; + axi_w_rData_last <= axi_wlast; + end + if(_zz_axiShared_b_ready) begin + _zz_axi_bresp <= axiShared_b_payload_resp; + end + if(axi_arready) begin + axi_ar_rData_addr <= axi_araddr; + axi_ar_rData_len <= axi_arlen; + axi_ar_rData_size <= axi_arsize; + axi_ar_rData_cache <= axi_arcache; + axi_ar_rData_prot <= axi_arprot; + end + if(_zz_axiShared_r_ready) begin + _zz_axi_rdata <= axiShared_r_payload_data; + _zz_axi_rresp <= axiShared_r_payload_resp; + _zz_axi_rlast <= axiShared_r_payload_last; + end + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + if(_zz_io_bus_rsp_ready) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_uart_0_io_logic_io_bus_rsp_payload_last; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_data; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_context; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + if(system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + end + + +endmodule + +module Axi4PeripheralBmbToApb3Bridge_be6ad777990c4e5089d0b11c63cc2698 ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [15:0] io_input_cmd_payload_fragment_address, + input wire [1:0] io_input_cmd_payload_fragment_length, + input wire [31:0] io_input_cmd_payload_fragment_data, + input wire [2:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [31:0] io_input_rsp_payload_fragment_data, + output wire [2:0] io_input_rsp_payload_fragment_context, + output wire [15:0] io_output_PADDR, + output wire [0:0] io_output_PSEL, + output wire io_output_PENABLE, + input wire io_output_PREADY, + output wire io_output_PWRITE, + output wire [31:0] io_output_PWDATA, + input wire [31:0] io_output_PRDATA, + input wire io_output_PSLVERROR, + input wire clk, + input wire reset +); + + wire bmbBuffer_cmd_valid; + reg bmbBuffer_cmd_ready; + wire bmbBuffer_cmd_payload_last; + wire [0:0] bmbBuffer_cmd_payload_fragment_opcode; + wire [15:0] bmbBuffer_cmd_payload_fragment_address; + wire [1:0] bmbBuffer_cmd_payload_fragment_length; + wire [31:0] bmbBuffer_cmd_payload_fragment_data; + wire [2:0] bmbBuffer_cmd_payload_fragment_context; + reg bmbBuffer_rsp_valid; + reg bmbBuffer_rsp_ready; + wire bmbBuffer_rsp_payload_last; + reg [0:0] bmbBuffer_rsp_payload_fragment_opcode; + wire [31:0] bmbBuffer_rsp_payload_fragment_data; + wire [2:0] bmbBuffer_rsp_payload_fragment_context; + wire io_input_rsp_isStall; + wire _zz_io_input_cmd_ready; + wire bmbBuffer_rsp_m2sPipe_valid; + wire bmbBuffer_rsp_m2sPipe_ready; + wire bmbBuffer_rsp_m2sPipe_payload_last; + wire [0:0] bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; + wire [31:0] bmbBuffer_rsp_m2sPipe_payload_fragment_data; + wire [2:0] bmbBuffer_rsp_m2sPipe_payload_fragment_context; + reg bmbBuffer_rsp_rValid; + reg bmbBuffer_rsp_rData_last; + reg [0:0] bmbBuffer_rsp_rData_fragment_opcode; + reg [31:0] bmbBuffer_rsp_rData_fragment_data; + reg [2:0] bmbBuffer_rsp_rData_fragment_context; + wire when_Stream_l375; + reg state; + wire when_BmbToApb3Bridge_l46; + + assign io_input_rsp_isStall = (io_input_rsp_valid && (! io_input_rsp_ready)); + assign _zz_io_input_cmd_ready = (! io_input_rsp_isStall); + assign io_input_cmd_ready = (bmbBuffer_cmd_ready && _zz_io_input_cmd_ready); + assign bmbBuffer_cmd_valid = (io_input_cmd_valid && _zz_io_input_cmd_ready); + assign bmbBuffer_cmd_payload_last = io_input_cmd_payload_last; + assign bmbBuffer_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign bmbBuffer_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign bmbBuffer_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign bmbBuffer_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign bmbBuffer_cmd_payload_fragment_context = io_input_cmd_payload_fragment_context; + always @(*) begin + bmbBuffer_rsp_ready = bmbBuffer_rsp_m2sPipe_ready; + if(when_Stream_l375) begin + bmbBuffer_rsp_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! bmbBuffer_rsp_m2sPipe_valid); + assign bmbBuffer_rsp_m2sPipe_valid = bmbBuffer_rsp_rValid; + assign bmbBuffer_rsp_m2sPipe_payload_last = bmbBuffer_rsp_rData_last; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_opcode = bmbBuffer_rsp_rData_fragment_opcode; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_data = bmbBuffer_rsp_rData_fragment_data; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_context = bmbBuffer_rsp_rData_fragment_context; + assign io_input_rsp_valid = bmbBuffer_rsp_m2sPipe_valid; + assign bmbBuffer_rsp_m2sPipe_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = bmbBuffer_rsp_m2sPipe_payload_last; + assign io_input_rsp_payload_fragment_opcode = bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = bmbBuffer_rsp_m2sPipe_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = bmbBuffer_rsp_m2sPipe_payload_fragment_context; + always @(*) begin + bmbBuffer_cmd_ready = 1'b0; + if(!when_BmbToApb3Bridge_l46) begin + if(io_output_PREADY) begin + bmbBuffer_cmd_ready = 1'b1; + end + end + end + + assign io_output_PSEL[0] = bmbBuffer_cmd_valid; + assign io_output_PENABLE = state; + assign io_output_PWRITE = (bmbBuffer_cmd_payload_fragment_opcode == 1'b1); + assign io_output_PADDR = bmbBuffer_cmd_payload_fragment_address; + assign io_output_PWDATA = bmbBuffer_cmd_payload_fragment_data; + always @(*) begin + bmbBuffer_rsp_valid = 1'b0; + if(!when_BmbToApb3Bridge_l46) begin + if(io_output_PREADY) begin + bmbBuffer_rsp_valid = 1'b1; + end + end + end + + assign bmbBuffer_rsp_payload_fragment_data = io_output_PRDATA; + assign when_BmbToApb3Bridge_l46 = (! state); + assign bmbBuffer_rsp_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign bmbBuffer_rsp_payload_last = 1'b1; + always @(*) begin + bmbBuffer_rsp_payload_fragment_opcode = 1'b0; + if(io_output_PSLVERROR) begin + bmbBuffer_rsp_payload_fragment_opcode = 1'b1; + end + end + + always @(posedge clk) begin + if(reset) begin + bmbBuffer_rsp_rValid <= 1'b0; + state <= 1'b0; + end else begin + if(bmbBuffer_rsp_ready) begin + bmbBuffer_rsp_rValid <= bmbBuffer_rsp_valid; + end + if(when_BmbToApb3Bridge_l46) begin + state <= bmbBuffer_cmd_valid; + end else begin + if(io_output_PREADY) begin + state <= 1'b0; + end + end + end + end + + always @(posedge clk) begin + if(bmbBuffer_rsp_ready) begin + bmbBuffer_rsp_rData_last <= bmbBuffer_rsp_payload_last; + bmbBuffer_rsp_rData_fragment_opcode <= bmbBuffer_rsp_payload_fragment_opcode; + bmbBuffer_rsp_rData_fragment_data <= bmbBuffer_rsp_payload_fragment_data; + bmbBuffer_rsp_rData_fragment_context <= bmbBuffer_rsp_payload_fragment_context; + end + end + + +endmodule + +module Axi4PeripheralBmbWatchdog_be6ad777990c4e5089d0b11c63cc2698 ( + input wire io_bus_cmd_valid, + output wire io_bus_cmd_ready, + input wire io_bus_cmd_payload_last, + input wire [0:0] io_bus_cmd_payload_fragment_opcode, + input wire [7:0] io_bus_cmd_payload_fragment_address, + input wire [1:0] io_bus_cmd_payload_fragment_length, + input wire [31:0] io_bus_cmd_payload_fragment_data, + input wire [2:0] io_bus_cmd_payload_fragment_context, + output wire io_bus_rsp_valid, + input wire io_bus_rsp_ready, + output wire io_bus_rsp_payload_last, + output wire [0:0] io_bus_rsp_payload_fragment_opcode, + output wire [31:0] io_bus_rsp_payload_fragment_data, + output wire [2:0] io_bus_rsp_payload_fragment_context, + output wire [1:0] io_panics, + input wire io_heartBeat, + input wire clk, + input wire reset +); + + wire wd_prescaler_io_clear; + wire wd_prescaler_io_overflow; + wire wd_counters_0_timer_io_full; + wire [15:0] wd_counters_0_timer_io_value; + wire wd_counters_1_timer_io_full; + wire [15:0] wd_counters_1_timer_io_value; + reg [1:0] wd_api_enables; + reg wd_api_heartbeat; + reg [1:0] wd_api_panics; + wire wd_counters_0_clear; + reg wd_counters_0_full; + wire wd_counters_1_clear; + reg wd_counters_1_full; + wire busCtrl_readErrorFlag; + wire busCtrl_writeErrorFlag; + wire busCtrl_readHaltTrigger; + wire busCtrl_writeHaltTrigger; + wire busCtrl_rsp_valid; + wire busCtrl_rsp_ready; + wire busCtrl_rsp_payload_last; + reg [0:0] busCtrl_rsp_payload_fragment_opcode; + reg [31:0] busCtrl_rsp_payload_fragment_data; + wire [2:0] busCtrl_rsp_payload_fragment_context; + wire _zz_busCtrl_rsp_ready; + reg _zz_busCtrl_rsp_ready_1; + wire _zz_io_bus_rsp_valid; + reg _zz_io_bus_rsp_valid_1; + reg _zz_io_bus_rsp_payload_last; + reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_bus_rsp_payload_fragment_data; + reg [2:0] _zz_io_bus_rsp_payload_fragment_context; + wire when_Stream_l375; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire io_bus_cmd_fire; + wire busCtrl_doWrite; + wire busCtrl_doRead; + wire when_BmbSlaveFactory_l33; + wire when_BmbSlaveFactory_l35; + reg driver_unlocked; + reg _zz_when_Watchdog_l42; + wire when_Watchdog_l42; + reg _zz_when_Watchdog_l43; + wire when_Watchdog_l43; + reg _zz_wd_api_heartbeat; + wire [1:0] _zz_when_Watchdog_l52; + reg _zz_when_Watchdog_l50; + wire when_Watchdog_l50; + wire when_Watchdog_l52; + wire when_Watchdog_l52_1; + reg _zz_when_Watchdog_l55; + wire when_Watchdog_l55; + wire when_Watchdog_l57; + wire when_Watchdog_l57_1; + reg [23:0] _zz_io_limit; + reg [15:0] _zz_io_limit_1; + reg [15:0] _zz_io_limit_2; + + Axi4PeripheralPrescaler_be6ad777990c4e5089d0b11c63cc2698 wd_prescaler ( + .io_clear (wd_prescaler_io_clear ), //i + .io_limit (_zz_io_limit[23:0] ), //i + .io_overflow (wd_prescaler_io_overflow), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralTimer_be6ad777990c4e5089d0b11c63cc2698 wd_counters_0_timer ( + .io_tick (wd_prescaler_io_overflow ), //i + .io_clear (wd_counters_0_clear ), //i + .io_limit (_zz_io_limit_1[15:0] ), //i + .io_full (wd_counters_0_timer_io_full ), //o + .io_value (wd_counters_0_timer_io_value[15:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralTimer_be6ad777990c4e5089d0b11c63cc2698 wd_counters_1_timer ( + .io_tick (wd_prescaler_io_overflow ), //i + .io_clear (wd_counters_1_clear ), //i + .io_limit (_zz_io_limit_2[15:0] ), //i + .io_full (wd_counters_1_timer_io_full ), //o + .io_value (wd_counters_1_timer_io_value[15:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + assign wd_prescaler_io_clear = (wd_api_heartbeat || (wd_api_enables == 2'b00)); + assign wd_counters_0_clear = ((! wd_api_enables[0]) || wd_api_heartbeat); + always @(*) begin + wd_api_panics[0] = wd_counters_0_full; + wd_api_panics[1] = wd_counters_1_full; + end + + assign wd_counters_1_clear = ((! wd_api_enables[1]) || wd_api_heartbeat); + assign busCtrl_readErrorFlag = 1'b0; + assign busCtrl_writeErrorFlag = 1'b0; + assign busCtrl_readHaltTrigger = 1'b0; + assign busCtrl_writeHaltTrigger = 1'b0; + assign _zz_busCtrl_rsp_ready = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); + assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready_1 && _zz_busCtrl_rsp_ready); + always @(*) begin + _zz_busCtrl_rsp_ready_1 = io_bus_rsp_ready; + if(when_Stream_l375) begin + _zz_busCtrl_rsp_ready_1 = 1'b1; + end + end + + assign when_Stream_l375 = (! _zz_io_bus_rsp_valid); + assign _zz_io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; + assign io_bus_rsp_valid = _zz_io_bus_rsp_valid; + assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; + assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; + assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; + assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; + assign busCtrl_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign busCtrl_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_doRead = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign busCtrl_rsp_valid = io_bus_cmd_valid; + assign io_bus_cmd_ready = busCtrl_rsp_ready; + assign busCtrl_rsp_payload_last = 1'b1; + assign when_BmbSlaveFactory_l33 = (busCtrl_doWrite && busCtrl_writeErrorFlag); + always @(*) begin + if(when_BmbSlaveFactory_l33) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + if(when_BmbSlaveFactory_l35) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + busCtrl_rsp_payload_fragment_opcode = 1'b0; + end + end + end + + assign when_BmbSlaveFactory_l35 = (busCtrl_doRead && busCtrl_readErrorFlag); + always @(*) begin + busCtrl_rsp_payload_fragment_data = 32'h0; + case(io_bus_cmd_payload_fragment_address) + 8'hc0 : begin + busCtrl_rsp_payload_fragment_data[15 : 0] = wd_counters_0_timer_io_value; + end + 8'hc4 : begin + busCtrl_rsp_payload_fragment_data[15 : 0] = wd_counters_1_timer_io_value; + end + default : begin + end + endcase + end + + assign busCtrl_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; + always @(*) begin + _zz_when_Watchdog_l42 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 8'h0 : begin + if(busCtrl_doWrite) begin + _zz_when_Watchdog_l42 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_Watchdog_l42 = (_zz_when_Watchdog_l42 && (io_bus_cmd_payload_fragment_data[31 : 0] == 32'h3c21b925)); + always @(*) begin + _zz_when_Watchdog_l43 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 8'h0 : begin + if(busCtrl_doWrite) begin + _zz_when_Watchdog_l43 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_Watchdog_l43 = (_zz_when_Watchdog_l43 && (io_bus_cmd_payload_fragment_data[31 : 0] == 32'h3c21b924)); + always @(*) begin + _zz_wd_api_heartbeat = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 8'h0 : begin + if(busCtrl_doWrite) begin + _zz_wd_api_heartbeat = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + wd_api_heartbeat = (_zz_wd_api_heartbeat && (io_bus_cmd_payload_fragment_data[31 : 0] == 32'had68e70d)); + if(io_heartBeat) begin + wd_api_heartbeat = 1'b1; + end + end + + always @(*) begin + _zz_when_Watchdog_l50 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 8'h04 : begin + if(busCtrl_doWrite) begin + _zz_when_Watchdog_l50 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_Watchdog_l50 = (_zz_when_Watchdog_l50 && driver_unlocked); + assign when_Watchdog_l52 = _zz_when_Watchdog_l52[0]; + assign when_Watchdog_l52_1 = _zz_when_Watchdog_l52[1]; + always @(*) begin + _zz_when_Watchdog_l55 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 8'h08 : begin + if(busCtrl_doWrite) begin + _zz_when_Watchdog_l55 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_Watchdog_l55 = (_zz_when_Watchdog_l55 && driver_unlocked); + assign when_Watchdog_l57 = _zz_when_Watchdog_l52[0]; + assign when_Watchdog_l57_1 = _zz_when_Watchdog_l52[1]; + assign io_panics = wd_api_panics; + assign _zz_when_Watchdog_l52 = io_bus_cmd_payload_fragment_data[1 : 0]; + always @(posedge clk) begin + if(reset) begin + wd_counters_0_full <= 1'b0; + wd_counters_1_full <= 1'b0; + _zz_io_bus_rsp_valid_1 <= 1'b0; + driver_unlocked <= 1'b1; + wd_api_enables <= 2'b00; + _zz_io_limit <= 24'h0; + _zz_io_limit_1 <= 16'h0; + _zz_io_limit_2 <= 16'h0; + end else begin + if(wd_counters_0_timer_io_full) begin + wd_counters_0_full <= 1'b1; + end + if(wd_counters_0_clear) begin + wd_counters_0_full <= 1'b0; + end + if(wd_counters_1_timer_io_full) begin + wd_counters_1_full <= 1'b1; + end + if(wd_counters_1_clear) begin + wd_counters_1_full <= 1'b0; + end + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_bus_rsp_valid_1 <= (busCtrl_rsp_valid && _zz_busCtrl_rsp_ready); + end + if(when_Watchdog_l42) begin + driver_unlocked <= 1'b1; + end + if(when_Watchdog_l43) begin + driver_unlocked <= 1'b0; + end + if(when_Watchdog_l50) begin + if(when_Watchdog_l52) begin + wd_api_enables[0] <= 1'b1; + end + if(when_Watchdog_l52_1) begin + wd_api_enables[1] <= 1'b1; + end + end + if(when_Watchdog_l55) begin + if(when_Watchdog_l57) begin + wd_api_enables[0] <= 1'b0; + end + if(when_Watchdog_l57_1) begin + wd_api_enables[1] <= 1'b0; + end + end + case(io_bus_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + if(driver_unlocked) begin + _zz_io_limit <= io_bus_cmd_payload_fragment_data[23 : 0]; + end + end + end + 8'h80 : begin + if(busCtrl_doWrite) begin + if(driver_unlocked) begin + _zz_io_limit_1 <= io_bus_cmd_payload_fragment_data[15 : 0]; + end + end + end + 8'h84 : begin + if(busCtrl_doWrite) begin + if(driver_unlocked) begin + _zz_io_limit_2 <= io_bus_cmd_payload_fragment_data[15 : 0]; + end + end + end + default : begin + end + endcase + end + end + + always @(posedge clk) begin + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_bus_rsp_payload_last <= busCtrl_rsp_payload_last; + _zz_io_bus_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; + _zz_io_bus_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; + _zz_io_bus_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; + end + end + + +endmodule + +module Axi4PeripheralBmbGpio2_be6ad777990c4e5089d0b11c63cc2698 ( + input wire [3:0] io_gpio_read, + output reg [3:0] io_gpio_write, + output reg [3:0] io_gpio_writeEnable, + input wire io_bus_cmd_valid, + output wire io_bus_cmd_ready, + input wire io_bus_cmd_payload_last, + input wire [0:0] io_bus_cmd_payload_fragment_opcode, + input wire [7:0] io_bus_cmd_payload_fragment_address, + input wire [1:0] io_bus_cmd_payload_fragment_length, + input wire [31:0] io_bus_cmd_payload_fragment_data, + input wire [2:0] io_bus_cmd_payload_fragment_context, + output wire io_bus_rsp_valid, + input wire io_bus_rsp_ready, + output wire io_bus_rsp_payload_last, + output wire [0:0] io_bus_rsp_payload_fragment_opcode, + output wire [31:0] io_bus_rsp_payload_fragment_data, + output wire [2:0] io_bus_rsp_payload_fragment_context, + output reg [3:0] io_interrupt, + input wire clk, + input wire reset +); + + wire mapper_readErrorFlag; + wire mapper_writeErrorFlag; + wire mapper_readHaltTrigger; + wire mapper_writeHaltTrigger; + wire mapper_rsp_valid; + wire mapper_rsp_ready; + wire mapper_rsp_payload_last; + reg [0:0] mapper_rsp_payload_fragment_opcode; + reg [31:0] mapper_rsp_payload_fragment_data; + wire [2:0] mapper_rsp_payload_fragment_context; + wire _zz_mapper_rsp_ready; + reg _zz_mapper_rsp_ready_1; + wire _zz_io_bus_rsp_valid; + reg _zz_io_bus_rsp_valid_1; + reg _zz_io_bus_rsp_payload_last; + reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_bus_rsp_payload_fragment_data; + reg [2:0] _zz_io_bus_rsp_payload_fragment_context; + wire when_Stream_l375; + wire mapper_askWrite; + wire mapper_askRead; + wire io_bus_cmd_fire; + wire mapper_doWrite; + wire mapper_doRead; + wire when_BmbSlaveFactory_l33; + wire when_BmbSlaveFactory_l35; + reg [3:0] io_gpio_read_delay_1; + reg [3:0] syncronized; + reg [3:0] last; + reg _zz_io_gpio_write; + reg _zz_io_gpio_writeEnable; + reg _zz_io_gpio_write_1; + reg _zz_io_gpio_writeEnable_1; + reg _zz_io_gpio_write_2; + reg _zz_io_gpio_writeEnable_2; + reg _zz_io_gpio_write_3; + reg _zz_io_gpio_writeEnable_3; + reg [3:0] interrupt_enable_high; + reg [3:0] interrupt_enable_low; + reg [3:0] interrupt_enable_rise; + reg [3:0] interrupt_enable_fall; + wire [3:0] interrupt_valid; + reg _zz_mapper_rsp_payload_fragment_data; + reg _zz_mapper_rsp_payload_fragment_data_1; + reg _zz_mapper_rsp_payload_fragment_data_2; + reg _zz_mapper_rsp_payload_fragment_data_3; + reg _zz_mapper_rsp_payload_fragment_data_4; + reg _zz_mapper_rsp_payload_fragment_data_5; + reg _zz_mapper_rsp_payload_fragment_data_6; + reg _zz_mapper_rsp_payload_fragment_data_7; + + assign mapper_readErrorFlag = 1'b0; + assign mapper_writeErrorFlag = 1'b0; + assign mapper_readHaltTrigger = 1'b0; + assign mapper_writeHaltTrigger = 1'b0; + assign _zz_mapper_rsp_ready = (! (mapper_readHaltTrigger || mapper_writeHaltTrigger)); + assign mapper_rsp_ready = (_zz_mapper_rsp_ready_1 && _zz_mapper_rsp_ready); + always @(*) begin + _zz_mapper_rsp_ready_1 = io_bus_rsp_ready; + if(when_Stream_l375) begin + _zz_mapper_rsp_ready_1 = 1'b1; + end + end + + assign when_Stream_l375 = (! _zz_io_bus_rsp_valid); + assign _zz_io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; + assign io_bus_rsp_valid = _zz_io_bus_rsp_valid; + assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; + assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; + assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; + assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; + assign mapper_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign mapper_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign mapper_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign mapper_doRead = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign mapper_rsp_valid = io_bus_cmd_valid; + assign io_bus_cmd_ready = mapper_rsp_ready; + assign mapper_rsp_payload_last = 1'b1; + assign when_BmbSlaveFactory_l33 = (mapper_doWrite && mapper_writeErrorFlag); + always @(*) begin + if(when_BmbSlaveFactory_l33) begin + mapper_rsp_payload_fragment_opcode = 1'b1; + end else begin + if(when_BmbSlaveFactory_l35) begin + mapper_rsp_payload_fragment_opcode = 1'b1; + end else begin + mapper_rsp_payload_fragment_opcode = 1'b0; + end + end + end + + assign when_BmbSlaveFactory_l35 = (mapper_doRead && mapper_readErrorFlag); + always @(*) begin + mapper_rsp_payload_fragment_data = 32'h0; + case(io_bus_cmd_payload_fragment_address) + 8'h0 : begin + mapper_rsp_payload_fragment_data[0 : 0] = syncronized[0]; + mapper_rsp_payload_fragment_data[1 : 1] = syncronized[1]; + mapper_rsp_payload_fragment_data[2 : 2] = syncronized[2]; + mapper_rsp_payload_fragment_data[3 : 3] = syncronized[3]; + end + 8'h04 : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_io_gpio_write; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_io_gpio_write_1; + mapper_rsp_payload_fragment_data[2 : 2] = _zz_io_gpio_write_2; + mapper_rsp_payload_fragment_data[3 : 3] = _zz_io_gpio_write_3; + end + 8'h08 : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_io_gpio_writeEnable; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_io_gpio_writeEnable_1; + mapper_rsp_payload_fragment_data[2 : 2] = _zz_io_gpio_writeEnable_2; + mapper_rsp_payload_fragment_data[3 : 3] = _zz_io_gpio_writeEnable_3; + end + 8'h20 : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_mapper_rsp_payload_fragment_data; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_mapper_rsp_payload_fragment_data_4; + end + 8'h24 : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_mapper_rsp_payload_fragment_data_1; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_mapper_rsp_payload_fragment_data_5; + end + 8'h28 : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_mapper_rsp_payload_fragment_data_2; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_mapper_rsp_payload_fragment_data_6; + end + 8'h2c : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_mapper_rsp_payload_fragment_data_3; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_mapper_rsp_payload_fragment_data_7; + end + default : begin + end + endcase + end + + assign mapper_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; + always @(*) begin + io_gpio_write[0] = _zz_io_gpio_write; + io_gpio_write[1] = _zz_io_gpio_write_1; + io_gpio_write[2] = _zz_io_gpio_write_2; + io_gpio_write[3] = _zz_io_gpio_write_3; + end + + always @(*) begin + io_gpio_writeEnable[0] = _zz_io_gpio_writeEnable; + io_gpio_writeEnable[1] = _zz_io_gpio_writeEnable_1; + io_gpio_writeEnable[2] = _zz_io_gpio_writeEnable_2; + io_gpio_writeEnable[3] = _zz_io_gpio_writeEnable_3; + end + + assign interrupt_valid = ((((interrupt_enable_high & syncronized) | (interrupt_enable_low & (~ syncronized))) | (interrupt_enable_rise & (syncronized & (~ last)))) | (interrupt_enable_fall & ((~ syncronized) & last))); + always @(*) begin + io_interrupt[0] = interrupt_valid[0]; + io_interrupt[1] = interrupt_valid[1]; + io_interrupt[2] = 1'b0; + io_interrupt[3] = 1'b0; + end + + always @(*) begin + interrupt_enable_rise[0] = _zz_mapper_rsp_payload_fragment_data; + interrupt_enable_rise[1] = _zz_mapper_rsp_payload_fragment_data_4; + interrupt_enable_rise[2] = 1'b0; + interrupt_enable_rise[3] = 1'b0; + end + + always @(*) begin + interrupt_enable_fall[0] = _zz_mapper_rsp_payload_fragment_data_1; + interrupt_enable_fall[1] = _zz_mapper_rsp_payload_fragment_data_5; + interrupt_enable_fall[2] = 1'b0; + interrupt_enable_fall[3] = 1'b0; + end + + always @(*) begin + interrupt_enable_high[0] = _zz_mapper_rsp_payload_fragment_data_2; + interrupt_enable_high[1] = _zz_mapper_rsp_payload_fragment_data_6; + interrupt_enable_high[2] = 1'b0; + interrupt_enable_high[3] = 1'b0; + end + + always @(*) begin + interrupt_enable_low[0] = _zz_mapper_rsp_payload_fragment_data_3; + interrupt_enable_low[1] = _zz_mapper_rsp_payload_fragment_data_7; + interrupt_enable_low[2] = 1'b0; + interrupt_enable_low[3] = 1'b0; + end + + always @(posedge clk) begin + if(reset) begin + _zz_io_bus_rsp_valid_1 <= 1'b0; + _zz_io_gpio_writeEnable <= 1'b0; + _zz_io_gpio_writeEnable_1 <= 1'b0; + _zz_io_gpio_writeEnable_2 <= 1'b0; + _zz_io_gpio_writeEnable_3 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_1 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_2 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_3 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_4 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_5 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_6 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_7 <= 1'b0; + end else begin + if(_zz_mapper_rsp_ready_1) begin + _zz_io_bus_rsp_valid_1 <= (mapper_rsp_valid && _zz_mapper_rsp_ready); + end + case(io_bus_cmd_payload_fragment_address) + 8'h08 : begin + if(mapper_doWrite) begin + _zz_io_gpio_writeEnable <= io_bus_cmd_payload_fragment_data[0]; + _zz_io_gpio_writeEnable_1 <= io_bus_cmd_payload_fragment_data[1]; + _zz_io_gpio_writeEnable_2 <= io_bus_cmd_payload_fragment_data[2]; + _zz_io_gpio_writeEnable_3 <= io_bus_cmd_payload_fragment_data[3]; + end + end + 8'h20 : begin + if(mapper_doWrite) begin + _zz_mapper_rsp_payload_fragment_data <= io_bus_cmd_payload_fragment_data[0]; + _zz_mapper_rsp_payload_fragment_data_4 <= io_bus_cmd_payload_fragment_data[1]; + end + end + 8'h24 : begin + if(mapper_doWrite) begin + _zz_mapper_rsp_payload_fragment_data_1 <= io_bus_cmd_payload_fragment_data[0]; + _zz_mapper_rsp_payload_fragment_data_5 <= io_bus_cmd_payload_fragment_data[1]; + end + end + 8'h28 : begin + if(mapper_doWrite) begin + _zz_mapper_rsp_payload_fragment_data_2 <= io_bus_cmd_payload_fragment_data[0]; + _zz_mapper_rsp_payload_fragment_data_6 <= io_bus_cmd_payload_fragment_data[1]; + end + end + 8'h2c : begin + if(mapper_doWrite) begin + _zz_mapper_rsp_payload_fragment_data_3 <= io_bus_cmd_payload_fragment_data[0]; + _zz_mapper_rsp_payload_fragment_data_7 <= io_bus_cmd_payload_fragment_data[1]; + end + end + default : begin + end + endcase + end + end + + always @(posedge clk) begin + if(_zz_mapper_rsp_ready_1) begin + _zz_io_bus_rsp_payload_last <= mapper_rsp_payload_last; + _zz_io_bus_rsp_payload_fragment_opcode <= mapper_rsp_payload_fragment_opcode; + _zz_io_bus_rsp_payload_fragment_data <= mapper_rsp_payload_fragment_data; + _zz_io_bus_rsp_payload_fragment_context <= mapper_rsp_payload_fragment_context; + end + io_gpio_read_delay_1 <= io_gpio_read; + syncronized <= io_gpio_read_delay_1; + last <= syncronized; + case(io_bus_cmd_payload_fragment_address) + 8'h04 : begin + if(mapper_doWrite) begin + _zz_io_gpio_write <= io_bus_cmd_payload_fragment_data[0]; + _zz_io_gpio_write_1 <= io_bus_cmd_payload_fragment_data[1]; + _zz_io_gpio_write_2 <= io_bus_cmd_payload_fragment_data[2]; + _zz_io_gpio_write_3 <= io_bus_cmd_payload_fragment_data[3]; + end + end + default : begin + end + endcase + end + + +endmodule + +module Axi4PeripheralBmbI2cCtrl_be6ad777990c4e5089d0b11c63cc2698 ( + input wire io_ctrl_cmd_valid, + output wire io_ctrl_cmd_ready, + input wire io_ctrl_cmd_payload_last, + input wire [0:0] io_ctrl_cmd_payload_fragment_opcode, + input wire [7:0] io_ctrl_cmd_payload_fragment_address, + input wire [1:0] io_ctrl_cmd_payload_fragment_length, + input wire [31:0] io_ctrl_cmd_payload_fragment_data, + input wire [2:0] io_ctrl_cmd_payload_fragment_context, + output wire io_ctrl_rsp_valid, + input wire io_ctrl_rsp_ready, + output wire io_ctrl_rsp_payload_last, + output wire [0:0] io_ctrl_rsp_payload_fragment_opcode, + output wire [31:0] io_ctrl_rsp_payload_fragment_data, + output wire [2:0] io_ctrl_rsp_payload_fragment_context, + output wire io_i2c_sda_write, + input wire io_i2c_sda_read, + output wire io_i2c_scl_write, + input wire io_i2c_scl_read, + output wire system_i2c_0_io_interrupt_source, + input wire clk, + input wire reset +); + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT = 4'd0; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE = 4'd1; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 = 4'd2; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 = 4'd3; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 = 4'd4; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW = 4'd5; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH = 4'd6; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART = 4'd7; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 = 4'd8; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 = 4'd9; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 = 4'd10; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF = 4'd11; + localparam Axi4PeripheralI2cSlaveCmdMode_NONE = 3'd0; + localparam Axi4PeripheralI2cSlaveCmdMode_START = 3'd1; + localparam Axi4PeripheralI2cSlaveCmdMode_RESTART = 3'd2; + localparam Axi4PeripheralI2cSlaveCmdMode_STOP = 3'd3; + localparam Axi4PeripheralI2cSlaveCmdMode_DROP = 3'd4; + localparam Axi4PeripheralI2cSlaveCmdMode_DRIVE = 3'd5; + localparam Axi4PeripheralI2cSlaveCmdMode_READ = 3'd6; + + reg i2cCtrl_io_config_timeoutClear; + reg i2cCtrl_io_bus_rsp_valid; + reg i2cCtrl_io_bus_rsp_enable; + reg i2cCtrl_io_bus_rsp_data; + wire i2cCtrl_io_i2c_scl_write; + wire i2cCtrl_io_i2c_sda_write; + wire [2:0] i2cCtrl_io_bus_cmd_kind; + wire i2cCtrl_io_bus_cmd_data; + wire i2cCtrl_io_timeout; + wire i2cCtrl_io_internals_inFrame; + wire i2cCtrl_io_internals_sdaRead; + wire i2cCtrl_io_internals_sclRead; + wire [6:0] _zz_bridge_addressFilter_hits_0; + wire [6:0] _zz_bridge_addressFilter_hits_1; + wire [0:0] _zz_bridge_masterLogic_start; + wire [0:0] _zz_bridge_masterLogic_stop; + wire [0:0] _zz_bridge_masterLogic_drop; + wire [0:0] _zz_bridge_masterLogic_recover; + wire [11:0] _zz_bridge_masterLogic_timer_value; + wire [0:0] _zz_bridge_masterLogic_timer_value_1; + wire [0:0] _zz_bridge_masterLogic_fsm_dropped_start; + wire [0:0] _zz_bridge_masterLogic_fsm_dropped_stop; + wire [0:0] _zz_bridge_masterLogic_fsm_dropped_recover; + wire [2:0] _zz_io_bus_rsp_data; + wire [2:0] _zz_bridge_rxData_value; + wire [0:0] _zz_bridge_interruptCtrl_start_flag; + wire [0:0] _zz_bridge_interruptCtrl_restart_flag; + wire [0:0] _zz_bridge_interruptCtrl_end_flag; + wire [0:0] _zz_bridge_interruptCtrl_drop_flag; + wire [0:0] _zz_bridge_interruptCtrl_filterGen_flag; + wire [0:0] _zz_bridge_interruptCtrl_clockGenExit_flag; + wire [0:0] _zz_bridge_interruptCtrl_clockGenEnter_flag; + wire busCtrl_readErrorFlag; + wire busCtrl_writeErrorFlag; + wire busCtrl_readHaltTrigger; + wire busCtrl_writeHaltTrigger; + wire busCtrl_rsp_valid; + wire busCtrl_rsp_ready; + wire busCtrl_rsp_payload_last; + reg [0:0] busCtrl_rsp_payload_fragment_opcode; + reg [31:0] busCtrl_rsp_payload_fragment_data; + wire [2:0] busCtrl_rsp_payload_fragment_context; + wire _zz_busCtrl_rsp_ready; + reg _zz_busCtrl_rsp_ready_1; + wire _zz_io_ctrl_rsp_valid; + reg _zz_io_ctrl_rsp_valid_1; + reg _zz_io_ctrl_rsp_payload_last; + reg [0:0] _zz_io_ctrl_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_ctrl_rsp_payload_fragment_data; + reg [2:0] _zz_io_ctrl_rsp_payload_fragment_context; + wire when_Stream_l375; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire io_ctrl_cmd_fire; + wire busCtrl_doWrite; + wire busCtrl_doRead; + wire when_BmbSlaveFactory_l33; + wire when_BmbSlaveFactory_l35; + wire bridge_busCtrlWithOffset_readErrorFlag; + wire bridge_busCtrlWithOffset_writeErrorFlag; + reg bridge_frameReset; + reg bridge_i2cBuffer_sda_write; + wire bridge_i2cBuffer_sda_read; + reg bridge_i2cBuffer_scl_write; + wire bridge_i2cBuffer_scl_read; + reg bridge_rxData_event; + reg bridge_rxData_listen; + reg bridge_rxData_valid; + reg [7:0] bridge_rxData_value; + reg when_I2cCtrl_l224; + reg bridge_rxAck_listen; + reg bridge_rxAck_valid; + reg bridge_rxAck_value; + reg when_I2cCtrl_l237; + reg bridge_txData_valid; + reg bridge_txData_repeat; + reg bridge_txData_enable; + reg [7:0] bridge_txData_value; + reg bridge_txData_forceDisable; + reg bridge_txData_disableOnDataConflict; + reg bridge_txAck_valid; + reg bridge_txAck_repeat; + reg bridge_txAck_enable; + reg bridge_txAck_value; + reg bridge_txAck_forceAck; + reg bridge_txAck_disableOnDataConflict; + reg bridge_addressFilter_addresses_0_enable; + reg [9:0] bridge_addressFilter_addresses_0_value; + reg bridge_addressFilter_addresses_0_is10Bit; + reg bridge_addressFilter_addresses_1_enable; + reg [9:0] bridge_addressFilter_addresses_1_value; + reg bridge_addressFilter_addresses_1_is10Bit; + reg [1:0] bridge_addressFilter_state; + reg [7:0] bridge_addressFilter_byte0; + reg [7:0] bridge_addressFilter_byte1; + wire bridge_addressFilter_byte0Is10Bit; + wire bridge_addressFilter_hits_0; + wire bridge_addressFilter_hits_1; + wire when_I2cCtrl_l306; + wire _zz_when_I2cCtrl_l310; + reg _zz_when_I2cCtrl_l310_1; + wire when_I2cCtrl_l310; + reg bridge_masterLogic_start; + reg when_BusSlaveFactory_l377; + wire when_BusSlaveFactory_l379; + reg bridge_masterLogic_stop; + reg when_BusSlaveFactory_l377_1; + wire when_BusSlaveFactory_l379_1; + reg bridge_masterLogic_drop; + reg when_BusSlaveFactory_l377_2; + wire when_BusSlaveFactory_l379_2; + reg bridge_masterLogic_recover; + reg when_BusSlaveFactory_l377_3; + wire when_BusSlaveFactory_l379_3; + reg [11:0] bridge_masterLogic_timer_value; + reg [11:0] bridge_masterLogic_timer_tLow; + reg [11:0] bridge_masterLogic_timer_tHigh; + reg [11:0] bridge_masterLogic_timer_tBuf; + wire bridge_masterLogic_timer_done; + wire bridge_masterLogic_txReady; + wire bridge_masterLogic_fsm_wantExit; + reg bridge_masterLogic_fsm_wantStart; + wire bridge_masterLogic_fsm_wantKill; + reg bridge_masterLogic_fsm_dropped_start; + reg bridge_masterLogic_fsm_dropped_stop; + reg bridge_masterLogic_fsm_dropped_recover; + reg bridge_masterLogic_fsm_dropped_trigger; + reg bridge_masterLogic_fsm_inFrameLate; + wire when_I2cCtrl_l363; + wire when_I2cCtrl_l363_1; + wire bridge_masterLogic_fsm_outOfSync; + wire bridge_masterLogic_fsm_isBusy; + reg when_BusSlaveFactory_l341; + wire when_BusSlaveFactory_l347; + reg when_BusSlaveFactory_l341_1; + wire when_BusSlaveFactory_l347_1; + reg when_BusSlaveFactory_l341_2; + wire when_BusSlaveFactory_l347_2; + reg [2:0] bridge_dataCounter; + reg bridge_inAckState; + reg bridge_wasntAck; + wire when_I2cCtrl_l523; + wire when_I2cCtrl_l546; + wire when_I2cCtrl_l566; + wire when_I2cCtrl_l570; + wire when_I2cCtrl_l574; + wire when_I2cCtrl_l578; + wire when_I2cCtrl_l588; + wire when_I2cCtrl_l601; + reg bridge_interruptCtrl_rxDataEnable; + reg bridge_interruptCtrl_rxAckEnable; + reg bridge_interruptCtrl_txDataEnable; + reg bridge_interruptCtrl_txAckEnable; + reg bridge_interruptCtrl_interrupt; + wire when_I2cCtrl_l634; + reg bridge_interruptCtrl_start_enable; + reg bridge_interruptCtrl_start_flag; + wire when_I2cCtrl_l634_1; + reg when_BusSlaveFactory_l341_3; + wire when_BusSlaveFactory_l347_3; + wire when_I2cCtrl_l634_2; + reg bridge_interruptCtrl_restart_enable; + reg bridge_interruptCtrl_restart_flag; + wire when_I2cCtrl_l634_3; + reg when_BusSlaveFactory_l341_4; + wire when_BusSlaveFactory_l347_4; + wire when_I2cCtrl_l634_4; + reg bridge_interruptCtrl_end_enable; + reg bridge_interruptCtrl_end_flag; + wire when_I2cCtrl_l634_5; + reg when_BusSlaveFactory_l341_5; + wire when_BusSlaveFactory_l347_5; + wire when_I2cCtrl_l634_6; + reg bridge_interruptCtrl_drop_enable; + reg bridge_interruptCtrl_drop_flag; + wire when_I2cCtrl_l634_7; + reg when_BusSlaveFactory_l341_6; + wire when_BusSlaveFactory_l347_6; + wire _zz_when_I2cCtrl_l634; + reg _zz_when_I2cCtrl_l634_1; + wire when_I2cCtrl_l634_8; + reg bridge_interruptCtrl_filterGen_enable; + reg bridge_interruptCtrl_filterGen_flag; + wire when_I2cCtrl_l634_9; + reg when_BusSlaveFactory_l341_7; + wire when_BusSlaveFactory_l347_7; + reg bridge_masterLogic_fsm_isBusy_regNext; + wire when_I2cCtrl_l634_10; + reg bridge_interruptCtrl_clockGenExit_enable; + reg bridge_interruptCtrl_clockGenExit_flag; + wire when_I2cCtrl_l634_11; + reg when_BusSlaveFactory_l341_8; + wire when_BusSlaveFactory_l347_8; + reg bridge_masterLogic_fsm_isBusy_regNext_1; + wire when_I2cCtrl_l634_12; + reg bridge_interruptCtrl_clockGenEnter_enable; + reg bridge_interruptCtrl_clockGenEnter_flag; + wire when_I2cCtrl_l634_13; + reg when_BusSlaveFactory_l341_9; + wire when_BusSlaveFactory_l347_9; + reg [9:0] _zz_io_config_samplingClockDivider; + reg [19:0] _zz_io_config_timeout; + reg [5:0] _zz_io_config_tsuData; + reg bridge_timeoutClear; + wire when_I2cCtrl_l659; + reg [3:0] bridge_masterLogic_fsm_stateReg; + reg [3:0] bridge_masterLogic_fsm_stateNext; + reg i2cCtrl_io_internals_inFrame_regNext; + wire when_I2cCtrl_l367; + wire when_I2cCtrl_l369; + wire when_I2cCtrl_l380; + wire when_I2cCtrl_l392; + wire when_I2cCtrl_l418; + wire when_I2cCtrl_l422; + wire when_I2cCtrl_l442; + wire when_I2cCtrl_l450; + wire when_I2cCtrl_l474; + wire when_StateMachine_l253; + wire when_StateMachine_l253_1; + wire when_StateMachine_l253_2; + wire when_StateMachine_l253_3; + wire when_StateMachine_l253_4; + wire when_StateMachine_l253_5; + wire when_I2cCtrl_l350; + reg bridge_slaveOverride_sda; + reg bridge_slaveOverride_scl; + wire when_I2cCtrl_l673; + wire when_I2cCtrl_l674; + reg bridge_i2cBuffer_scl_write_regNext; + reg bridge_i2cBuffer_sda_write_regNext; + `ifndef SYNTHESIS + reg [55:0] bridge_masterLogic_fsm_stateReg_string; + reg [55:0] bridge_masterLogic_fsm_stateNext_string; + `endif + + + assign _zz_bridge_addressFilter_hits_0 = (bridge_addressFilter_byte0 >>> 1'd1); + assign _zz_bridge_addressFilter_hits_1 = (bridge_addressFilter_byte0 >>> 1'd1); + assign _zz_bridge_masterLogic_start = 1'b1; + assign _zz_bridge_masterLogic_stop = 1'b1; + assign _zz_bridge_masterLogic_drop = 1'b1; + assign _zz_bridge_masterLogic_recover = 1'b1; + assign _zz_bridge_masterLogic_timer_value_1 = (! bridge_masterLogic_timer_done); + assign _zz_bridge_masterLogic_timer_value = {11'd0, _zz_bridge_masterLogic_timer_value_1}; + assign _zz_bridge_masterLogic_fsm_dropped_start = 1'b0; + assign _zz_bridge_masterLogic_fsm_dropped_stop = 1'b0; + assign _zz_bridge_masterLogic_fsm_dropped_recover = 1'b0; + assign _zz_io_bus_rsp_data = (3'b111 - bridge_dataCounter); + assign _zz_bridge_rxData_value = (3'b111 - bridge_dataCounter); + assign _zz_bridge_interruptCtrl_start_flag = 1'b0; + assign _zz_bridge_interruptCtrl_restart_flag = 1'b0; + assign _zz_bridge_interruptCtrl_end_flag = 1'b0; + assign _zz_bridge_interruptCtrl_drop_flag = 1'b0; + assign _zz_bridge_interruptCtrl_filterGen_flag = 1'b0; + assign _zz_bridge_interruptCtrl_clockGenExit_flag = 1'b0; + assign _zz_bridge_interruptCtrl_clockGenEnter_flag = 1'b0; + Axi4PeripheralI2cSlave_be6ad777990c4e5089d0b11c63cc2698 i2cCtrl ( + .io_i2c_sda_write (i2cCtrl_io_i2c_sda_write ), //o + .io_i2c_sda_read (bridge_i2cBuffer_sda_read ), //i + .io_i2c_scl_write (i2cCtrl_io_i2c_scl_write ), //o + .io_i2c_scl_read (bridge_i2cBuffer_scl_read ), //i + .io_config_samplingClockDivider (_zz_io_config_samplingClockDivider[9:0]), //i + .io_config_timeout (_zz_io_config_timeout[19:0] ), //i + .io_config_tsuData (_zz_io_config_tsuData[5:0] ), //i + .io_config_timeoutClear (i2cCtrl_io_config_timeoutClear ), //i + .io_bus_cmd_kind (i2cCtrl_io_bus_cmd_kind[2:0] ), //o + .io_bus_cmd_data (i2cCtrl_io_bus_cmd_data ), //o + .io_bus_rsp_valid (i2cCtrl_io_bus_rsp_valid ), //i + .io_bus_rsp_enable (i2cCtrl_io_bus_rsp_enable ), //i + .io_bus_rsp_data (i2cCtrl_io_bus_rsp_data ), //i + .io_timeout (i2cCtrl_io_timeout ), //o + .io_internals_inFrame (i2cCtrl_io_internals_inFrame ), //o + .io_internals_sdaRead (i2cCtrl_io_internals_sdaRead ), //o + .io_internals_sclRead (i2cCtrl_io_internals_sclRead ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + initial begin + `ifndef SYNTHESIS + _zz_io_config_timeout = {$urandom}; + _zz_io_config_tsuData = {$urandom}; + `endif + end + + `ifndef SYNTHESIS + always @(*) begin + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT : bridge_masterLogic_fsm_stateReg_string = "BOOT "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : bridge_masterLogic_fsm_stateReg_string = "IDLE "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : bridge_masterLogic_fsm_stateReg_string = "START1 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : bridge_masterLogic_fsm_stateReg_string = "START2 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : bridge_masterLogic_fsm_stateReg_string = "START3 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : bridge_masterLogic_fsm_stateReg_string = "LOW "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : bridge_masterLogic_fsm_stateReg_string = "HIGH "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : bridge_masterLogic_fsm_stateReg_string = "RESTART"; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : bridge_masterLogic_fsm_stateReg_string = "STOP1 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : bridge_masterLogic_fsm_stateReg_string = "STOP2 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : bridge_masterLogic_fsm_stateReg_string = "STOP3 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : bridge_masterLogic_fsm_stateReg_string = "TBUF "; + default : bridge_masterLogic_fsm_stateReg_string = "???????"; + endcase + end + always @(*) begin + case(bridge_masterLogic_fsm_stateNext) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT : bridge_masterLogic_fsm_stateNext_string = "BOOT "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : bridge_masterLogic_fsm_stateNext_string = "IDLE "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : bridge_masterLogic_fsm_stateNext_string = "START1 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : bridge_masterLogic_fsm_stateNext_string = "START2 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : bridge_masterLogic_fsm_stateNext_string = "START3 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : bridge_masterLogic_fsm_stateNext_string = "LOW "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : bridge_masterLogic_fsm_stateNext_string = "HIGH "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : bridge_masterLogic_fsm_stateNext_string = "RESTART"; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : bridge_masterLogic_fsm_stateNext_string = "STOP1 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : bridge_masterLogic_fsm_stateNext_string = "STOP2 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : bridge_masterLogic_fsm_stateNext_string = "STOP3 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : bridge_masterLogic_fsm_stateNext_string = "TBUF "; + default : bridge_masterLogic_fsm_stateNext_string = "???????"; + endcase + end + `endif + + assign busCtrl_readErrorFlag = 1'b0; + assign busCtrl_writeErrorFlag = 1'b0; + assign busCtrl_readHaltTrigger = 1'b0; + assign busCtrl_writeHaltTrigger = 1'b0; + assign _zz_busCtrl_rsp_ready = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); + assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready_1 && _zz_busCtrl_rsp_ready); + always @(*) begin + _zz_busCtrl_rsp_ready_1 = io_ctrl_rsp_ready; + if(when_Stream_l375) begin + _zz_busCtrl_rsp_ready_1 = 1'b1; + end + end + + assign when_Stream_l375 = (! _zz_io_ctrl_rsp_valid); + assign _zz_io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid_1; + assign io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid; + assign io_ctrl_rsp_payload_last = _zz_io_ctrl_rsp_payload_last; + assign io_ctrl_rsp_payload_fragment_opcode = _zz_io_ctrl_rsp_payload_fragment_opcode; + assign io_ctrl_rsp_payload_fragment_data = _zz_io_ctrl_rsp_payload_fragment_data; + assign io_ctrl_rsp_payload_fragment_context = _zz_io_ctrl_rsp_payload_fragment_context; + assign busCtrl_askWrite = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_askRead = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign io_ctrl_cmd_fire = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); + assign busCtrl_doWrite = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_doRead = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign busCtrl_rsp_valid = io_ctrl_cmd_valid; + assign io_ctrl_cmd_ready = busCtrl_rsp_ready; + assign busCtrl_rsp_payload_last = 1'b1; + assign when_BmbSlaveFactory_l33 = (busCtrl_doWrite && busCtrl_writeErrorFlag); + always @(*) begin + if(when_BmbSlaveFactory_l33) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + if(when_BmbSlaveFactory_l35) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + busCtrl_rsp_payload_fragment_opcode = 1'b0; + end + end + end + + assign when_BmbSlaveFactory_l35 = (busCtrl_doRead && busCtrl_readErrorFlag); + always @(*) begin + busCtrl_rsp_payload_fragment_data = 32'h0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h08 : begin + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_rxData_valid; + busCtrl_rsp_payload_fragment_data[7 : 0] = bridge_rxData_value; + end + 8'h0c : begin + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_rxAck_valid; + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_rxAck_value; + end + 8'h0 : begin + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_txData_valid; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_txData_enable; + end + 8'h04 : begin + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_txAck_valid; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_txAck_enable; + end + 8'h80 : begin + busCtrl_rsp_payload_fragment_data[1 : 0] = {bridge_addressFilter_hits_1,bridge_addressFilter_hits_0}; + end + 8'h84 : begin + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_addressFilter_byte0[0]; + end + 8'h40 : begin + busCtrl_rsp_payload_fragment_data[4 : 4] = bridge_masterLogic_start; + busCtrl_rsp_payload_fragment_data[5 : 5] = bridge_masterLogic_stop; + busCtrl_rsp_payload_fragment_data[6 : 6] = bridge_masterLogic_drop; + busCtrl_rsp_payload_fragment_data[7 : 7] = bridge_masterLogic_recover; + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_masterLogic_fsm_isBusy; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_masterLogic_fsm_dropped_start; + busCtrl_rsp_payload_fragment_data[10 : 10] = bridge_masterLogic_fsm_dropped_stop; + busCtrl_rsp_payload_fragment_data[11 : 11] = bridge_masterLogic_fsm_dropped_recover; + end + 8'h20 : begin + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_interruptCtrl_rxDataEnable; + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_interruptCtrl_rxAckEnable; + busCtrl_rsp_payload_fragment_data[2 : 2] = bridge_interruptCtrl_txDataEnable; + busCtrl_rsp_payload_fragment_data[3 : 3] = bridge_interruptCtrl_txAckEnable; + busCtrl_rsp_payload_fragment_data[4 : 4] = bridge_interruptCtrl_start_enable; + busCtrl_rsp_payload_fragment_data[5 : 5] = bridge_interruptCtrl_restart_enable; + busCtrl_rsp_payload_fragment_data[6 : 6] = bridge_interruptCtrl_end_enable; + busCtrl_rsp_payload_fragment_data[7 : 7] = bridge_interruptCtrl_drop_enable; + busCtrl_rsp_payload_fragment_data[17 : 17] = bridge_interruptCtrl_filterGen_enable; + busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_interruptCtrl_clockGenExit_enable; + busCtrl_rsp_payload_fragment_data[16 : 16] = bridge_interruptCtrl_clockGenEnter_enable; + end + 8'h24 : begin + busCtrl_rsp_payload_fragment_data[4 : 4] = bridge_interruptCtrl_start_flag; + busCtrl_rsp_payload_fragment_data[5 : 5] = bridge_interruptCtrl_restart_flag; + busCtrl_rsp_payload_fragment_data[6 : 6] = bridge_interruptCtrl_end_flag; + busCtrl_rsp_payload_fragment_data[7 : 7] = bridge_interruptCtrl_drop_flag; + busCtrl_rsp_payload_fragment_data[17 : 17] = bridge_interruptCtrl_filterGen_flag; + busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_interruptCtrl_clockGenExit_flag; + busCtrl_rsp_payload_fragment_data[16 : 16] = bridge_interruptCtrl_clockGenEnter_flag; + end + 8'h44 : begin + busCtrl_rsp_payload_fragment_data[0 : 0] = i2cCtrl_io_internals_inFrame; + busCtrl_rsp_payload_fragment_data[1 : 1] = i2cCtrl_io_internals_sdaRead; + busCtrl_rsp_payload_fragment_data[2 : 2] = i2cCtrl_io_internals_sclRead; + end + 8'h48 : begin + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_slaveOverride_sda; + busCtrl_rsp_payload_fragment_data[2 : 2] = bridge_slaveOverride_scl; + end + default : begin + end + endcase + end + + assign busCtrl_rsp_payload_fragment_context = io_ctrl_cmd_payload_fragment_context; + assign bridge_busCtrlWithOffset_readErrorFlag = 1'b0; + assign bridge_busCtrlWithOffset_writeErrorFlag = 1'b0; + always @(*) begin + bridge_frameReset = 1'b0; + case(i2cCtrl_io_bus_cmd_kind) + Axi4PeripheralI2cSlaveCmdMode_START : begin + bridge_frameReset = 1'b1; + end + Axi4PeripheralI2cSlaveCmdMode_RESTART : begin + bridge_frameReset = 1'b1; + end + Axi4PeripheralI2cSlaveCmdMode_STOP : begin + bridge_frameReset = 1'b1; + end + Axi4PeripheralI2cSlaveCmdMode_DROP : begin + bridge_frameReset = 1'b1; + end + default : begin + end + endcase + end + + always @(*) begin + bridge_i2cBuffer_sda_write = i2cCtrl_io_i2c_sda_write; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + bridge_i2cBuffer_sda_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + bridge_i2cBuffer_sda_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + bridge_i2cBuffer_sda_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + bridge_i2cBuffer_sda_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + end + endcase + if(when_I2cCtrl_l673) begin + bridge_i2cBuffer_sda_write = 1'b0; + end + end + + always @(*) begin + bridge_i2cBuffer_scl_write = i2cCtrl_io_i2c_scl_write; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + bridge_i2cBuffer_scl_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + if(bridge_masterLogic_timer_done) begin + if(when_I2cCtrl_l418) begin + bridge_i2cBuffer_scl_write = 1'b0; + end else begin + if(when_I2cCtrl_l422) begin + bridge_i2cBuffer_scl_write = 1'b0; + end + end + end else begin + bridge_i2cBuffer_scl_write = 1'b0; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + bridge_i2cBuffer_scl_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + end + endcase + if(when_I2cCtrl_l674) begin + bridge_i2cBuffer_scl_write = 1'b0; + end + end + + always @(*) begin + when_I2cCtrl_l224 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h08 : begin + if(busCtrl_doRead) begin + when_I2cCtrl_l224 = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + when_I2cCtrl_l237 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h0c : begin + if(busCtrl_doRead) begin + when_I2cCtrl_l237 = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + bridge_txData_forceDisable = 1'b0; + if(when_I2cCtrl_l601) begin + bridge_txData_forceDisable = 1'b0; + end + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + if(bridge_masterLogic_timer_done) begin + if(when_I2cCtrl_l418) begin + bridge_txData_forceDisable = 1'b1; + end else begin + if(when_I2cCtrl_l422) begin + bridge_txData_forceDisable = 1'b1; + end + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + end + endcase + end + + always @(*) begin + bridge_txAck_forceAck = 1'b0; + if(when_I2cCtrl_l306) begin + bridge_txAck_forceAck = 1'b1; + end + end + + assign bridge_addressFilter_byte0Is10Bit = (bridge_addressFilter_byte0[7 : 3] == 5'h1e); + assign bridge_addressFilter_hits_0 = (bridge_addressFilter_addresses_0_enable && ((! bridge_addressFilter_addresses_0_is10Bit) ? ((_zz_bridge_addressFilter_hits_0 == bridge_addressFilter_addresses_0_value[6 : 0]) && (bridge_addressFilter_state != 2'b00)) : (({bridge_addressFilter_byte0[2 : 1],bridge_addressFilter_byte1} == bridge_addressFilter_addresses_0_value) && (bridge_addressFilter_state == 2'b10)))); + assign bridge_addressFilter_hits_1 = (bridge_addressFilter_addresses_1_enable && ((! bridge_addressFilter_addresses_1_is10Bit) ? ((_zz_bridge_addressFilter_hits_1 == bridge_addressFilter_addresses_1_value[6 : 0]) && (bridge_addressFilter_state != 2'b00)) : (({bridge_addressFilter_byte0[2 : 1],bridge_addressFilter_byte1} == bridge_addressFilter_addresses_1_value) && (bridge_addressFilter_state == 2'b10)))); + assign when_I2cCtrl_l306 = ((bridge_addressFilter_byte0Is10Bit && (bridge_addressFilter_state == 2'b01)) && (|{((bridge_addressFilter_addresses_1_enable && bridge_addressFilter_addresses_1_is10Bit) && (bridge_addressFilter_byte0[2 : 1] == bridge_addressFilter_addresses_1_value[9 : 8])),((bridge_addressFilter_addresses_0_enable && bridge_addressFilter_addresses_0_is10Bit) && (bridge_addressFilter_byte0[2 : 1] == bridge_addressFilter_addresses_0_value[9 : 8]))})); + assign _zz_when_I2cCtrl_l310 = (|{bridge_addressFilter_hits_1,bridge_addressFilter_hits_0}); + assign when_I2cCtrl_l310 = (_zz_when_I2cCtrl_l310 && (! _zz_when_I2cCtrl_l310_1)); + always @(*) begin + when_BusSlaveFactory_l377 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l377 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379 = io_ctrl_cmd_payload_fragment_data[4]; + always @(*) begin + when_BusSlaveFactory_l377_1 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l377_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_1 = io_ctrl_cmd_payload_fragment_data[5]; + always @(*) begin + when_BusSlaveFactory_l377_2 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l377_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_2 = io_ctrl_cmd_payload_fragment_data[6]; + always @(*) begin + when_BusSlaveFactory_l377_3 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l377_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_3 = io_ctrl_cmd_payload_fragment_data[7]; + assign bridge_masterLogic_timer_done = (bridge_masterLogic_timer_value == 12'h0); + assign bridge_masterLogic_fsm_wantExit = 1'b0; + always @(*) begin + bridge_masterLogic_fsm_wantStart = 1'b0; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + bridge_masterLogic_fsm_wantStart = 1'b1; + end + endcase + end + + assign bridge_masterLogic_fsm_wantKill = 1'b0; + always @(*) begin + bridge_masterLogic_fsm_dropped_trigger = 1'b0; + if(when_I2cCtrl_l350) begin + bridge_masterLogic_fsm_dropped_trigger = 1'b1; + end + end + + assign when_I2cCtrl_l363 = (! i2cCtrl_io_internals_sclRead); + assign when_I2cCtrl_l363_1 = (! i2cCtrl_io_internals_inFrame); + assign bridge_masterLogic_fsm_outOfSync = ((! i2cCtrl_io_internals_inFrame) && ((! i2cCtrl_io_internals_sdaRead) || (! i2cCtrl_io_internals_sclRead))); + assign bridge_masterLogic_fsm_isBusy = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE)) && (! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF))); + always @(*) begin + when_BusSlaveFactory_l341 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347 = io_ctrl_cmd_payload_fragment_data[9]; + always @(*) begin + when_BusSlaveFactory_l341_1 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_1 = io_ctrl_cmd_payload_fragment_data[10]; + always @(*) begin + when_BusSlaveFactory_l341_2 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_2 = io_ctrl_cmd_payload_fragment_data[11]; + assign bridge_masterLogic_txReady = (bridge_inAckState ? bridge_txAck_valid : bridge_txData_valid); + assign when_I2cCtrl_l523 = (! bridge_inAckState); + always @(*) begin + if(when_I2cCtrl_l523) begin + i2cCtrl_io_bus_rsp_valid = ((bridge_txData_valid && (! (bridge_rxData_valid && bridge_rxData_listen))) && (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DRIVE)); + if(bridge_txData_forceDisable) begin + i2cCtrl_io_bus_rsp_valid = 1'b1; + end + end else begin + i2cCtrl_io_bus_rsp_valid = ((bridge_txAck_valid && (! (bridge_rxAck_valid && bridge_rxAck_listen))) && (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DRIVE)); + if(bridge_txAck_forceAck) begin + i2cCtrl_io_bus_rsp_valid = 1'b1; + end + end + if(when_I2cCtrl_l546) begin + i2cCtrl_io_bus_rsp_valid = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DRIVE); + end + end + + always @(*) begin + if(when_I2cCtrl_l523) begin + i2cCtrl_io_bus_rsp_enable = bridge_txData_enable; + if(bridge_txData_forceDisable) begin + i2cCtrl_io_bus_rsp_enable = 1'b0; + end + end else begin + i2cCtrl_io_bus_rsp_enable = bridge_txAck_enable; + if(bridge_txAck_forceAck) begin + i2cCtrl_io_bus_rsp_enable = 1'b1; + end + end + if(when_I2cCtrl_l546) begin + i2cCtrl_io_bus_rsp_enable = 1'b0; + end + end + + always @(*) begin + if(when_I2cCtrl_l523) begin + i2cCtrl_io_bus_rsp_data = bridge_txData_value[_zz_io_bus_rsp_data]; + end else begin + i2cCtrl_io_bus_rsp_data = bridge_txAck_value; + if(bridge_txAck_forceAck) begin + i2cCtrl_io_bus_rsp_data = 1'b0; + end + end + end + + assign when_I2cCtrl_l546 = (bridge_wasntAck && (! bridge_masterLogic_fsm_isBusy)); + assign when_I2cCtrl_l566 = (! bridge_inAckState); + assign when_I2cCtrl_l570 = (i2cCtrl_io_bus_rsp_data != i2cCtrl_io_bus_cmd_data); + assign when_I2cCtrl_l574 = (bridge_dataCounter == 3'b111); + assign when_I2cCtrl_l578 = (bridge_txData_valid && (! bridge_txData_repeat)); + assign when_I2cCtrl_l588 = (bridge_txAck_valid && (! bridge_txAck_repeat)); + assign when_I2cCtrl_l601 = ((i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_STOP) || (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DROP)); + always @(*) begin + bridge_interruptCtrl_interrupt = ((((bridge_interruptCtrl_rxDataEnable && bridge_rxData_valid) || (bridge_interruptCtrl_rxAckEnable && bridge_rxAck_valid)) || (bridge_interruptCtrl_txDataEnable && (! bridge_txData_valid))) || (bridge_interruptCtrl_txAckEnable && (! bridge_txAck_valid))); + if(bridge_interruptCtrl_start_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_restart_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_end_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_drop_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_filterGen_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_clockGenExit_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_clockGenEnter_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + end + + assign when_I2cCtrl_l634 = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_START); + assign when_I2cCtrl_l634_1 = (! bridge_interruptCtrl_start_enable); + always @(*) begin + when_BusSlaveFactory_l341_3 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_3 = io_ctrl_cmd_payload_fragment_data[4]; + assign when_I2cCtrl_l634_2 = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_RESTART); + assign when_I2cCtrl_l634_3 = (! bridge_interruptCtrl_restart_enable); + always @(*) begin + when_BusSlaveFactory_l341_4 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_4 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_4 = io_ctrl_cmd_payload_fragment_data[5]; + assign when_I2cCtrl_l634_4 = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_STOP); + assign when_I2cCtrl_l634_5 = (! bridge_interruptCtrl_end_enable); + always @(*) begin + when_BusSlaveFactory_l341_5 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_5 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_5 = io_ctrl_cmd_payload_fragment_data[6]; + assign when_I2cCtrl_l634_6 = ((i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DROP) || bridge_masterLogic_fsm_dropped_trigger); + assign when_I2cCtrl_l634_7 = (! bridge_interruptCtrl_drop_enable); + always @(*) begin + when_BusSlaveFactory_l341_6 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_6 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_6 = io_ctrl_cmd_payload_fragment_data[7]; + assign _zz_when_I2cCtrl_l634 = (|{bridge_addressFilter_hits_1,bridge_addressFilter_hits_0}); + assign when_I2cCtrl_l634_8 = (_zz_when_I2cCtrl_l634 && (! _zz_when_I2cCtrl_l634_1)); + assign when_I2cCtrl_l634_9 = (! bridge_interruptCtrl_filterGen_enable); + always @(*) begin + when_BusSlaveFactory_l341_7 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_7 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_7 = io_ctrl_cmd_payload_fragment_data[17]; + assign when_I2cCtrl_l634_10 = ((! bridge_masterLogic_fsm_isBusy) && bridge_masterLogic_fsm_isBusy_regNext); + assign when_I2cCtrl_l634_11 = (! bridge_interruptCtrl_clockGenExit_enable); + always @(*) begin + when_BusSlaveFactory_l341_8 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_8 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_8 = io_ctrl_cmd_payload_fragment_data[15]; + assign when_I2cCtrl_l634_12 = (bridge_masterLogic_fsm_isBusy && (! bridge_masterLogic_fsm_isBusy_regNext_1)); + assign when_I2cCtrl_l634_13 = (! bridge_interruptCtrl_clockGenEnter_enable); + always @(*) begin + when_BusSlaveFactory_l341_9 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_9 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_9 = io_ctrl_cmd_payload_fragment_data[16]; + always @(*) begin + i2cCtrl_io_config_timeoutClear = bridge_timeoutClear; + if(when_I2cCtrl_l659) begin + i2cCtrl_io_config_timeoutClear = 1'b1; + end + end + + assign when_I2cCtrl_l659 = ((! i2cCtrl_io_internals_inFrame) && (! bridge_masterLogic_fsm_isBusy)); + always @(*) begin + bridge_masterLogic_fsm_stateNext = bridge_masterLogic_fsm_stateReg; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + if(when_I2cCtrl_l367) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF; + end else begin + if(when_I2cCtrl_l369) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1; + end else begin + if(bridge_masterLogic_recover) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW; + end + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + if(when_I2cCtrl_l380) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + if(when_I2cCtrl_l392) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + if(bridge_masterLogic_timer_done) begin + if(when_I2cCtrl_l418) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1; + end else begin + if(when_I2cCtrl_l422) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART; + end else begin + if(i2cCtrl_io_internals_sclRead) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH; + end + end + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + if(when_I2cCtrl_l442) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + if(!when_I2cCtrl_l450) begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1; + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + if(!when_I2cCtrl_l474) begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3; + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + if(i2cCtrl_io_internals_sdaRead) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE; + end + end + default : begin + end + endcase + if(when_I2cCtrl_l350) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF; + end + if(bridge_masterLogic_fsm_wantStart) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE; + end + if(bridge_masterLogic_fsm_wantKill) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT; + end + end + + assign when_I2cCtrl_l367 = ((! i2cCtrl_io_internals_inFrame) && i2cCtrl_io_internals_inFrame_regNext); + assign when_I2cCtrl_l369 = (bridge_masterLogic_start && (! bridge_masterLogic_fsm_inFrameLate)); + assign when_I2cCtrl_l380 = (! bridge_masterLogic_fsm_outOfSync); + assign when_I2cCtrl_l392 = (bridge_masterLogic_timer_done || (! i2cCtrl_io_internals_sclRead)); + assign when_I2cCtrl_l418 = ((bridge_masterLogic_stop && (! bridge_inAckState)) || (bridge_masterLogic_recover && i2cCtrl_io_internals_sdaRead)); + assign when_I2cCtrl_l422 = (bridge_masterLogic_start && (! bridge_inAckState)); + assign when_I2cCtrl_l442 = (bridge_masterLogic_timer_done || (! i2cCtrl_io_internals_sclRead)); + assign when_I2cCtrl_l450 = (! i2cCtrl_io_internals_sclRead); + assign when_I2cCtrl_l474 = (! i2cCtrl_io_internals_sclRead); + assign when_StateMachine_l253 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2)); + assign when_StateMachine_l253_1 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3)); + assign when_StateMachine_l253_2 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW)); + assign when_StateMachine_l253_3 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH)); + assign when_StateMachine_l253_4 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1)); + assign when_StateMachine_l253_5 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF)); + assign when_I2cCtrl_l350 = (bridge_masterLogic_drop || ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE)) && ((i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DROP) || i2cCtrl_io_timeout))); + assign when_I2cCtrl_l673 = (! bridge_slaveOverride_sda); + assign when_I2cCtrl_l674 = (! bridge_slaveOverride_scl); + assign io_i2c_scl_write = bridge_i2cBuffer_scl_write_regNext; + assign io_i2c_sda_write = bridge_i2cBuffer_sda_write_regNext; + assign bridge_i2cBuffer_scl_read = io_i2c_scl_read; + assign bridge_i2cBuffer_sda_read = io_i2c_sda_read; + assign system_i2c_0_io_interrupt_source = bridge_interruptCtrl_interrupt; + always @(posedge clk) begin + if(reset) begin + _zz_io_ctrl_rsp_valid_1 <= 1'b0; + bridge_rxData_event <= 1'b0; + bridge_rxData_listen <= 1'b0; + bridge_rxData_valid <= 1'b0; + bridge_rxAck_listen <= 1'b0; + bridge_rxAck_valid <= 1'b0; + bridge_txData_valid <= 1'b1; + bridge_txData_repeat <= 1'b1; + bridge_txData_enable <= 1'b0; + bridge_txAck_valid <= 1'b1; + bridge_txAck_repeat <= 1'b1; + bridge_txAck_enable <= 1'b0; + bridge_addressFilter_addresses_0_enable <= 1'b0; + bridge_addressFilter_addresses_1_enable <= 1'b0; + bridge_addressFilter_state <= 2'b00; + bridge_masterLogic_start <= 1'b0; + bridge_masterLogic_stop <= 1'b0; + bridge_masterLogic_drop <= 1'b0; + bridge_masterLogic_recover <= 1'b0; + bridge_masterLogic_fsm_dropped_start <= 1'b0; + bridge_masterLogic_fsm_dropped_stop <= 1'b0; + bridge_masterLogic_fsm_dropped_recover <= 1'b0; + bridge_dataCounter <= 3'b000; + bridge_inAckState <= 1'b0; + bridge_wasntAck <= 1'b0; + bridge_interruptCtrl_rxDataEnable <= 1'b0; + bridge_interruptCtrl_rxAckEnable <= 1'b0; + bridge_interruptCtrl_txDataEnable <= 1'b0; + bridge_interruptCtrl_txAckEnable <= 1'b0; + bridge_interruptCtrl_start_enable <= 1'b0; + bridge_interruptCtrl_start_flag <= 1'b0; + bridge_interruptCtrl_restart_enable <= 1'b0; + bridge_interruptCtrl_restart_flag <= 1'b0; + bridge_interruptCtrl_end_enable <= 1'b0; + bridge_interruptCtrl_end_flag <= 1'b0; + bridge_interruptCtrl_drop_enable <= 1'b0; + bridge_interruptCtrl_drop_flag <= 1'b0; + bridge_interruptCtrl_filterGen_enable <= 1'b0; + bridge_interruptCtrl_filterGen_flag <= 1'b0; + bridge_interruptCtrl_clockGenExit_enable <= 1'b0; + bridge_interruptCtrl_clockGenExit_flag <= 1'b0; + bridge_interruptCtrl_clockGenEnter_enable <= 1'b0; + bridge_interruptCtrl_clockGenEnter_flag <= 1'b0; + _zz_io_config_samplingClockDivider <= 10'h0; + bridge_masterLogic_fsm_stateReg <= Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT; + bridge_slaveOverride_sda <= 1'b1; + bridge_slaveOverride_scl <= 1'b1; + bridge_i2cBuffer_scl_write_regNext <= 1'b1; + bridge_i2cBuffer_sda_write_regNext <= 1'b1; + end else begin + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_ctrl_rsp_valid_1 <= (busCtrl_rsp_valid && _zz_busCtrl_rsp_ready); + end + bridge_rxData_event <= 1'b0; + if(when_I2cCtrl_l224) begin + bridge_rxData_valid <= 1'b0; + end + if(when_I2cCtrl_l237) begin + bridge_rxAck_valid <= 1'b0; + end + if(bridge_rxData_event) begin + case(bridge_addressFilter_state) + 2'b00 : begin + bridge_addressFilter_state <= 2'b01; + end + 2'b01 : begin + bridge_addressFilter_state <= 2'b10; + end + default : begin + end + endcase + end + if(bridge_frameReset) begin + bridge_addressFilter_state <= 2'b00; + end + if(when_I2cCtrl_l310) begin + bridge_txAck_valid <= 1'b0; + end + if(when_BusSlaveFactory_l377) begin + if(when_BusSlaveFactory_l379) begin + bridge_masterLogic_start <= _zz_bridge_masterLogic_start[0]; + end + end + if(when_BusSlaveFactory_l377_1) begin + if(when_BusSlaveFactory_l379_1) begin + bridge_masterLogic_stop <= _zz_bridge_masterLogic_stop[0]; + end + end + if(when_BusSlaveFactory_l377_2) begin + if(when_BusSlaveFactory_l379_2) begin + bridge_masterLogic_drop <= _zz_bridge_masterLogic_drop[0]; + end + end + if(when_BusSlaveFactory_l377_3) begin + if(when_BusSlaveFactory_l379_3) begin + bridge_masterLogic_recover <= _zz_bridge_masterLogic_recover[0]; + end + end + if(when_BusSlaveFactory_l341) begin + if(when_BusSlaveFactory_l347) begin + bridge_masterLogic_fsm_dropped_start <= _zz_bridge_masterLogic_fsm_dropped_start[0]; + end + end + if(when_BusSlaveFactory_l341_1) begin + if(when_BusSlaveFactory_l347_1) begin + bridge_masterLogic_fsm_dropped_stop <= _zz_bridge_masterLogic_fsm_dropped_stop[0]; + end + end + if(when_BusSlaveFactory_l341_2) begin + if(when_BusSlaveFactory_l347_2) begin + bridge_masterLogic_fsm_dropped_recover <= _zz_bridge_masterLogic_fsm_dropped_recover[0]; + end + end + case(i2cCtrl_io_bus_cmd_kind) + Axi4PeripheralI2cSlaveCmdMode_READ : begin + if(when_I2cCtrl_l566) begin + bridge_dataCounter <= (bridge_dataCounter + 3'b001); + if(when_I2cCtrl_l570) begin + if(bridge_txData_disableOnDataConflict) begin + bridge_txData_enable <= 1'b0; + end + if(bridge_txAck_disableOnDataConflict) begin + bridge_txAck_enable <= 1'b0; + end + end + if(when_I2cCtrl_l574) begin + if(bridge_rxData_listen) begin + bridge_rxData_valid <= 1'b1; + end + bridge_rxData_event <= 1'b1; + bridge_inAckState <= 1'b1; + if(when_I2cCtrl_l578) begin + bridge_txData_valid <= 1'b0; + end + end + end else begin + if(bridge_rxAck_listen) begin + bridge_rxAck_valid <= 1'b1; + end + bridge_inAckState <= 1'b0; + bridge_wasntAck <= i2cCtrl_io_bus_cmd_data; + if(when_I2cCtrl_l588) begin + bridge_txAck_valid <= 1'b0; + end + end + end + default : begin + end + endcase + if(bridge_frameReset) begin + bridge_inAckState <= 1'b0; + bridge_dataCounter <= 3'b000; + bridge_wasntAck <= 1'b0; + end + if(when_I2cCtrl_l601) begin + bridge_txData_valid <= 1'b1; + bridge_txData_enable <= 1'b0; + bridge_txData_repeat <= 1'b1; + bridge_txAck_valid <= 1'b1; + bridge_txAck_enable <= 1'b0; + bridge_txAck_repeat <= 1'b1; + bridge_rxData_listen <= 1'b0; + bridge_rxAck_listen <= 1'b0; + end + if(when_I2cCtrl_l634) begin + bridge_interruptCtrl_start_flag <= 1'b1; + end + if(when_I2cCtrl_l634_1) begin + bridge_interruptCtrl_start_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_3) begin + if(when_BusSlaveFactory_l347_3) begin + bridge_interruptCtrl_start_flag <= _zz_bridge_interruptCtrl_start_flag[0]; + end + end + if(when_I2cCtrl_l634_2) begin + bridge_interruptCtrl_restart_flag <= 1'b1; + end + if(when_I2cCtrl_l634_3) begin + bridge_interruptCtrl_restart_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_4) begin + if(when_BusSlaveFactory_l347_4) begin + bridge_interruptCtrl_restart_flag <= _zz_bridge_interruptCtrl_restart_flag[0]; + end + end + if(when_I2cCtrl_l634_4) begin + bridge_interruptCtrl_end_flag <= 1'b1; + end + if(when_I2cCtrl_l634_5) begin + bridge_interruptCtrl_end_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_5) begin + if(when_BusSlaveFactory_l347_5) begin + bridge_interruptCtrl_end_flag <= _zz_bridge_interruptCtrl_end_flag[0]; + end + end + if(when_I2cCtrl_l634_6) begin + bridge_interruptCtrl_drop_flag <= 1'b1; + end + if(when_I2cCtrl_l634_7) begin + bridge_interruptCtrl_drop_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_6) begin + if(when_BusSlaveFactory_l347_6) begin + bridge_interruptCtrl_drop_flag <= _zz_bridge_interruptCtrl_drop_flag[0]; + end + end + if(when_I2cCtrl_l634_8) begin + bridge_interruptCtrl_filterGen_flag <= 1'b1; + end + if(when_I2cCtrl_l634_9) begin + bridge_interruptCtrl_filterGen_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_7) begin + if(when_BusSlaveFactory_l347_7) begin + bridge_interruptCtrl_filterGen_flag <= _zz_bridge_interruptCtrl_filterGen_flag[0]; + end + end + if(when_I2cCtrl_l634_10) begin + bridge_interruptCtrl_clockGenExit_flag <= 1'b1; + end + if(when_I2cCtrl_l634_11) begin + bridge_interruptCtrl_clockGenExit_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_8) begin + if(when_BusSlaveFactory_l347_8) begin + bridge_interruptCtrl_clockGenExit_flag <= _zz_bridge_interruptCtrl_clockGenExit_flag[0]; + end + end + if(when_I2cCtrl_l634_12) begin + bridge_interruptCtrl_clockGenEnter_flag <= 1'b1; + end + if(when_I2cCtrl_l634_13) begin + bridge_interruptCtrl_clockGenEnter_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_9) begin + if(when_BusSlaveFactory_l347_9) begin + bridge_interruptCtrl_clockGenEnter_flag <= _zz_bridge_interruptCtrl_clockGenEnter_flag[0]; + end + end + bridge_masterLogic_fsm_stateReg <= bridge_masterLogic_fsm_stateNext; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + if(!when_I2cCtrl_l367) begin + if(when_I2cCtrl_l369) begin + bridge_txData_valid <= 1'b0; + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_start <= 1'b0; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + if(i2cCtrl_io_internals_sdaRead) begin + bridge_masterLogic_stop <= 1'b0; + bridge_masterLogic_recover <= 1'b0; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + end + endcase + if(when_I2cCtrl_l350) begin + bridge_masterLogic_start <= 1'b0; + bridge_masterLogic_stop <= 1'b0; + bridge_masterLogic_drop <= 1'b0; + bridge_masterLogic_recover <= 1'b0; + if(bridge_masterLogic_start) begin + bridge_masterLogic_fsm_dropped_start <= 1'b1; + end + if(bridge_masterLogic_stop) begin + bridge_masterLogic_fsm_dropped_stop <= 1'b1; + end + end + bridge_i2cBuffer_scl_write_regNext <= bridge_i2cBuffer_scl_write; + bridge_i2cBuffer_sda_write_regNext <= bridge_i2cBuffer_sda_write; + case(io_ctrl_cmd_payload_fragment_address) + 8'h08 : begin + if(busCtrl_doWrite) begin + bridge_rxData_listen <= io_ctrl_cmd_payload_fragment_data[9]; + end + end + 8'h0c : begin + if(busCtrl_doWrite) begin + bridge_rxAck_listen <= io_ctrl_cmd_payload_fragment_data[9]; + end + end + 8'h0 : begin + if(busCtrl_doWrite) begin + bridge_txData_repeat <= io_ctrl_cmd_payload_fragment_data[10]; + bridge_txData_valid <= io_ctrl_cmd_payload_fragment_data[8]; + bridge_txData_enable <= io_ctrl_cmd_payload_fragment_data[9]; + end + end + 8'h04 : begin + if(busCtrl_doWrite) begin + bridge_txAck_repeat <= io_ctrl_cmd_payload_fragment_data[10]; + bridge_txAck_valid <= io_ctrl_cmd_payload_fragment_data[8]; + bridge_txAck_enable <= io_ctrl_cmd_payload_fragment_data[9]; + end + end + 8'h88 : begin + if(busCtrl_doWrite) begin + bridge_addressFilter_addresses_0_enable <= io_ctrl_cmd_payload_fragment_data[15]; + end + end + 8'h8c : begin + if(busCtrl_doWrite) begin + bridge_addressFilter_addresses_1_enable <= io_ctrl_cmd_payload_fragment_data[15]; + end + end + 8'h20 : begin + if(busCtrl_doWrite) begin + bridge_interruptCtrl_rxDataEnable <= io_ctrl_cmd_payload_fragment_data[0]; + bridge_interruptCtrl_rxAckEnable <= io_ctrl_cmd_payload_fragment_data[1]; + bridge_interruptCtrl_txDataEnable <= io_ctrl_cmd_payload_fragment_data[2]; + bridge_interruptCtrl_txAckEnable <= io_ctrl_cmd_payload_fragment_data[3]; + bridge_interruptCtrl_start_enable <= io_ctrl_cmd_payload_fragment_data[4]; + bridge_interruptCtrl_restart_enable <= io_ctrl_cmd_payload_fragment_data[5]; + bridge_interruptCtrl_end_enable <= io_ctrl_cmd_payload_fragment_data[6]; + bridge_interruptCtrl_drop_enable <= io_ctrl_cmd_payload_fragment_data[7]; + bridge_interruptCtrl_filterGen_enable <= io_ctrl_cmd_payload_fragment_data[17]; + bridge_interruptCtrl_clockGenExit_enable <= io_ctrl_cmd_payload_fragment_data[15]; + bridge_interruptCtrl_clockGenEnter_enable <= io_ctrl_cmd_payload_fragment_data[16]; + end + end + 8'h28 : begin + if(busCtrl_doWrite) begin + _zz_io_config_samplingClockDivider <= io_ctrl_cmd_payload_fragment_data[9 : 0]; + end + end + 8'h48 : begin + if(busCtrl_doWrite) begin + bridge_slaveOverride_sda <= io_ctrl_cmd_payload_fragment_data[1]; + bridge_slaveOverride_scl <= io_ctrl_cmd_payload_fragment_data[2]; + end + end + default : begin + end + endcase + end + end + + always @(posedge clk) begin + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_ctrl_rsp_payload_last <= busCtrl_rsp_payload_last; + _zz_io_ctrl_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; + _zz_io_ctrl_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; + _zz_io_ctrl_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; + end + if(bridge_rxData_event) begin + case(bridge_addressFilter_state) + 2'b00 : begin + bridge_addressFilter_byte0 <= bridge_rxData_value; + end + 2'b01 : begin + bridge_addressFilter_byte1 <= bridge_rxData_value; + end + default : begin + end + endcase + end + _zz_when_I2cCtrl_l310_1 <= _zz_when_I2cCtrl_l310; + bridge_masterLogic_timer_value <= (bridge_masterLogic_timer_value - _zz_bridge_masterLogic_timer_value); + if(when_I2cCtrl_l363) begin + bridge_masterLogic_fsm_inFrameLate <= 1'b1; + end + if(when_I2cCtrl_l363_1) begin + bridge_masterLogic_fsm_inFrameLate <= 1'b0; + end + case(i2cCtrl_io_bus_cmd_kind) + Axi4PeripheralI2cSlaveCmdMode_READ : begin + if(when_I2cCtrl_l566) begin + bridge_rxData_value[_zz_bridge_rxData_value] <= i2cCtrl_io_bus_cmd_data; + end else begin + bridge_rxAck_value <= i2cCtrl_io_bus_cmd_data; + end + end + default : begin + end + endcase + if(when_I2cCtrl_l601) begin + bridge_txData_disableOnDataConflict <= 1'b0; + bridge_txAck_disableOnDataConflict <= 1'b0; + end + _zz_when_I2cCtrl_l634_1 <= _zz_when_I2cCtrl_l634; + bridge_masterLogic_fsm_isBusy_regNext <= bridge_masterLogic_fsm_isBusy; + bridge_masterLogic_fsm_isBusy_regNext_1 <= bridge_masterLogic_fsm_isBusy; + bridge_timeoutClear <= 1'b0; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + if(when_I2cCtrl_l450) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + if(when_I2cCtrl_l474) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + end + endcase + if(when_StateMachine_l253) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; + end + if(when_StateMachine_l253_1) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tLow; + end + if(when_StateMachine_l253_2) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tLow; + end + if(when_StateMachine_l253_3) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; + end + if(when_StateMachine_l253_4) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; + end + if(when_StateMachine_l253_5) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tBuf; + end + case(io_ctrl_cmd_payload_fragment_address) + 8'h0 : begin + if(busCtrl_doWrite) begin + bridge_txData_value <= io_ctrl_cmd_payload_fragment_data[7 : 0]; + bridge_txData_disableOnDataConflict <= io_ctrl_cmd_payload_fragment_data[11]; + end + end + 8'h04 : begin + if(busCtrl_doWrite) begin + bridge_txAck_value <= io_ctrl_cmd_payload_fragment_data[0]; + bridge_txAck_disableOnDataConflict <= io_ctrl_cmd_payload_fragment_data[11]; + end + end + 8'h88 : begin + if(busCtrl_doWrite) begin + bridge_addressFilter_addresses_0_value <= io_ctrl_cmd_payload_fragment_data[9 : 0]; + bridge_addressFilter_addresses_0_is10Bit <= io_ctrl_cmd_payload_fragment_data[14]; + end + end + 8'h8c : begin + if(busCtrl_doWrite) begin + bridge_addressFilter_addresses_1_value <= io_ctrl_cmd_payload_fragment_data[9 : 0]; + bridge_addressFilter_addresses_1_is10Bit <= io_ctrl_cmd_payload_fragment_data[14]; + end + end + 8'h50 : begin + if(busCtrl_doWrite) begin + bridge_masterLogic_timer_tLow <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 8'h54 : begin + if(busCtrl_doWrite) begin + bridge_masterLogic_timer_tHigh <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 8'h58 : begin + if(busCtrl_doWrite) begin + bridge_masterLogic_timer_tBuf <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 8'h2c : begin + if(busCtrl_doWrite) begin + _zz_io_config_timeout <= io_ctrl_cmd_payload_fragment_data[19 : 0]; + bridge_timeoutClear <= 1'b1; + end + end + 8'h30 : begin + if(busCtrl_doWrite) begin + _zz_io_config_tsuData <= io_ctrl_cmd_payload_fragment_data[5 : 0]; + end + end + default : begin + end + endcase + end + + always @(posedge clk) begin + if(reset) begin + i2cCtrl_io_internals_inFrame_regNext <= 1'b0; + end else begin + i2cCtrl_io_internals_inFrame_regNext <= i2cCtrl_io_internals_inFrame; + end + end + + +endmodule + +module Axi4PeripheralBmbSpiXdrMasterCtrl_be6ad777990c4e5089d0b11c63cc2698 ( + input wire io_ctrl_cmd_valid, + output wire io_ctrl_cmd_ready, + input wire io_ctrl_cmd_payload_last, + input wire [0:0] io_ctrl_cmd_payload_fragment_opcode, + input wire [11:0] io_ctrl_cmd_payload_fragment_address, + input wire [1:0] io_ctrl_cmd_payload_fragment_length, + input wire [31:0] io_ctrl_cmd_payload_fragment_data, + input wire [2:0] io_ctrl_cmd_payload_fragment_context, + output wire io_ctrl_rsp_valid, + input wire io_ctrl_rsp_ready, + output wire io_ctrl_rsp_payload_last, + output wire [0:0] io_ctrl_rsp_payload_fragment_opcode, + output wire [31:0] io_ctrl_rsp_payload_fragment_data, + output wire [2:0] io_ctrl_rsp_payload_fragment_context, + output wire [0:0] io_spi_sclk_write, + output wire io_spi_data_0_writeEnable, + input wire [0:0] io_spi_data_0_read, + output wire [0:0] io_spi_data_0_write, + output wire io_spi_data_1_writeEnable, + input wire [0:0] io_spi_data_1_read, + output wire [0:0] io_spi_data_1_write, + output wire io_spi_data_2_writeEnable, + input wire [0:0] io_spi_data_2_read, + output wire [0:0] io_spi_data_2_write, + output wire io_spi_data_3_writeEnable, + input wire [0:0] io_spi_data_3_read, + output wire [0:0] io_spi_data_3_write, + output wire [3:0] io_spi_ss, + output wire system_spi_0_io_interrupt_source, + input wire clk, + input wire reset +); + + wire ctrl_io_rsp_queueWithOccupancy_io_pop_ready; + wire ctrl_io_cmd_ready; + wire ctrl_io_rsp_valid; + wire [7:0] ctrl_io_rsp_payload_data; + wire [0:0] ctrl_io_spi_sclk_write; + wire [3:0] ctrl_io_spi_ss; + wire [0:0] ctrl_io_spi_data_0_write; + wire ctrl_io_spi_data_0_writeEnable; + wire [0:0] ctrl_io_spi_data_1_write; + wire ctrl_io_spi_data_1_writeEnable; + wire [0:0] ctrl_io_spi_data_2_write; + wire ctrl_io_spi_data_2_writeEnable; + wire [0:0] ctrl_io_spi_data_3_write; + wire ctrl_io_spi_data_3_writeEnable; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; + wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy; + wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; + wire ctrl_io_rsp_queueWithOccupancy_io_push_ready; + wire ctrl_io_rsp_queueWithOccupancy_io_pop_valid; + wire [7:0] ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_occupancy; + wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_availability; + wire factory_readErrorFlag; + wire factory_writeErrorFlag; + wire factory_readHaltTrigger; + wire factory_writeHaltTrigger; + wire factory_rsp_valid; + wire factory_rsp_ready; + wire factory_rsp_payload_last; + reg [0:0] factory_rsp_payload_fragment_opcode; + reg [31:0] factory_rsp_payload_fragment_data; + wire [2:0] factory_rsp_payload_fragment_context; + wire _zz_factory_rsp_ready; + reg _zz_factory_rsp_ready_1; + wire _zz_io_ctrl_rsp_valid; + reg _zz_io_ctrl_rsp_valid_1; + reg _zz_io_ctrl_rsp_payload_last; + reg [0:0] _zz_io_ctrl_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_ctrl_rsp_payload_fragment_data; + reg [2:0] _zz_io_ctrl_rsp_payload_fragment_context; + wire when_Stream_l375; + wire factory_askWrite; + wire factory_askRead; + wire io_ctrl_cmd_fire; + wire factory_doWrite; + wire factory_doRead; + wire when_BmbSlaveFactory_l33; + wire when_BmbSlaveFactory_l35; + wire [31:0] mapping_cmdLogic_writeData; + reg mapping_cmdLogic_doRegular; + reg mapping_cmdLogic_doWriteLarge; + reg mapping_cmdLogic_doReadWriteLarge; + wire mapping_cmdLogic_streamUnbuffered_valid; + wire mapping_cmdLogic_streamUnbuffered_ready; + wire mapping_cmdLogic_streamUnbuffered_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_payload_read; + wire mapping_cmdLogic_streamUnbuffered_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_payload_data; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write; + reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; + reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; + wire when_Stream_l375_1; + wire ctrl_io_rsp_toStream_valid; + wire ctrl_io_rsp_toStream_ready; + wire [7:0] ctrl_io_rsp_toStream_payload_data; + reg _zz_io_pop_ready; + reg _zz_io_pop_ready_1; + reg mapping_interruptCtrl_cmdIntEnable; + reg mapping_interruptCtrl_rspIntEnable; + wire mapping_interruptCtrl_cmdInt; + wire mapping_interruptCtrl_rspInt; + wire mapping_interruptCtrl_interrupt; + reg _zz_io_config_kind_cpol; + reg _zz_io_config_kind_cpha; + reg [1:0] _zz_io_config_mod; + reg [11:0] _zz_io_config_sclkToggle; + reg [11:0] _zz_io_config_ss_setup; + reg [11:0] _zz_io_config_ss_hold; + reg [11:0] _zz_io_config_ss_disable; + reg [3:0] _zz_io_config_ss_activeHigh; + wire [1:0] _zz_io_config_kind_cpol_1; + + Axi4PeripheralTopLevel_be6ad777990c4e5089d0b11c63cc2698 ctrl ( + .io_config_kind_cpol (_zz_io_config_kind_cpol ), //i + .io_config_kind_cpha (_zz_io_config_kind_cpha ), //i + .io_config_sclkToggle (_zz_io_config_sclkToggle[11:0] ), //i + .io_config_mod (_zz_io_config_mod[1:0] ), //i + .io_config_ss_activeHigh (_zz_io_config_ss_activeHigh[3:0] ), //i + .io_config_ss_setup (_zz_io_config_ss_setup[11:0] ), //i + .io_config_ss_hold (_zz_io_config_ss_hold[11:0] ), //i + .io_config_ss_disable (_zz_io_config_ss_disable[11:0] ), //i + .io_cmd_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid ), //i + .io_cmd_ready (ctrl_io_cmd_ready ), //o + .io_cmd_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind ), //i + .io_cmd_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read ), //i + .io_cmd_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write ), //i + .io_cmd_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data[7:0]), //i + .io_rsp_valid (ctrl_io_rsp_valid ), //o + .io_rsp_payload_data (ctrl_io_rsp_payload_data[7:0] ), //o + .io_spi_sclk_write (ctrl_io_spi_sclk_write ), //o + .io_spi_data_0_writeEnable (ctrl_io_spi_data_0_writeEnable ), //o + .io_spi_data_0_read (io_spi_data_0_read ), //i + .io_spi_data_0_write (ctrl_io_spi_data_0_write ), //o + .io_spi_data_1_writeEnable (ctrl_io_spi_data_1_writeEnable ), //o + .io_spi_data_1_read (io_spi_data_1_read ), //i + .io_spi_data_1_write (ctrl_io_spi_data_1_write ), //o + .io_spi_data_2_writeEnable (ctrl_io_spi_data_2_writeEnable ), //o + .io_spi_data_2_read (io_spi_data_2_read ), //i + .io_spi_data_2_write (ctrl_io_spi_data_2_write ), //o + .io_spi_data_3_writeEnable (ctrl_io_spi_data_3_writeEnable ), //o + .io_spi_data_3_read (io_spi_data_3_read ), //i + .io_spi_data_3_write (ctrl_io_spi_data_3_write ), //o + .io_spi_ss (ctrl_io_spi_ss[3:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralStreamFifo_2_be6ad777990c4e5089d0b11c63cc2698 mapping_cmdLogic_streamUnbuffered_queueWithAvailability ( + .io_push_valid (mapping_cmdLogic_streamUnbuffered_valid ), //i + .io_push_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready ), //o + .io_push_payload_kind (mapping_cmdLogic_streamUnbuffered_payload_kind ), //i + .io_push_payload_read (mapping_cmdLogic_streamUnbuffered_payload_read ), //i + .io_push_payload_write (mapping_cmdLogic_streamUnbuffered_payload_write ), //i + .io_push_payload_data (mapping_cmdLogic_streamUnbuffered_payload_data[7:0] ), //i + .io_pop_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid ), //o + .io_pop_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ), //i + .io_pop_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind ), //o + .io_pop_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read ), //o + .io_pop_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write ), //o + .io_pop_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data[7:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy[8:0] ), //o + .io_availability (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability[8:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralStreamFifo_3_be6ad777990c4e5089d0b11c63cc2698 ctrl_io_rsp_queueWithOccupancy ( + .io_push_valid (ctrl_io_rsp_toStream_valid ), //i + .io_push_ready (ctrl_io_rsp_queueWithOccupancy_io_push_ready ), //o + .io_push_payload_data (ctrl_io_rsp_toStream_payload_data[7:0] ), //i + .io_pop_valid (ctrl_io_rsp_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (ctrl_io_rsp_queueWithOccupancy_io_pop_ready ), //i + .io_pop_payload_data (ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data[7:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (ctrl_io_rsp_queueWithOccupancy_io_occupancy[8:0] ), //o + .io_availability (ctrl_io_rsp_queueWithOccupancy_io_availability[8:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + assign factory_readErrorFlag = 1'b0; + assign factory_writeErrorFlag = 1'b0; + assign factory_readHaltTrigger = 1'b0; + assign factory_writeHaltTrigger = 1'b0; + assign _zz_factory_rsp_ready = (! (factory_readHaltTrigger || factory_writeHaltTrigger)); + assign factory_rsp_ready = (_zz_factory_rsp_ready_1 && _zz_factory_rsp_ready); + always @(*) begin + _zz_factory_rsp_ready_1 = io_ctrl_rsp_ready; + if(when_Stream_l375) begin + _zz_factory_rsp_ready_1 = 1'b1; + end + end + + assign when_Stream_l375 = (! _zz_io_ctrl_rsp_valid); + assign _zz_io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid_1; + assign io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid; + assign io_ctrl_rsp_payload_last = _zz_io_ctrl_rsp_payload_last; + assign io_ctrl_rsp_payload_fragment_opcode = _zz_io_ctrl_rsp_payload_fragment_opcode; + assign io_ctrl_rsp_payload_fragment_data = _zz_io_ctrl_rsp_payload_fragment_data; + assign io_ctrl_rsp_payload_fragment_context = _zz_io_ctrl_rsp_payload_fragment_context; + assign factory_askWrite = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign factory_askRead = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign io_ctrl_cmd_fire = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); + assign factory_doWrite = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign factory_doRead = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign factory_rsp_valid = io_ctrl_cmd_valid; + assign io_ctrl_cmd_ready = factory_rsp_ready; + assign factory_rsp_payload_last = 1'b1; + assign when_BmbSlaveFactory_l33 = (factory_doWrite && factory_writeErrorFlag); + always @(*) begin + if(when_BmbSlaveFactory_l33) begin + factory_rsp_payload_fragment_opcode = 1'b1; + end else begin + if(when_BmbSlaveFactory_l35) begin + factory_rsp_payload_fragment_opcode = 1'b1; + end else begin + factory_rsp_payload_fragment_opcode = 1'b0; + end + end + end + + assign when_BmbSlaveFactory_l35 = (factory_doRead && factory_readErrorFlag); + always @(*) begin + factory_rsp_payload_fragment_data = 32'h0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + factory_rsp_payload_fragment_data[31 : 31] = (! ctrl_io_rsp_queueWithOccupancy_io_pop_valid); + factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + end + 12'h004 : begin + factory_rsp_payload_fragment_data[8 : 0] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; + factory_rsp_payload_fragment_data[24 : 16] = ctrl_io_rsp_queueWithOccupancy_io_occupancy; + end + 12'h00c : begin + factory_rsp_payload_fragment_data[16 : 16] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; + factory_rsp_payload_fragment_data[0 : 0] = mapping_interruptCtrl_cmdIntEnable; + factory_rsp_payload_fragment_data[1 : 1] = mapping_interruptCtrl_rspIntEnable; + factory_rsp_payload_fragment_data[8 : 8] = mapping_interruptCtrl_cmdInt; + factory_rsp_payload_fragment_data[9 : 9] = mapping_interruptCtrl_rspInt; + end + 12'h058 : begin + factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + end + default : begin + end + endcase + end + + assign factory_rsp_payload_fragment_context = io_ctrl_cmd_payload_fragment_context; + always @(*) begin + mapping_cmdLogic_doRegular = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doRegular = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + mapping_cmdLogic_doWriteLarge = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h050 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doWriteLarge = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + mapping_cmdLogic_doReadWriteLarge = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h054 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doReadWriteLarge = 1'b1; + end + end + default : begin + end + endcase + end + + assign mapping_cmdLogic_streamUnbuffered_valid = ((mapping_cmdLogic_doRegular || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_write = (((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[8]) || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_read = ((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[9]) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_kind = (mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[11]); + assign mapping_cmdLogic_streamUnbuffered_payload_data = mapping_cmdLogic_writeData[7:0]; + assign mapping_cmdLogic_streamUnbuffered_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid || (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN)); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data); + always @(*) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; + if(when_Stream_l375_1) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375_1 = (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready = ctrl_io_cmd_ready; + assign ctrl_io_rsp_toStream_valid = ctrl_io_rsp_valid; + assign ctrl_io_rsp_toStream_payload_data = ctrl_io_rsp_payload_data; + assign ctrl_io_rsp_toStream_ready = ctrl_io_rsp_queueWithOccupancy_io_push_ready; + always @(*) begin + _zz_io_pop_ready = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + if(factory_doRead) begin + _zz_io_pop_ready = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + _zz_io_pop_ready_1 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h058 : begin + if(factory_doRead) begin + _zz_io_pop_ready_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign ctrl_io_rsp_queueWithOccupancy_io_pop_ready = (_zz_io_pop_ready || _zz_io_pop_ready_1); + assign mapping_interruptCtrl_cmdInt = (mapping_interruptCtrl_cmdIntEnable && (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid)); + assign mapping_interruptCtrl_rspInt = (mapping_interruptCtrl_rspIntEnable && ctrl_io_rsp_queueWithOccupancy_io_pop_valid); + assign mapping_interruptCtrl_interrupt = (mapping_interruptCtrl_rspInt || mapping_interruptCtrl_cmdInt); + assign io_spi_sclk_write = ctrl_io_spi_sclk_write; + assign io_spi_data_0_writeEnable = ctrl_io_spi_data_0_writeEnable; + assign io_spi_data_0_write = ctrl_io_spi_data_0_write; + assign io_spi_data_1_writeEnable = ctrl_io_spi_data_1_writeEnable; + assign io_spi_data_1_write = ctrl_io_spi_data_1_write; + assign io_spi_data_2_writeEnable = ctrl_io_spi_data_2_writeEnable; + assign io_spi_data_2_write = ctrl_io_spi_data_2_write; + assign io_spi_data_3_writeEnable = ctrl_io_spi_data_3_writeEnable; + assign io_spi_data_3_write = ctrl_io_spi_data_3_write; + assign io_spi_ss = ctrl_io_spi_ss; + assign system_spi_0_io_interrupt_source = mapping_interruptCtrl_interrupt; + assign mapping_cmdLogic_writeData = io_ctrl_cmd_payload_fragment_data[31 : 0]; + assign _zz_io_config_kind_cpol_1 = io_ctrl_cmd_payload_fragment_data[1 : 0]; + always @(posedge clk) begin + if(reset) begin + _zz_io_ctrl_rsp_valid_1 <= 1'b0; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN <= 1'b1; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= 1'b0; + mapping_interruptCtrl_cmdIntEnable <= 1'b0; + mapping_interruptCtrl_rspIntEnable <= 1'b0; + _zz_io_config_ss_activeHigh <= 4'b0000; + end else begin + if(_zz_factory_rsp_ready_1) begin + _zz_io_ctrl_rsp_valid_1 <= (factory_rsp_valid && _zz_factory_rsp_ready); + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN <= 1'b0; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN <= 1'b1; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; + end + case(io_ctrl_cmd_payload_fragment_address) + 12'h00c : begin + if(factory_doWrite) begin + mapping_interruptCtrl_cmdIntEnable <= io_ctrl_cmd_payload_fragment_data[0]; + mapping_interruptCtrl_rspIntEnable <= io_ctrl_cmd_payload_fragment_data[1]; + end + end + 12'h030 : begin + if(factory_doWrite) begin + _zz_io_config_ss_activeHigh <= io_ctrl_cmd_payload_fragment_data[3 : 0]; + end + end + default : begin + end + endcase + end + end + + always @(posedge clk) begin + if(_zz_factory_rsp_ready_1) begin + _zz_io_ctrl_rsp_payload_last <= factory_rsp_payload_last; + _zz_io_ctrl_rsp_payload_fragment_opcode <= factory_rsp_payload_fragment_opcode; + _zz_io_ctrl_rsp_payload_fragment_data <= factory_rsp_payload_fragment_data; + _zz_io_ctrl_rsp_payload_fragment_context <= factory_rsp_payload_fragment_context; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; + end + case(io_ctrl_cmd_payload_fragment_address) + 12'h008 : begin + if(factory_doWrite) begin + _zz_io_config_kind_cpol <= _zz_io_config_kind_cpol_1[0]; + _zz_io_config_kind_cpha <= _zz_io_config_kind_cpol_1[1]; + _zz_io_config_mod <= io_ctrl_cmd_payload_fragment_data[5 : 4]; + end + end + 12'h020 : begin + if(factory_doWrite) begin + _zz_io_config_sclkToggle <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h024 : begin + if(factory_doWrite) begin + _zz_io_config_ss_setup <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h028 : begin + if(factory_doWrite) begin + _zz_io_config_ss_hold <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h02c : begin + if(factory_doWrite) begin + _zz_io_config_ss_disable <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + default : begin + end + endcase + end + + +endmodule + +module Axi4PeripheralBmbUartCtrl_be6ad777990c4e5089d0b11c63cc2698 ( + input wire io_bus_cmd_valid, + output wire io_bus_cmd_ready, + input wire io_bus_cmd_payload_last, + input wire [0:0] io_bus_cmd_payload_fragment_opcode, + input wire [5:0] io_bus_cmd_payload_fragment_address, + input wire [1:0] io_bus_cmd_payload_fragment_length, + input wire [31:0] io_bus_cmd_payload_fragment_data, + input wire [2:0] io_bus_cmd_payload_fragment_context, + output wire io_bus_rsp_valid, + input wire io_bus_rsp_ready, + output wire io_bus_rsp_payload_last, + output wire [0:0] io_bus_rsp_payload_fragment_opcode, + output wire [31:0] io_bus_rsp_payload_fragment_data, + output wire [2:0] io_bus_rsp_payload_fragment_context, + output wire io_uart_txd, + input wire io_uart_rxd, + output wire system_uart_0_io_interrupt_source, + input wire clk, + input wire reset +); + localparam Axi4PeripheralUartStopType_ONE = 1'd0; + localparam Axi4PeripheralUartStopType_TWO = 1'd1; + localparam Axi4PeripheralUartParityType_NONE = 2'd0; + localparam Axi4PeripheralUartParityType_EVEN = 2'd1; + localparam Axi4PeripheralUartParityType_ODD = 2'd2; + + reg uartCtrl_io_read_queueWithOccupancy_io_pop_ready; + wire uartCtrl_io_write_ready; + wire uartCtrl_io_read_valid; + wire [7:0] uartCtrl_io_read_payload; + wire uartCtrl_io_uart_txd; + wire uartCtrl_io_readError; + wire uartCtrl_io_readBreak; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_availability; + wire uartCtrl_io_read_queueWithOccupancy_io_push_ready; + wire uartCtrl_io_read_queueWithOccupancy_io_pop_valid; + wire [7:0] uartCtrl_io_read_queueWithOccupancy_io_pop_payload; + wire [7:0] uartCtrl_io_read_queueWithOccupancy_io_occupancy; + wire [7:0] uartCtrl_io_read_queueWithOccupancy_io_availability; + wire [0:0] _zz_bridge_misc_readError; + wire [0:0] _zz_bridge_misc_readOverflowError; + wire [0:0] _zz_bridge_misc_breakDetected; + wire [0:0] _zz_bridge_misc_doBreak; + wire [0:0] _zz_bridge_misc_doBreak_1; + wire [7:0] _zz_busCtrl_rsp_payload_fragment_data; + wire busCtrl_readErrorFlag; + wire busCtrl_writeErrorFlag; + wire busCtrl_readHaltTrigger; + wire busCtrl_writeHaltTrigger; + wire busCtrl_rsp_valid; + wire busCtrl_rsp_ready; + wire busCtrl_rsp_payload_last; + reg [0:0] busCtrl_rsp_payload_fragment_opcode; + reg [31:0] busCtrl_rsp_payload_fragment_data; + wire [2:0] busCtrl_rsp_payload_fragment_context; + wire _zz_busCtrl_rsp_ready; + reg _zz_busCtrl_rsp_ready_1; + wire _zz_io_bus_rsp_valid; + reg _zz_io_bus_rsp_valid_1; + reg _zz_io_bus_rsp_payload_last; + reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_bus_rsp_payload_fragment_data; + reg [2:0] _zz_io_bus_rsp_payload_fragment_context; + wire when_Stream_l375; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire io_bus_cmd_fire; + wire busCtrl_doWrite; + wire busCtrl_doRead; + wire when_BmbSlaveFactory_l33; + wire when_BmbSlaveFactory_l35; + wire bridge_busCtrlWrapped_readErrorFlag; + wire bridge_busCtrlWrapped_writeErrorFlag; + reg [2:0] bridge_uartConfigReg_frame_dataLength; + reg [0:0] bridge_uartConfigReg_frame_stop; + reg [1:0] bridge_uartConfigReg_frame_parity; + reg [19:0] bridge_uartConfigReg_clockDivider; + reg _zz_bridge_write_streamUnbuffered_valid; + wire bridge_write_streamUnbuffered_valid; + wire bridge_write_streamUnbuffered_ready; + wire [7:0] bridge_write_streamUnbuffered_payload; + reg bridge_read_streamBreaked_valid; + reg bridge_read_streamBreaked_ready; + wire [7:0] bridge_read_streamBreaked_payload; + reg bridge_interruptCtrl_writeIntEnable; + reg bridge_interruptCtrl_readIntEnable; + wire bridge_interruptCtrl_readInt; + wire bridge_interruptCtrl_writeInt; + wire bridge_interruptCtrl_interrupt; + reg bridge_misc_readError; + reg when_BusSlaveFactory_l341; + wire when_BusSlaveFactory_l347; + reg bridge_misc_readOverflowError; + reg when_BusSlaveFactory_l341_1; + wire when_BusSlaveFactory_l347_1; + wire uartCtrl_io_read_isStall; + reg bridge_misc_breakDetected; + reg uartCtrl_io_readBreak_regNext; + wire when_UartCtrl_l155; + reg when_BusSlaveFactory_l341_2; + wire when_BusSlaveFactory_l347_2; + reg bridge_misc_doBreak; + reg when_BusSlaveFactory_l377; + wire when_BusSlaveFactory_l379; + reg when_BusSlaveFactory_l341_3; + wire when_BusSlaveFactory_l347_3; + wire [1:0] _zz_bridge_uartConfigReg_frame_parity; + wire [0:0] _zz_bridge_uartConfigReg_frame_stop; + wire when_BmbSlaveFactory_l77; + `ifndef SYNTHESIS + reg [23:0] bridge_uartConfigReg_frame_stop_string; + reg [31:0] bridge_uartConfigReg_frame_parity_string; + reg [31:0] _zz_bridge_uartConfigReg_frame_parity_string; + reg [23:0] _zz_bridge_uartConfigReg_frame_stop_string; + `endif + + + assign _zz_bridge_misc_readError = 1'b0; + assign _zz_bridge_misc_readOverflowError = 1'b0; + assign _zz_bridge_misc_breakDetected = 1'b0; + assign _zz_bridge_misc_doBreak = 1'b1; + assign _zz_bridge_misc_doBreak_1 = 1'b0; + assign _zz_busCtrl_rsp_payload_fragment_data = (8'h80 - bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy); + Axi4PeripheralUartCtrl_be6ad777990c4e5089d0b11c63cc2698 uartCtrl ( + .io_config_frame_dataLength (bridge_uartConfigReg_frame_dataLength[2:0] ), //i + .io_config_frame_stop (bridge_uartConfigReg_frame_stop ), //i + .io_config_frame_parity (bridge_uartConfigReg_frame_parity[1:0] ), //i + .io_config_clockDivider (bridge_uartConfigReg_clockDivider[19:0] ), //i + .io_write_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //i + .io_write_ready (uartCtrl_io_write_ready ), //o + .io_write_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0]), //i + .io_read_valid (uartCtrl_io_read_valid ), //o + .io_read_ready (uartCtrl_io_read_queueWithOccupancy_io_push_ready ), //i + .io_read_payload (uartCtrl_io_read_payload[7:0] ), //o + .io_uart_txd (uartCtrl_io_uart_txd ), //o + .io_uart_rxd (io_uart_rxd ), //i + .io_readError (uartCtrl_io_readError ), //o + .io_writeBreak (bridge_misc_doBreak ), //i + .io_readBreak (uartCtrl_io_readBreak ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralStreamFifo_be6ad777990c4e5089d0b11c63cc2698 bridge_write_streamUnbuffered_queueWithOccupancy ( + .io_push_valid (bridge_write_streamUnbuffered_valid ), //i + .io_push_ready (bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready ), //o + .io_push_payload (bridge_write_streamUnbuffered_payload[7:0] ), //i + .io_pop_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (uartCtrl_io_write_ready ), //i + .io_pop_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy[7:0] ), //o + .io_availability (bridge_write_streamUnbuffered_queueWithOccupancy_io_availability[7:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralStreamFifo_be6ad777990c4e5089d0b11c63cc2698 uartCtrl_io_read_queueWithOccupancy ( + .io_push_valid (uartCtrl_io_read_valid ), //i + .io_push_ready (uartCtrl_io_read_queueWithOccupancy_io_push_ready ), //o + .io_push_payload (uartCtrl_io_read_payload[7:0] ), //i + .io_pop_valid (uartCtrl_io_read_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (uartCtrl_io_read_queueWithOccupancy_io_pop_ready ), //i + .io_pop_payload (uartCtrl_io_read_queueWithOccupancy_io_pop_payload[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (uartCtrl_io_read_queueWithOccupancy_io_occupancy[7:0] ), //o + .io_availability (uartCtrl_io_read_queueWithOccupancy_io_availability[7:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(bridge_uartConfigReg_frame_stop) + Axi4PeripheralUartStopType_ONE : bridge_uartConfigReg_frame_stop_string = "ONE"; + Axi4PeripheralUartStopType_TWO : bridge_uartConfigReg_frame_stop_string = "TWO"; + default : bridge_uartConfigReg_frame_stop_string = "???"; + endcase + end + always @(*) begin + case(bridge_uartConfigReg_frame_parity) + Axi4PeripheralUartParityType_NONE : bridge_uartConfigReg_frame_parity_string = "NONE"; + Axi4PeripheralUartParityType_EVEN : bridge_uartConfigReg_frame_parity_string = "EVEN"; + Axi4PeripheralUartParityType_ODD : bridge_uartConfigReg_frame_parity_string = "ODD "; + default : bridge_uartConfigReg_frame_parity_string = "????"; + endcase + end + always @(*) begin + case(_zz_bridge_uartConfigReg_frame_parity) + Axi4PeripheralUartParityType_NONE : _zz_bridge_uartConfigReg_frame_parity_string = "NONE"; + Axi4PeripheralUartParityType_EVEN : _zz_bridge_uartConfigReg_frame_parity_string = "EVEN"; + Axi4PeripheralUartParityType_ODD : _zz_bridge_uartConfigReg_frame_parity_string = "ODD "; + default : _zz_bridge_uartConfigReg_frame_parity_string = "????"; + endcase + end + always @(*) begin + case(_zz_bridge_uartConfigReg_frame_stop) + Axi4PeripheralUartStopType_ONE : _zz_bridge_uartConfigReg_frame_stop_string = "ONE"; + Axi4PeripheralUartStopType_TWO : _zz_bridge_uartConfigReg_frame_stop_string = "TWO"; + default : _zz_bridge_uartConfigReg_frame_stop_string = "???"; + endcase + end + `endif + + assign io_uart_txd = uartCtrl_io_uart_txd; + assign busCtrl_readErrorFlag = 1'b0; + assign busCtrl_writeErrorFlag = 1'b0; + assign busCtrl_readHaltTrigger = 1'b0; + assign busCtrl_writeHaltTrigger = 1'b0; + assign _zz_busCtrl_rsp_ready = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); + assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready_1 && _zz_busCtrl_rsp_ready); + always @(*) begin + _zz_busCtrl_rsp_ready_1 = io_bus_rsp_ready; + if(when_Stream_l375) begin + _zz_busCtrl_rsp_ready_1 = 1'b1; + end + end + + assign when_Stream_l375 = (! _zz_io_bus_rsp_valid); + assign _zz_io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; + assign io_bus_rsp_valid = _zz_io_bus_rsp_valid; + assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; + assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; + assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; + assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; + assign busCtrl_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign busCtrl_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_doRead = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign busCtrl_rsp_valid = io_bus_cmd_valid; + assign io_bus_cmd_ready = busCtrl_rsp_ready; + assign busCtrl_rsp_payload_last = 1'b1; + assign when_BmbSlaveFactory_l33 = (busCtrl_doWrite && busCtrl_writeErrorFlag); + always @(*) begin + if(when_BmbSlaveFactory_l33) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + if(when_BmbSlaveFactory_l35) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + busCtrl_rsp_payload_fragment_opcode = 1'b0; + end + end + end + + assign when_BmbSlaveFactory_l35 = (busCtrl_doRead && busCtrl_readErrorFlag); + always @(*) begin + busCtrl_rsp_payload_fragment_data = 32'h0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + busCtrl_rsp_payload_fragment_data[16 : 16] = (bridge_read_streamBreaked_valid ^ 1'b0); + busCtrl_rsp_payload_fragment_data[7 : 0] = bridge_read_streamBreaked_payload; + end + 6'h04 : begin + busCtrl_rsp_payload_fragment_data[23 : 16] = _zz_busCtrl_rsp_payload_fragment_data; + busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; + busCtrl_rsp_payload_fragment_data[31 : 24] = uartCtrl_io_read_queueWithOccupancy_io_occupancy; + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_interruptCtrl_writeIntEnable; + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_interruptCtrl_readIntEnable; + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_interruptCtrl_writeInt; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_interruptCtrl_readInt; + end + 6'h10 : begin + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_misc_readError; + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_misc_readOverflowError; + busCtrl_rsp_payload_fragment_data[8 : 8] = uartCtrl_io_readBreak; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_misc_breakDetected; + end + default : begin + end + endcase + end + + assign busCtrl_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; + assign bridge_busCtrlWrapped_readErrorFlag = 1'b0; + assign bridge_busCtrlWrapped_writeErrorFlag = 1'b0; + always @(*) begin + _zz_bridge_write_streamUnbuffered_valid = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + if(busCtrl_doWrite) begin + _zz_bridge_write_streamUnbuffered_valid = 1'b1; + end + end + default : begin + end + endcase + end + + assign bridge_write_streamUnbuffered_valid = _zz_bridge_write_streamUnbuffered_valid; + assign bridge_write_streamUnbuffered_payload = io_bus_cmd_payload_fragment_data[7 : 0]; + assign bridge_write_streamUnbuffered_ready = bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + always @(*) begin + bridge_read_streamBreaked_valid = uartCtrl_io_read_queueWithOccupancy_io_pop_valid; + if(uartCtrl_io_readBreak) begin + bridge_read_streamBreaked_valid = 1'b0; + end + end + + always @(*) begin + uartCtrl_io_read_queueWithOccupancy_io_pop_ready = bridge_read_streamBreaked_ready; + if(uartCtrl_io_readBreak) begin + uartCtrl_io_read_queueWithOccupancy_io_pop_ready = 1'b1; + end + end + + assign bridge_read_streamBreaked_payload = uartCtrl_io_read_queueWithOccupancy_io_pop_payload; + always @(*) begin + bridge_read_streamBreaked_ready = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + if(busCtrl_doRead) begin + bridge_read_streamBreaked_ready = 1'b1; + end + end + default : begin + end + endcase + end + + assign bridge_interruptCtrl_readInt = (bridge_interruptCtrl_readIntEnable && bridge_read_streamBreaked_valid); + assign bridge_interruptCtrl_writeInt = (bridge_interruptCtrl_writeIntEnable && (! bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid)); + assign bridge_interruptCtrl_interrupt = (bridge_interruptCtrl_readInt || bridge_interruptCtrl_writeInt); + always @(*) begin + when_BusSlaveFactory_l341 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347 = io_bus_cmd_payload_fragment_data[0]; + always @(*) begin + when_BusSlaveFactory_l341_1 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_1 = io_bus_cmd_payload_fragment_data[1]; + assign uartCtrl_io_read_isStall = (uartCtrl_io_read_valid && (! uartCtrl_io_read_queueWithOccupancy_io_push_ready)); + assign when_UartCtrl_l155 = (uartCtrl_io_readBreak && (! uartCtrl_io_readBreak_regNext)); + always @(*) begin + when_BusSlaveFactory_l341_2 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_2 = io_bus_cmd_payload_fragment_data[9]; + always @(*) begin + when_BusSlaveFactory_l377 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l377 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379 = io_bus_cmd_payload_fragment_data[10]; + always @(*) begin + when_BusSlaveFactory_l341_3 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_3 = io_bus_cmd_payload_fragment_data[11]; + assign system_uart_0_io_interrupt_source = bridge_interruptCtrl_interrupt; + assign _zz_bridge_uartConfigReg_frame_parity = io_bus_cmd_payload_fragment_data[9 : 8]; + assign _zz_bridge_uartConfigReg_frame_stop = io_bus_cmd_payload_fragment_data[16 : 16]; + assign when_BmbSlaveFactory_l77 = ((io_bus_cmd_payload_fragment_address & (~ 6'h03)) == 6'h08); + always @(posedge clk) begin + if(reset) begin + _zz_io_bus_rsp_valid_1 <= 1'b0; + bridge_uartConfigReg_clockDivider <= 20'h0; + bridge_uartConfigReg_clockDivider <= 20'h000d8; + bridge_uartConfigReg_frame_dataLength <= 3'b111; + bridge_uartConfigReg_frame_parity <= Axi4PeripheralUartParityType_NONE; + bridge_uartConfigReg_frame_stop <= Axi4PeripheralUartStopType_ONE; + bridge_interruptCtrl_writeIntEnable <= 1'b0; + bridge_interruptCtrl_readIntEnable <= 1'b0; + bridge_misc_readError <= 1'b0; + bridge_misc_readOverflowError <= 1'b0; + bridge_misc_breakDetected <= 1'b0; + bridge_misc_doBreak <= 1'b0; + end else begin + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_bus_rsp_valid_1 <= (busCtrl_rsp_valid && _zz_busCtrl_rsp_ready); + end + if(when_BusSlaveFactory_l341) begin + if(when_BusSlaveFactory_l347) begin + bridge_misc_readError <= _zz_bridge_misc_readError[0]; + end + end + if(uartCtrl_io_readError) begin + bridge_misc_readError <= 1'b1; + end + if(when_BusSlaveFactory_l341_1) begin + if(when_BusSlaveFactory_l347_1) begin + bridge_misc_readOverflowError <= _zz_bridge_misc_readOverflowError[0]; + end + end + if(uartCtrl_io_read_isStall) begin + bridge_misc_readOverflowError <= 1'b1; + end + if(when_UartCtrl_l155) begin + bridge_misc_breakDetected <= 1'b1; + end + if(when_BusSlaveFactory_l341_2) begin + if(when_BusSlaveFactory_l347_2) begin + bridge_misc_breakDetected <= _zz_bridge_misc_breakDetected[0]; + end + end + if(when_BusSlaveFactory_l377) begin + if(when_BusSlaveFactory_l379) begin + bridge_misc_doBreak <= _zz_bridge_misc_doBreak[0]; + end + end + if(when_BusSlaveFactory_l341_3) begin + if(when_BusSlaveFactory_l347_3) begin + bridge_misc_doBreak <= _zz_bridge_misc_doBreak_1[0]; + end + end + case(io_bus_cmd_payload_fragment_address) + 6'h0c : begin + if(busCtrl_doWrite) begin + bridge_uartConfigReg_frame_dataLength <= io_bus_cmd_payload_fragment_data[2 : 0]; + bridge_uartConfigReg_frame_parity <= _zz_bridge_uartConfigReg_frame_parity; + bridge_uartConfigReg_frame_stop <= _zz_bridge_uartConfigReg_frame_stop; + end + end + 6'h04 : begin + if(busCtrl_doWrite) begin + bridge_interruptCtrl_writeIntEnable <= io_bus_cmd_payload_fragment_data[0]; + bridge_interruptCtrl_readIntEnable <= io_bus_cmd_payload_fragment_data[1]; + end + end + default : begin + end + endcase + if(when_BmbSlaveFactory_l77) begin + if(busCtrl_doWrite) begin + bridge_uartConfigReg_clockDivider[19 : 0] <= io_bus_cmd_payload_fragment_data[19 : 0]; + end + end + end + end + + always @(posedge clk) begin + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_bus_rsp_payload_last <= busCtrl_rsp_payload_last; + _zz_io_bus_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; + _zz_io_bus_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; + _zz_io_bus_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; + end + uartCtrl_io_readBreak_regNext <= uartCtrl_io_readBreak; + end + + +endmodule + +module Axi4PeripheralBmbDecoder_1_be6ad777990c4e5089d0b11c63cc2698 ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [23:0] io_input_cmd_payload_fragment_address, + input wire [1:0] io_input_cmd_payload_fragment_length, + input wire [31:0] io_input_cmd_payload_fragment_data, + input wire [3:0] io_input_cmd_payload_fragment_mask, + input wire [2:0] io_input_cmd_payload_fragment_context, + output reg io_input_rsp_valid, + input wire io_input_rsp_ready, + output reg io_input_rsp_payload_last, + output reg [0:0] io_input_rsp_payload_fragment_opcode, + output wire [31:0] io_input_rsp_payload_fragment_data, + output reg [2:0] io_input_rsp_payload_fragment_context, + output reg io_outputs_0_cmd_valid, + input wire io_outputs_0_cmd_ready, + output wire io_outputs_0_cmd_payload_last, + output wire [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_0_cmd_payload_fragment_address, + output wire [1:0] io_outputs_0_cmd_payload_fragment_length, + output wire [31:0] io_outputs_0_cmd_payload_fragment_data, + output wire [3:0] io_outputs_0_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_0_cmd_payload_fragment_context, + input wire io_outputs_0_rsp_valid, + output wire io_outputs_0_rsp_ready, + input wire io_outputs_0_rsp_payload_last, + input wire [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_0_rsp_payload_fragment_data, + input wire [2:0] io_outputs_0_rsp_payload_fragment_context, + output reg io_outputs_1_cmd_valid, + input wire io_outputs_1_cmd_ready, + output wire io_outputs_1_cmd_payload_last, + output wire [0:0] io_outputs_1_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_1_cmd_payload_fragment_address, + output wire [1:0] io_outputs_1_cmd_payload_fragment_length, + output wire [31:0] io_outputs_1_cmd_payload_fragment_data, + output wire [3:0] io_outputs_1_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_1_cmd_payload_fragment_context, + input wire io_outputs_1_rsp_valid, + output wire io_outputs_1_rsp_ready, + input wire io_outputs_1_rsp_payload_last, + input wire [0:0] io_outputs_1_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_1_rsp_payload_fragment_data, + input wire [2:0] io_outputs_1_rsp_payload_fragment_context, + output reg io_outputs_2_cmd_valid, + input wire io_outputs_2_cmd_ready, + output wire io_outputs_2_cmd_payload_last, + output wire [0:0] io_outputs_2_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_2_cmd_payload_fragment_address, + output wire [1:0] io_outputs_2_cmd_payload_fragment_length, + output wire [31:0] io_outputs_2_cmd_payload_fragment_data, + output wire [3:0] io_outputs_2_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_2_cmd_payload_fragment_context, + input wire io_outputs_2_rsp_valid, + output wire io_outputs_2_rsp_ready, + input wire io_outputs_2_rsp_payload_last, + input wire [0:0] io_outputs_2_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_2_rsp_payload_fragment_data, + input wire [2:0] io_outputs_2_rsp_payload_fragment_context, + output reg io_outputs_3_cmd_valid, + input wire io_outputs_3_cmd_ready, + output wire io_outputs_3_cmd_payload_last, + output wire [0:0] io_outputs_3_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_3_cmd_payload_fragment_address, + output wire [1:0] io_outputs_3_cmd_payload_fragment_length, + output wire [31:0] io_outputs_3_cmd_payload_fragment_data, + output wire [3:0] io_outputs_3_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_3_cmd_payload_fragment_context, + input wire io_outputs_3_rsp_valid, + output wire io_outputs_3_rsp_ready, + input wire io_outputs_3_rsp_payload_last, + input wire [0:0] io_outputs_3_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_3_rsp_payload_fragment_data, + input wire [2:0] io_outputs_3_rsp_payload_fragment_context, + output reg io_outputs_4_cmd_valid, + input wire io_outputs_4_cmd_ready, + output wire io_outputs_4_cmd_payload_last, + output wire [0:0] io_outputs_4_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_4_cmd_payload_fragment_address, + output wire [1:0] io_outputs_4_cmd_payload_fragment_length, + output wire [31:0] io_outputs_4_cmd_payload_fragment_data, + output wire [3:0] io_outputs_4_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_4_cmd_payload_fragment_context, + input wire io_outputs_4_rsp_valid, + output wire io_outputs_4_rsp_ready, + input wire io_outputs_4_rsp_payload_last, + input wire [0:0] io_outputs_4_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_4_rsp_payload_fragment_data, + input wire [2:0] io_outputs_4_rsp_payload_fragment_context, + output reg io_outputs_5_cmd_valid, + input wire io_outputs_5_cmd_ready, + output wire io_outputs_5_cmd_payload_last, + output wire [0:0] io_outputs_5_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_5_cmd_payload_fragment_address, + output wire [1:0] io_outputs_5_cmd_payload_fragment_length, + output wire [31:0] io_outputs_5_cmd_payload_fragment_data, + output wire [3:0] io_outputs_5_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_5_cmd_payload_fragment_context, + input wire io_outputs_5_rsp_valid, + output wire io_outputs_5_rsp_ready, + input wire io_outputs_5_rsp_payload_last, + input wire [0:0] io_outputs_5_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_5_rsp_payload_fragment_data, + input wire [2:0] io_outputs_5_rsp_payload_fragment_context, + input wire clk, + input wire reset +); + + wire [6:0] _zz_logic_rspPendingCounter; + wire [6:0] _zz_logic_rspPendingCounter_1; + wire [0:0] _zz_logic_rspPendingCounter_2; + wire [6:0] _zz_logic_rspPendingCounter_3; + wire [0:0] _zz_logic_rspPendingCounter_4; + reg _zz_io_input_rsp_payload_last_4; + reg [0:0] _zz_io_input_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_input_rsp_payload_fragment_data; + reg [2:0] _zz_io_input_rsp_payload_fragment_context; + wire logic_input_valid; + reg logic_input_ready; + wire logic_input_payload_last; + wire [0:0] logic_input_payload_fragment_opcode; + wire [23:0] logic_input_payload_fragment_address; + wire [1:0] logic_input_payload_fragment_length; + wire [31:0] logic_input_payload_fragment_data; + wire [3:0] logic_input_payload_fragment_mask; + wire [2:0] logic_input_payload_fragment_context; + wire logic_hitsS0_0; + wire logic_hitsS0_1; + wire logic_hitsS0_2; + wire logic_hitsS0_3; + wire logic_hitsS0_4; + wire logic_hitsS0_5; + wire logic_noHitS0; + wire _zz_io_outputs_0_cmd_payload_last; + wire _zz_io_outputs_1_cmd_payload_last; + wire _zz_io_outputs_2_cmd_payload_last; + wire _zz_io_outputs_3_cmd_payload_last; + wire _zz_io_outputs_4_cmd_payload_last; + wire _zz_io_outputs_5_cmd_payload_last; + reg [6:0] logic_rspPendingCounter; + wire logic_input_fire; + wire io_input_rsp_fire; + wire logic_cmdWait; + wire when_BmbDecoder_l56; + reg logic_rspHits_0; + reg logic_rspHits_1; + reg logic_rspHits_2; + reg logic_rspHits_3; + reg logic_rspHits_4; + reg logic_rspHits_5; + wire logic_rspPending; + wire logic_rspNoHitValid; + reg logic_rspNoHit_doIt; + wire when_BmbDecoder_l60; + wire when_BmbDecoder_l60_1; + reg logic_rspNoHit_singleBeatRsp; + reg [2:0] logic_rspNoHit_context; + wire _zz_io_input_rsp_payload_last; + wire _zz_io_input_rsp_payload_last_1; + wire _zz_io_input_rsp_payload_last_2; + wire [2:0] _zz_io_input_rsp_payload_last_3; + + assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); + assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); + assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; + assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; + always @(*) begin + case(_zz_io_input_rsp_payload_last_3) + 3'b000 : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_0_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_0_rsp_payload_fragment_context; + end + 3'b001 : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_1_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_1_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_1_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_1_rsp_payload_fragment_context; + end + 3'b010 : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_2_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_2_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_2_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_2_rsp_payload_fragment_context; + end + 3'b011 : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_3_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_3_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_3_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_3_rsp_payload_fragment_context; + end + 3'b100 : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_4_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_4_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_4_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_4_rsp_payload_fragment_context; + end + default : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_5_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_5_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_5_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_5_rsp_payload_fragment_context; + end + endcase + end + + assign logic_input_valid = io_input_cmd_valid; + assign io_input_cmd_ready = logic_input_ready; + assign logic_input_payload_last = io_input_cmd_payload_last; + assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign logic_input_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign logic_noHitS0 = (! (|{logic_hitsS0_5,{logic_hitsS0_4,{logic_hitsS0_3,{logic_hitsS0_2,{logic_hitsS0_1,logic_hitsS0_0}}}}})); + assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 24'h00003f)) == 24'h010000); + always @(*) begin + io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); + if(logic_cmdWait) begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; + assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; + assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_0_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_1 = ((io_input_cmd_payload_fragment_address & (~ 24'h000fff)) == 24'h030000); + always @(*) begin + io_outputs_1_cmd_valid = (logic_input_valid && logic_hitsS0_1); + if(logic_cmdWait) begin + io_outputs_1_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_1_cmd_payload_last = logic_input_payload_last; + assign io_outputs_1_cmd_payload_last = _zz_io_outputs_1_cmd_payload_last; + assign io_outputs_1_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_1_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_1_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_1_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_1_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_1_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_2 = ((io_input_cmd_payload_fragment_address & (~ 24'h0000ff)) == 24'h020000); + always @(*) begin + io_outputs_2_cmd_valid = (logic_input_valid && logic_hitsS0_2); + if(logic_cmdWait) begin + io_outputs_2_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_2_cmd_payload_last = logic_input_payload_last; + assign io_outputs_2_cmd_payload_last = _zz_io_outputs_2_cmd_payload_last; + assign io_outputs_2_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_2_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_2_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_2_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_2_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_2_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_3 = ((io_input_cmd_payload_fragment_address & (~ 24'h0000ff)) == 24'h040000); + always @(*) begin + io_outputs_3_cmd_valid = (logic_input_valid && logic_hitsS0_3); + if(logic_cmdWait) begin + io_outputs_3_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_3_cmd_payload_last = logic_input_payload_last; + assign io_outputs_3_cmd_payload_last = _zz_io_outputs_3_cmd_payload_last; + assign io_outputs_3_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_3_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_3_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_3_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_3_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_3_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_4 = ((io_input_cmd_payload_fragment_address & (~ 24'h0000ff)) == 24'h050000); + always @(*) begin + io_outputs_4_cmd_valid = (logic_input_valid && logic_hitsS0_4); + if(logic_cmdWait) begin + io_outputs_4_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_4_cmd_payload_last = logic_input_payload_last; + assign io_outputs_4_cmd_payload_last = _zz_io_outputs_4_cmd_payload_last; + assign io_outputs_4_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_4_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_4_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_4_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_4_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_4_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_5 = ((io_input_cmd_payload_fragment_address & (~ 24'h00ffff)) == 24'h100000); + always @(*) begin + io_outputs_5_cmd_valid = (logic_input_valid && logic_hitsS0_5); + if(logic_cmdWait) begin + io_outputs_5_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_5_cmd_payload_last = logic_input_payload_last; + assign io_outputs_5_cmd_payload_last = _zz_io_outputs_5_cmd_payload_last; + assign io_outputs_5_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_5_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_5_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_5_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_5_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_5_cmd_payload_fragment_context = logic_input_payload_fragment_context; + always @(*) begin + logic_input_ready = ((|{(logic_hitsS0_5 && io_outputs_5_cmd_ready),{(logic_hitsS0_4 && io_outputs_4_cmd_ready),{(logic_hitsS0_3 && io_outputs_3_cmd_ready),{(logic_hitsS0_2 && io_outputs_2_cmd_ready),{(logic_hitsS0_1 && io_outputs_1_cmd_ready),(logic_hitsS0_0 && io_outputs_0_cmd_ready)}}}}}) || logic_noHitS0); + if(logic_cmdWait) begin + logic_input_ready = 1'b0; + end + end + + assign logic_input_fire = (logic_input_valid && logic_input_ready); + assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); + assign logic_rspPending = (logic_rspPendingCounter != 7'h0); + assign logic_rspNoHitValid = (! (|{logic_rspHits_5,{logic_rspHits_4,{logic_rspHits_3,{logic_rspHits_2,{logic_rspHits_1,logic_rspHits_0}}}}})); + assign when_BmbDecoder_l60 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign when_BmbDecoder_l60_1 = ((logic_input_fire && logic_noHitS0) && logic_input_payload_last); + always @(*) begin + io_input_rsp_valid = ((|{io_outputs_5_rsp_valid,{io_outputs_4_rsp_valid,{io_outputs_3_rsp_valid,{io_outputs_2_rsp_valid,{io_outputs_1_rsp_valid,io_outputs_0_rsp_valid}}}}}) || (logic_rspPending && logic_rspNoHitValid)); + if(logic_rspNoHit_doIt) begin + io_input_rsp_valid = 1'b1; + end + end + + assign _zz_io_input_rsp_payload_last = ((logic_rspHits_1 || logic_rspHits_3) || logic_rspHits_5); + assign _zz_io_input_rsp_payload_last_1 = (logic_rspHits_2 || logic_rspHits_3); + assign _zz_io_input_rsp_payload_last_2 = (logic_rspHits_4 || logic_rspHits_5); + assign _zz_io_input_rsp_payload_last_3 = {_zz_io_input_rsp_payload_last_2,{_zz_io_input_rsp_payload_last_1,_zz_io_input_rsp_payload_last}}; + always @(*) begin + io_input_rsp_payload_last = _zz_io_input_rsp_payload_last_4; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_last = 1'b1; + end + end + + always @(*) begin + io_input_rsp_payload_fragment_opcode = _zz_io_input_rsp_payload_fragment_opcode; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_opcode = 1'b1; + end + end + + assign io_input_rsp_payload_fragment_data = _zz_io_input_rsp_payload_fragment_data; + always @(*) begin + io_input_rsp_payload_fragment_context = _zz_io_input_rsp_payload_fragment_context; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_context = logic_rspNoHit_context; + end + end + + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign io_outputs_1_rsp_ready = io_input_rsp_ready; + assign io_outputs_2_rsp_ready = io_input_rsp_ready; + assign io_outputs_3_rsp_ready = io_input_rsp_ready; + assign io_outputs_4_rsp_ready = io_input_rsp_ready; + assign io_outputs_5_rsp_ready = io_input_rsp_ready; + assign logic_cmdWait = ((logic_rspPending && (((((((logic_hitsS0_0 != logic_rspHits_0) || (logic_hitsS0_1 != logic_rspHits_1)) || (logic_hitsS0_2 != logic_rspHits_2)) || (logic_hitsS0_3 != logic_rspHits_3)) || (logic_hitsS0_4 != logic_rspHits_4)) || (logic_hitsS0_5 != logic_rspHits_5)) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); + always @(posedge clk) begin + if(reset) begin + logic_rspPendingCounter <= 7'h0; + logic_rspNoHit_doIt <= 1'b0; + end else begin + logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); + if(when_BmbDecoder_l60) begin + logic_rspNoHit_doIt <= 1'b0; + end + if(when_BmbDecoder_l60_1) begin + logic_rspNoHit_doIt <= 1'b1; + end + end + end + + always @(posedge clk) begin + if(when_BmbDecoder_l56) begin + logic_rspHits_0 <= logic_hitsS0_0; + logic_rspHits_1 <= logic_hitsS0_1; + logic_rspHits_2 <= logic_hitsS0_2; + logic_rspHits_3 <= logic_hitsS0_3; + logic_rspHits_4 <= logic_hitsS0_4; + logic_rspHits_5 <= logic_hitsS0_5; + end + if(logic_input_fire) begin + logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); + end + if(logic_input_fire) begin + logic_rspNoHit_context <= logic_input_payload_fragment_context; + end + end + + +endmodule + +module Axi4PeripheralBmbUnburstify_be6ad777990c4e5089d0b11c63cc2698 ( + input wire io_input_cmd_valid, + output reg io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_source, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [23:0] io_input_cmd_payload_fragment_address, + input wire [9:0] io_input_cmd_payload_fragment_length, + input wire [31:0] io_input_cmd_payload_fragment_data, + input wire [3:0] io_input_cmd_payload_fragment_mask, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_source, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [31:0] io_input_rsp_payload_fragment_data, + output reg io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output reg [0:0] io_output_cmd_payload_fragment_opcode, + output reg [23:0] io_output_cmd_payload_fragment_address, + output reg [1:0] io_output_cmd_payload_fragment_length, + output wire [31:0] io_output_cmd_payload_fragment_data, + output wire [3:0] io_output_cmd_payload_fragment_mask, + output wire [2:0] io_output_cmd_payload_fragment_context, + input wire io_output_rsp_valid, + output reg io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [31:0] io_output_rsp_payload_fragment_data, + input wire [2:0] io_output_rsp_payload_fragment_context, + input wire clk, + input wire reset +); + + wire [7:0] _zz_buffer_last; + wire [0:0] _zz_buffer_last_1; + wire [11:0] _zz_buffer_addressIncr; + wire doResult; + reg buffer_valid; + reg [0:0] buffer_opcode; + reg [0:0] buffer_source; + reg [23:0] buffer_address; + reg [7:0] buffer_beat; + wire buffer_last; + wire [23:0] buffer_addressIncr; + wire buffer_isWrite; + wire io_output_cmd_fire; + wire [7:0] cmdTransferBeatCount; + wire requireBuffer; + reg cmdContext_drop; + reg cmdContext_last; + reg [0:0] cmdContext_source; + wire rspContext_drop; + wire rspContext_last; + wire [0:0] rspContext_source; + wire [2:0] _zz_rspContext_drop; + wire when_Stream_l445; + reg io_output_rsp_thrown_valid; + wire io_output_rsp_thrown_ready; + wire io_output_rsp_thrown_payload_last; + wire [0:0] io_output_rsp_thrown_payload_fragment_opcode; + wire [31:0] io_output_rsp_thrown_payload_fragment_data; + wire [2:0] io_output_rsp_thrown_payload_fragment_context; + + assign _zz_buffer_last_1 = 1'b1; + assign _zz_buffer_last = {7'd0, _zz_buffer_last_1}; + assign _zz_buffer_addressIncr = (buffer_address[11 : 0] + 12'h004); + assign buffer_last = (buffer_beat == _zz_buffer_last); + assign buffer_addressIncr = {buffer_address[23 : 12],(_zz_buffer_addressIncr & (~ 12'h003))}; + assign buffer_isWrite = (buffer_opcode == 1'b1); + assign io_output_cmd_fire = (io_output_cmd_valid && io_output_cmd_ready); + assign cmdTransferBeatCount = io_input_cmd_payload_fragment_length[9 : 2]; + assign requireBuffer = (cmdTransferBeatCount != 8'h0); + assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign io_output_cmd_payload_last = 1'b1; + assign io_output_cmd_payload_fragment_context = {cmdContext_source,{cmdContext_last,cmdContext_drop}}; + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_address = buffer_addressIncr; + end else begin + io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + if(requireBuffer) begin + io_output_cmd_payload_fragment_address[1 : 0] = 2'b00; + end + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_opcode = buffer_opcode; + end else begin + io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_length = 2'b11; + end else begin + if(requireBuffer) begin + io_output_cmd_payload_fragment_length = 2'b11; + end else begin + io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length[1:0]; + end + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_source = buffer_source; + end else begin + cmdContext_source = io_input_cmd_payload_fragment_source; + end + end + + always @(*) begin + io_input_cmd_ready = 1'b0; + if(buffer_valid) begin + io_input_cmd_ready = (buffer_isWrite && io_output_cmd_ready); + end else begin + io_input_cmd_ready = io_output_cmd_ready; + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_valid = (! (buffer_isWrite && (! io_input_cmd_valid))); + end else begin + io_output_cmd_valid = io_input_cmd_valid; + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_last = buffer_last; + end else begin + cmdContext_last = (! requireBuffer); + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_drop = buffer_isWrite; + end else begin + cmdContext_drop = (io_input_cmd_payload_fragment_opcode == 1'b1); + end + end + + assign _zz_rspContext_drop = io_output_rsp_payload_fragment_context; + assign rspContext_drop = _zz_rspContext_drop[0]; + assign rspContext_last = _zz_rspContext_drop[1]; + assign rspContext_source = _zz_rspContext_drop[2 : 2]; + assign when_Stream_l445 = (! (rspContext_last || (! rspContext_drop))); + always @(*) begin + io_output_rsp_thrown_valid = io_output_rsp_valid; + if(when_Stream_l445) begin + io_output_rsp_thrown_valid = 1'b0; + end + end + + always @(*) begin + io_output_rsp_ready = io_output_rsp_thrown_ready; + if(when_Stream_l445) begin + io_output_rsp_ready = 1'b1; + end + end + + assign io_output_rsp_thrown_payload_last = io_output_rsp_payload_last; + assign io_output_rsp_thrown_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_output_rsp_thrown_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_output_rsp_thrown_payload_fragment_context = io_output_rsp_payload_fragment_context; + assign io_input_rsp_valid = io_output_rsp_thrown_valid; + assign io_output_rsp_thrown_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = rspContext_last; + assign io_input_rsp_payload_fragment_source = rspContext_source; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + always @(posedge clk) begin + if(reset) begin + buffer_valid <= 1'b0; + end else begin + if(io_output_cmd_fire) begin + if(buffer_last) begin + buffer_valid <= 1'b0; + end + end + if(!buffer_valid) begin + buffer_valid <= (requireBuffer && io_output_cmd_fire); + end + end + end + + always @(posedge clk) begin + if(io_output_cmd_fire) begin + buffer_beat <= (buffer_beat - 8'h01); + buffer_address[11 : 0] <= buffer_addressIncr[11 : 0]; + end + if(!buffer_valid) begin + buffer_opcode <= io_input_cmd_payload_fragment_opcode; + buffer_source <= io_input_cmd_payload_fragment_source; + buffer_address <= io_input_cmd_payload_fragment_address; + buffer_beat <= cmdTransferBeatCount; + end + end + + +endmodule + +module Axi4PeripheralBmbDecoder_be6ad777990c4e5089d0b11c63cc2698 ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_source, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [23:0] io_input_cmd_payload_fragment_address, + input wire [9:0] io_input_cmd_payload_fragment_length, + input wire [31:0] io_input_cmd_payload_fragment_data, + input wire [3:0] io_input_cmd_payload_fragment_mask, + output reg io_input_rsp_valid, + input wire io_input_rsp_ready, + output reg io_input_rsp_payload_last, + output reg [0:0] io_input_rsp_payload_fragment_source, + output reg [0:0] io_input_rsp_payload_fragment_opcode, + output wire [31:0] io_input_rsp_payload_fragment_data, + output reg io_outputs_0_cmd_valid, + input wire io_outputs_0_cmd_ready, + output wire io_outputs_0_cmd_payload_last, + output wire [0:0] io_outputs_0_cmd_payload_fragment_source, + output wire [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_0_cmd_payload_fragment_address, + output wire [9:0] io_outputs_0_cmd_payload_fragment_length, + output wire [31:0] io_outputs_0_cmd_payload_fragment_data, + output wire [3:0] io_outputs_0_cmd_payload_fragment_mask, + input wire io_outputs_0_rsp_valid, + output wire io_outputs_0_rsp_ready, + input wire io_outputs_0_rsp_payload_last, + input wire [0:0] io_outputs_0_rsp_payload_fragment_source, + input wire [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_0_rsp_payload_fragment_data, + input wire clk, + input wire reset +); + + wire [6:0] _zz_logic_rspPendingCounter; + wire [6:0] _zz_logic_rspPendingCounter_1; + wire [0:0] _zz_logic_rspPendingCounter_2; + wire [6:0] _zz_logic_rspPendingCounter_3; + wire [0:0] _zz_logic_rspPendingCounter_4; + wire logic_input_valid; + reg logic_input_ready; + wire logic_input_payload_last; + wire [0:0] logic_input_payload_fragment_source; + wire [0:0] logic_input_payload_fragment_opcode; + wire [23:0] logic_input_payload_fragment_address; + wire [9:0] logic_input_payload_fragment_length; + wire [31:0] logic_input_payload_fragment_data; + wire [3:0] logic_input_payload_fragment_mask; + wire logic_hitsS0_0; + wire logic_noHitS0; + wire _zz_io_outputs_0_cmd_payload_last; + reg [6:0] logic_rspPendingCounter; + wire logic_input_fire; + wire io_input_rsp_fire; + wire logic_cmdWait; + wire when_BmbDecoder_l56; + reg logic_rspHits_0; + wire logic_rspPending; + wire logic_rspNoHitValid; + reg logic_rspNoHit_doIt; + wire when_BmbDecoder_l60; + wire when_BmbDecoder_l60_1; + reg logic_rspNoHit_singleBeatRsp; + reg [0:0] logic_rspNoHit_source; + reg [7:0] logic_rspNoHit_counter; + wire when_BmbDecoder_l81; + + assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); + assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); + assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; + assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; + assign logic_input_valid = io_input_cmd_valid; + assign io_input_cmd_ready = logic_input_ready; + assign logic_input_payload_last = io_input_cmd_payload_last; + assign logic_input_payload_fragment_source = io_input_cmd_payload_fragment_source; + assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign logic_noHitS0 = (! (|logic_hitsS0_0)); + assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 24'hffffff)) == 24'h0); + always @(*) begin + io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); + if(logic_cmdWait) begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; + assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; + assign io_outputs_0_cmd_payload_fragment_source = logic_input_payload_fragment_source; + assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + always @(*) begin + logic_input_ready = ((|(logic_hitsS0_0 && io_outputs_0_cmd_ready)) || logic_noHitS0); + if(logic_cmdWait) begin + logic_input_ready = 1'b0; + end + end + + assign logic_input_fire = (logic_input_valid && logic_input_ready); + assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); + assign logic_rspPending = (logic_rspPendingCounter != 7'h0); + assign logic_rspNoHitValid = (! (|logic_rspHits_0)); + assign when_BmbDecoder_l60 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign when_BmbDecoder_l60_1 = ((logic_input_fire && logic_noHitS0) && logic_input_payload_last); + always @(*) begin + io_input_rsp_valid = ((|io_outputs_0_rsp_valid) || (logic_rspPending && logic_rspNoHitValid)); + if(logic_rspNoHit_doIt) begin + io_input_rsp_valid = 1'b1; + end + end + + always @(*) begin + io_input_rsp_payload_last = io_outputs_0_rsp_payload_last; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_last = 1'b0; + if(when_BmbDecoder_l81) begin + io_input_rsp_payload_last = 1'b1; + end + if(logic_rspNoHit_singleBeatRsp) begin + io_input_rsp_payload_last = 1'b1; + end + end + end + + always @(*) begin + io_input_rsp_payload_fragment_source = io_outputs_0_rsp_payload_fragment_source; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_source = logic_rspNoHit_source; + end + end + + always @(*) begin + io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_opcode = 1'b1; + end + end + + assign io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + assign when_BmbDecoder_l81 = (logic_rspNoHit_counter == 8'h0); + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign logic_cmdWait = ((logic_rspPending && ((logic_hitsS0_0 != logic_rspHits_0) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); + always @(posedge clk) begin + if(reset) begin + logic_rspPendingCounter <= 7'h0; + logic_rspNoHit_doIt <= 1'b0; + end else begin + logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); + if(when_BmbDecoder_l60) begin + logic_rspNoHit_doIt <= 1'b0; + end + if(when_BmbDecoder_l60_1) begin + logic_rspNoHit_doIt <= 1'b1; + end + end + end + + always @(posedge clk) begin + if(when_BmbDecoder_l56) begin + logic_rspHits_0 <= logic_hitsS0_0; + end + if(logic_input_fire) begin + logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); + end + if(logic_input_fire) begin + logic_rspNoHit_source <= logic_input_payload_fragment_source; + end + if(logic_input_fire) begin + logic_rspNoHit_counter <= logic_input_payload_fragment_length[9 : 2]; + end + if(logic_rspNoHit_doIt) begin + if(io_input_rsp_fire) begin + logic_rspNoHit_counter <= (logic_rspNoHit_counter - 8'h01); + end + end + end + + +endmodule + +module Axi4PeripheralAxi4SharedToBmb_be6ad777990c4e5089d0b11c63cc2698 ( + input wire io_axi_arw_valid, + output wire io_axi_arw_ready, + input wire [23:0] io_axi_arw_payload_addr, + input wire [7:0] io_axi_arw_payload_len, + input wire [2:0] io_axi_arw_payload_size, + input wire [3:0] io_axi_arw_payload_cache, + input wire [2:0] io_axi_arw_payload_prot, + input wire io_axi_arw_payload_write, + input wire io_axi_w_valid, + output wire io_axi_w_ready, + input wire [31:0] io_axi_w_payload_data, + input wire [3:0] io_axi_w_payload_strb, + input wire io_axi_w_payload_last, + output wire io_axi_b_valid, + input wire io_axi_b_ready, + output reg [1:0] io_axi_b_payload_resp, + output wire io_axi_r_valid, + input wire io_axi_r_ready, + output wire [31:0] io_axi_r_payload_data, + output reg [1:0] io_axi_r_payload_resp, + output wire io_axi_r_payload_last, + output wire io_bmb_cmd_valid, + input wire io_bmb_cmd_ready, + output wire io_bmb_cmd_payload_last, + output wire [0:0] io_bmb_cmd_payload_fragment_source, + output wire [0:0] io_bmb_cmd_payload_fragment_opcode, + output wire [23:0] io_bmb_cmd_payload_fragment_address, + output wire [9:0] io_bmb_cmd_payload_fragment_length, + output wire [31:0] io_bmb_cmd_payload_fragment_data, + output wire [3:0] io_bmb_cmd_payload_fragment_mask, + input wire io_bmb_rsp_valid, + output wire io_bmb_rsp_ready, + input wire io_bmb_rsp_payload_last, + input wire [0:0] io_bmb_rsp_payload_fragment_source, + input wire [0:0] io_bmb_rsp_payload_fragment_opcode, + input wire [31:0] io_bmb_rsp_payload_fragment_data +); + + wire [9:0] _zz_io_bmb_cmd_payload_fragment_length; + wire hazard; + wire io_bmb_cmd_fire; + wire rspIsWrite; + wire when_Axi4SharedToBmb_l42; + wire when_Axi4SharedToBmb_l49; + + assign _zz_io_bmb_cmd_payload_fragment_length = ({2'd0,io_axi_arw_payload_len} <<< 2'd2); + assign hazard = (io_axi_arw_payload_write && (! io_axi_w_valid)); + assign io_bmb_cmd_valid = (io_axi_arw_valid && (! hazard)); + assign io_bmb_cmd_payload_fragment_source = io_axi_arw_payload_write; + assign io_bmb_cmd_payload_fragment_opcode = io_axi_arw_payload_write; + assign io_bmb_cmd_payload_fragment_address = io_axi_arw_payload_addr; + assign io_bmb_cmd_payload_fragment_length = (_zz_io_bmb_cmd_payload_fragment_length | 10'h003); + assign io_bmb_cmd_payload_fragment_data = io_axi_w_payload_data; + assign io_bmb_cmd_payload_fragment_mask = io_axi_w_payload_strb; + assign io_bmb_cmd_payload_last = ((! io_axi_arw_payload_write) || io_axi_w_payload_last); + assign io_bmb_cmd_fire = (io_bmb_cmd_valid && io_bmb_cmd_ready); + assign io_axi_arw_ready = (io_bmb_cmd_fire && io_bmb_cmd_payload_last); + assign io_axi_w_ready = (io_bmb_cmd_fire && (io_bmb_cmd_payload_fragment_opcode == 1'b1)); + assign rspIsWrite = io_bmb_rsp_payload_fragment_source[0]; + assign io_axi_b_valid = (io_bmb_rsp_valid && rspIsWrite); + always @(*) begin + io_axi_b_payload_resp = 2'b00; + if(when_Axi4SharedToBmb_l42) begin + io_axi_b_payload_resp = 2'b11; + end + end + + assign when_Axi4SharedToBmb_l42 = (io_bmb_rsp_payload_fragment_opcode == 1'b1); + assign io_axi_r_valid = (io_bmb_rsp_valid && (! rspIsWrite)); + assign io_axi_r_payload_data = io_bmb_rsp_payload_fragment_data; + assign io_axi_r_payload_last = io_bmb_rsp_payload_last; + always @(*) begin + io_axi_r_payload_resp = 2'b00; + if(when_Axi4SharedToBmb_l49) begin + io_axi_r_payload_resp = 2'b11; + end + end + + assign when_Axi4SharedToBmb_l49 = (io_bmb_rsp_payload_fragment_opcode == 1'b1); + assign io_bmb_rsp_ready = (rspIsWrite ? io_axi_b_ready : io_axi_r_ready); + +endmodule + +module Axi4PeripheralStreamArbiter_be6ad777990c4e5089d0b11c63cc2698 ( + input wire io_inputs_0_valid, + output wire io_inputs_0_ready, + input wire [23:0] io_inputs_0_payload_addr, + input wire [7:0] io_inputs_0_payload_len, + input wire [2:0] io_inputs_0_payload_size, + input wire [3:0] io_inputs_0_payload_cache, + input wire [2:0] io_inputs_0_payload_prot, + input wire io_inputs_1_valid, + output wire io_inputs_1_ready, + input wire [23:0] io_inputs_1_payload_addr, + input wire [7:0] io_inputs_1_payload_len, + input wire [2:0] io_inputs_1_payload_size, + input wire [3:0] io_inputs_1_payload_cache, + input wire [2:0] io_inputs_1_payload_prot, + output wire io_output_valid, + input wire io_output_ready, + output wire [23:0] io_output_payload_addr, + output wire [7:0] io_output_payload_len, + output wire [2:0] io_output_payload_size, + output wire [3:0] io_output_payload_cache, + output wire [2:0] io_output_payload_prot, + output wire [0:0] io_chosen, + output wire [1:0] io_chosenOH, + input wire clk, + input wire reset +); + + wire [3:0] _zz__zz_maskProposal_0_2; + wire [3:0] _zz__zz_maskProposal_0_2_1; + wire [1:0] _zz__zz_maskProposal_0_2_2; + reg locked; + wire maskProposal_0; + wire maskProposal_1; + reg maskLocked_0; + reg maskLocked_1; + wire maskRouted_0; + wire maskRouted_1; + wire [1:0] _zz_maskProposal_0; + wire [3:0] _zz_maskProposal_0_1; + wire [3:0] _zz_maskProposal_0_2; + wire [1:0] _zz_maskProposal_0_3; + wire io_output_fire; + wire _zz_io_chosen; + + assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); + assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; + assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; + assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); + assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); + assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; + assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; + assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); + assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); + assign maskProposal_0 = _zz_maskProposal_0_3[0]; + assign maskProposal_1 = _zz_maskProposal_0_3[1]; + assign io_output_fire = (io_output_valid && io_output_ready); + assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); + assign io_output_payload_addr = (maskRouted_0 ? io_inputs_0_payload_addr : io_inputs_1_payload_addr); + assign io_output_payload_len = (maskRouted_0 ? io_inputs_0_payload_len : io_inputs_1_payload_len); + assign io_output_payload_size = (maskRouted_0 ? io_inputs_0_payload_size : io_inputs_1_payload_size); + assign io_output_payload_cache = (maskRouted_0 ? io_inputs_0_payload_cache : io_inputs_1_payload_cache); + assign io_output_payload_prot = (maskRouted_0 ? io_inputs_0_payload_prot : io_inputs_1_payload_prot); + assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); + assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); + assign io_chosenOH = {maskRouted_1,maskRouted_0}; + assign _zz_io_chosen = io_chosenOH[1]; + assign io_chosen = _zz_io_chosen; + always @(posedge clk) begin + if(reset) begin + locked <= 1'b0; + maskLocked_0 <= 1'b0; + maskLocked_1 <= 1'b1; + end else begin + if(io_output_valid) begin + maskLocked_0 <= maskRouted_0; + maskLocked_1 <= maskRouted_1; + end + if(io_output_valid) begin + locked <= 1'b1; + end + if(io_output_fire) begin + locked <= 1'b0; + end + end + end + + +endmodule + +//Axi4PeripheralTimer_1 replaced by Axi4PeripheralTimer_be6ad777990c4e5089d0b11c63cc2698 + +module Axi4PeripheralTimer_be6ad777990c4e5089d0b11c63cc2698 ( + input wire io_tick, + input wire io_clear, + input wire [15:0] io_limit, + output wire io_full, + output wire [15:0] io_value, + input wire clk, + input wire reset +); + + wire [15:0] _zz_counter; + wire [0:0] _zz_counter_1; + reg [15:0] counter; + wire limitHit; + reg inhibitFull; + + assign _zz_counter_1 = (! limitHit); + assign _zz_counter = {15'd0, _zz_counter_1}; + assign limitHit = (counter == io_limit); + assign io_full = ((limitHit && io_tick) && (! inhibitFull)); + assign io_value = counter; + always @(posedge clk) begin + if(reset) begin + inhibitFull <= 1'b0; + end else begin + if(io_tick) begin + inhibitFull <= limitHit; + end + if(io_clear) begin + inhibitFull <= 1'b0; + end + end + end + + always @(posedge clk) begin + if(io_tick) begin + counter <= (counter + _zz_counter); + end + if(io_clear) begin + counter <= 16'h0; + end + end + + +endmodule + +module Axi4PeripheralPrescaler_be6ad777990c4e5089d0b11c63cc2698 ( + input wire io_clear, + input wire [23:0] io_limit, + output wire io_overflow, + input wire clk, + input wire reset +); + + reg [23:0] counter; + wire when_Prescaler_l17; + + assign when_Prescaler_l17 = (io_clear || io_overflow); + assign io_overflow = (counter == io_limit); + always @(posedge clk) begin + counter <= (counter + 24'h000001); + if(when_Prescaler_l17) begin + counter <= 24'h0; + end + end + + +endmodule + +module Axi4PeripheralI2cSlave_be6ad777990c4e5089d0b11c63cc2698 ( + output wire io_i2c_sda_write, + input wire io_i2c_sda_read, + output wire io_i2c_scl_write, + input wire io_i2c_scl_read, + input wire [9:0] io_config_samplingClockDivider, + input wire [19:0] io_config_timeout, + input wire [5:0] io_config_tsuData, + input wire io_config_timeoutClear, + output reg [2:0] io_bus_cmd_kind, + output wire io_bus_cmd_data, + input wire io_bus_rsp_valid, + input wire io_bus_rsp_enable, + input wire io_bus_rsp_data, + output wire io_timeout, + output wire io_internals_inFrame, + output wire io_internals_sdaRead, + output wire io_internals_sclRead, + input wire clk, + input wire reset +); + localparam Axi4PeripheralI2cSlaveCmdMode_NONE = 3'd0; + localparam Axi4PeripheralI2cSlaveCmdMode_START = 3'd1; + localparam Axi4PeripheralI2cSlaveCmdMode_RESTART = 3'd2; + localparam Axi4PeripheralI2cSlaveCmdMode_STOP = 3'd3; + localparam Axi4PeripheralI2cSlaveCmdMode_DROP = 3'd4; + localparam Axi4PeripheralI2cSlaveCmdMode_DRIVE = 3'd5; + localparam Axi4PeripheralI2cSlaveCmdMode_READ = 3'd6; + + wire io_i2c_scl_read_buffercc_io_dataOut; + wire io_i2c_sda_read_buffercc_io_dataOut; + reg [9:0] filter_timer_counter; + wire filter_timer_tick; + wire filter_sampler_sclSync; + wire filter_sampler_sdaSync; + wire filter_sampler_sclSamples_0; + wire filter_sampler_sclSamples_1; + wire filter_sampler_sclSamples_2; + wire _zz_filter_sampler_sclSamples_0; + reg _zz_filter_sampler_sclSamples_1; + reg _zz_filter_sampler_sclSamples_2; + wire filter_sampler_sdaSamples_0; + wire filter_sampler_sdaSamples_1; + wire filter_sampler_sdaSamples_2; + wire _zz_filter_sampler_sdaSamples_0; + reg _zz_filter_sampler_sdaSamples_1; + reg _zz_filter_sampler_sdaSamples_2; + reg filter_sda; + reg filter_scl; + wire when_Misc_l82; + wire when_Misc_l85; + wire sclEdge_rise; + wire sclEdge_fall; + wire sclEdge_toggle; + reg filter_scl_regNext; + wire sdaEdge_rise; + wire sdaEdge_fall; + wire sdaEdge_toggle; + reg filter_sda_regNext; + wire detector_start; + wire detector_stop; + reg [5:0] tsuData_counter; + wire tsuData_done; + reg tsuData_reset; + wire when_I2CSlave_l191; + reg ctrl_inFrame; + reg ctrl_inFrameData; + reg ctrl_sdaWrite; + reg ctrl_sclWrite; + wire ctrl_rspBufferIn_valid; + reg ctrl_rspBufferIn_ready; + wire ctrl_rspBufferIn_payload_enable; + wire ctrl_rspBufferIn_payload_data; + wire ctrl_rspBuffer_valid; + reg ctrl_rspBuffer_ready; + wire ctrl_rspBuffer_payload_enable; + wire ctrl_rspBuffer_payload_data; + reg ctrl_rspBufferIn_rValid; + reg ctrl_rspBufferIn_rData_enable; + reg ctrl_rspBufferIn_rData_data; + wire when_Stream_l375; + wire ctrl_rspAhead_valid; + wire ctrl_rspAhead_payload_enable; + wire ctrl_rspAhead_payload_data; + wire when_I2CSlave_l241; + wire when_I2CSlave_l245; + wire when_I2CSlave_l251; + wire [2:0] _zz_io_bus_cmd_kind; + reg timeout_enabled; + reg [19:0] timeout_counter; + wire timeout_tick; + wire when_I2CSlave_l270; + wire when_I2CSlave_l276; + wire [2:0] _zz_io_bus_cmd_kind_1; + `ifndef SYNTHESIS + reg [55:0] io_bus_cmd_kind_string; + reg [55:0] _zz_io_bus_cmd_kind_string; + reg [55:0] _zz_io_bus_cmd_kind_1_string; + `endif + + + (* keep_hierarchy = "TRUE" *) Axi4PeripheralBufferCC_1_be6ad777990c4e5089d0b11c63cc2698 io_i2c_scl_read_buffercc ( + .io_dataIn (io_i2c_scl_read ), //i + .io_dataOut (io_i2c_scl_read_buffercc_io_dataOut), //o + .clk (clk ), //i + .reset (reset ) //i + ); + (* keep_hierarchy = "TRUE" *) Axi4PeripheralBufferCC_1_be6ad777990c4e5089d0b11c63cc2698 io_i2c_sda_read_buffercc ( + .io_dataIn (io_i2c_sda_read ), //i + .io_dataOut (io_i2c_sda_read_buffercc_io_dataOut), //o + .clk (clk ), //i + .reset (reset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_bus_cmd_kind) + Axi4PeripheralI2cSlaveCmdMode_NONE : io_bus_cmd_kind_string = "NONE "; + Axi4PeripheralI2cSlaveCmdMode_START : io_bus_cmd_kind_string = "START "; + Axi4PeripheralI2cSlaveCmdMode_RESTART : io_bus_cmd_kind_string = "RESTART"; + Axi4PeripheralI2cSlaveCmdMode_STOP : io_bus_cmd_kind_string = "STOP "; + Axi4PeripheralI2cSlaveCmdMode_DROP : io_bus_cmd_kind_string = "DROP "; + Axi4PeripheralI2cSlaveCmdMode_DRIVE : io_bus_cmd_kind_string = "DRIVE "; + Axi4PeripheralI2cSlaveCmdMode_READ : io_bus_cmd_kind_string = "READ "; + default : io_bus_cmd_kind_string = "???????"; + endcase + end + always @(*) begin + case(_zz_io_bus_cmd_kind) + Axi4PeripheralI2cSlaveCmdMode_NONE : _zz_io_bus_cmd_kind_string = "NONE "; + Axi4PeripheralI2cSlaveCmdMode_START : _zz_io_bus_cmd_kind_string = "START "; + Axi4PeripheralI2cSlaveCmdMode_RESTART : _zz_io_bus_cmd_kind_string = "RESTART"; + Axi4PeripheralI2cSlaveCmdMode_STOP : _zz_io_bus_cmd_kind_string = "STOP "; + Axi4PeripheralI2cSlaveCmdMode_DROP : _zz_io_bus_cmd_kind_string = "DROP "; + Axi4PeripheralI2cSlaveCmdMode_DRIVE : _zz_io_bus_cmd_kind_string = "DRIVE "; + Axi4PeripheralI2cSlaveCmdMode_READ : _zz_io_bus_cmd_kind_string = "READ "; + default : _zz_io_bus_cmd_kind_string = "???????"; + endcase + end + always @(*) begin + case(_zz_io_bus_cmd_kind_1) + Axi4PeripheralI2cSlaveCmdMode_NONE : _zz_io_bus_cmd_kind_1_string = "NONE "; + Axi4PeripheralI2cSlaveCmdMode_START : _zz_io_bus_cmd_kind_1_string = "START "; + Axi4PeripheralI2cSlaveCmdMode_RESTART : _zz_io_bus_cmd_kind_1_string = "RESTART"; + Axi4PeripheralI2cSlaveCmdMode_STOP : _zz_io_bus_cmd_kind_1_string = "STOP "; + Axi4PeripheralI2cSlaveCmdMode_DROP : _zz_io_bus_cmd_kind_1_string = "DROP "; + Axi4PeripheralI2cSlaveCmdMode_DRIVE : _zz_io_bus_cmd_kind_1_string = "DRIVE "; + Axi4PeripheralI2cSlaveCmdMode_READ : _zz_io_bus_cmd_kind_1_string = "READ "; + default : _zz_io_bus_cmd_kind_1_string = "???????"; + endcase + end + `endif + + assign filter_timer_tick = (filter_timer_counter == 10'h0); + assign filter_sampler_sclSync = io_i2c_scl_read_buffercc_io_dataOut; + assign filter_sampler_sdaSync = io_i2c_sda_read_buffercc_io_dataOut; + assign _zz_filter_sampler_sclSamples_0 = filter_sampler_sclSync; + assign filter_sampler_sclSamples_0 = _zz_filter_sampler_sclSamples_0; + assign filter_sampler_sclSamples_1 = _zz_filter_sampler_sclSamples_1; + assign filter_sampler_sclSamples_2 = _zz_filter_sampler_sclSamples_2; + assign _zz_filter_sampler_sdaSamples_0 = filter_sampler_sdaSync; + assign filter_sampler_sdaSamples_0 = _zz_filter_sampler_sdaSamples_0; + assign filter_sampler_sdaSamples_1 = _zz_filter_sampler_sdaSamples_1; + assign filter_sampler_sdaSamples_2 = _zz_filter_sampler_sdaSamples_2; + assign when_Misc_l82 = (&{(filter_sampler_sdaSamples_2 != filter_sda),{(filter_sampler_sdaSamples_1 != filter_sda),(filter_sampler_sdaSamples_0 != filter_sda)}}); + assign when_Misc_l85 = (&{(filter_sampler_sclSamples_2 != filter_scl),{(filter_sampler_sclSamples_1 != filter_scl),(filter_sampler_sclSamples_0 != filter_scl)}}); + assign sclEdge_rise = ((! filter_scl_regNext) && filter_scl); + assign sclEdge_fall = (filter_scl_regNext && (! filter_scl)); + assign sclEdge_toggle = (filter_scl_regNext != filter_scl); + assign sdaEdge_rise = ((! filter_sda_regNext) && filter_sda); + assign sdaEdge_fall = (filter_sda_regNext && (! filter_sda)); + assign sdaEdge_toggle = (filter_sda_regNext != filter_sda); + assign detector_start = (filter_scl && sdaEdge_fall); + assign detector_stop = (filter_scl && sdaEdge_rise); + assign tsuData_done = (tsuData_counter == 6'h0); + always @(*) begin + tsuData_reset = 1'b0; + if(ctrl_inFrameData) begin + tsuData_reset = (! ctrl_rspAhead_valid); + end + end + + assign when_I2CSlave_l191 = (! tsuData_done); + always @(*) begin + ctrl_sdaWrite = 1'b1; + if(ctrl_inFrameData) begin + if(when_I2CSlave_l251) begin + ctrl_sdaWrite = ctrl_rspAhead_payload_data; + end + end + end + + always @(*) begin + ctrl_sclWrite = 1'b1; + if(ctrl_inFrameData) begin + if(when_I2CSlave_l245) begin + ctrl_sclWrite = 1'b0; + end + end + end + + always @(*) begin + ctrl_rspBufferIn_ready = ctrl_rspBuffer_ready; + if(when_Stream_l375) begin + ctrl_rspBufferIn_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! ctrl_rspBuffer_valid); + assign ctrl_rspBuffer_valid = ctrl_rspBufferIn_rValid; + assign ctrl_rspBuffer_payload_enable = ctrl_rspBufferIn_rData_enable; + assign ctrl_rspBuffer_payload_data = ctrl_rspBufferIn_rData_data; + assign ctrl_rspAhead_valid = (ctrl_rspBuffer_valid ? ctrl_rspBuffer_valid : ctrl_rspBufferIn_valid); + assign ctrl_rspAhead_payload_enable = (ctrl_rspBuffer_valid ? ctrl_rspBuffer_payload_enable : ctrl_rspBufferIn_payload_enable); + assign ctrl_rspAhead_payload_data = (ctrl_rspBuffer_valid ? ctrl_rspBuffer_payload_data : ctrl_rspBufferIn_payload_data); + assign ctrl_rspBufferIn_valid = io_bus_rsp_valid; + assign ctrl_rspBufferIn_payload_enable = io_bus_rsp_enable; + assign ctrl_rspBufferIn_payload_data = io_bus_rsp_data; + always @(*) begin + ctrl_rspBuffer_ready = 1'b0; + if(ctrl_inFrame) begin + if(sclEdge_fall) begin + ctrl_rspBuffer_ready = 1'b1; + end + end + end + + always @(*) begin + io_bus_cmd_kind = Axi4PeripheralI2cSlaveCmdMode_NONE; + if(ctrl_inFrame) begin + if(sclEdge_rise) begin + io_bus_cmd_kind = Axi4PeripheralI2cSlaveCmdMode_READ; + end + end + if(ctrl_inFrameData) begin + if(when_I2CSlave_l241) begin + io_bus_cmd_kind = Axi4PeripheralI2cSlaveCmdMode_DRIVE; + end + end + if(detector_start) begin + io_bus_cmd_kind = _zz_io_bus_cmd_kind; + end + if(when_I2CSlave_l276) begin + if(ctrl_inFrame) begin + io_bus_cmd_kind = _zz_io_bus_cmd_kind_1; + end + end + end + + assign io_bus_cmd_data = filter_sda; + assign when_I2CSlave_l241 = ((! ctrl_rspBuffer_valid) || ctrl_rspBuffer_ready); + assign when_I2CSlave_l245 = ((! ctrl_rspAhead_valid) || (ctrl_rspAhead_payload_enable && (! tsuData_done))); + assign when_I2CSlave_l251 = (ctrl_rspAhead_valid && ctrl_rspAhead_payload_enable); + assign _zz_io_bus_cmd_kind = (ctrl_inFrame ? Axi4PeripheralI2cSlaveCmdMode_RESTART : Axi4PeripheralI2cSlaveCmdMode_START); + assign timeout_tick = (timeout_enabled && (timeout_counter == 20'h0)); + assign when_I2CSlave_l270 = (((timeout_tick || sclEdge_toggle) || (((! ctrl_inFrame) && filter_scl) && filter_sda)) || io_config_timeoutClear); + assign io_timeout = timeout_tick; + assign when_I2CSlave_l276 = (detector_stop || timeout_tick); + assign _zz_io_bus_cmd_kind_1 = (timeout_tick ? Axi4PeripheralI2cSlaveCmdMode_DROP : Axi4PeripheralI2cSlaveCmdMode_STOP); + assign io_internals_inFrame = ctrl_inFrame; + assign io_internals_sdaRead = filter_sda; + assign io_internals_sclRead = filter_scl; + assign io_i2c_scl_write = ctrl_sclWrite; + assign io_i2c_sda_write = ctrl_sdaWrite; + always @(posedge clk) begin + if(reset) begin + filter_timer_counter <= 10'h0; + _zz_filter_sampler_sclSamples_1 <= 1'b1; + _zz_filter_sampler_sclSamples_2 <= 1'b1; + _zz_filter_sampler_sdaSamples_1 <= 1'b1; + _zz_filter_sampler_sdaSamples_2 <= 1'b1; + filter_sda <= 1'b1; + filter_scl <= 1'b1; + filter_scl_regNext <= 1'b1; + filter_sda_regNext <= 1'b1; + tsuData_counter <= 6'h0; + ctrl_inFrame <= 1'b0; + ctrl_inFrameData <= 1'b0; + ctrl_rspBufferIn_rValid <= 1'b0; + timeout_counter <= 20'h0; + end else begin + filter_timer_counter <= (filter_timer_counter - 10'h001); + if(filter_timer_tick) begin + filter_timer_counter <= io_config_samplingClockDivider; + end + if(filter_timer_tick) begin + _zz_filter_sampler_sclSamples_1 <= _zz_filter_sampler_sclSamples_0; + end + if(filter_timer_tick) begin + _zz_filter_sampler_sclSamples_2 <= _zz_filter_sampler_sclSamples_1; + end + if(filter_timer_tick) begin + _zz_filter_sampler_sdaSamples_1 <= _zz_filter_sampler_sdaSamples_0; + end + if(filter_timer_tick) begin + _zz_filter_sampler_sdaSamples_2 <= _zz_filter_sampler_sdaSamples_1; + end + if(filter_timer_tick) begin + if(when_Misc_l82) begin + filter_sda <= filter_sampler_sdaSamples_2; + end + if(when_Misc_l85) begin + filter_scl <= filter_sampler_sclSamples_2; + end + end + filter_scl_regNext <= filter_scl; + filter_sda_regNext <= filter_sda; + if(when_I2CSlave_l191) begin + tsuData_counter <= (tsuData_counter - 6'h01); + end + if(tsuData_reset) begin + tsuData_counter <= io_config_tsuData; + end + if(ctrl_rspBufferIn_ready) begin + ctrl_rspBufferIn_rValid <= ctrl_rspBufferIn_valid; + end + if(ctrl_inFrame) begin + if(sclEdge_fall) begin + ctrl_inFrameData <= 1'b1; + end + end + if(detector_start) begin + ctrl_inFrame <= 1'b1; + ctrl_inFrameData <= 1'b0; + end + timeout_counter <= (timeout_counter - 20'h00001); + if(when_I2CSlave_l270) begin + timeout_counter <= io_config_timeout; + end + if(when_I2CSlave_l276) begin + ctrl_inFrame <= 1'b0; + ctrl_inFrameData <= 1'b0; + end + end + end + + always @(posedge clk) begin + if(ctrl_rspBufferIn_ready) begin + ctrl_rspBufferIn_rData_enable <= ctrl_rspBufferIn_payload_enable; + ctrl_rspBufferIn_rData_data <= ctrl_rspBufferIn_payload_data; + end + timeout_enabled <= (io_config_timeout != 20'h0); + end + + +endmodule + +module Axi4PeripheralStreamFifo_3_be6ad777990c4e5089d0b11c63cc2698 ( + input wire io_push_valid, + output wire io_push_ready, + input wire [7:0] io_push_payload_data, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [7:0] io_pop_payload_data, + input wire io_flush, + output wire [8:0] io_occupancy, + output wire [8:0] io_availability, + input wire clk, + input wire reset +); + + reg [7:0] logic_ram_spinal_port1; + reg _zz_1; + wire logic_ptr_doPush; + wire logic_ptr_doPop; + wire logic_ptr_full; + wire logic_ptr_empty; + reg [8:0] logic_ptr_push; + reg [8:0] logic_ptr_pop; + wire [8:0] logic_ptr_occupancy; + wire [8:0] logic_ptr_popOnIo; + wire when_Stream_l1248; + reg logic_ptr_wentUp; + wire io_push_fire; + wire logic_push_onRam_write_valid; + wire [7:0] logic_push_onRam_write_payload_address; + wire [7:0] logic_push_onRam_write_payload_data_data; + wire logic_pop_addressGen_valid; + reg logic_pop_addressGen_ready; + wire [7:0] logic_pop_addressGen_payload; + wire logic_pop_addressGen_fire; + wire logic_pop_sync_readArbitation_valid; + wire logic_pop_sync_readArbitation_ready; + wire [7:0] logic_pop_sync_readArbitation_payload; + reg logic_pop_addressGen_rValid; + reg [7:0] logic_pop_addressGen_rData; + wire when_Stream_l375; + wire logic_pop_sync_readPort_cmd_valid; + wire [7:0] logic_pop_sync_readPort_cmd_payload; + wire [7:0] logic_pop_sync_readPort_rsp_data; + wire logic_pop_sync_readArbitation_translated_valid; + wire logic_pop_sync_readArbitation_translated_ready; + wire [7:0] logic_pop_sync_readArbitation_translated_payload_data; + wire logic_pop_sync_readArbitation_fire; + reg [8:0] logic_pop_sync_popReg; + reg [7:0] logic_ram [0:255]; + + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data_data; + end + end + + always @(posedge clk) begin + if(logic_pop_sync_readPort_cmd_valid) begin + logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_push_onRam_write_valid) begin + _zz_1 = 1'b1; + end + end + + assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); + assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 9'h100) == 9'h0); + assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop); + assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo); + assign io_push_ready = (! logic_ptr_full); + assign io_push_fire = (io_push_valid && io_push_ready); + assign logic_ptr_doPush = io_push_fire; + assign logic_push_onRam_write_valid = io_push_fire; + assign logic_push_onRam_write_payload_address = logic_ptr_push[7:0]; + assign logic_push_onRam_write_payload_data_data = io_push_payload_data; + assign logic_pop_addressGen_valid = (! logic_ptr_empty); + assign logic_pop_addressGen_payload = logic_ptr_pop[7:0]; + assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); + assign logic_ptr_doPop = logic_pop_addressGen_fire; + always @(*) begin + logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; + if(when_Stream_l375) begin + logic_pop_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); + assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; + assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; + assign logic_pop_sync_readPort_rsp_data = logic_ram_spinal_port1[7 : 0]; + assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; + assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; + assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; + assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; + assign logic_pop_sync_readArbitation_translated_payload_data = logic_pop_sync_readPort_rsp_data; + assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; + assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_data = logic_pop_sync_readArbitation_translated_payload_data; + assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); + assign logic_ptr_popOnIo = logic_pop_sync_popReg; + assign io_occupancy = logic_ptr_occupancy; + assign io_availability = (9'h100 - logic_ptr_occupancy); + always @(posedge clk) begin + if(reset) begin + logic_ptr_push <= 9'h0; + logic_ptr_pop <= 9'h0; + logic_ptr_wentUp <= 1'b0; + logic_pop_addressGen_rValid <= 1'b0; + logic_pop_sync_popReg <= 9'h0; + end else begin + if(when_Stream_l1248) begin + logic_ptr_wentUp <= logic_ptr_doPush; + end + if(io_flush) begin + logic_ptr_wentUp <= 1'b0; + end + if(logic_ptr_doPush) begin + logic_ptr_push <= (logic_ptr_push + 9'h001); + end + if(logic_ptr_doPop) begin + logic_ptr_pop <= (logic_ptr_pop + 9'h001); + end + if(io_flush) begin + logic_ptr_push <= 9'h0; + logic_ptr_pop <= 9'h0; + end + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; + end + if(io_flush) begin + logic_pop_addressGen_rValid <= 1'b0; + end + if(logic_pop_sync_readArbitation_fire) begin + logic_pop_sync_popReg <= logic_ptr_pop; + end + if(io_flush) begin + logic_pop_sync_popReg <= 9'h0; + end + end + end + + always @(posedge clk) begin + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rData <= logic_pop_addressGen_payload; + end + end + + +endmodule + +module Axi4PeripheralStreamFifo_2_be6ad777990c4e5089d0b11c63cc2698 ( + input wire io_push_valid, + output wire io_push_ready, + input wire io_push_payload_kind, + input wire io_push_payload_read, + input wire io_push_payload_write, + input wire [7:0] io_push_payload_data, + output wire io_pop_valid, + input wire io_pop_ready, + output wire io_pop_payload_kind, + output wire io_pop_payload_read, + output wire io_pop_payload_write, + output wire [7:0] io_pop_payload_data, + input wire io_flush, + output wire [8:0] io_occupancy, + output wire [8:0] io_availability, + input wire clk, + input wire reset +); + + reg [10:0] logic_ram_spinal_port1; + wire [10:0] _zz_logic_ram_port; + reg _zz_1; + wire logic_ptr_doPush; + wire logic_ptr_doPop; + wire logic_ptr_full; + wire logic_ptr_empty; + reg [8:0] logic_ptr_push; + reg [8:0] logic_ptr_pop; + wire [8:0] logic_ptr_occupancy; + wire [8:0] logic_ptr_popOnIo; + wire when_Stream_l1248; + reg logic_ptr_wentUp; + wire io_push_fire; + wire logic_push_onRam_write_valid; + wire [7:0] logic_push_onRam_write_payload_address; + wire logic_push_onRam_write_payload_data_kind; + wire logic_push_onRam_write_payload_data_read; + wire logic_push_onRam_write_payload_data_write; + wire [7:0] logic_push_onRam_write_payload_data_data; + wire logic_pop_addressGen_valid; + reg logic_pop_addressGen_ready; + wire [7:0] logic_pop_addressGen_payload; + wire logic_pop_addressGen_fire; + wire logic_pop_sync_readArbitation_valid; + wire logic_pop_sync_readArbitation_ready; + wire [7:0] logic_pop_sync_readArbitation_payload; + reg logic_pop_addressGen_rValid; + reg [7:0] logic_pop_addressGen_rData; + wire when_Stream_l375; + wire logic_pop_sync_readPort_cmd_valid; + wire [7:0] logic_pop_sync_readPort_cmd_payload; + wire logic_pop_sync_readPort_rsp_kind; + wire logic_pop_sync_readPort_rsp_read; + wire logic_pop_sync_readPort_rsp_write; + wire [7:0] logic_pop_sync_readPort_rsp_data; + wire [10:0] _zz_logic_pop_sync_readPort_rsp_kind; + wire logic_pop_sync_readArbitation_translated_valid; + wire logic_pop_sync_readArbitation_translated_ready; + wire logic_pop_sync_readArbitation_translated_payload_kind; + wire logic_pop_sync_readArbitation_translated_payload_read; + wire logic_pop_sync_readArbitation_translated_payload_write; + wire [7:0] logic_pop_sync_readArbitation_translated_payload_data; + wire logic_pop_sync_readArbitation_fire; + reg [8:0] logic_pop_sync_popReg; + reg [10:0] logic_ram [0:255]; + + assign _zz_logic_ram_port = {logic_push_onRam_write_payload_data_data,{logic_push_onRam_write_payload_data_write,{logic_push_onRam_write_payload_data_read,logic_push_onRam_write_payload_data_kind}}}; + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_push_onRam_write_payload_address] <= _zz_logic_ram_port; + end + end + + always @(posedge clk) begin + if(logic_pop_sync_readPort_cmd_valid) begin + logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_push_onRam_write_valid) begin + _zz_1 = 1'b1; + end + end + + assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); + assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 9'h100) == 9'h0); + assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop); + assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo); + assign io_push_ready = (! logic_ptr_full); + assign io_push_fire = (io_push_valid && io_push_ready); + assign logic_ptr_doPush = io_push_fire; + assign logic_push_onRam_write_valid = io_push_fire; + assign logic_push_onRam_write_payload_address = logic_ptr_push[7:0]; + assign logic_push_onRam_write_payload_data_kind = io_push_payload_kind; + assign logic_push_onRam_write_payload_data_read = io_push_payload_read; + assign logic_push_onRam_write_payload_data_write = io_push_payload_write; + assign logic_push_onRam_write_payload_data_data = io_push_payload_data; + assign logic_pop_addressGen_valid = (! logic_ptr_empty); + assign logic_pop_addressGen_payload = logic_ptr_pop[7:0]; + assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); + assign logic_ptr_doPop = logic_pop_addressGen_fire; + always @(*) begin + logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; + if(when_Stream_l375) begin + logic_pop_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); + assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; + assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; + assign _zz_logic_pop_sync_readPort_rsp_kind = logic_ram_spinal_port1; + assign logic_pop_sync_readPort_rsp_kind = _zz_logic_pop_sync_readPort_rsp_kind[0]; + assign logic_pop_sync_readPort_rsp_read = _zz_logic_pop_sync_readPort_rsp_kind[1]; + assign logic_pop_sync_readPort_rsp_write = _zz_logic_pop_sync_readPort_rsp_kind[2]; + assign logic_pop_sync_readPort_rsp_data = _zz_logic_pop_sync_readPort_rsp_kind[10 : 3]; + assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; + assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; + assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; + assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; + assign logic_pop_sync_readArbitation_translated_payload_kind = logic_pop_sync_readPort_rsp_kind; + assign logic_pop_sync_readArbitation_translated_payload_read = logic_pop_sync_readPort_rsp_read; + assign logic_pop_sync_readArbitation_translated_payload_write = logic_pop_sync_readPort_rsp_write; + assign logic_pop_sync_readArbitation_translated_payload_data = logic_pop_sync_readPort_rsp_data; + assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; + assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_kind = logic_pop_sync_readArbitation_translated_payload_kind; + assign io_pop_payload_read = logic_pop_sync_readArbitation_translated_payload_read; + assign io_pop_payload_write = logic_pop_sync_readArbitation_translated_payload_write; + assign io_pop_payload_data = logic_pop_sync_readArbitation_translated_payload_data; + assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); + assign logic_ptr_popOnIo = logic_pop_sync_popReg; + assign io_occupancy = logic_ptr_occupancy; + assign io_availability = (9'h100 - logic_ptr_occupancy); + always @(posedge clk) begin + if(reset) begin + logic_ptr_push <= 9'h0; + logic_ptr_pop <= 9'h0; + logic_ptr_wentUp <= 1'b0; + logic_pop_addressGen_rValid <= 1'b0; + logic_pop_sync_popReg <= 9'h0; + end else begin + if(when_Stream_l1248) begin + logic_ptr_wentUp <= logic_ptr_doPush; + end + if(io_flush) begin + logic_ptr_wentUp <= 1'b0; + end + if(logic_ptr_doPush) begin + logic_ptr_push <= (logic_ptr_push + 9'h001); + end + if(logic_ptr_doPop) begin + logic_ptr_pop <= (logic_ptr_pop + 9'h001); + end + if(io_flush) begin + logic_ptr_push <= 9'h0; + logic_ptr_pop <= 9'h0; + end + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; + end + if(io_flush) begin + logic_pop_addressGen_rValid <= 1'b0; + end + if(logic_pop_sync_readArbitation_fire) begin + logic_pop_sync_popReg <= logic_ptr_pop; + end + if(io_flush) begin + logic_pop_sync_popReg <= 9'h0; + end + end + end + + always @(posedge clk) begin + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rData <= logic_pop_addressGen_payload; + end + end + + +endmodule + +module Axi4PeripheralTopLevel_be6ad777990c4e5089d0b11c63cc2698 ( + input wire io_config_kind_cpol, + input wire io_config_kind_cpha, + input wire [11:0] io_config_sclkToggle, + input wire [1:0] io_config_mod, + input wire [3:0] io_config_ss_activeHigh, + input wire [11:0] io_config_ss_setup, + input wire [11:0] io_config_ss_hold, + input wire [11:0] io_config_ss_disable, + input wire io_cmd_valid, + output reg io_cmd_ready, + input wire io_cmd_payload_kind, + input wire io_cmd_payload_read, + input wire io_cmd_payload_write, + input wire [7:0] io_cmd_payload_data, + output wire io_rsp_valid, + output wire [7:0] io_rsp_payload_data, + output wire [0:0] io_spi_sclk_write, + output reg io_spi_data_0_writeEnable, + input wire [0:0] io_spi_data_0_read, + output reg [0:0] io_spi_data_0_write, + output reg io_spi_data_1_writeEnable, + input wire [0:0] io_spi_data_1_read, + output reg [0:0] io_spi_data_1_write, + output reg io_spi_data_2_writeEnable, + input wire [0:0] io_spi_data_2_read, + output reg [0:0] io_spi_data_2_write, + output reg io_spi_data_3_writeEnable, + input wire [0:0] io_spi_data_3_read, + output reg [0:0] io_spi_data_3_write, + output wire [3:0] io_spi_ss, + input wire clk, + input wire reset +); + + reg [0:0] _zz_outputPhy_dataWrite_3; + wire [2:0] _zz_outputPhy_dataWrite_4; + reg [1:0] _zz_outputPhy_dataWrite_5; + wire [1:0] _zz_outputPhy_dataWrite_6; + wire [2:0] _zz_outputPhy_dataWrite_7; + reg [3:0] _zz_outputPhy_dataWrite_8; + wire [0:0] _zz_outputPhy_dataWrite_9; + wire [2:0] _zz_outputPhy_dataWrite_10; + wire [3:0] _zz_inputPhy_dataRead; + wire [3:0] _zz_inputPhy_dataRead_1; + wire [3:0] _zz_inputPhy_dataRead_2; + wire [3:0] _zz_inputPhy_dataRead_3; + wire [3:0] _zz_inputPhy_dataRead_4; + wire [3:0] _zz_inputPhy_dataRead_5; + wire [3:0] _zz_inputPhy_dataRead_6; + wire [8:0] _zz_inputPhy_bufferNext; + wire [10:0] _zz_inputPhy_bufferNext_1; + reg [11:0] timer_counter; + reg timer_reset; + wire timer_ss_setupHit; + wire timer_ss_holdHit; + wire timer_ss_disableHit; + wire timer_sclkToggleHit; + reg fsm_state; + reg [2:0] fsm_counter; + reg [2:0] _zz_fsm_counterPlus; + wire [2:0] fsm_counterPlus; + reg fsm_fastRate; + reg fsm_isDdr; + reg [2:0] fsm_counterMax; + reg fsm_lateSampling; + reg fsm_readFill; + reg fsm_readDone; + reg [3:0] fsm_ss; + wire when_SpiXdrMasterCtrl_l741; + wire when_SpiXdrMasterCtrl_l744; + wire when_SpiXdrMasterCtrl_l751; + wire when_SpiXdrMasterCtrl_l753; + wire when_SpiXdrMasterCtrl_l760; + wire when_SpiXdrMasterCtrl_l766; + wire when_SpiXdrMasterCtrl_l783; + reg [0:0] outputPhy_sclkWrite; + wire [0:0] _zz_io_spi_sclk_write; + wire when_SpiXdrMasterCtrl_l798; + reg [3:0] outputPhy_dataWrite; + reg [2:0] outputPhy_widthSel; + reg [2:0] outputPhy_offset; + wire [7:0] _zz_outputPhy_dataWrite; + wire [7:0] _zz_outputPhy_dataWrite_1; + wire [7:0] _zz_outputPhy_dataWrite_2; + wire when_SpiXdrMasterCtrl_l841; + wire when_SpiXdrMasterCtrl_l841_1; + reg [1:0] io_config_mod_delay_1; + reg [1:0] inputPhy_mod; + reg fsm_readFill_delay_1; + reg inputPhy_readFill; + reg fsm_readDone_delay_1; + reg inputPhy_readDone; + reg [6:0] inputPhy_buffer; + reg [7:0] inputPhy_bufferNext; + reg [2:0] inputPhy_widthSel; + wire [3:0] inputPhy_dataWrite; + reg [3:0] inputPhy_dataRead; + reg fsm_state_delay_1; + reg fsm_state_delay_2; + wire when_SpiXdrMasterCtrl_l863; + reg [3:0] inputPhy_dataReadBuffer; + + assign _zz_outputPhy_dataWrite_4 = (outputPhy_offset - fsm_counter); + assign _zz_outputPhy_dataWrite_6 = (_zz_outputPhy_dataWrite_7 >>> 1'd1); + assign _zz_outputPhy_dataWrite_7 = (outputPhy_offset - fsm_counter); + assign _zz_outputPhy_dataWrite_9 = (_zz_outputPhy_dataWrite_10 >>> 2'd2); + assign _zz_outputPhy_dataWrite_10 = (outputPhy_offset - fsm_counter); + assign _zz_inputPhy_dataRead = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_1 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_2 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_3 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_4 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_5 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_6 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[1 : 0]}; + assign _zz_inputPhy_bufferNext_1 = {inputPhy_buffer,inputPhy_dataRead[3 : 0]}; + always @(*) begin + case(_zz_outputPhy_dataWrite_4) + 3'b000 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[0 : 0]; + 3'b001 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[1 : 1]; + 3'b010 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[2 : 2]; + 3'b011 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[3 : 3]; + 3'b100 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[4 : 4]; + 3'b101 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[5 : 5]; + 3'b110 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[6 : 6]; + default : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[7 : 7]; + endcase + end + + always @(*) begin + case(_zz_outputPhy_dataWrite_6) + 2'b00 : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[1 : 0]; + 2'b01 : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[3 : 2]; + 2'b10 : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[5 : 4]; + default : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[7 : 6]; + endcase + end + + always @(*) begin + case(_zz_outputPhy_dataWrite_9) + 1'b0 : _zz_outputPhy_dataWrite_8 = _zz_outputPhy_dataWrite_2[3 : 0]; + default : _zz_outputPhy_dataWrite_8 = _zz_outputPhy_dataWrite_2[7 : 4]; + endcase + end + + always @(*) begin + timer_reset = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l741) begin + timer_reset = timer_sclkToggleHit; + end else begin + if(!when_SpiXdrMasterCtrl_l760) begin + if(when_SpiXdrMasterCtrl_l766) begin + if(timer_ss_holdHit) begin + timer_reset = 1'b1; + end + end + end + end + end + if(when_SpiXdrMasterCtrl_l783) begin + timer_reset = 1'b1; + end + end + + assign timer_ss_setupHit = (timer_counter == io_config_ss_setup); + assign timer_ss_holdHit = (timer_counter == io_config_ss_hold); + assign timer_ss_disableHit = (timer_counter == io_config_ss_disable); + assign timer_sclkToggleHit = (timer_counter == io_config_sclkToggle); + always @(*) begin + _zz_fsm_counterPlus = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + _zz_fsm_counterPlus = 3'b001; + end + 2'b01 : begin + _zz_fsm_counterPlus = 3'b010; + end + 2'b10 : begin + _zz_fsm_counterPlus = 3'b100; + end + default : begin + end + endcase + end + + assign fsm_counterPlus = (fsm_counter + _zz_fsm_counterPlus); + always @(*) begin + fsm_fastRate = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_fastRate = 1'b0; + end + 2'b01 : begin + fsm_fastRate = 1'b0; + end + 2'b10 : begin + fsm_fastRate = 1'b0; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_isDdr = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_isDdr = 1'b0; + end + 2'b01 : begin + fsm_isDdr = 1'b0; + end + 2'b10 : begin + fsm_isDdr = 1'b0; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_counterMax = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + fsm_counterMax = 3'b111; + end + 2'b01 : begin + fsm_counterMax = 3'b110; + end + 2'b10 : begin + fsm_counterMax = 3'b100; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_lateSampling = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_lateSampling = 1'b1; + end + 2'b01 : begin + fsm_lateSampling = 1'b1; + end + 2'b10 : begin + fsm_lateSampling = 1'b1; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_readFill = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l741) begin + if(when_SpiXdrMasterCtrl_l744) begin + fsm_readFill = 1'b1; + end + end + end + end + + always @(*) begin + fsm_readDone = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l741) begin + if(when_SpiXdrMasterCtrl_l744) begin + fsm_readDone = (io_cmd_payload_read && (fsm_counter == fsm_counterMax)); + end + end + end + end + + assign io_spi_ss = (~ (fsm_ss ^ io_config_ss_activeHigh)); + always @(*) begin + io_cmd_ready = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l741) begin + if(when_SpiXdrMasterCtrl_l751) begin + if(when_SpiXdrMasterCtrl_l753) begin + io_cmd_ready = 1'b1; + end + end + end else begin + if(when_SpiXdrMasterCtrl_l760) begin + if(timer_ss_setupHit) begin + io_cmd_ready = 1'b1; + end + end else begin + if(!when_SpiXdrMasterCtrl_l766) begin + if(timer_ss_disableHit) begin + io_cmd_ready = 1'b1; + end + end + end + end + end + end + + assign when_SpiXdrMasterCtrl_l741 = (! io_cmd_payload_kind); + assign when_SpiXdrMasterCtrl_l744 = ((timer_sclkToggleHit && (((! fsm_state) ^ fsm_lateSampling) || fsm_isDdr)) || fsm_fastRate); + assign when_SpiXdrMasterCtrl_l751 = ((timer_sclkToggleHit && (fsm_state || fsm_isDdr)) || fsm_fastRate); + assign when_SpiXdrMasterCtrl_l753 = (fsm_counter == fsm_counterMax); + assign when_SpiXdrMasterCtrl_l760 = io_cmd_payload_data[7]; + assign when_SpiXdrMasterCtrl_l766 = (! fsm_state); + assign when_SpiXdrMasterCtrl_l783 = ((! io_cmd_valid) || io_cmd_ready); + always @(*) begin + outputPhy_sclkWrite = 1'b0; + if(when_SpiXdrMasterCtrl_l798) begin + case(io_config_mod) + 2'b00 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + 2'b01 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + 2'b10 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + default : begin + end + endcase + end + end + + assign _zz_io_spi_sclk_write[0] = io_config_kind_cpol; + assign io_spi_sclk_write = (outputPhy_sclkWrite ^ _zz_io_spi_sclk_write); + assign when_SpiXdrMasterCtrl_l798 = (io_cmd_valid && (! io_cmd_payload_kind)); + always @(*) begin + outputPhy_widthSel = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + outputPhy_widthSel = 3'b000; + end + 2'b01 : begin + outputPhy_widthSel = 3'b001; + end + 2'b10 : begin + outputPhy_widthSel = 3'b010; + end + default : begin + end + endcase + end + + always @(*) begin + outputPhy_offset = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + outputPhy_offset = 3'b111; + end + 2'b01 : begin + outputPhy_offset = 3'b111; + end + 2'b10 : begin + outputPhy_offset = 3'b111; + end + default : begin + end + endcase + end + + always @(*) begin + outputPhy_dataWrite = 4'bxxxx; + case(outputPhy_widthSel) + 3'b000 : begin + outputPhy_dataWrite[0 : 0] = _zz_outputPhy_dataWrite_3; + end + 3'b001 : begin + outputPhy_dataWrite[1 : 0] = _zz_outputPhy_dataWrite_5; + end + 3'b010 : begin + outputPhy_dataWrite[3 : 0] = _zz_outputPhy_dataWrite_8; + end + default : begin + end + endcase + end + + assign _zz_outputPhy_dataWrite = io_cmd_payload_data; + assign _zz_outputPhy_dataWrite_1 = io_cmd_payload_data; + assign _zz_outputPhy_dataWrite_2 = io_cmd_payload_data; + always @(*) begin + io_spi_data_0_writeEnable = 1'b0; + case(io_config_mod) + 2'b00 : begin + io_spi_data_0_writeEnable = 1'b1; + end + 2'b01 : begin + if(when_SpiXdrMasterCtrl_l841) begin + io_spi_data_0_writeEnable = 1'b1; + end + end + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l841_1) begin + io_spi_data_0_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_1_writeEnable = 1'b0; + case(io_config_mod) + 2'b01 : begin + if(when_SpiXdrMasterCtrl_l841) begin + io_spi_data_1_writeEnable = 1'b1; + end + end + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l841_1) begin + io_spi_data_1_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_2_writeEnable = 1'b0; + case(io_config_mod) + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l841_1) begin + io_spi_data_2_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_3_writeEnable = 1'b0; + case(io_config_mod) + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l841_1) begin + io_spi_data_3_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_0_write = 1'bx; + case(io_config_mod) + 2'b00 : begin + io_spi_data_0_write[0] = (outputPhy_dataWrite[0] || (! (io_cmd_valid && io_cmd_payload_write))); + end + 2'b01 : begin + io_spi_data_0_write[0] = outputPhy_dataWrite[0]; + end + 2'b10 : begin + io_spi_data_0_write[0] = outputPhy_dataWrite[0]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_1_write = 1'bx; + case(io_config_mod) + 2'b01 : begin + io_spi_data_1_write[0] = outputPhy_dataWrite[1]; + end + 2'b10 : begin + io_spi_data_1_write[0] = outputPhy_dataWrite[1]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_2_write = 1'bx; + case(io_config_mod) + 2'b10 : begin + io_spi_data_2_write[0] = outputPhy_dataWrite[2]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_3_write = 1'bx; + case(io_config_mod) + 2'b10 : begin + io_spi_data_3_write[0] = outputPhy_dataWrite[3]; + end + default : begin + end + endcase + end + + assign when_SpiXdrMasterCtrl_l841 = (io_cmd_valid && io_cmd_payload_write); + assign when_SpiXdrMasterCtrl_l841_1 = (io_cmd_valid && io_cmd_payload_write); + always @(*) begin + inputPhy_bufferNext = 8'bxxxxxxxx; + case(inputPhy_widthSel) + 3'b000 : begin + inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[0 : 0]}; + end + 3'b001 : begin + inputPhy_bufferNext = _zz_inputPhy_bufferNext[7:0]; + end + 3'b010 : begin + inputPhy_bufferNext = _zz_inputPhy_bufferNext_1[7:0]; + end + default : begin + end + endcase + end + + always @(*) begin + inputPhy_widthSel = 3'bxxx; + case(inputPhy_mod) + 2'b00 : begin + inputPhy_widthSel = 3'b000; + end + 2'b01 : begin + inputPhy_widthSel = 3'b001; + end + 2'b10 : begin + inputPhy_widthSel = 3'b010; + end + default : begin + end + endcase + end + + assign when_SpiXdrMasterCtrl_l863 = (! fsm_state_delay_2); + always @(*) begin + inputPhy_dataRead = 4'bxxxx; + case(inputPhy_mod) + 2'b00 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead[1]; + end + 2'b01 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead_1[0]; + inputPhy_dataRead[1] = _zz_inputPhy_dataRead_2[1]; + end + 2'b10 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead_3[0]; + inputPhy_dataRead[1] = _zz_inputPhy_dataRead_4[1]; + inputPhy_dataRead[2] = _zz_inputPhy_dataRead_5[2]; + inputPhy_dataRead[3] = _zz_inputPhy_dataRead_6[3]; + end + default : begin + end + endcase + end + + assign io_rsp_valid = inputPhy_readDone; + assign io_rsp_payload_data = inputPhy_bufferNext; + always @(posedge clk) begin + timer_counter <= (timer_counter + 12'h001); + if(timer_reset) begin + timer_counter <= 12'h0; + end + io_config_mod_delay_1 <= io_config_mod; + inputPhy_mod <= io_config_mod_delay_1; + fsm_state_delay_1 <= fsm_state; + fsm_state_delay_2 <= fsm_state_delay_1; + if(when_SpiXdrMasterCtrl_l863) begin + inputPhy_dataReadBuffer <= {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + end + case(inputPhy_widthSel) + 3'b000 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + 3'b001 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + 3'b010 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + default : begin + end + endcase + end + + always @(posedge clk) begin + if(reset) begin + fsm_state <= 1'b0; + fsm_counter <= 3'b000; + fsm_ss <= 4'b0000; + fsm_readFill_delay_1 <= 1'b0; + inputPhy_readFill <= 1'b0; + fsm_readDone_delay_1 <= 1'b0; + inputPhy_readDone <= 1'b0; + end else begin + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l741) begin + if(timer_sclkToggleHit) begin + fsm_state <= (! fsm_state); + end + if(when_SpiXdrMasterCtrl_l751) begin + fsm_counter <= fsm_counterPlus; + if(when_SpiXdrMasterCtrl_l753) begin + fsm_state <= 1'b0; + end + end + end else begin + if(when_SpiXdrMasterCtrl_l760) begin + fsm_ss[io_cmd_payload_data[1 : 0]] <= 1'b1; + end else begin + if(when_SpiXdrMasterCtrl_l766) begin + if(timer_ss_holdHit) begin + fsm_state <= 1'b1; + end + end else begin + fsm_ss[io_cmd_payload_data[1 : 0]] <= 1'b0; + end + end + end + end + if(when_SpiXdrMasterCtrl_l783) begin + fsm_state <= 1'b0; + fsm_counter <= 3'b000; + end + fsm_readFill_delay_1 <= fsm_readFill; + inputPhy_readFill <= fsm_readFill_delay_1; + fsm_readDone_delay_1 <= fsm_readDone; + inputPhy_readDone <= fsm_readDone_delay_1; + end + end + + +endmodule + +//Axi4PeripheralStreamFifo_1 replaced by Axi4PeripheralStreamFifo_be6ad777990c4e5089d0b11c63cc2698 + +module Axi4PeripheralStreamFifo_be6ad777990c4e5089d0b11c63cc2698 ( + input wire io_push_valid, + output wire io_push_ready, + input wire [7:0] io_push_payload, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [7:0] io_pop_payload, + input wire io_flush, + output wire [7:0] io_occupancy, + output wire [7:0] io_availability, + input wire clk, + input wire reset +); + + reg [7:0] logic_ram_spinal_port1; + reg _zz_1; + wire logic_ptr_doPush; + wire logic_ptr_doPop; + wire logic_ptr_full; + wire logic_ptr_empty; + reg [7:0] logic_ptr_push; + reg [7:0] logic_ptr_pop; + wire [7:0] logic_ptr_occupancy; + wire [7:0] logic_ptr_popOnIo; + wire when_Stream_l1248; + reg logic_ptr_wentUp; + wire io_push_fire; + wire logic_push_onRam_write_valid; + wire [6:0] logic_push_onRam_write_payload_address; + wire [7:0] logic_push_onRam_write_payload_data; + wire logic_pop_addressGen_valid; + reg logic_pop_addressGen_ready; + wire [6:0] logic_pop_addressGen_payload; + wire logic_pop_addressGen_fire; + wire logic_pop_sync_readArbitation_valid; + wire logic_pop_sync_readArbitation_ready; + wire [6:0] logic_pop_sync_readArbitation_payload; + reg logic_pop_addressGen_rValid; + reg [6:0] logic_pop_addressGen_rData; + wire when_Stream_l375; + wire logic_pop_sync_readPort_cmd_valid; + wire [6:0] logic_pop_sync_readPort_cmd_payload; + wire [7:0] logic_pop_sync_readPort_rsp; + wire logic_pop_sync_readArbitation_translated_valid; + wire logic_pop_sync_readArbitation_translated_ready; + wire [7:0] logic_pop_sync_readArbitation_translated_payload; + wire logic_pop_sync_readArbitation_fire; + reg [7:0] logic_pop_sync_popReg; + reg [7:0] logic_ram [0:127]; + + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data; + end + end + + always @(posedge clk) begin + if(logic_pop_sync_readPort_cmd_valid) begin + logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_push_onRam_write_valid) begin + _zz_1 = 1'b1; + end + end + + assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); + assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 8'h80) == 8'h0); + assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop); + assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo); + assign io_push_ready = (! logic_ptr_full); + assign io_push_fire = (io_push_valid && io_push_ready); + assign logic_ptr_doPush = io_push_fire; + assign logic_push_onRam_write_valid = io_push_fire; + assign logic_push_onRam_write_payload_address = logic_ptr_push[6:0]; + assign logic_push_onRam_write_payload_data = io_push_payload; + assign logic_pop_addressGen_valid = (! logic_ptr_empty); + assign logic_pop_addressGen_payload = logic_ptr_pop[6:0]; + assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); + assign logic_ptr_doPop = logic_pop_addressGen_fire; + always @(*) begin + logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; + if(when_Stream_l375) begin + logic_pop_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); + assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; + assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; + assign logic_pop_sync_readPort_rsp = logic_ram_spinal_port1; + assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; + assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; + assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; + assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; + assign logic_pop_sync_readArbitation_translated_payload = logic_pop_sync_readPort_rsp; + assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; + assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload = logic_pop_sync_readArbitation_translated_payload; + assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); + assign logic_ptr_popOnIo = logic_pop_sync_popReg; + assign io_occupancy = logic_ptr_occupancy; + assign io_availability = (8'h80 - logic_ptr_occupancy); + always @(posedge clk) begin + if(reset) begin + logic_ptr_push <= 8'h0; + logic_ptr_pop <= 8'h0; + logic_ptr_wentUp <= 1'b0; + logic_pop_addressGen_rValid <= 1'b0; + logic_pop_sync_popReg <= 8'h0; + end else begin + if(when_Stream_l1248) begin + logic_ptr_wentUp <= logic_ptr_doPush; + end + if(io_flush) begin + logic_ptr_wentUp <= 1'b0; + end + if(logic_ptr_doPush) begin + logic_ptr_push <= (logic_ptr_push + 8'h01); + end + if(logic_ptr_doPop) begin + logic_ptr_pop <= (logic_ptr_pop + 8'h01); + end + if(io_flush) begin + logic_ptr_push <= 8'h0; + logic_ptr_pop <= 8'h0; + end + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; + end + if(io_flush) begin + logic_pop_addressGen_rValid <= 1'b0; + end + if(logic_pop_sync_readArbitation_fire) begin + logic_pop_sync_popReg <= logic_ptr_pop; + end + if(io_flush) begin + logic_pop_sync_popReg <= 8'h0; + end + end + end + + always @(posedge clk) begin + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rData <= logic_pop_addressGen_payload; + end + end + + +endmodule + +module Axi4PeripheralUartCtrl_be6ad777990c4e5089d0b11c63cc2698 ( + input wire [2:0] io_config_frame_dataLength, + input wire [0:0] io_config_frame_stop, + input wire [1:0] io_config_frame_parity, + input wire [19:0] io_config_clockDivider, + input wire io_write_valid, + output reg io_write_ready, + input wire [7:0] io_write_payload, + output wire io_read_valid, + input wire io_read_ready, + output wire [7:0] io_read_payload, + output wire io_uart_txd, + input wire io_uart_rxd, + output wire io_readError, + input wire io_writeBreak, + output wire io_readBreak, + input wire clk, + input wire reset +); + localparam Axi4PeripheralUartStopType_ONE = 1'd0; + localparam Axi4PeripheralUartStopType_TWO = 1'd1; + localparam Axi4PeripheralUartParityType_NONE = 2'd0; + localparam Axi4PeripheralUartParityType_EVEN = 2'd1; + localparam Axi4PeripheralUartParityType_ODD = 2'd2; + + wire tx_io_write_ready; + wire tx_io_txd; + wire rx_io_read_valid; + wire [7:0] rx_io_read_payload; + wire rx_io_rts; + wire rx_io_error; + wire rx_io_break; + reg [19:0] clockDivider_counter; + wire clockDivider_tick; + reg clockDivider_tickReg; + reg io_write_thrown_valid; + wire io_write_thrown_ready; + wire [7:0] io_write_thrown_payload; + `ifndef SYNTHESIS + reg [23:0] io_config_frame_stop_string; + reg [31:0] io_config_frame_parity_string; + `endif + + + Axi4PeripheralUartCtrlTx_be6ad777990c4e5089d0b11c63cc2698 tx ( + .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i + .io_configFrame_stop (io_config_frame_stop ), //i + .io_configFrame_parity (io_config_frame_parity[1:0] ), //i + .io_samplingTick (clockDivider_tickReg ), //i + .io_write_valid (io_write_thrown_valid ), //i + .io_write_ready (tx_io_write_ready ), //o + .io_write_payload (io_write_thrown_payload[7:0] ), //i + .io_cts (1'b0 ), //i + .io_txd (tx_io_txd ), //o + .io_break (io_writeBreak ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralUartCtrlRx_be6ad777990c4e5089d0b11c63cc2698 rx ( + .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i + .io_configFrame_stop (io_config_frame_stop ), //i + .io_configFrame_parity (io_config_frame_parity[1:0] ), //i + .io_samplingTick (clockDivider_tickReg ), //i + .io_read_valid (rx_io_read_valid ), //o + .io_read_ready (io_read_ready ), //i + .io_read_payload (rx_io_read_payload[7:0] ), //o + .io_rxd (io_uart_rxd ), //i + .io_rts (rx_io_rts ), //o + .io_error (rx_io_error ), //o + .io_break (rx_io_break ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_config_frame_stop) + Axi4PeripheralUartStopType_ONE : io_config_frame_stop_string = "ONE"; + Axi4PeripheralUartStopType_TWO : io_config_frame_stop_string = "TWO"; + default : io_config_frame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_config_frame_parity) + Axi4PeripheralUartParityType_NONE : io_config_frame_parity_string = "NONE"; + Axi4PeripheralUartParityType_EVEN : io_config_frame_parity_string = "EVEN"; + Axi4PeripheralUartParityType_ODD : io_config_frame_parity_string = "ODD "; + default : io_config_frame_parity_string = "????"; + endcase + end + `endif + + assign clockDivider_tick = (clockDivider_counter == 20'h0); + always @(*) begin + io_write_thrown_valid = io_write_valid; + if(rx_io_break) begin + io_write_thrown_valid = 1'b0; + end + end + + always @(*) begin + io_write_ready = io_write_thrown_ready; + if(rx_io_break) begin + io_write_ready = 1'b1; + end + end + + assign io_write_thrown_payload = io_write_payload; + assign io_write_thrown_ready = tx_io_write_ready; + assign io_read_valid = rx_io_read_valid; + assign io_read_payload = rx_io_read_payload; + assign io_uart_txd = tx_io_txd; + assign io_readError = rx_io_error; + assign io_readBreak = rx_io_break; + always @(posedge clk) begin + if(reset) begin + clockDivider_counter <= 20'h0; + clockDivider_tickReg <= 1'b0; + end else begin + clockDivider_tickReg <= clockDivider_tick; + clockDivider_counter <= (clockDivider_counter - 20'h00001); + if(clockDivider_tick) begin + clockDivider_counter <= io_config_clockDivider; + end + end + end + + +endmodule + +//Axi4PeripheralBufferCC_2 replaced by Axi4PeripheralBufferCC_1_be6ad777990c4e5089d0b11c63cc2698 + +module Axi4PeripheralBufferCC_1_be6ad777990c4e5089d0b11c63cc2698 ( + input wire io_dataIn, + output wire io_dataOut, + input wire clk, + input wire reset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge clk) begin + if(reset) begin + buffers_0 <= 1'b1; + buffers_1 <= 1'b1; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module Axi4PeripheralUartCtrlRx_be6ad777990c4e5089d0b11c63cc2698 ( + input wire [2:0] io_configFrame_dataLength, + input wire [0:0] io_configFrame_stop, + input wire [1:0] io_configFrame_parity, + input wire io_samplingTick, + output wire io_read_valid, + input wire io_read_ready, + output wire [7:0] io_read_payload, + input wire io_rxd, + output wire io_rts, + output reg io_error, + output wire io_break, + input wire clk, + input wire reset +); + localparam Axi4PeripheralUartStopType_ONE = 1'd0; + localparam Axi4PeripheralUartStopType_TWO = 1'd1; + localparam Axi4PeripheralUartParityType_NONE = 2'd0; + localparam Axi4PeripheralUartParityType_EVEN = 2'd1; + localparam Axi4PeripheralUartParityType_ODD = 2'd2; + localparam Axi4PeripheralUartCtrlRxState_IDLE = 3'd0; + localparam Axi4PeripheralUartCtrlRxState_START = 3'd1; + localparam Axi4PeripheralUartCtrlRxState_DATA = 3'd2; + localparam Axi4PeripheralUartCtrlRxState_PARITY = 3'd3; + localparam Axi4PeripheralUartCtrlRxState_STOP = 3'd4; + + wire io_rxd_buffercc_io_dataOut; + wire _zz_sampler_value; + wire _zz_sampler_value_1; + wire _zz_sampler_value_2; + wire _zz_sampler_value_3; + wire _zz_sampler_value_4; + wire _zz_sampler_value_5; + wire _zz_sampler_value_6; + wire [2:0] _zz_when_UartCtrlRx_l139; + wire [0:0] _zz_when_UartCtrlRx_l139_1; + reg _zz_io_rts; + wire sampler_synchroniser; + wire sampler_samples_0; + reg sampler_samples_1; + reg sampler_samples_2; + reg sampler_samples_3; + reg sampler_samples_4; + reg sampler_value; + reg sampler_tick; + reg [2:0] bitTimer_counter; + reg bitTimer_tick; + wire when_UartCtrlRx_l43; + reg [2:0] bitCounter_value; + reg [6:0] break_counter; + wire break_valid; + wire when_UartCtrlRx_l69; + reg [2:0] stateMachine_state; + reg stateMachine_parity; + reg [7:0] stateMachine_shifter; + reg stateMachine_validReg; + wire when_UartCtrlRx_l93; + wire when_UartCtrlRx_l103; + wire when_UartCtrlRx_l111; + wire when_UartCtrlRx_l113; + wire when_UartCtrlRx_l125; + wire when_UartCtrlRx_l136; + wire when_UartCtrlRx_l139; + `ifndef SYNTHESIS + reg [23:0] io_configFrame_stop_string; + reg [31:0] io_configFrame_parity_string; + reg [47:0] stateMachine_state_string; + `endif + + + assign _zz_when_UartCtrlRx_l139_1 = ((io_configFrame_stop == Axi4PeripheralUartStopType_ONE) ? 1'b0 : 1'b1); + assign _zz_when_UartCtrlRx_l139 = {2'd0, _zz_when_UartCtrlRx_l139_1}; + assign _zz_sampler_value = ((((1'b0 || ((_zz_sampler_value_1 && sampler_samples_1) && sampler_samples_2)) || (((_zz_sampler_value_2 && sampler_samples_0) && sampler_samples_1) && sampler_samples_3)) || (((1'b1 && sampler_samples_0) && sampler_samples_2) && sampler_samples_3)) || (((1'b1 && sampler_samples_1) && sampler_samples_2) && sampler_samples_3)); + assign _zz_sampler_value_3 = (((1'b1 && sampler_samples_0) && sampler_samples_1) && sampler_samples_4); + assign _zz_sampler_value_4 = ((1'b1 && sampler_samples_0) && sampler_samples_2); + assign _zz_sampler_value_5 = (1'b1 && sampler_samples_1); + assign _zz_sampler_value_6 = 1'b1; + assign _zz_sampler_value_1 = (1'b1 && sampler_samples_0); + assign _zz_sampler_value_2 = 1'b1; + (* keep_hierarchy = "TRUE" *) Axi4PeripheralBufferCC_be6ad777990c4e5089d0b11c63cc2698 io_rxd_buffercc ( + .io_dataIn (io_rxd ), //i + .io_dataOut (io_rxd_buffercc_io_dataOut), //o + .clk (clk ), //i + .reset (reset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_configFrame_stop) + Axi4PeripheralUartStopType_ONE : io_configFrame_stop_string = "ONE"; + Axi4PeripheralUartStopType_TWO : io_configFrame_stop_string = "TWO"; + default : io_configFrame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_configFrame_parity) + Axi4PeripheralUartParityType_NONE : io_configFrame_parity_string = "NONE"; + Axi4PeripheralUartParityType_EVEN : io_configFrame_parity_string = "EVEN"; + Axi4PeripheralUartParityType_ODD : io_configFrame_parity_string = "ODD "; + default : io_configFrame_parity_string = "????"; + endcase + end + always @(*) begin + case(stateMachine_state) + Axi4PeripheralUartCtrlRxState_IDLE : stateMachine_state_string = "IDLE "; + Axi4PeripheralUartCtrlRxState_START : stateMachine_state_string = "START "; + Axi4PeripheralUartCtrlRxState_DATA : stateMachine_state_string = "DATA "; + Axi4PeripheralUartCtrlRxState_PARITY : stateMachine_state_string = "PARITY"; + Axi4PeripheralUartCtrlRxState_STOP : stateMachine_state_string = "STOP "; + default : stateMachine_state_string = "??????"; + endcase + end + `endif + + always @(*) begin + io_error = 1'b0; + case(stateMachine_state) + Axi4PeripheralUartCtrlRxState_IDLE : begin + end + Axi4PeripheralUartCtrlRxState_START : begin + end + Axi4PeripheralUartCtrlRxState_DATA : begin + end + Axi4PeripheralUartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + if(!when_UartCtrlRx_l125) begin + io_error = 1'b1; + end + end + end + default : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l136) begin + io_error = 1'b1; + end + end + end + endcase + end + + assign io_rts = _zz_io_rts; + assign sampler_synchroniser = io_rxd_buffercc_io_dataOut; + assign sampler_samples_0 = sampler_synchroniser; + always @(*) begin + bitTimer_tick = 1'b0; + if(sampler_tick) begin + if(when_UartCtrlRx_l43) begin + bitTimer_tick = 1'b1; + end + end + end + + assign when_UartCtrlRx_l43 = (bitTimer_counter == 3'b000); + assign break_valid = (break_counter == 7'h68); + assign when_UartCtrlRx_l69 = (io_samplingTick && (! break_valid)); + assign io_break = break_valid; + assign io_read_valid = stateMachine_validReg; + assign when_UartCtrlRx_l93 = ((sampler_tick && (! sampler_value)) && (! break_valid)); + assign when_UartCtrlRx_l103 = (sampler_value == 1'b1); + assign when_UartCtrlRx_l111 = (bitCounter_value == io_configFrame_dataLength); + assign when_UartCtrlRx_l113 = (io_configFrame_parity == Axi4PeripheralUartParityType_NONE); + assign when_UartCtrlRx_l125 = (stateMachine_parity == sampler_value); + assign when_UartCtrlRx_l136 = (! sampler_value); + assign when_UartCtrlRx_l139 = (bitCounter_value == _zz_when_UartCtrlRx_l139); + assign io_read_payload = stateMachine_shifter; + always @(posedge clk) begin + if(reset) begin + _zz_io_rts <= 1'b0; + sampler_samples_1 <= 1'b1; + sampler_samples_2 <= 1'b1; + sampler_samples_3 <= 1'b1; + sampler_samples_4 <= 1'b1; + sampler_value <= 1'b1; + sampler_tick <= 1'b0; + break_counter <= 7'h0; + stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; + stateMachine_validReg <= 1'b0; + end else begin + _zz_io_rts <= (! io_read_ready); + if(io_samplingTick) begin + sampler_samples_1 <= sampler_samples_0; + end + if(io_samplingTick) begin + sampler_samples_2 <= sampler_samples_1; + end + if(io_samplingTick) begin + sampler_samples_3 <= sampler_samples_2; + end + if(io_samplingTick) begin + sampler_samples_4 <= sampler_samples_3; + end + sampler_value <= ((((((_zz_sampler_value || _zz_sampler_value_3) || (_zz_sampler_value_4 && sampler_samples_4)) || ((_zz_sampler_value_5 && sampler_samples_2) && sampler_samples_4)) || (((_zz_sampler_value_6 && sampler_samples_0) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_1) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_2) && sampler_samples_3) && sampler_samples_4)); + sampler_tick <= io_samplingTick; + if(sampler_value) begin + break_counter <= 7'h0; + end else begin + if(when_UartCtrlRx_l69) begin + break_counter <= (break_counter + 7'h01); + end + end + stateMachine_validReg <= 1'b0; + case(stateMachine_state) + Axi4PeripheralUartCtrlRxState_IDLE : begin + if(when_UartCtrlRx_l93) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_START; + end + end + Axi4PeripheralUartCtrlRxState_START : begin + if(bitTimer_tick) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_DATA; + if(when_UartCtrlRx_l103) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; + end + end + end + Axi4PeripheralUartCtrlRxState_DATA : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l111) begin + if(when_UartCtrlRx_l113) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_STOP; + stateMachine_validReg <= 1'b1; + end else begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_PARITY; + end + end + end + end + Axi4PeripheralUartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l125) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_STOP; + stateMachine_validReg <= 1'b1; + end else begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; + end + end + end + default : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l136) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; + end else begin + if(when_UartCtrlRx_l139) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; + end + end + end + end + endcase + end + end + + always @(posedge clk) begin + if(sampler_tick) begin + bitTimer_counter <= (bitTimer_counter - 3'b001); + end + if(bitTimer_tick) begin + bitCounter_value <= (bitCounter_value + 3'b001); + end + if(bitTimer_tick) begin + stateMachine_parity <= (stateMachine_parity ^ sampler_value); + end + case(stateMachine_state) + Axi4PeripheralUartCtrlRxState_IDLE : begin + if(when_UartCtrlRx_l93) begin + bitTimer_counter <= 3'b010; + end + end + Axi4PeripheralUartCtrlRxState_START : begin + if(bitTimer_tick) begin + bitCounter_value <= 3'b000; + stateMachine_parity <= (io_configFrame_parity == Axi4PeripheralUartParityType_ODD); + end + end + Axi4PeripheralUartCtrlRxState_DATA : begin + if(bitTimer_tick) begin + stateMachine_shifter[bitCounter_value] <= sampler_value; + if(when_UartCtrlRx_l111) begin + bitCounter_value <= 3'b000; + end + end + end + Axi4PeripheralUartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + bitCounter_value <= 3'b000; + end + end + default : begin + end + endcase + end + + +endmodule + +module Axi4PeripheralUartCtrlTx_be6ad777990c4e5089d0b11c63cc2698 ( + input wire [2:0] io_configFrame_dataLength, + input wire [0:0] io_configFrame_stop, + input wire [1:0] io_configFrame_parity, + input wire io_samplingTick, + input wire io_write_valid, + output reg io_write_ready, + input wire [7:0] io_write_payload, + input wire io_cts, + output wire io_txd, + input wire io_break, + input wire clk, + input wire reset +); + localparam Axi4PeripheralUartStopType_ONE = 1'd0; + localparam Axi4PeripheralUartStopType_TWO = 1'd1; + localparam Axi4PeripheralUartParityType_NONE = 2'd0; + localparam Axi4PeripheralUartParityType_EVEN = 2'd1; + localparam Axi4PeripheralUartParityType_ODD = 2'd2; + localparam Axi4PeripheralUartCtrlTxState_IDLE = 3'd0; + localparam Axi4PeripheralUartCtrlTxState_START = 3'd1; + localparam Axi4PeripheralUartCtrlTxState_DATA = 3'd2; + localparam Axi4PeripheralUartCtrlTxState_PARITY = 3'd3; + localparam Axi4PeripheralUartCtrlTxState_STOP = 3'd4; + + wire [2:0] _zz_clockDivider_counter_valueNext; + wire [0:0] _zz_clockDivider_counter_valueNext_1; + wire [2:0] _zz_when_UartCtrlTx_l93; + wire [0:0] _zz_when_UartCtrlTx_l93_1; + reg clockDivider_counter_willIncrement; + wire clockDivider_counter_willClear; + reg [2:0] clockDivider_counter_valueNext; + reg [2:0] clockDivider_counter_value; + wire clockDivider_counter_willOverflowIfInc; + wire clockDivider_counter_willOverflow; + reg [2:0] tickCounter_value; + reg [2:0] stateMachine_state; + reg stateMachine_parity; + reg stateMachine_txd; + wire when_UartCtrlTx_l58; + wire when_UartCtrlTx_l73; + wire when_UartCtrlTx_l76; + wire when_UartCtrlTx_l93; + wire [2:0] _zz_stateMachine_state; + reg _zz_io_txd; + `ifndef SYNTHESIS + reg [23:0] io_configFrame_stop_string; + reg [31:0] io_configFrame_parity_string; + reg [47:0] stateMachine_state_string; + reg [47:0] _zz_stateMachine_state_string; + `endif + + + assign _zz_clockDivider_counter_valueNext_1 = clockDivider_counter_willIncrement; + assign _zz_clockDivider_counter_valueNext = {2'd0, _zz_clockDivider_counter_valueNext_1}; + assign _zz_when_UartCtrlTx_l93_1 = ((io_configFrame_stop == Axi4PeripheralUartStopType_ONE) ? 1'b0 : 1'b1); + assign _zz_when_UartCtrlTx_l93 = {2'd0, _zz_when_UartCtrlTx_l93_1}; + `ifndef SYNTHESIS + always @(*) begin + case(io_configFrame_stop) + Axi4PeripheralUartStopType_ONE : io_configFrame_stop_string = "ONE"; + Axi4PeripheralUartStopType_TWO : io_configFrame_stop_string = "TWO"; + default : io_configFrame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_configFrame_parity) + Axi4PeripheralUartParityType_NONE : io_configFrame_parity_string = "NONE"; + Axi4PeripheralUartParityType_EVEN : io_configFrame_parity_string = "EVEN"; + Axi4PeripheralUartParityType_ODD : io_configFrame_parity_string = "ODD "; + default : io_configFrame_parity_string = "????"; + endcase + end + always @(*) begin + case(stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : stateMachine_state_string = "IDLE "; + Axi4PeripheralUartCtrlTxState_START : stateMachine_state_string = "START "; + Axi4PeripheralUartCtrlTxState_DATA : stateMachine_state_string = "DATA "; + Axi4PeripheralUartCtrlTxState_PARITY : stateMachine_state_string = "PARITY"; + Axi4PeripheralUartCtrlTxState_STOP : stateMachine_state_string = "STOP "; + default : stateMachine_state_string = "??????"; + endcase + end + always @(*) begin + case(_zz_stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : _zz_stateMachine_state_string = "IDLE "; + Axi4PeripheralUartCtrlTxState_START : _zz_stateMachine_state_string = "START "; + Axi4PeripheralUartCtrlTxState_DATA : _zz_stateMachine_state_string = "DATA "; + Axi4PeripheralUartCtrlTxState_PARITY : _zz_stateMachine_state_string = "PARITY"; + Axi4PeripheralUartCtrlTxState_STOP : _zz_stateMachine_state_string = "STOP "; + default : _zz_stateMachine_state_string = "??????"; + endcase + end + `endif + + always @(*) begin + clockDivider_counter_willIncrement = 1'b0; + if(io_samplingTick) begin + clockDivider_counter_willIncrement = 1'b1; + end + end + + assign clockDivider_counter_willClear = 1'b0; + assign clockDivider_counter_willOverflowIfInc = (clockDivider_counter_value == 3'b111); + assign clockDivider_counter_willOverflow = (clockDivider_counter_willOverflowIfInc && clockDivider_counter_willIncrement); + always @(*) begin + clockDivider_counter_valueNext = (clockDivider_counter_value + _zz_clockDivider_counter_valueNext); + if(clockDivider_counter_willClear) begin + clockDivider_counter_valueNext = 3'b000; + end + end + + always @(*) begin + stateMachine_txd = 1'b1; + case(stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : begin + end + Axi4PeripheralUartCtrlTxState_START : begin + stateMachine_txd = 1'b0; + end + Axi4PeripheralUartCtrlTxState_DATA : begin + stateMachine_txd = io_write_payload[tickCounter_value]; + end + Axi4PeripheralUartCtrlTxState_PARITY : begin + stateMachine_txd = stateMachine_parity; + end + default : begin + end + endcase + end + + always @(*) begin + io_write_ready = io_break; + case(stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : begin + end + Axi4PeripheralUartCtrlTxState_START : begin + end + Axi4PeripheralUartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + io_write_ready = 1'b1; + end + end + end + Axi4PeripheralUartCtrlTxState_PARITY : begin + end + default : begin + end + endcase + end + + assign when_UartCtrlTx_l58 = ((io_write_valid && (! io_cts)) && clockDivider_counter_willOverflow); + assign when_UartCtrlTx_l73 = (tickCounter_value == io_configFrame_dataLength); + assign when_UartCtrlTx_l76 = (io_configFrame_parity == Axi4PeripheralUartParityType_NONE); + assign when_UartCtrlTx_l93 = (tickCounter_value == _zz_when_UartCtrlTx_l93); + assign _zz_stateMachine_state = (io_write_valid ? Axi4PeripheralUartCtrlTxState_START : Axi4PeripheralUartCtrlTxState_IDLE); + assign io_txd = _zz_io_txd; + always @(posedge clk) begin + if(reset) begin + clockDivider_counter_value <= 3'b000; + stateMachine_state <= Axi4PeripheralUartCtrlTxState_IDLE; + _zz_io_txd <= 1'b1; + end else begin + clockDivider_counter_value <= clockDivider_counter_valueNext; + case(stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : begin + if(when_UartCtrlTx_l58) begin + stateMachine_state <= Axi4PeripheralUartCtrlTxState_START; + end + end + Axi4PeripheralUartCtrlTxState_START : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_state <= Axi4PeripheralUartCtrlTxState_DATA; + end + end + Axi4PeripheralUartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + if(when_UartCtrlTx_l76) begin + stateMachine_state <= Axi4PeripheralUartCtrlTxState_STOP; + end else begin + stateMachine_state <= Axi4PeripheralUartCtrlTxState_PARITY; + end + end + end + end + Axi4PeripheralUartCtrlTxState_PARITY : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_state <= Axi4PeripheralUartCtrlTxState_STOP; + end + end + default : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l93) begin + stateMachine_state <= _zz_stateMachine_state; + end + end + end + endcase + _zz_io_txd <= (stateMachine_txd && (! io_break)); + end + end + + always @(posedge clk) begin + if(clockDivider_counter_willOverflow) begin + tickCounter_value <= (tickCounter_value + 3'b001); + end + if(clockDivider_counter_willOverflow) begin + stateMachine_parity <= (stateMachine_parity ^ stateMachine_txd); + end + case(stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : begin + end + Axi4PeripheralUartCtrlTxState_START : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_parity <= (io_configFrame_parity == Axi4PeripheralUartParityType_ODD); + tickCounter_value <= 3'b000; + end + end + Axi4PeripheralUartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + tickCounter_value <= 3'b000; + end + end + end + Axi4PeripheralUartCtrlTxState_PARITY : begin + if(clockDivider_counter_willOverflow) begin + tickCounter_value <= 3'b000; + end + end + default : begin + end + endcase + end + + +endmodule + +module Axi4PeripheralBufferCC_be6ad777990c4e5089d0b11c63cc2698 ( + input wire io_dataIn, + output wire io_dataOut, + input wire clk, + input wire reset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge clk) begin + if(reset) begin + buffers_0 <= 1'b0; + buffers_1 <= 1'b0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_define.vh b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_define.vh new file mode 100644 index 0000000..3efcf53 --- /dev/null +++ b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_define.vh @@ -0,0 +1,46 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2026.1.132 +// IP Version: 1.23.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2026 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam PERI_FREQ = 200; diff --git a/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.v b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.v new file mode 100644 index 0000000..8b0ee7a --- /dev/null +++ b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.v @@ -0,0 +1,148 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2026.1.132 +// IP Version: 1.23.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2026 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +EfxSapphireHpSoc_slb u_EfxSapphireHpSoc_slb +( + .io_peripheralClk ( io_peripheralClk ), + .io_peripheralReset ( io_peripheralReset ), + .io_asyncReset ( io_asyncReset ), + .io_gpio_sw_n ( io_gpio_sw_n ), + .pll_peripheral_locked ( pll_peripheral_locked ), + .pll_system_locked ( pll_system_locked ), + .jtagCtrl_capture ( jtagCtrl_capture ), + .jtagCtrl_enable ( jtagCtrl_enable ), + .jtagCtrl_reset ( jtagCtrl_reset ), + .jtagCtrl_shift ( jtagCtrl_shift ), + .jtagCtrl_tdi ( jtagCtrl_tdi ), + .jtagCtrl_tdo ( jtagCtrl_tdo ), + .jtagCtrl_update ( jtagCtrl_update ), + .ut_jtagCtrl_capture ( ut_jtagCtrl_capture ), + .ut_jtagCtrl_enable ( ut_jtagCtrl_enable ), + .ut_jtagCtrl_reset ( ut_jtagCtrl_reset ), + .ut_jtagCtrl_shift ( ut_jtagCtrl_shift ), + .ut_jtagCtrl_tdi ( ut_jtagCtrl_tdi ), + .ut_jtagCtrl_tdo ( ut_jtagCtrl_tdo ), + .ut_jtagCtrl_update ( ut_jtagCtrl_update ), + .system_spi_0_io_data_0_read ( system_spi_0_io_data_0_read ), + .system_spi_0_io_data_0_write ( system_spi_0_io_data_0_write ), + .system_spi_0_io_data_0_writeEnable ( system_spi_0_io_data_0_writeEnable ), + .system_spi_0_io_data_1_read ( system_spi_0_io_data_1_read ), + .system_spi_0_io_data_1_write ( system_spi_0_io_data_1_write ), + .system_spi_0_io_data_1_writeEnable ( system_spi_0_io_data_1_writeEnable ), + .system_spi_0_io_data_2_read ( system_spi_0_io_data_2_read ), + .system_spi_0_io_data_2_write ( system_spi_0_io_data_2_write ), + .system_spi_0_io_data_2_writeEnable ( system_spi_0_io_data_2_writeEnable ), + .system_spi_0_io_data_3_read ( system_spi_0_io_data_3_read ), + .system_spi_0_io_data_3_write ( system_spi_0_io_data_3_write ), + .system_spi_0_io_data_3_writeEnable ( system_spi_0_io_data_3_writeEnable ), + .system_spi_0_io_sclk_write ( system_spi_0_io_sclk_write ), + .system_spi_0_io_ss ( system_spi_0_io_ss ), + .system_uart_0_io_rxd ( system_uart_0_io_rxd ), + .system_uart_0_io_txd ( system_uart_0_io_txd ), + .system_i2c_0_io_scl_read ( system_i2c_0_io_scl_read ), + .system_i2c_0_io_scl_write ( system_i2c_0_io_scl_write ), + .system_i2c_0_io_sda_read ( system_i2c_0_io_sda_read ), + .system_gpio_0_io_read ( system_gpio_0_io_read ), + .system_gpio_0_io_write ( system_gpio_0_io_write ), + .system_gpio_0_io_writeEnable ( system_gpio_0_io_writeEnable ), + .cfg_done ( cfg_done ), + .cfg_start ( cfg_start ), + .cfg_sel ( cfg_sel ), + .cfg_reset ( cfg_reset ), + .axiAInterrupt ( axiAInterrupt ), + .axiA_awaddr ( axiA_awaddr ), + .axiA_awlen ( axiA_awlen ), + .axiA_awsize ( axiA_awsize ), + .axiA_awburst ( axiA_awburst ), + .axiA_awlock ( axiA_awlock ), + .axiA_awcache ( axiA_awcache ), + .axiA_awprot ( axiA_awprot ), + .axiA_awqos ( axiA_awqos ), + .axiA_awregion ( axiA_awregion ), + .axiA_awvalid ( axiA_awvalid ), + .axiA_awready ( axiA_awready ), + .axiA_wdata ( axiA_wdata ), + .axiA_wstrb ( axiA_wstrb ), + .axiA_wvalid ( axiA_wvalid ), + .axiA_wlast ( axiA_wlast ), + .axiA_wready ( axiA_wready ), + .axiA_bresp ( axiA_bresp ), + .axiA_bvalid ( axiA_bvalid ), + .axiA_bready ( axiA_bready ), + .axiA_araddr ( axiA_araddr ), + .axiA_arlen ( axiA_arlen ), + .axiA_arsize ( axiA_arsize ), + .axiA_arburst ( axiA_arburst ), + .axiA_arlock ( axiA_arlock ), + .axiA_arcache ( axiA_arcache ), + .axiA_arprot ( axiA_arprot ), + .axiA_arqos ( axiA_arqos ), + .axiA_arregion ( axiA_arregion ), + .axiA_arvalid ( axiA_arvalid ), + .axiA_arready ( axiA_arready ), + .axiA_rdata ( axiA_rdata ), + .axiA_rresp ( axiA_rresp ), + .axiA_rlast ( axiA_rlast ), + .axiA_rvalid ( axiA_rvalid ), + .axiA_rready ( axiA_rready ), + .userInterruptA ( userInterruptA ), + .userInterruptB ( userInterruptB ), + .userInterruptC ( userInterruptC ), + .userInterruptD ( userInterruptD ), + .userInterruptE ( userInterruptE ), + .userInterruptF ( userInterruptF ), + .io_apbSlave_0_PADDR ( io_apbSlave_0_PADDR ), + .io_apbSlave_0_PENABLE ( io_apbSlave_0_PENABLE ), + .io_apbSlave_0_PRDATA ( io_apbSlave_0_PRDATA ), + .io_apbSlave_0_PREADY ( io_apbSlave_0_PREADY ), + .io_apbSlave_0_PSEL ( io_apbSlave_0_PSEL ), + .io_apbSlave_0_PSLVERROR ( io_apbSlave_0_PSLVERROR ), + .io_apbSlave_0_PWDATA ( io_apbSlave_0_PWDATA ), + .io_apbSlave_0_PWRITE ( io_apbSlave_0_PWRITE ), + .system_i2c_0_io_sda_write ( system_i2c_0_io_sda_write ), + .system_i2c_0_io_sda_writeEnable ( system_i2c_0_io_sda_writeEnable ), + .system_i2c_0_io_scl_writeEnable ( system_i2c_0_io_scl_writeEnable ), + .system_watchdog_hardPanic_reset ( system_watchdog_hardPanic_reset ) +); diff --git a/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.vhd b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.vhd new file mode 100644 index 0000000..e587f31 --- /dev/null +++ b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_slb_tmpl.vhd @@ -0,0 +1,251 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2026 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +component EfxSapphireHpSoc_slb is +port ( + io_peripheralClk : in std_logic; + io_peripheralReset : in std_logic; + io_asyncReset : out std_logic; + io_gpio_sw_n : in std_logic; + pll_peripheral_locked : in std_logic; + pll_system_locked : in std_logic; + jtagCtrl_capture : out std_logic; + jtagCtrl_enable : out std_logic; + jtagCtrl_reset : out std_logic; + jtagCtrl_shift : out std_logic; + jtagCtrl_tdi : out std_logic; + jtagCtrl_tdo : in std_logic; + jtagCtrl_update : out std_logic; + ut_jtagCtrl_capture : in std_logic; + ut_jtagCtrl_enable : in std_logic; + ut_jtagCtrl_reset : in std_logic; + ut_jtagCtrl_shift : in std_logic; + ut_jtagCtrl_tdi : in std_logic; + ut_jtagCtrl_tdo : out std_logic; + ut_jtagCtrl_update : in std_logic; + system_spi_0_io_data_0_read : in std_logic; + system_spi_0_io_data_0_write : out std_logic; + system_spi_0_io_data_0_writeEnable : out std_logic; + system_spi_0_io_data_1_read : in std_logic; + system_spi_0_io_data_1_write : out std_logic; + system_spi_0_io_data_1_writeEnable : out std_logic; + system_spi_0_io_data_2_read : in std_logic; + system_spi_0_io_data_2_write : out std_logic; + system_spi_0_io_data_2_writeEnable : out std_logic; + system_spi_0_io_data_3_read : in std_logic; + system_spi_0_io_data_3_write : out std_logic; + system_spi_0_io_data_3_writeEnable : out std_logic; + system_spi_0_io_sclk_write : out std_logic; + system_spi_0_io_ss : out std_logic_vector(3 downto 0); + system_uart_0_io_rxd : in std_logic; + system_uart_0_io_txd : out std_logic; + system_i2c_0_io_scl_read : in std_logic; + system_i2c_0_io_scl_write : out std_logic; + system_i2c_0_io_sda_read : in std_logic; + system_gpio_0_io_read : in std_logic_vector(3 downto 0); + system_gpio_0_io_write : out std_logic_vector(3 downto 0); + system_gpio_0_io_writeEnable : out std_logic_vector(3 downto 0); + cfg_done : in std_logic; + cfg_start : out std_logic; + cfg_sel : out std_logic; + cfg_reset : out std_logic; + axiAInterrupt : out std_logic; + axiA_awaddr : in std_logic_vector(31 downto 0); + axiA_awlen : in std_logic_vector(7 downto 0); + axiA_awsize : in std_logic_vector(2 downto 0); + axiA_awburst : in std_logic_vector(1 downto 0); + axiA_awlock : in std_logic; + axiA_awcache : in std_logic_vector(3 downto 0); + axiA_awprot : in std_logic_vector(2 downto 0); + axiA_awqos : in std_logic_vector(3 downto 0); + axiA_awregion : in std_logic_vector(3 downto 0); + axiA_awvalid : in std_logic; + axiA_awready : out std_logic; + axiA_wdata : in std_logic_vector(31 downto 0); + axiA_wstrb : in std_logic_vector(3 downto 0); + axiA_wvalid : in std_logic; + axiA_wlast : in std_logic; + axiA_wready : out std_logic; + axiA_bresp : out std_logic_vector(1 downto 0); + axiA_bvalid : out std_logic; + axiA_bready : in std_logic; + axiA_araddr : in std_logic_vector(31 downto 0); + axiA_arlen : in std_logic_vector(7 downto 0); + axiA_arsize : in std_logic_vector(2 downto 0); + axiA_arburst : in std_logic_vector(1 downto 0); + axiA_arlock : in std_logic; + axiA_arcache : in std_logic_vector(3 downto 0); + axiA_arprot : in std_logic_vector(2 downto 0); + axiA_arqos : in std_logic_vector(3 downto 0); + axiA_arregion : in std_logic_vector(3 downto 0); + axiA_arvalid : in std_logic; + axiA_arready : out std_logic; + axiA_rdata : out std_logic_vector(31 downto 0); + axiA_rresp : out std_logic_vector(1 downto 0); + axiA_rlast : out std_logic; + axiA_rvalid : out std_logic; + axiA_rready : in std_logic; + userInterruptA : out std_logic; + userInterruptB : out std_logic; + userInterruptC : out std_logic; + userInterruptD : out std_logic; + userInterruptE : out std_logic; + userInterruptF : out std_logic; + io_apbSlave_0_PADDR : out std_logic_vector(31 downto 0); + io_apbSlave_0_PENABLE : out std_logic; + io_apbSlave_0_PRDATA : in std_logic_vector(31 downto 0); + io_apbSlave_0_PREADY : in std_logic; + io_apbSlave_0_PSEL : out std_logic; + io_apbSlave_0_PSLVERROR : in std_logic; + io_apbSlave_0_PWDATA : out std_logic_vector(31 downto 0); + io_apbSlave_0_PWRITE : out std_logic; + system_i2c_0_io_sda_write : out std_logic; + system_i2c_0_io_sda_writeEnable : out std_logic; + system_i2c_0_io_scl_writeEnable : out std_logic; + system_watchdog_hardPanic_reset : out std_logic +); +end component EfxSapphireHpSoc_slb; + +---------------------- End COMPONENT Declaration ------------ +------------- Begin Cut here for INSTANTIATION Template ----- +u_EfxSapphireHpSoc_slb : EfxSapphireHpSoc_slb +port map ( + io_peripheralClk => io_peripheralClk, + io_peripheralReset => io_peripheralReset, + io_asyncReset => io_asyncReset, + io_gpio_sw_n => io_gpio_sw_n, + pll_peripheral_locked => pll_peripheral_locked, + pll_system_locked => pll_system_locked, + jtagCtrl_capture => jtagCtrl_capture, + jtagCtrl_enable => jtagCtrl_enable, + jtagCtrl_reset => jtagCtrl_reset, + jtagCtrl_shift => jtagCtrl_shift, + jtagCtrl_tdi => jtagCtrl_tdi, + jtagCtrl_tdo => jtagCtrl_tdo, + jtagCtrl_update => jtagCtrl_update, + ut_jtagCtrl_capture => ut_jtagCtrl_capture, + ut_jtagCtrl_enable => ut_jtagCtrl_enable, + ut_jtagCtrl_reset => ut_jtagCtrl_reset, + ut_jtagCtrl_shift => ut_jtagCtrl_shift, + ut_jtagCtrl_tdi => ut_jtagCtrl_tdi, + ut_jtagCtrl_tdo => ut_jtagCtrl_tdo, + ut_jtagCtrl_update => ut_jtagCtrl_update, + system_spi_0_io_data_0_read => system_spi_0_io_data_0_read, + system_spi_0_io_data_0_write => system_spi_0_io_data_0_write, + system_spi_0_io_data_0_writeEnable => system_spi_0_io_data_0_writeEnable, + system_spi_0_io_data_1_read => system_spi_0_io_data_1_read, + system_spi_0_io_data_1_write => system_spi_0_io_data_1_write, + system_spi_0_io_data_1_writeEnable => system_spi_0_io_data_1_writeEnable, + system_spi_0_io_data_2_read => system_spi_0_io_data_2_read, + system_spi_0_io_data_2_write => system_spi_0_io_data_2_write, + system_spi_0_io_data_2_writeEnable => system_spi_0_io_data_2_writeEnable, + system_spi_0_io_data_3_read => system_spi_0_io_data_3_read, + system_spi_0_io_data_3_write => system_spi_0_io_data_3_write, + system_spi_0_io_data_3_writeEnable => system_spi_0_io_data_3_writeEnable, + system_spi_0_io_sclk_write => system_spi_0_io_sclk_write, + system_spi_0_io_ss => system_spi_0_io_ss, + system_uart_0_io_rxd => system_uart_0_io_rxd, + system_uart_0_io_txd => system_uart_0_io_txd, + system_i2c_0_io_scl_read => system_i2c_0_io_scl_read, + system_i2c_0_io_scl_write => system_i2c_0_io_scl_write, + system_i2c_0_io_sda_read => system_i2c_0_io_sda_read, + system_gpio_0_io_read => system_gpio_0_io_read, + system_gpio_0_io_write => system_gpio_0_io_write, + system_gpio_0_io_writeEnable => system_gpio_0_io_writeEnable, + cfg_done => cfg_done, + cfg_start => cfg_start, + cfg_sel => cfg_sel, + cfg_reset => cfg_reset, + axiAInterrupt => axiAInterrupt, + axiA_awaddr => axiA_awaddr, + axiA_awlen => axiA_awlen, + axiA_awsize => axiA_awsize, + axiA_awburst => axiA_awburst, + axiA_awlock => axiA_awlock, + axiA_awcache => axiA_awcache, + axiA_awprot => axiA_awprot, + axiA_awqos => axiA_awqos, + axiA_awregion => axiA_awregion, + axiA_awvalid => axiA_awvalid, + axiA_awready => axiA_awready, + axiA_wdata => axiA_wdata, + axiA_wstrb => axiA_wstrb, + axiA_wvalid => axiA_wvalid, + axiA_wlast => axiA_wlast, + axiA_wready => axiA_wready, + axiA_bresp => axiA_bresp, + axiA_bvalid => axiA_bvalid, + axiA_bready => axiA_bready, + axiA_araddr => axiA_araddr, + axiA_arlen => axiA_arlen, + axiA_arsize => axiA_arsize, + axiA_arburst => axiA_arburst, + axiA_arlock => axiA_arlock, + axiA_arcache => axiA_arcache, + axiA_arprot => axiA_arprot, + axiA_arqos => axiA_arqos, + axiA_arregion => axiA_arregion, + axiA_arvalid => axiA_arvalid, + axiA_arready => axiA_arready, + axiA_rdata => axiA_rdata, + axiA_rresp => axiA_rresp, + axiA_rlast => axiA_rlast, + axiA_rvalid => axiA_rvalid, + axiA_rready => axiA_rready, + userInterruptA => userInterruptA, + userInterruptB => userInterruptB, + userInterruptC => userInterruptC, + userInterruptD => userInterruptD, + userInterruptE => userInterruptE, + userInterruptF => userInterruptF, + io_apbSlave_0_PADDR => io_apbSlave_0_PADDR, + io_apbSlave_0_PENABLE => io_apbSlave_0_PENABLE, + io_apbSlave_0_PRDATA => io_apbSlave_0_PRDATA, + io_apbSlave_0_PREADY => io_apbSlave_0_PREADY, + io_apbSlave_0_PSEL => io_apbSlave_0_PSEL, + io_apbSlave_0_PSLVERROR => io_apbSlave_0_PSLVERROR, + io_apbSlave_0_PWDATA => io_apbSlave_0_PWDATA, + io_apbSlave_0_PWRITE => io_apbSlave_0_PWRITE, + system_i2c_0_io_sda_write => system_i2c_0_io_sda_write, + system_i2c_0_io_sda_writeEnable => system_i2c_0_io_sda_writeEnable, + system_i2c_0_io_scl_writeEnable => system_i2c_0_io_scl_writeEnable, + system_watchdog_hardPanic_reset => system_watchdog_hardPanic_reset +); + +------------------------ End INSTANTIATION Template --------- diff --git a/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_wrapper.v b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_wrapper.v new file mode 100644 index 0000000..cc9ad4b --- /dev/null +++ b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/EfxSapphireHpSoc_wrapper.v @@ -0,0 +1,402 @@ +module EfxSapphireHpSoc_wrapper ( +output system_uart_0_io_txd, +input system_uart_0_io_rxd, +input io_cfuClk, +input io_cfuReset, +output userInterruptC, +input [3:0] system_gpio_0_io_read, +output [3:0] system_gpio_0_io_write, +output [3:0] system_gpio_0_io_writeEnable, +input cpu1_customInstruction_cmd_valid, +output cpu1_customInstruction_cmd_ready, +input [9:0] cpu1_customInstruction_function_id, +input [31:0] cpu1_customInstruction_inputs_0, +input [31:0] cpu1_customInstruction_inputs_1, +output cpu1_customInstruction_rsp_valid, +input cpu1_customInstruction_rsp_ready, +output [31:0] cpu1_customInstruction_outputs_0, +output system_watchdog_hardPanic_reset, +output jtagCtrl_tdi, +input jtagCtrl_tdo, +output jtagCtrl_enable, +output jtagCtrl_capture, +output jtagCtrl_shift, +output jtagCtrl_update, +output jtagCtrl_reset, +input ut_jtagCtrl_tdi, +output ut_jtagCtrl_tdo, +input ut_jtagCtrl_enable, +input ut_jtagCtrl_capture, +input ut_jtagCtrl_shift, +input ut_jtagCtrl_update, +input ut_jtagCtrl_reset, +output system_i2c_0_io_sda_writeEnable, +output system_i2c_0_io_sda_write, +input system_i2c_0_io_sda_read, +output system_i2c_0_io_scl_writeEnable, +output system_i2c_0_io_scl_write, +input system_i2c_0_io_scl_read, +output userInterruptD, +input cpu0_customInstruction_cmd_valid, +output cpu0_customInstruction_cmd_ready, +input [9:0] cpu0_customInstruction_function_id, +input [31:0] cpu0_customInstruction_inputs_0, +input [31:0] cpu0_customInstruction_inputs_1, +output cpu0_customInstruction_rsp_valid, +input cpu0_customInstruction_rsp_ready, +output [31:0] cpu0_customInstruction_outputs_0, +output system_spi_0_io_sclk_write, +output system_spi_0_io_data_0_writeEnable, +input system_spi_0_io_data_0_read, +output system_spi_0_io_data_0_write, +output system_spi_0_io_data_1_writeEnable, +input system_spi_0_io_data_1_read, +output system_spi_0_io_data_1_write, +output system_spi_0_io_data_2_writeEnable, +input system_spi_0_io_data_2_read, +output system_spi_0_io_data_2_write, +output system_spi_0_io_data_3_writeEnable, +input system_spi_0_io_data_3_read, +output system_spi_0_io_data_3_write, +output [3:0] system_spi_0_io_ss, +output userInterruptF, +output userInterruptG, +output userInterruptE, +output userInterruptI, +output userInterruptH, +input cpu2_customInstruction_cmd_valid, +output cpu2_customInstruction_cmd_ready, +input [9:0] cpu2_customInstruction_function_id, +input [31:0] cpu2_customInstruction_inputs_0, +input [31:0] cpu2_customInstruction_inputs_1, +output cpu2_customInstruction_rsp_valid, +input cpu2_customInstruction_rsp_ready, +output [31:0] cpu2_customInstruction_outputs_0, +input cpu3_customInstruction_cmd_valid, +output cpu3_customInstruction_cmd_ready, +input [9:0] cpu3_customInstruction_function_id, +input [31:0] cpu3_customInstruction_inputs_0, +input [31:0] cpu3_customInstruction_inputs_1, +output cpu3_customInstruction_rsp_valid, +input cpu3_customInstruction_rsp_ready, +output [31:0] cpu3_customInstruction_outputs_0, +output userInterruptB, +output userInterruptA, +output io_ddrMasters_0_aw_valid, +input io_ddrMasters_0_aw_ready, +output [31:0] io_ddrMasters_0_aw_payload_addr, +output [3:0] io_ddrMasters_0_aw_payload_id, +output [3:0] io_ddrMasters_0_aw_payload_region, +output [7:0] io_ddrMasters_0_aw_payload_len, +output [2:0] io_ddrMasters_0_aw_payload_size, +output [1:0] io_ddrMasters_0_aw_payload_burst, +output io_ddrMasters_0_aw_payload_lock, +output [3:0] io_ddrMasters_0_aw_payload_cache, +output [3:0] io_ddrMasters_0_aw_payload_qos, +output [2:0] io_ddrMasters_0_aw_payload_prot, +output io_ddrMasters_0_aw_payload_allStrb, +output io_ddrMasters_0_w_valid, +input io_ddrMasters_0_w_ready, +output [127:0] io_ddrMasters_0_w_payload_data, +output [15:0] io_ddrMasters_0_w_payload_strb, +output io_ddrMasters_0_w_payload_last, +input io_ddrMasters_0_b_valid, +output io_ddrMasters_0_b_ready, +input [3:0] io_ddrMasters_0_b_payload_id, +input [1:0] io_ddrMasters_0_b_payload_resp, +output io_ddrMasters_0_ar_valid, +input io_ddrMasters_0_ar_ready, +output [31:0] io_ddrMasters_0_ar_payload_addr, +output [3:0] io_ddrMasters_0_ar_payload_id, +output [3:0] io_ddrMasters_0_ar_payload_region, +output [7:0] io_ddrMasters_0_ar_payload_len, +output [2:0] io_ddrMasters_0_ar_payload_size, +output [1:0] io_ddrMasters_0_ar_payload_burst, +output io_ddrMasters_0_ar_payload_lock, +output [3:0] io_ddrMasters_0_ar_payload_cache, +output [3:0] io_ddrMasters_0_ar_payload_qos, +output [2:0] io_ddrMasters_0_ar_payload_prot, +input io_ddrMasters_0_r_valid, +output io_ddrMasters_0_r_ready, +input [127:0] io_ddrMasters_0_r_payload_data, +input [3:0] io_ddrMasters_0_r_payload_id, +input [1:0] io_ddrMasters_0_r_payload_resp, +input io_ddrMasters_0_r_payload_last, +input io_ddrMasters_0_clk, +input io_ddrMasters_0_reset, +input [31:0] axiA_awaddr, +input [7:0] axiA_awlen, +input [2:0] axiA_awsize, +input [1:0] axiA_awburst, +input axiA_awlock, +input [3:0] axiA_awcache, +input [2:0] axiA_awprot, +input [3:0] axiA_awqos, +input [3:0] axiA_awregion, +input axiA_awvalid, +output axiA_awready, +input [31:0] axiA_wdata, +input [3:0] axiA_wstrb, +input axiA_wvalid, +input axiA_wlast, +output axiA_wready, +output [1:0] axiA_bresp, +output axiA_bvalid, +input axiA_bready, +input [31:0] axiA_araddr, +input [7:0] axiA_arlen, +input [2:0] axiA_arsize, +input [1:0] axiA_arburst, +input axiA_arlock, +input [3:0] axiA_arcache, +input [2:0] axiA_arprot, +input [3:0] axiA_arqos, +input [3:0] axiA_arregion, +input axiA_arvalid, +output axiA_arready, +output [31:0] axiA_rdata, +output [1:0] axiA_rresp, +output axiA_rlast, +output axiA_rvalid, +input axiA_rready, +output axiAInterrupt, +input cfg_done, +output cfg_start, +output cfg_sel, +output cfg_reset, +input io_peripheralClk, +input io_peripheralReset, +output io_asyncReset, +input io_gpio_sw_n, +input pll_peripheral_locked, +input pll_system_locked +); + +wire [15:0] io_apbSlave_0_PADDR; +wire io_apbSlave_0_PSEL; +wire io_apbSlave_0_PENABLE; +wire io_apbSlave_0_PREADY; +wire io_apbSlave_0_PWRITE; +wire [31:0] io_apbSlave_0_PWDATA; +wire [31:0] io_apbSlave_0_PRDATA; +wire io_apbSlave_0_PSLVERROR; + + +assign userInterruptG = 1'b0; //USER TO MODIFY +assign userInterruptH = 1'b0; //USER TO MODIFY +assign userInterruptI = 1'b0; //USER TO MODIFY + +/**/ +/* INFO: USER TO MODIFY CODES BELOW */ +/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */ +/**/ +assign io_apbSlave_0_PREADY = 1'b1; +assign io_apbSlave_0_PRDATA = 32'd0; +//io_apbSlave_0_PADDR; +//io_apbSlave_0_PSEL; +//io_apbSlave_0_PENABLE; +//io_apbSlave_0_PWRITE; +//io_apbSlave_0_PWDATA; +//io_apbSlave_0_PSLVERROR; +/**/ +/* INFO: USER TO MODIFY CODES BELOW */ +/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */ +/**/ +assign cpu1_customInstruction_cmd_ready = 1'b1; +assign cpu1_customInstruction_rsp_valid = 1'b0; +assign cpu1_customInstruction_outputs_0 = 32'd0; +//io_cfuClk +//io_cfyReset +//cpu1_customInstruction_rsp_ready +//cpu1_customInstruction_cmd_valid +//cpu1_customInstruction_function_id +//cpu1_customInstruction_inputs_0 +//cpu1_customInstruction_inputs_1 + +/**/ +/* INFO: USER TO MODIFY CODES BELOW */ +/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */ +/**/ +assign cpu3_customInstruction_cmd_ready = 1'b1; +assign cpu3_customInstruction_rsp_valid = 1'b0; +assign cpu3_customInstruction_outputs_0 = 32'd0; +//io_cfuClk +//io_cfyReset +//cpu3_customInstruction_rsp_ready +//cpu3_customInstruction_cmd_valid +//cpu3_customInstruction_function_id +//cpu3_customInstruction_inputs_0 +//cpu3_customInstruction_inputs_1 + +/**/ +/* INFO: USER TO MODIFY CODES BELOW */ +/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */ +/**/ +assign io_ddrMasters_0_aw_payload_addr = 32'd0; +assign io_ddrMasters_0_aw_payload_id = 4'd0; +assign io_ddrMasters_0_aw_payload_region = 4'd0; +assign io_ddrMasters_0_aw_payload_len = 8'd0; +assign io_ddrMasters_0_aw_payload_size = 3'd0; +assign io_ddrMasters_0_aw_payload_burst = 2'd0; +assign io_ddrMasters_0_aw_payload_lock = 1'b0; +assign io_ddrMasters_0_aw_payload_cache = 4'd0; +assign io_ddrMasters_0_aw_payload_qos = 4'd0; +assign io_ddrMasters_0_aw_payload_prot = 3'd0; +assign io_ddrMasters_0_aw_payload_allStrb = 1'b0; +assign io_ddrMasters_0_w_valid = 1'b0; +//io_ddrMasters_0_w_ready +assign io_ddrMasters_0_w_payload_data = 128'd0; +assign io_ddrMasters_0_w_payload_strb = 16'd0; +assign io_ddrMasters_0_w_payload_last = 1'b0; +//io_ddrMasters_0_b_valid +assign io_ddrMasters_0_b_ready = 1'b1; +//io_ddrMasters_0_b_payload_id +//io_ddrMasters_0_b_payload_resp +assign io_ddrMasters_0_ar_valid = 1'b0; +//io_ddrMasters_0_ar_ready +assign io_ddrMasters_0_ar_payload_addr = 32'd0; +assign io_ddrMasters_0_ar_payload_id = 4'd0; +assign io_ddrMasters_0_ar_payload_region = 4'd0; +assign io_ddrMasters_0_ar_payload_len = 8'd0; +assign io_ddrMasters_0_ar_payload_size = 3'd0; +assign io_ddrMasters_0_ar_payload_burst = 2'd0; +assign io_ddrMasters_0_ar_payload_lock = 1'b0; +assign io_ddrMasters_0_ar_payload_cache = 4'd0; +assign io_ddrMasters_0_ar_payload_qos = 4'd0; +assign io_ddrMasters_0_ar_payload_pro = 3'd0; +//io_ddrMasters_0_r_valid +assign io_ddrMasters_0_r_ready = 1'b1; +//io_ddrMasters_0_r_payload_data +//io_ddrMasters_0_r_payload_id +//io_ddrMasters_0_r_payload_resp +//io_ddrMasters_0_r_payload_last + +/**/ +/* INFO: USER TO MODIFY CODES BELOW */ +/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */ +/**/ +assign cpu0_customInstruction_cmd_ready = 1'b1; +assign cpu0_customInstruction_rsp_valid = 1'b0; +assign cpu0_customInstruction_outputs_0 = 32'd0; +//io_cfuClk +//io_cfyReset +//cpu0_customInstruction_rsp_ready +//cpu0_customInstruction_cmd_valid +//cpu0_customInstruction_function_id +//cpu0_customInstruction_inputs_0 +//cpu0_customInstruction_inputs_1 + +/**/ +/* INFO: USER TO MODIFY CODES BELOW */ +/* INFO: REFER EXAMPLE DESIGN FOR IMPLEMENTATION DETAILS */ +/**/ +assign cpu2_customInstruction_cmd_ready = 1'b1; +assign cpu2_customInstruction_rsp_valid = 1'b0; +assign cpu2_customInstruction_outputs_0 = 32'd0; +//io_cfuClk +//io_cfyReset +//cpu2_customInstruction_rsp_ready +//cpu2_customInstruction_cmd_valid +//cpu2_customInstruction_function_id +//cpu2_customInstruction_inputs_0 +//cpu2_customInstruction_inputs_1 + + + +//axi4 bridge to various I/O +EfxSapphireHpSoc_slb u_top_peripherals( +.userInterruptA(userInterruptA), +.jtagCtrl_tdi(jtagCtrl_tdi), +.jtagCtrl_tdo(jtagCtrl_tdo), +.jtagCtrl_enable(jtagCtrl_enable), +.jtagCtrl_capture(jtagCtrl_capture), +.jtagCtrl_shift(jtagCtrl_shift), +.jtagCtrl_update(jtagCtrl_update), +.jtagCtrl_reset(jtagCtrl_reset), +.ut_jtagCtrl_tdi(ut_jtagCtrl_tdi), +.ut_jtagCtrl_tdo(ut_jtagCtrl_tdo), +.ut_jtagCtrl_enable(ut_jtagCtrl_enable), +.ut_jtagCtrl_capture(ut_jtagCtrl_capture), +.ut_jtagCtrl_shift(ut_jtagCtrl_shift), +.ut_jtagCtrl_update(ut_jtagCtrl_update), +.ut_jtagCtrl_reset(ut_jtagCtrl_reset), +.userInterruptE(userInterruptE), +.userInterruptF(userInterruptF), +.userInterruptB(userInterruptB), +.io_apbSlave_0_PADDR(io_apbSlave_0_PADDR), +.io_apbSlave_0_PSEL(io_apbSlave_0_PSEL), +.io_apbSlave_0_PENABLE(io_apbSlave_0_PENABLE), +.io_apbSlave_0_PREADY(io_apbSlave_0_PREADY), +.io_apbSlave_0_PWRITE(io_apbSlave_0_PWRITE), +.io_apbSlave_0_PWDATA(io_apbSlave_0_PWDATA), +.io_apbSlave_0_PRDATA(io_apbSlave_0_PRDATA), +.io_apbSlave_0_PSLVERROR(io_apbSlave_0_PSLVERROR), +.system_watchdog_hardPanic_reset(system_watchdog_hardPanic_reset), +.system_spi_0_io_sclk_write(system_spi_0_io_sclk_write), +.system_spi_0_io_data_0_writeEnable(system_spi_0_io_data_0_writeEnable), +.system_spi_0_io_data_0_read(system_spi_0_io_data_0_read), +.system_spi_0_io_data_0_write(system_spi_0_io_data_0_write), +.system_spi_0_io_data_1_writeEnable(system_spi_0_io_data_1_writeEnable), +.system_spi_0_io_data_1_read(system_spi_0_io_data_1_read), +.system_spi_0_io_data_1_write(system_spi_0_io_data_1_write), +.system_spi_0_io_data_2_writeEnable(system_spi_0_io_data_2_writeEnable), +.system_spi_0_io_data_2_read(system_spi_0_io_data_2_read), +.system_spi_0_io_data_2_write(system_spi_0_io_data_2_write), +.system_spi_0_io_data_3_writeEnable(system_spi_0_io_data_3_writeEnable), +.system_spi_0_io_data_3_read(system_spi_0_io_data_3_read), +.system_spi_0_io_data_3_write(system_spi_0_io_data_3_write), +.system_spi_0_io_ss(system_spi_0_io_ss), +.system_uart_0_io_txd(system_uart_0_io_txd), +.system_uart_0_io_rxd(system_uart_0_io_rxd), +.userInterruptC(userInterruptC), +.system_gpio_0_io_read(system_gpio_0_io_read), +.system_gpio_0_io_write(system_gpio_0_io_write), +.system_gpio_0_io_writeEnable(system_gpio_0_io_writeEnable), +.userInterruptD(userInterruptD), +.system_i2c_0_io_sda_writeEnable(system_i2c_0_io_sda_writeEnable), +.system_i2c_0_io_sda_write(system_i2c_0_io_sda_write), +.system_i2c_0_io_sda_read(system_i2c_0_io_sda_read), +.system_i2c_0_io_scl_writeEnable(system_i2c_0_io_scl_writeEnable), +.system_i2c_0_io_scl_write(system_i2c_0_io_scl_write), +.system_i2c_0_io_scl_read(system_i2c_0_io_scl_read), +.axiA_awvalid(axiA_awvalid), +.axiA_awready(axiA_awready), +.axiA_awaddr(axiA_awaddr), +.axiA_awlen(axiA_awlen), +.axiA_awsize(axiA_awsize), +.axiA_awcache(axiA_awcache), +.axiA_awprot(axiA_awprot), +.axiA_wvalid(axiA_wvalid), +.axiA_wready(axiA_wready), +.axiA_wdata(axiA_wdata), +.axiA_wstrb(axiA_wstrb), +.axiA_wlast(axiA_wlast), +.axiA_bvalid(axiA_bvalid), +.axiA_bready(axiA_bready), +.axiA_bresp(axiA_bresp), +.axiA_arvalid(axiA_arvalid), +.axiA_arready(axiA_arready), +.axiA_araddr(axiA_araddr), +.axiA_arlen(axiA_arlen), +.axiA_arsize(axiA_arsize), +.axiA_arcache(axiA_arcache), +.axiA_arprot(axiA_arprot), +.axiA_rvalid(axiA_rvalid), +.axiA_rready(axiA_rready), +.axiA_rdata(axiA_rdata), +.axiA_rresp(axiA_rresp), +.axiA_rlast(axiA_rlast), +.axiAInterrupt(axiAInterrupt), +.cfg_done(cfg_done), +.cfg_start(cfg_start), +.cfg_sel(cfg_sel), +.cfg_reset(cfg_reset), +.io_peripheralClk(io_peripheralClk), +.io_peripheralReset(io_peripheralReset), +.io_asyncReset(io_asyncReset), +.io_gpio_sw_n(io_gpio_sw_n), +.pll_peripheral_locked(pll_peripheral_locked), +.pll_system_locked(pll_system_locked) +); + +endmodule diff --git a/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/hard_ip_args.ini b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/hard_ip_args.ini new file mode 100644 index 0000000..5536035 --- /dev/null +++ b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/hard_ip_args.ini @@ -0,0 +1,224 @@ +[parameters] +pll_soc_sys_clk_name = soc_pll_sys_clk +hidden_min_freq = 0 +pll_soc_sys_clk_ref_freq_hidden = 100 +pll_soc_sys_clk_ref_freq = 100 +pll_soc_sys_clkout1_freq = 1000 +pll_soc_sys_clkout1_phase = 0 +pll_soc_sys_clkout2_freq = 250 +pll_soc_sys_clkout2_phase = 0 +pll_soc_mem_clk_name = soc_pll_peri_clk +pll_soc_mem_clk_ref_freq = 25 +pll_soc_mem_clkout1_freq = 250 +pll_soc_mem_clkout1_phase = 0 +pll_soc_mem_clkout2_freq = 250 +pll_soc_mem_clkout2_phase = 0 +pll_lpddr4_name = soc_ddr_pll +pll_lpddr4_ref_freq = 25 +pll_lpddr4_clkout0_freq = 100 +pll_lpddr4_clkout0_phase = 0 +pll_lpddr4_clkout3_freq = 533 +pll_lpddr4_clkout3_phase = 0 +ddr_data_width = 32 +ddr_memory_density = 8G +ddr_memory_type = LPDDR4x +ddr_physical_rank = 1 +ddr_pin_name = soc_ddr_inst1 +gpio_bus_name = system_gpio_0 +hard_jtag_inst_name = soc_jtag_inst1 +uart0_gpio_inst_name = system_uart_0 +spi0_gpio_inst_name = system_spi_0 +i2c0_gpio_inst_name = system_i2c_0 +jtag_gpio_inst_name = io_jtag +soc_pin_name = qcrv32_inst1 +intf_axim = 1 +intf_ci_0 = 1 +intf_ci_1 = 1 +intf_ci_2 = 1 +intf_ci_3 = 1 +co_debug = 0 +intf_jtag_type = 0 +intf_uintr = 9 +peri_spi_0 = 1 +peri_spi_1 = 0 +peri_spi_2 = 0 +peri_i2c_0 = 1 +peri_i2c_1 = 0 +peri_i2c_2 = 0 +peri_gpio_0 = 1 +peri_gpio_1 = 0 +peri_wdt_0 = 1 +peri_apb_0 = 1 +peri_apb_1 = 0 +peri_apb_2 = 0 +peri_apb_3 = 0 +peri_apb_4 = 0 +peri_gen = 1 +peri_uart_0 = 1 +peri_uart_1 = 0 +peri_uart_2 = 0 +peri_gpio_0_width = 4 +peri_gpio_1_width = 4 +peri_apb_0_size = 65536 +peri_apb_1_size = 4096 +peri_apb_2_size = 4096 +peri_apb_3_size = 4096 +peri_apb_4_size = 4096 +peri_freq = 200 +app_overwrite = 0 +app_overwrite_path = +peri_count = 6 +peri_tcount = 6 +intf_jtag_tap_sel = 8 +intf_axis = 1 +peri_pin_assign = 1 +pll_soc_mem_resource = PLL_TR0 +sys_freq = 1000 +sys_freq_hidden = 1000 +pll_soc_sys_clkout3_freq = 250 +pll_soc_sys_clkout3_phase = 0 +pll_soc_mem_clkout3_freq = 250 +pll_soc_mem_clkout3_phase = 0 +pll_soc_mem_clkout4_freq = 200 +pll_soc_mem_clkout4_phase = 0 +pll_soc_sys_resource = PLL_BL0 +pll_lpddr4_resource = PLL_BL2 +pll_res_assign = 0 +pll_soc_sys_clkout0_freq = 100 +pll_soc_sys_clkout0_phase = 0 +pll_soc_mem_clkout0_freq = 100 +pll_soc_mem_clkout0_phase = 0 +pll_lpddr4_clkout1_freq = 33 +pll_lpddr4_clkout1_phase = 0 +mem_freq = 250 +axim_freq = 250 +cfu_freq = 125 +ddr_freq = 800 +pll_res_assign_2 = 0 +ddr_res_assign = 0 +peri_res_assign = 0 +pll_soc_sys_ext_clk_src = 1 +pll_soc_mem_ext_clk_src = 0 +peri_sdhc = 0 +peri_tsemac = 0 +sw_ftdi_ch_num = 6011 +sw_app_size = 2044 +sw_app_size_custom = 0 +sw_stack_size = 8 +sw_stack_size_custom = 0 +sw_board = Ti375C529 Development Kit +sw_board_custom = +sw_ftdi_target_ch = 1 +sw_ftdi_ch_num_soft = 6011 +sw_ftdi_target_ch_soft = 0 +sw_frtos_app_size = 16380 +sw_frtos_app_size_custom = 0 +sw_frtos_stack_size = 4 +sw_frtos_stack_size_custom = 0 +package_type = 529 +family_type = TITANIUM +axi_pipeline = 0 +axi_write_buffer = 0 + +[ports] +io_peripheralclk = io_peripheralClk +io_peripheralreset = io_peripheralReset +io_asyncreset = io_asyncReset +io_gpio_sw_n = io_gpio_sw_n +pll_peripheral_locked = pll_peripheral_locked +pll_system_locked = pll_system_locked +jtagctrl_capture = jtagCtrl_capture +jtagctrl_enable = jtagCtrl_enable +jtagctrl_reset = jtagCtrl_reset +jtagctrl_shift = jtagCtrl_shift +jtagctrl_tdi = jtagCtrl_tdi +jtagctrl_tdo = jtagCtrl_tdo +jtagctrl_update = jtagCtrl_update +ut_jtagctrl_capture = ut_jtagCtrl_capture +ut_jtagctrl_enable = ut_jtagCtrl_enable +ut_jtagctrl_reset = ut_jtagCtrl_reset +ut_jtagctrl_shift = ut_jtagCtrl_shift +ut_jtagctrl_tdi = ut_jtagCtrl_tdi +ut_jtagctrl_tdo = ut_jtagCtrl_tdo +ut_jtagctrl_update = ut_jtagCtrl_update +system_spi_0_io_data_0_read = system_spi_0_io_data_0_read +system_spi_0_io_data_0_write = system_spi_0_io_data_0_write +system_spi_0_io_data_0_writeenable = system_spi_0_io_data_0_writeEnable +system_spi_0_io_data_1_read = system_spi_0_io_data_1_read +system_spi_0_io_data_1_write = system_spi_0_io_data_1_write +system_spi_0_io_data_1_writeenable = system_spi_0_io_data_1_writeEnable +system_spi_0_io_data_2_read = system_spi_0_io_data_2_read +system_spi_0_io_data_2_write = system_spi_0_io_data_2_write +system_spi_0_io_data_2_writeenable = system_spi_0_io_data_2_writeEnable +system_spi_0_io_data_3_read = system_spi_0_io_data_3_read +system_spi_0_io_data_3_write = system_spi_0_io_data_3_write +system_spi_0_io_data_3_writeenable = system_spi_0_io_data_3_writeEnable +system_spi_0_io_sclk_write = system_spi_0_io_sclk_write +system_spi_0_io_ss = system_spi_0_io_ss +system_uart_0_io_rxd = system_uart_0_io_rxd +system_uart_0_io_txd = system_uart_0_io_txd +system_i2c_0_io_scl_read = system_i2c_0_io_scl_read +system_i2c_0_io_scl_write = system_i2c_0_io_scl_write +system_i2c_0_io_sda_read = system_i2c_0_io_sda_read +system_gpio_0_io_read = system_gpio_0_io_read +system_gpio_0_io_write = system_gpio_0_io_write +system_gpio_0_io_writeenable = system_gpio_0_io_writeEnable +cfg_done = cfg_done +cfg_start = cfg_start +cfg_sel = cfg_sel +cfg_reset = cfg_reset +axiainterrupt = axiAInterrupt +axia_awaddr = axiA_awaddr +axia_awlen = axiA_awlen +axia_awsize = axiA_awsize +axia_awburst = axiA_awburst +axia_awlock = axiA_awlock +axia_awcache = axiA_awcache +axia_awprot = axiA_awprot +axia_awqos = axiA_awqos +axia_awregion = axiA_awregion +axia_awvalid = axiA_awvalid +axia_awready = axiA_awready +axia_wdata = axiA_wdata +axia_wstrb = axiA_wstrb +axia_wvalid = axiA_wvalid +axia_wlast = axiA_wlast +axia_wready = axiA_wready +axia_bresp = axiA_bresp +axia_bvalid = axiA_bvalid +axia_bready = axiA_bready +axia_araddr = axiA_araddr +axia_arlen = axiA_arlen +axia_arsize = axiA_arsize +axia_arburst = axiA_arburst +axia_arlock = axiA_arlock +axia_arcache = axiA_arcache +axia_arprot = axiA_arprot +axia_arqos = axiA_arqos +axia_arregion = axiA_arregion +axia_arvalid = axiA_arvalid +axia_arready = axiA_arready +axia_rdata = axiA_rdata +axia_rresp = axiA_rresp +axia_rlast = axiA_rlast +axia_rvalid = axiA_rvalid +axia_rready = axiA_rready +userinterrupta = userInterruptA +userinterruptb = userInterruptB +userinterruptc = userInterruptC +userinterruptd = userInterruptD +userinterrupte = userInterruptE +userinterruptf = userInterruptF +io_apbslave_0_paddr = io_apbSlave_0_PADDR +io_apbslave_0_penable = io_apbSlave_0_PENABLE +io_apbslave_0_prdata = io_apbSlave_0_PRDATA +io_apbslave_0_pready = io_apbSlave_0_PREADY +io_apbslave_0_psel = io_apbSlave_0_PSEL +io_apbslave_0_pslverror = io_apbSlave_0_PSLVERROR +io_apbslave_0_pwdata = io_apbSlave_0_PWDATA +io_apbslave_0_pwrite = io_apbSlave_0_PWRITE +system_i2c_0_io_sda_write = system_i2c_0_io_sda_write +system_i2c_0_io_sda_writeenable = system_i2c_0_io_sda_writeEnable +system_i2c_0_io_scl_writeenable = system_i2c_0_io_scl_writeEnable +system_watchdog_hardpanic_reset = system_watchdog_hardPanic_reset + diff --git a/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/ipm/component.pickle b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/ipm/component.pickle new file mode 100644 index 0000000..608aebf Binary files /dev/null and b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/ipm/component.pickle differ diff --git a/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/ipm/graph.pickle b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/ipm/graph.pickle new file mode 100644 index 0000000..4f76955 Binary files /dev/null and b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/ipm/graph.pickle differ diff --git a/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/ipm_pt_map.json b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/ipm_pt_map.json new file mode 100644 index 0000000..45a8436 --- /dev/null +++ b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/ipm_pt_map.json @@ -0,0 +1,20 @@ +{ + "PLL": {}, + "GPIO": { + "UART": [], + "SPI": [], + "I2C": [], + "JTAG": [], + "GPIO": [] + }, + "SOC": { + "SOC_PIN_NAME": { + "SOC_PIN_NAME": "qcrv32_inst1" + } + }, + "JTAG": { + "HARD_JTAG_INST_NAME": { + "HARD_JTAG_INST_NAME": "soc_jtag_inst1" + } + } +} \ No newline at end of file diff --git a/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/settings.json b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/settings.json new file mode 100644 index 0000000..84b6da3 --- /dev/null +++ b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/settings.json @@ -0,0 +1,134 @@ +{ + "args": [ + "-o", + "EfxSapphireHpSoc_slb", + "--base_path", + "ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "soc", + "name": "efx_hard_soc", + "version": "1.23.0" + } + ], + "conf": { + "PLL_SOC_SYS_CLK_NAME": "\"soc_pll_sys_clk\"", + "PLL_SOC_SYS_CLK_REF_FREQ_HIDDEN": "\"100\"", + "PLL_SOC_SYS_CLK_REF_FREQ": "\"100\"", + "PLL_SOC_SYS_CLKOUT1_PHASE": "\"0\"", + "PLL_SOC_SYS_CLKOUT2_PHASE": "\"0\"", + "PLL_SOC_MEM_CLK_NAME": "\"soc_pll_peri_clk\"", + "PLL_SOC_MEM_CLK_REF_FREQ": "\"25\"", + "PLL_SOC_MEM_CLKOUT1_FREQ": "\"250\"", + "PLL_SOC_MEM_CLKOUT1_PHASE": "\"0\"", + "PLL_SOC_MEM_CLKOUT2_FREQ": "\"250\"", + "PLL_SOC_MEM_CLKOUT2_PHASE": "\"0\"", + "PLL_LPDDR4_NAME": "\"soc_ddr_pll\"", + "PLL_LPDDR4_REF_FREQ": "\"25\"", + "PLL_LPDDR4_CLKOUT0_FREQ": "\"100\"", + "PLL_LPDDR4_CLKOUT0_PHASE": "\"0\"", + "PLL_LPDDR4_CLKOUT3_FREQ": "\"533\"", + "PLL_LPDDR4_CLKOUT3_PHASE": "\"0\"", + "DDR_DATA_WIDTH": "32", + "DDR_MEMORY_DENSITY": "\"8G\"", + "DDR_MEMORY_TYPE": "\"LPDDR4x\"", + "DDR_PHYSICAL_RANK": "1", + "DDR_PIN_NAME": "\"soc_ddr_inst1\"", + "INTF_AXIM": "1'b1", + "INTF_CI_0": "1'b1", + "INTF_CI_1": "1'b1", + "INTF_CI_2": "1'b1", + "INTF_CI_3": "1'b1", + "CO_DEBUG": "1'b0", + "INTF_JTAG_TYPE": "0", + "INTF_UINTR": "9", + "PERI_SPI_0": "1'b1", + "PERI_SPI_1": "1'b0", + "PERI_SPI_2": "1'b0", + "PERI_I2C_0": "1'b1", + "PERI_I2C_1": "1'b0", + "PERI_I2C_2": "1'b0", + "PERI_GPIO_0": "1'b1", + "PERI_GPIO_1": "1'b0", + "PERI_WDT_0": "1'b1", + "PERI_APB_0": "1'b1", + "PERI_APB_1": "1'b0", + "PERI_APB_2": "1'b0", + "PERI_APB_3": "1'b0", + "PERI_APB_4": "1'b0", + "PERI_GEN": "1'b1", + "PERI_UART_0": "1'b1", + "PERI_UART_1": "1'b0", + "PERI_UART_2": "1'b0", + "PERI_GPIO_0_WIDTH": "4", + "PERI_GPIO_1_WIDTH": "4", + "PERI_APB_0_SIZE": "65536", + "PERI_APB_1_SIZE": "4096", + "PERI_APB_2_SIZE": "4096", + "PERI_APB_3_SIZE": "4096", + "PERI_APB_4_SIZE": "4096", + "PERI_FREQ": "200", + "APP_OVERWRITE": "1'b0", + "APP_OVERWRITE_PATH": "\"''\"", + "INTF_JTAG_TAP_SEL": "8", + "INTF_AXIS": "1'b1", + "PERI_PIN_ASSIGN": "1'b1", + "PLL_SOC_MEM_RESOURCE": "\"PLL_TR0\"", + "SYS_FREQ": "1000", + "SYS_FREQ_HIDDEN": "1000", + "PLL_SOC_SYS_CLKOUT3_FREQ": "\"250\"", + "PLL_SOC_SYS_CLKOUT3_PHASE": "\"0\"", + "PLL_SOC_MEM_CLKOUT3_FREQ": "\"250\"", + "PLL_SOC_MEM_CLKOUT3_PHASE": "\"0\"", + "PLL_SOC_MEM_CLKOUT4_PHASE": "\"0\"", + "PLL_SOC_SYS_RESOURCE": "\"PLL_BL0\"", + "PLL_LPDDR4_RESOURCE": "\"PLL_BL2\"", + "PLL_RES_ASSIGN": "1'b0", + "PLL_SOC_SYS_CLKOUT0_FREQ": "\"100\"", + "PLL_SOC_SYS_CLKOUT0_PHASE": "\"0\"", + "PLL_SOC_MEM_CLKOUT0_FREQ": "\"100\"", + "PLL_SOC_MEM_CLKOUT0_PHASE": "\"0\"", + "PLL_LPDDR4_CLKOUT1_FREQ": "\"33\"", + "PLL_LPDDR4_CLKOUT1_PHASE": "\"0\"", + "MEM_FREQ": "250", + "AXIM_FREQ": "250", + "CFU_FREQ": "125", + "DDR_FREQ": "800", + "PLL_RES_ASSIGN_2": "1'b0", + "DDR_RES_ASSIGN": "1'b0", + "PERI_RES_ASSIGN": "1'b0", + "PLL_SOC_SYS_EXT_CLK_SRC": "1", + "PLL_SOC_MEM_EXT_CLK_SRC": "0", + "PERI_SDHC": "1'b0", + "PERI_TSEMAC": "1'b0", + "SW_FTDI_CH_NUM": "6011", + "SW_APP_SIZE": "2044", + "SW_APP_SIZE_CUSTOM": "0", + "SW_STACK_SIZE": "8", + "SW_STACK_SIZE_CUSTOM": "0", + "SW_BOARD": "\"Ti375C529 Development Kit\"", + "SW_BOARD_CUSTOM": "\"\"", + "SW_FTDI_TARGET_CH": "1", + "SW_FTDI_CH_NUM_SOFT": "6011", + "SW_FTDI_TARGET_CH_SOFT": "0", + "SW_FRTOS_APP_SIZE": "16380", + "SW_FRTOS_APP_SIZE_CUSTOM": "0", + "SW_FRTOS_STACK_SIZE": "4", + "SW_FRTOS_STACK_SIZE_CUSTOM": "0", + "PACKAGE_TYPE": "\"529\"", + "FAMILY_TYPE": "\"TITANIUM\"", + "AXI_PIPELINE": "1'b0", + "AXI_WRITE_BUFFER": "1'b0" + }, + "output": { + "external_script_Peripheral_Generator": [], + "external_source_source": [], + "external_script_PT_Configuration": [], + "external_script_Peripheral_Post_Script": [], + "external_script_Embedded_SW": [] + }, + "ooc_synthesis": {}, + "sw_version": "2026.1.132", + "external_path_option": "RELATIVE_PATH" +} \ No newline at end of file diff --git a/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/source/Axi4PeripheralTop.v b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/source/Axi4PeripheralTop.v new file mode 100644 index 0000000..48546f3 --- /dev/null +++ b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/source/Axi4PeripheralTop.v @@ -0,0 +1,8069 @@ +// Generator : SpinalHDL dev git head : a69f4b9a329be784802c37cd8038b7dc9aec3094 +// Component : Axi4PeripheralTop + +`timescale 1ns/1ps + +module Axi4PeripheralTop ( + input wire axi_awvalid, + output wire axi_awready, + input wire [23:0] axi_awaddr, + input wire [7:0] axi_awlen, + input wire [2:0] axi_awsize, + input wire [3:0] axi_awcache, + input wire [2:0] axi_awprot, + input wire axi_wvalid, + output wire axi_wready, + input wire [31:0] axi_wdata, + input wire [3:0] axi_wstrb, + input wire axi_wlast, + output wire axi_bvalid, + input wire axi_bready, + output wire [1:0] axi_bresp, + input wire axi_arvalid, + output wire axi_arready, + input wire [23:0] axi_araddr, + input wire [7:0] axi_arlen, + input wire [2:0] axi_arsize, + input wire [3:0] axi_arcache, + input wire [2:0] axi_arprot, + output wire axi_rvalid, + input wire axi_rready, + output wire [31:0] axi_rdata, + output wire [1:0] axi_rresp, + output wire axi_rlast, + output wire system_uart_0_io_txd, + input wire system_uart_0_io_rxd, + output wire system_i2c_0_io_sda_write, + input wire system_i2c_0_io_sda_read, + output wire system_i2c_0_io_scl_write, + input wire system_i2c_0_io_scl_read, + input wire [3:0] system_gpio_0_io_read, + output wire [3:0] system_gpio_0_io_write, + output wire [3:0] system_gpio_0_io_writeEnable, + output wire [15:0] io_apbSlave_0_PADDR, + output wire [0:0] io_apbSlave_0_PSEL, + output wire io_apbSlave_0_PENABLE, + input wire io_apbSlave_0_PREADY, + output wire io_apbSlave_0_PWRITE, + output wire [31:0] io_apbSlave_0_PWDATA, + input wire [31:0] io_apbSlave_0_PRDATA, + input wire io_apbSlave_0_PSLVERROR, + output wire system_uart_0_io_interrupt, + output wire system_spi_0_io_interrupt, + output wire [0:0] system_spi_0_io_sclk_write, + output wire system_spi_0_io_data_0_writeEnable, + input wire [0:0] system_spi_0_io_data_0_read, + output wire [0:0] system_spi_0_io_data_0_write, + output wire system_spi_0_io_data_1_writeEnable, + input wire [0:0] system_spi_0_io_data_1_read, + output wire [0:0] system_spi_0_io_data_1_write, + output wire system_spi_0_io_data_2_writeEnable, + input wire [0:0] system_spi_0_io_data_2_read, + output wire [0:0] system_spi_0_io_data_2_write, + output wire system_spi_0_io_data_3_writeEnable, + input wire [0:0] system_spi_0_io_data_3_read, + output wire [0:0] system_spi_0_io_data_3_write, + output wire [3:0] system_spi_0_io_ss, + output wire system_i2c_0_io_interrupt, + output wire system_gpio_0_io_interrupts_0, + output wire system_gpio_0_io_interrupts_1, + output wire system_watchdog_logic_panics_0, + output wire system_watchdog_hardPanic_reset, + input wire clk, + input wire reset +); + + wire streamArbiter_io_inputs_0_ready; + wire streamArbiter_io_inputs_1_ready; + wire streamArbiter_io_output_valid; + wire [23:0] streamArbiter_io_output_payload_addr; + wire [7:0] streamArbiter_io_output_payload_len; + wire [2:0] streamArbiter_io_output_payload_size; + wire [3:0] streamArbiter_io_output_payload_cache; + wire [2:0] streamArbiter_io_output_payload_prot; + wire [0:0] streamArbiter_io_chosen; + wire [1:0] streamArbiter_io_chosenOH; + wire axiToBmb_io_axi_arw_ready; + wire axiToBmb_io_axi_w_ready; + wire axiToBmb_io_axi_b_valid; + wire [1:0] axiToBmb_io_axi_b_payload_resp; + wire axiToBmb_io_axi_r_valid; + wire [31:0] axiToBmb_io_axi_r_payload_data; + wire [1:0] axiToBmb_io_axi_r_payload_resp; + wire axiToBmb_io_axi_r_payload_last; + wire axiToBmb_io_bmb_cmd_valid; + wire axiToBmb_io_bmb_cmd_payload_last; + wire [0:0] axiToBmb_io_bmb_cmd_payload_fragment_source; + wire [0:0] axiToBmb_io_bmb_cmd_payload_fragment_opcode; + wire [23:0] axiToBmb_io_bmb_cmd_payload_fragment_address; + wire [9:0] axiToBmb_io_bmb_cmd_payload_fragment_length; + wire [31:0] axiToBmb_io_bmb_cmd_payload_fragment_data; + wire [3:0] axiToBmb_io_bmb_cmd_payload_fragment_mask; + wire axiToBmb_io_bmb_rsp_ready; + wire bmbHandle_decoder_io_input_cmd_ready; + wire bmbHandle_decoder_io_input_rsp_valid; + wire bmbHandle_decoder_io_input_rsp_payload_last; + wire [0:0] bmbHandle_decoder_io_input_rsp_payload_fragment_source; + wire [0:0] bmbHandle_decoder_io_input_rsp_payload_fragment_opcode; + wire [31:0] bmbHandle_decoder_io_input_rsp_payload_fragment_data; + wire bmbHandle_decoder_io_outputs_0_cmd_valid; + wire bmbHandle_decoder_io_outputs_0_cmd_payload_last; + wire [0:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_source; + wire [0:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_opcode; + wire [23:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_address; + wire [9:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_length; + wire [31:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_data; + wire [3:0] bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_mask; + wire bmbHandle_decoder_io_outputs_0_rsp_ready; + wire bmbHandle_unburstify_io_input_cmd_ready; + wire bmbHandle_unburstify_io_input_rsp_valid; + wire bmbHandle_unburstify_io_input_rsp_payload_last; + wire [0:0] bmbHandle_unburstify_io_input_rsp_payload_fragment_source; + wire [0:0] bmbHandle_unburstify_io_input_rsp_payload_fragment_opcode; + wire [31:0] bmbHandle_unburstify_io_input_rsp_payload_fragment_data; + wire bmbHandle_unburstify_io_output_cmd_valid; + wire bmbHandle_unburstify_io_output_cmd_payload_last; + wire [0:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_opcode; + wire [23:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_address; + wire [1:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_length; + wire [31:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_data; + wire [3:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_mask; + wire [2:0] bmbHandle_unburstify_io_output_cmd_payload_fragment_context; + wire bmbHandle_unburstify_io_output_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_input_cmd_ready; + wire bmbPeripheral_bmb_decoder_io_input_rsp_valid; + wire bmbPeripheral_bmb_decoder_io_input_rsp_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode; + wire [31:0] bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data; + wire [2:0] bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready; + wire bmbPeripheral_bmb_decoder_io_outputs_5_cmd_valid; + wire bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_decoder_io_outputs_5_rsp_ready; + wire system_uart_0_io_logic_io_bus_cmd_ready; + wire system_uart_0_io_logic_io_bus_rsp_valid; + wire system_uart_0_io_logic_io_bus_rsp_payload_last; + wire [0:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode; + wire [31:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_data; + wire [2:0] system_uart_0_io_logic_io_bus_rsp_payload_fragment_context; + wire system_uart_0_io_logic_io_uart_txd; + wire system_uart_0_io_logic_system_uart_0_io_interrupt_source; + wire system_spi_0_io_logic_io_ctrl_cmd_ready; + wire system_spi_0_io_logic_io_ctrl_rsp_valid; + wire system_spi_0_io_logic_io_ctrl_rsp_payload_last; + wire [0:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; + wire [31:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data; + wire [2:0] system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context; + wire [0:0] system_spi_0_io_logic_io_spi_sclk_write; + wire [3:0] system_spi_0_io_logic_io_spi_ss; + wire [0:0] system_spi_0_io_logic_io_spi_data_0_write; + wire system_spi_0_io_logic_io_spi_data_0_writeEnable; + wire [0:0] system_spi_0_io_logic_io_spi_data_1_write; + wire system_spi_0_io_logic_io_spi_data_1_writeEnable; + wire [0:0] system_spi_0_io_logic_io_spi_data_2_write; + wire system_spi_0_io_logic_io_spi_data_2_writeEnable; + wire [0:0] system_spi_0_io_logic_io_spi_data_3_write; + wire system_spi_0_io_logic_io_spi_data_3_writeEnable; + wire system_spi_0_io_logic_system_spi_0_io_interrupt_source; + wire system_i2c_0_io_logic_io_ctrl_cmd_ready; + wire system_i2c_0_io_logic_io_ctrl_rsp_valid; + wire system_i2c_0_io_logic_io_ctrl_rsp_payload_last; + wire [0:0] system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; + wire [31:0] system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_data; + wire [2:0] system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_context; + wire system_i2c_0_io_logic_io_i2c_scl_write; + wire system_i2c_0_io_logic_io_i2c_sda_write; + wire system_i2c_0_io_logic_system_i2c_0_io_interrupt_source; + wire [3:0] system_gpio_0_io_logic_io_gpio_write; + wire [3:0] system_gpio_0_io_logic_io_gpio_writeEnable; + wire system_gpio_0_io_logic_io_bus_cmd_ready; + wire system_gpio_0_io_logic_io_bus_rsp_valid; + wire system_gpio_0_io_logic_io_bus_rsp_payload_last; + wire [0:0] system_gpio_0_io_logic_io_bus_rsp_payload_fragment_opcode; + wire [31:0] system_gpio_0_io_logic_io_bus_rsp_payload_fragment_data; + wire [2:0] system_gpio_0_io_logic_io_bus_rsp_payload_fragment_context; + wire [3:0] system_gpio_0_io_logic_io_interrupt; + wire system_watchdog_logic_logic_io_bus_cmd_ready; + wire system_watchdog_logic_logic_io_bus_rsp_valid; + wire system_watchdog_logic_logic_io_bus_rsp_payload_last; + wire [0:0] system_watchdog_logic_logic_io_bus_rsp_payload_fragment_opcode; + wire [31:0] system_watchdog_logic_logic_io_bus_rsp_payload_fragment_data; + wire [2:0] system_watchdog_logic_logic_io_bus_rsp_payload_fragment_context; + wire [1:0] system_watchdog_logic_logic_io_panics; + wire io_apbSlave_0_logic_io_input_cmd_ready; + wire io_apbSlave_0_logic_io_input_rsp_valid; + wire io_apbSlave_0_logic_io_input_rsp_payload_last; + wire [0:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode; + wire [31:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_data; + wire [2:0] io_apbSlave_0_logic_io_input_rsp_payload_fragment_context; + wire [15:0] io_apbSlave_0_logic_io_output_PADDR; + wire [0:0] io_apbSlave_0_logic_io_output_PSEL; + wire io_apbSlave_0_logic_io_output_PENABLE; + wire io_apbSlave_0_logic_io_output_PWRITE; + wire [31:0] io_apbSlave_0_logic_io_output_PWDATA; + wire _zz_axiShared_b_ready; + wire _zz_axiShared_r_ready; + wire axi_aw_halfPipe_valid; + wire axi_aw_halfPipe_ready; + wire [23:0] axi_aw_halfPipe_payload_addr; + wire [7:0] axi_aw_halfPipe_payload_len; + wire [2:0] axi_aw_halfPipe_payload_size; + wire [3:0] axi_aw_halfPipe_payload_cache; + wire [2:0] axi_aw_halfPipe_payload_prot; + reg axi_aw_rValid; + wire axi_aw_halfPipe_fire; + reg [23:0] axi_aw_rData_addr; + reg [7:0] axi_aw_rData_len; + reg [2:0] axi_aw_rData_size; + reg [3:0] axi_aw_rData_cache; + reg [2:0] axi_aw_rData_prot; + wire axi_w_halfPipe_valid; + wire axi_w_halfPipe_ready; + wire [31:0] axi_w_halfPipe_payload_data; + wire [3:0] axi_w_halfPipe_payload_strb; + wire axi_w_halfPipe_payload_last; + reg axi_w_rValid; + wire axi_w_halfPipe_fire; + reg [31:0] axi_w_rData_data; + reg [3:0] axi_w_rData_strb; + reg axi_w_rData_last; + wire _zz_axi_bvalid; + reg _zz_axi_bvalid_1; + reg [1:0] _zz_axi_bresp; + wire axi_ar_halfPipe_valid; + wire axi_ar_halfPipe_ready; + wire [23:0] axi_ar_halfPipe_payload_addr; + wire [7:0] axi_ar_halfPipe_payload_len; + wire [2:0] axi_ar_halfPipe_payload_size; + wire [3:0] axi_ar_halfPipe_payload_cache; + wire [2:0] axi_ar_halfPipe_payload_prot; + reg axi_ar_rValid; + wire axi_ar_halfPipe_fire; + reg [23:0] axi_ar_rData_addr; + reg [7:0] axi_ar_rData_len; + reg [2:0] axi_ar_rData_size; + reg [3:0] axi_ar_rData_cache; + reg [2:0] axi_ar_rData_prot; + wire _zz_axi_rvalid; + reg _zz_axi_rvalid_1; + reg [31:0] _zz_axi_rdata; + reg [1:0] _zz_axi_rresp; + reg _zz_axi_rlast; + wire axiShared_arw_valid; + wire axiShared_arw_ready; + wire [23:0] axiShared_arw_payload_addr; + wire [7:0] axiShared_arw_payload_len; + wire [2:0] axiShared_arw_payload_size; + wire [3:0] axiShared_arw_payload_cache; + wire [2:0] axiShared_arw_payload_prot; + wire axiShared_arw_payload_write; + wire axiShared_w_valid; + wire axiShared_w_ready; + wire [31:0] axiShared_w_payload_data; + wire [3:0] axiShared_w_payload_strb; + wire axiShared_w_payload_last; + wire axiShared_b_valid; + wire axiShared_b_ready; + wire [1:0] axiShared_b_payload_resp; + wire axiShared_r_valid; + wire axiShared_r_ready; + wire [31:0] axiShared_r_payload_data; + wire [1:0] axiShared_r_payload_resp; + wire axiShared_r_payload_last; + wire bmbPeripheral_bmb_cmd_valid; + wire bmbPeripheral_bmb_cmd_ready; + wire bmbPeripheral_bmb_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_rsp_valid; + wire bmbPeripheral_bmb_rsp_ready; + wire bmbPeripheral_bmb_rsp_payload_last; + wire [0:0] bmbPeripheral_bmb_rsp_payload_fragment_opcode; + wire [31:0] bmbPeripheral_bmb_rsp_payload_fragment_data; + wire [2:0] bmbPeripheral_bmb_rsp_payload_fragment_context; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [3:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + wire [2:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_gpio_0_io_interrupts_0_source; + wire system_gpio_0_io_interrupts_1_source; + wire system_gpio_0_io_interrupts_2; + wire system_gpio_0_io_interrupts_3; + wire system_watchdog_logic_panics_0_source; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire _zz_io_bus_rsp_ready; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last; + wire [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode; + wire [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address; + wire [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length; + wire [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data; + wire [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context; + reg system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + wire system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire; + reg system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + reg [0:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + reg [5:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + reg [1:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + reg [31:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + reg [2:0] system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + wire _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + reg _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + reg _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + reg [0:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + reg [31:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + reg [2:0] _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last; + wire [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode; + wire [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address; + wire [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length; + wire [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data; + wire [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context; + reg system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + wire system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire; + reg system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + reg [0:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + reg [11:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + reg [1:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + reg [31:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + reg [2:0] system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [7:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last; + wire [0:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode; + wire [7:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address; + wire [1:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length; + wire [31:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data; + wire [2:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context; + reg system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + wire system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire; + reg system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + reg [0:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + reg [7:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + reg [1:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + reg [31:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + reg [2:0] system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [7:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [7:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + wire [0:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + wire [15:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + wire [1:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + wire [31:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + wire [2:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + wire io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + wire [0:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + wire [31:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + wire [2:0] io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + wire bmbPeripheral_bmb_withoutMask_cmd_valid; + wire bmbPeripheral_bmb_withoutMask_cmd_ready; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context; + wire bmbPeripheral_bmb_withoutMask_rsp_valid; + wire bmbPeripheral_bmb_withoutMask_rsp_ready; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context; + wire bmbPeripheral_bmb_withoutMask_cmd_valid_1; + wire bmbPeripheral_bmb_withoutMask_cmd_ready_1; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_1; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1; + wire bmbPeripheral_bmb_withoutMask_rsp_valid_1; + wire bmbPeripheral_bmb_withoutMask_rsp_ready_1; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_1; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1; + wire bmbPeripheral_bmb_withoutMask_cmd_valid_2; + wire bmbPeripheral_bmb_withoutMask_cmd_ready_2; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_2; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2; + wire bmbPeripheral_bmb_withoutMask_rsp_valid_2; + wire bmbPeripheral_bmb_withoutMask_rsp_ready_2; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_2; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2; + wire bmbPeripheral_bmb_withoutMask_cmd_valid_3; + wire bmbPeripheral_bmb_withoutMask_cmd_ready_3; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_3; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3; + wire bmbPeripheral_bmb_withoutMask_rsp_valid_3; + wire bmbPeripheral_bmb_withoutMask_rsp_ready_3; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_3; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3; + wire bmbPeripheral_bmb_withoutMask_cmd_valid_4; + wire bmbPeripheral_bmb_withoutMask_cmd_ready_4; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_4; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4; + wire bmbPeripheral_bmb_withoutMask_rsp_valid_4; + wire bmbPeripheral_bmb_withoutMask_rsp_ready_4; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_4; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4; + wire bmbPeripheral_bmb_withoutMask_cmd_valid_5; + wire bmbPeripheral_bmb_withoutMask_cmd_ready_5; + wire bmbPeripheral_bmb_withoutMask_cmd_payload_last_5; + wire [0:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_5; + wire [23:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_5; + wire [1:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_5; + wire [31:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_5; + wire [2:0] bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_5; + wire bmbPeripheral_bmb_withoutMask_rsp_valid_5; + wire bmbPeripheral_bmb_withoutMask_rsp_ready_5; + wire bmbPeripheral_bmb_withoutMask_rsp_payload_last_5; + wire [0:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_5; + wire [31:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_5; + wire [2:0] bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_5; + + Axi4PeripheralStreamArbiter streamArbiter ( + .io_inputs_0_valid (axi_ar_halfPipe_valid ), //i + .io_inputs_0_ready (streamArbiter_io_inputs_0_ready ), //o + .io_inputs_0_payload_addr (axi_ar_halfPipe_payload_addr[23:0] ), //i + .io_inputs_0_payload_len (axi_ar_halfPipe_payload_len[7:0] ), //i + .io_inputs_0_payload_size (axi_ar_halfPipe_payload_size[2:0] ), //i + .io_inputs_0_payload_cache (axi_ar_halfPipe_payload_cache[3:0] ), //i + .io_inputs_0_payload_prot (axi_ar_halfPipe_payload_prot[2:0] ), //i + .io_inputs_1_valid (axi_aw_halfPipe_valid ), //i + .io_inputs_1_ready (streamArbiter_io_inputs_1_ready ), //o + .io_inputs_1_payload_addr (axi_aw_halfPipe_payload_addr[23:0] ), //i + .io_inputs_1_payload_len (axi_aw_halfPipe_payload_len[7:0] ), //i + .io_inputs_1_payload_size (axi_aw_halfPipe_payload_size[2:0] ), //i + .io_inputs_1_payload_cache (axi_aw_halfPipe_payload_cache[3:0] ), //i + .io_inputs_1_payload_prot (axi_aw_halfPipe_payload_prot[2:0] ), //i + .io_output_valid (streamArbiter_io_output_valid ), //o + .io_output_ready (axiShared_arw_ready ), //i + .io_output_payload_addr (streamArbiter_io_output_payload_addr[23:0]), //o + .io_output_payload_len (streamArbiter_io_output_payload_len[7:0] ), //o + .io_output_payload_size (streamArbiter_io_output_payload_size[2:0] ), //o + .io_output_payload_cache (streamArbiter_io_output_payload_cache[3:0]), //o + .io_output_payload_prot (streamArbiter_io_output_payload_prot[2:0] ), //o + .io_chosen (streamArbiter_io_chosen ), //o + .io_chosenOH (streamArbiter_io_chosenOH[1:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralAxi4SharedToBmb axiToBmb ( + .io_axi_arw_valid (axiShared_arw_valid ), //i + .io_axi_arw_ready (axiToBmb_io_axi_arw_ready ), //o + .io_axi_arw_payload_addr (axiShared_arw_payload_addr[23:0] ), //i + .io_axi_arw_payload_len (axiShared_arw_payload_len[7:0] ), //i + .io_axi_arw_payload_size (axiShared_arw_payload_size[2:0] ), //i + .io_axi_arw_payload_cache (axiShared_arw_payload_cache[3:0] ), //i + .io_axi_arw_payload_prot (axiShared_arw_payload_prot[2:0] ), //i + .io_axi_arw_payload_write (axiShared_arw_payload_write ), //i + .io_axi_w_valid (axiShared_w_valid ), //i + .io_axi_w_ready (axiToBmb_io_axi_w_ready ), //o + .io_axi_w_payload_data (axiShared_w_payload_data[31:0] ), //i + .io_axi_w_payload_strb (axiShared_w_payload_strb[3:0] ), //i + .io_axi_w_payload_last (axiShared_w_payload_last ), //i + .io_axi_b_valid (axiToBmb_io_axi_b_valid ), //o + .io_axi_b_ready (axiShared_b_ready ), //i + .io_axi_b_payload_resp (axiToBmb_io_axi_b_payload_resp[1:0] ), //o + .io_axi_r_valid (axiToBmb_io_axi_r_valid ), //o + .io_axi_r_ready (axiShared_r_ready ), //i + .io_axi_r_payload_data (axiToBmb_io_axi_r_payload_data[31:0] ), //o + .io_axi_r_payload_resp (axiToBmb_io_axi_r_payload_resp[1:0] ), //o + .io_axi_r_payload_last (axiToBmb_io_axi_r_payload_last ), //o + .io_bmb_cmd_valid (axiToBmb_io_bmb_cmd_valid ), //o + .io_bmb_cmd_ready (bmbHandle_decoder_io_input_cmd_ready ), //i + .io_bmb_cmd_payload_last (axiToBmb_io_bmb_cmd_payload_last ), //o + .io_bmb_cmd_payload_fragment_source (axiToBmb_io_bmb_cmd_payload_fragment_source ), //o + .io_bmb_cmd_payload_fragment_opcode (axiToBmb_io_bmb_cmd_payload_fragment_opcode ), //o + .io_bmb_cmd_payload_fragment_address (axiToBmb_io_bmb_cmd_payload_fragment_address[23:0] ), //o + .io_bmb_cmd_payload_fragment_length (axiToBmb_io_bmb_cmd_payload_fragment_length[9:0] ), //o + .io_bmb_cmd_payload_fragment_data (axiToBmb_io_bmb_cmd_payload_fragment_data[31:0] ), //o + .io_bmb_cmd_payload_fragment_mask (axiToBmb_io_bmb_cmd_payload_fragment_mask[3:0] ), //o + .io_bmb_rsp_valid (bmbHandle_decoder_io_input_rsp_valid ), //i + .io_bmb_rsp_ready (axiToBmb_io_bmb_rsp_ready ), //o + .io_bmb_rsp_payload_last (bmbHandle_decoder_io_input_rsp_payload_last ), //i + .io_bmb_rsp_payload_fragment_source (bmbHandle_decoder_io_input_rsp_payload_fragment_source ), //i + .io_bmb_rsp_payload_fragment_opcode (bmbHandle_decoder_io_input_rsp_payload_fragment_opcode ), //i + .io_bmb_rsp_payload_fragment_data (bmbHandle_decoder_io_input_rsp_payload_fragment_data[31:0]) //i + ); + Axi4PeripheralBmbDecoder bmbHandle_decoder ( + .io_input_cmd_valid (axiToBmb_io_bmb_cmd_valid ), //i + .io_input_cmd_ready (bmbHandle_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (axiToBmb_io_bmb_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (axiToBmb_io_bmb_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (axiToBmb_io_bmb_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (axiToBmb_io_bmb_cmd_payload_fragment_address[23:0] ), //i + .io_input_cmd_payload_fragment_length (axiToBmb_io_bmb_cmd_payload_fragment_length[9:0] ), //i + .io_input_cmd_payload_fragment_data (axiToBmb_io_bmb_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (axiToBmb_io_bmb_cmd_payload_fragment_mask[3:0] ), //i + .io_input_rsp_valid (bmbHandle_decoder_io_input_rsp_valid ), //o + .io_input_rsp_ready (axiToBmb_io_bmb_rsp_ready ), //i + .io_input_rsp_payload_last (bmbHandle_decoder_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (bmbHandle_decoder_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (bmbHandle_decoder_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (bmbHandle_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_valid (bmbHandle_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (bmbHandle_unburstify_io_input_cmd_ready ), //i + .io_outputs_0_cmd_payload_last (bmbHandle_decoder_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_source (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_source ), //o + .io_outputs_0_cmd_payload_fragment_opcode (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_address[23:0]), //o + .io_outputs_0_cmd_payload_fragment_length (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_length[9:0] ), //o + .io_outputs_0_cmd_payload_fragment_data (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_mask (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_0_rsp_valid (bmbHandle_unburstify_io_input_rsp_valid ), //i + .io_outputs_0_rsp_ready (bmbHandle_decoder_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (bmbHandle_unburstify_io_input_rsp_payload_last ), //i + .io_outputs_0_rsp_payload_fragment_source (bmbHandle_unburstify_io_input_rsp_payload_fragment_source ), //i + .io_outputs_0_rsp_payload_fragment_opcode (bmbHandle_unburstify_io_input_rsp_payload_fragment_opcode ), //i + .io_outputs_0_rsp_payload_fragment_data (bmbHandle_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbUnburstify bmbHandle_unburstify ( + .io_input_cmd_valid (bmbHandle_decoder_io_outputs_0_cmd_valid ), //i + .io_input_cmd_ready (bmbHandle_unburstify_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (bmbHandle_decoder_io_outputs_0_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_address[23:0] ), //i + .io_input_cmd_payload_fragment_length (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_length[9:0] ), //i + .io_input_cmd_payload_fragment_data (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (bmbHandle_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //i + .io_input_rsp_valid (bmbHandle_unburstify_io_input_rsp_valid ), //o + .io_input_rsp_ready (bmbHandle_decoder_io_outputs_0_rsp_ready ), //i + .io_input_rsp_payload_last (bmbHandle_unburstify_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (bmbHandle_unburstify_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (bmbHandle_unburstify_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (bmbHandle_unburstify_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_output_cmd_valid (bmbHandle_unburstify_io_output_cmd_valid ), //o + .io_output_cmd_ready (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready ), //i + .io_output_cmd_payload_last (bmbHandle_unburstify_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (bmbHandle_unburstify_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (bmbHandle_unburstify_io_output_cmd_payload_fragment_address[23:0] ), //o + .io_output_cmd_payload_fragment_length (bmbHandle_unburstify_io_output_cmd_payload_fragment_length[1:0] ), //o + .io_output_cmd_payload_fragment_data (bmbHandle_unburstify_io_output_cmd_payload_fragment_data[31:0] ), //o + .io_output_cmd_payload_fragment_mask (bmbHandle_unburstify_io_output_cmd_payload_fragment_mask[3:0] ), //o + .io_output_cmd_payload_fragment_context (bmbHandle_unburstify_io_output_cmd_payload_fragment_context[2:0] ), //o + .io_output_rsp_valid (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid ), //i + .io_output_rsp_ready (bmbHandle_unburstify_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data[31:0] ), //i + .io_output_rsp_payload_fragment_context (bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context[2:0]), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbDecoder_1 bmbPeripheral_bmb_decoder ( + .io_input_cmd_valid (bmbPeripheral_bmb_cmd_valid ), //i + .io_input_cmd_ready (bmbPeripheral_bmb_decoder_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (bmbPeripheral_bmb_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (bmbPeripheral_bmb_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (bmbPeripheral_bmb_cmd_payload_fragment_address[23:0] ), //i + .io_input_cmd_payload_fragment_length (bmbPeripheral_bmb_cmd_payload_fragment_length[1:0] ), //i + .io_input_cmd_payload_fragment_data (bmbPeripheral_bmb_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_mask (bmbPeripheral_bmb_cmd_payload_fragment_mask[3:0] ), //i + .io_input_cmd_payload_fragment_context (bmbPeripheral_bmb_cmd_payload_fragment_context[2:0] ), //i + .io_input_rsp_valid (bmbPeripheral_bmb_decoder_io_input_rsp_valid ), //o + .io_input_rsp_ready (bmbPeripheral_bmb_rsp_ready ), //i + .io_input_rsp_payload_last (bmbPeripheral_bmb_decoder_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context[2:0] ), //o + .io_outputs_0_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid ), //o + .io_outputs_0_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready ), //i + .io_outputs_0_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last ), //o + .io_outputs_0_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode ), //o + .io_outputs_0_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address[23:0]), //o + .io_outputs_0_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_0_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_0_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_0_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_0_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid ), //i + .io_outputs_0_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready ), //o + .io_outputs_0_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last ), //i + .io_outputs_0_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode ), //i + .io_outputs_0_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data[31:0] ), //i + .io_outputs_0_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context[2:0] ), //i + .io_outputs_1_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid ), //o + .io_outputs_1_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_1 ), //i + .io_outputs_1_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last ), //o + .io_outputs_1_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode ), //o + .io_outputs_1_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address[23:0]), //o + .io_outputs_1_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_1_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_1_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_1_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_1_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_1 ), //i + .io_outputs_1_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready ), //o + .io_outputs_1_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 ), //i + .io_outputs_1_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 ), //i + .io_outputs_1_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1[31:0] ), //i + .io_outputs_1_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1[2:0] ), //i + .io_outputs_2_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid ), //o + .io_outputs_2_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_2 ), //i + .io_outputs_2_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last ), //o + .io_outputs_2_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode ), //o + .io_outputs_2_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address[23:0]), //o + .io_outputs_2_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_2_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_2_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_2_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_2_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_2 ), //i + .io_outputs_2_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready ), //o + .io_outputs_2_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 ), //i + .io_outputs_2_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 ), //i + .io_outputs_2_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2[31:0] ), //i + .io_outputs_2_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2[2:0] ), //i + .io_outputs_3_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid ), //o + .io_outputs_3_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_3 ), //i + .io_outputs_3_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last ), //o + .io_outputs_3_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode ), //o + .io_outputs_3_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address[23:0]), //o + .io_outputs_3_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_3_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_3_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_3_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_3_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_3 ), //i + .io_outputs_3_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready ), //o + .io_outputs_3_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 ), //i + .io_outputs_3_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 ), //i + .io_outputs_3_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3[31:0] ), //i + .io_outputs_3_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3[2:0] ), //i + .io_outputs_4_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid ), //o + .io_outputs_4_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_4 ), //i + .io_outputs_4_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last ), //o + .io_outputs_4_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode ), //o + .io_outputs_4_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address[23:0]), //o + .io_outputs_4_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_4_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_4_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_4_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_4_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_4 ), //i + .io_outputs_4_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready ), //o + .io_outputs_4_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 ), //i + .io_outputs_4_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 ), //i + .io_outputs_4_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4[31:0] ), //i + .io_outputs_4_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4[2:0] ), //i + .io_outputs_5_cmd_valid (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_valid ), //o + .io_outputs_5_cmd_ready (bmbPeripheral_bmb_withoutMask_cmd_ready_5 ), //i + .io_outputs_5_cmd_payload_last (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_last ), //o + .io_outputs_5_cmd_payload_fragment_opcode (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_opcode ), //o + .io_outputs_5_cmd_payload_fragment_address (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_address[23:0]), //o + .io_outputs_5_cmd_payload_fragment_length (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_length[1:0] ), //o + .io_outputs_5_cmd_payload_fragment_data (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_data[31:0] ), //o + .io_outputs_5_cmd_payload_fragment_mask (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_mask[3:0] ), //o + .io_outputs_5_cmd_payload_fragment_context (bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_context[2:0] ), //o + .io_outputs_5_rsp_valid (bmbPeripheral_bmb_withoutMask_rsp_valid_5 ), //i + .io_outputs_5_rsp_ready (bmbPeripheral_bmb_decoder_io_outputs_5_rsp_ready ), //o + .io_outputs_5_rsp_payload_last (bmbPeripheral_bmb_withoutMask_rsp_payload_last_5 ), //i + .io_outputs_5_rsp_payload_fragment_opcode (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_5 ), //i + .io_outputs_5_rsp_payload_fragment_data (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_5[31:0] ), //i + .io_outputs_5_rsp_payload_fragment_context (bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_5[2:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbUartCtrl system_uart_0_io_logic ( + .io_bus_cmd_valid (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i + .io_bus_cmd_ready (system_uart_0_io_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[5:0]), //i + .io_bus_cmd_payload_fragment_length (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_context (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[2:0]), //i + .io_bus_rsp_valid (system_uart_0_io_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (_zz_io_bus_rsp_ready ), //i + .io_bus_rsp_payload_last (system_uart_0_io_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_uart_0_io_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_uart_0_io_logic_io_bus_rsp_payload_fragment_context[2:0] ), //o + .io_uart_txd (system_uart_0_io_logic_io_uart_txd ), //o + .io_uart_rxd (system_uart_0_io_rxd ), //i + .system_uart_0_io_interrupt_source (system_uart_0_io_logic_system_uart_0_io_interrupt_source ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbSpiXdrMasterCtrl system_spi_0_io_logic ( + .io_ctrl_cmd_valid (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i + .io_ctrl_cmd_ready (system_spi_0_io_logic_io_ctrl_cmd_ready ), //o + .io_ctrl_cmd_payload_last (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i + .io_ctrl_cmd_payload_fragment_opcode (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i + .io_ctrl_cmd_payload_fragment_address (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[11:0]), //i + .io_ctrl_cmd_payload_fragment_length (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i + .io_ctrl_cmd_payload_fragment_data (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i + .io_ctrl_cmd_payload_fragment_context (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[2:0] ), //i + .io_ctrl_rsp_valid (system_spi_0_io_logic_io_ctrl_rsp_valid ), //o + .io_ctrl_rsp_ready (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_ctrl_rsp_payload_last (system_spi_0_io_logic_io_ctrl_rsp_payload_last ), //o + .io_ctrl_rsp_payload_fragment_opcode (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode ), //o + .io_ctrl_rsp_payload_fragment_data (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data[31:0] ), //o + .io_ctrl_rsp_payload_fragment_context (system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context[2:0] ), //o + .io_spi_sclk_write (system_spi_0_io_logic_io_spi_sclk_write ), //o + .io_spi_data_0_writeEnable (system_spi_0_io_logic_io_spi_data_0_writeEnable ), //o + .io_spi_data_0_read (system_spi_0_io_data_0_read ), //i + .io_spi_data_0_write (system_spi_0_io_logic_io_spi_data_0_write ), //o + .io_spi_data_1_writeEnable (system_spi_0_io_logic_io_spi_data_1_writeEnable ), //o + .io_spi_data_1_read (system_spi_0_io_data_1_read ), //i + .io_spi_data_1_write (system_spi_0_io_logic_io_spi_data_1_write ), //o + .io_spi_data_2_writeEnable (system_spi_0_io_logic_io_spi_data_2_writeEnable ), //o + .io_spi_data_2_read (system_spi_0_io_data_2_read ), //i + .io_spi_data_2_write (system_spi_0_io_logic_io_spi_data_2_write ), //o + .io_spi_data_3_writeEnable (system_spi_0_io_logic_io_spi_data_3_writeEnable ), //o + .io_spi_data_3_read (system_spi_0_io_data_3_read ), //i + .io_spi_data_3_write (system_spi_0_io_logic_io_spi_data_3_write ), //o + .io_spi_ss (system_spi_0_io_logic_io_spi_ss[3:0] ), //o + .system_spi_0_io_interrupt_source (system_spi_0_io_logic_system_spi_0_io_interrupt_source ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbI2cCtrl system_i2c_0_io_logic ( + .io_ctrl_cmd_valid (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid ), //i + .io_ctrl_cmd_ready (system_i2c_0_io_logic_io_ctrl_cmd_ready ), //o + .io_ctrl_cmd_payload_last (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last ), //i + .io_ctrl_cmd_payload_fragment_opcode (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode ), //i + .io_ctrl_cmd_payload_fragment_address (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address[7:0]), //i + .io_ctrl_cmd_payload_fragment_length (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length[1:0] ), //i + .io_ctrl_cmd_payload_fragment_data (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data[31:0] ), //i + .io_ctrl_cmd_payload_fragment_context (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context[2:0]), //i + .io_ctrl_rsp_valid (system_i2c_0_io_logic_io_ctrl_rsp_valid ), //o + .io_ctrl_rsp_ready (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_ctrl_rsp_payload_last (system_i2c_0_io_logic_io_ctrl_rsp_payload_last ), //o + .io_ctrl_rsp_payload_fragment_opcode (system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_opcode ), //o + .io_ctrl_rsp_payload_fragment_data (system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_data[31:0] ), //o + .io_ctrl_rsp_payload_fragment_context (system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_context[2:0] ), //o + .io_i2c_sda_write (system_i2c_0_io_logic_io_i2c_sda_write ), //o + .io_i2c_sda_read (system_i2c_0_io_sda_read ), //i + .io_i2c_scl_write (system_i2c_0_io_logic_io_i2c_scl_write ), //o + .io_i2c_scl_read (system_i2c_0_io_scl_read ), //i + .system_i2c_0_io_interrupt_source (system_i2c_0_io_logic_system_i2c_0_io_interrupt_source ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbGpio2 system_gpio_0_io_logic ( + .io_gpio_read (system_gpio_0_io_read[3:0] ), //i + .io_gpio_write (system_gpio_0_io_logic_io_gpio_write[3:0] ), //o + .io_gpio_writeEnable (system_gpio_0_io_logic_io_gpio_writeEnable[3:0] ), //o + .io_bus_cmd_valid (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i + .io_bus_cmd_ready (system_gpio_0_io_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[7:0]), //i + .io_bus_cmd_payload_fragment_length (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_context (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[2:0]), //i + .io_bus_rsp_valid (system_gpio_0_io_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_bus_rsp_payload_last (system_gpio_0_io_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_gpio_0_io_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_gpio_0_io_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_gpio_0_io_logic_io_bus_rsp_payload_fragment_context[2:0] ), //o + .io_interrupt (system_gpio_0_io_logic_io_interrupt[3:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbWatchdog system_watchdog_logic_logic ( + .io_bus_cmd_valid (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i + .io_bus_cmd_ready (system_watchdog_logic_logic_io_bus_cmd_ready ), //o + .io_bus_cmd_payload_last (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i + .io_bus_cmd_payload_fragment_opcode (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i + .io_bus_cmd_payload_fragment_address (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[7:0]), //i + .io_bus_cmd_payload_fragment_length (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i + .io_bus_cmd_payload_fragment_data (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i + .io_bus_cmd_payload_fragment_context (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[2:0]), //i + .io_bus_rsp_valid (system_watchdog_logic_logic_io_bus_rsp_valid ), //o + .io_bus_rsp_ready (system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_bus_rsp_payload_last (system_watchdog_logic_logic_io_bus_rsp_payload_last ), //o + .io_bus_rsp_payload_fragment_opcode (system_watchdog_logic_logic_io_bus_rsp_payload_fragment_opcode ), //o + .io_bus_rsp_payload_fragment_data (system_watchdog_logic_logic_io_bus_rsp_payload_fragment_data[31:0] ), //o + .io_bus_rsp_payload_fragment_context (system_watchdog_logic_logic_io_bus_rsp_payload_fragment_context[2:0] ), //o + .io_panics (system_watchdog_logic_logic_io_panics[1:0] ), //o + .io_heartBeat (1'b0 ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralBmbToApb3Bridge io_apbSlave_0_logic ( + .io_input_cmd_valid (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid ), //i + .io_input_cmd_ready (io_apbSlave_0_logic_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address[15:0]), //i + .io_input_cmd_payload_fragment_length (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length[1:0] ), //i + .io_input_cmd_payload_fragment_data (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data[31:0] ), //i + .io_input_cmd_payload_fragment_context (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context[2:0] ), //i + .io_input_rsp_valid (io_apbSlave_0_logic_io_input_rsp_valid ), //o + .io_input_rsp_ready (io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready ), //i + .io_input_rsp_payload_last (io_apbSlave_0_logic_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (io_apbSlave_0_logic_io_input_rsp_payload_fragment_data[31:0] ), //o + .io_input_rsp_payload_fragment_context (io_apbSlave_0_logic_io_input_rsp_payload_fragment_context[2:0] ), //o + .io_output_PADDR (io_apbSlave_0_logic_io_output_PADDR[15:0] ), //o + .io_output_PSEL (io_apbSlave_0_logic_io_output_PSEL ), //o + .io_output_PENABLE (io_apbSlave_0_logic_io_output_PENABLE ), //o + .io_output_PREADY (io_apbSlave_0_PREADY ), //i + .io_output_PWRITE (io_apbSlave_0_logic_io_output_PWRITE ), //o + .io_output_PWDATA (io_apbSlave_0_logic_io_output_PWDATA[31:0] ), //o + .io_output_PRDATA (io_apbSlave_0_PRDATA[31:0] ), //i + .io_output_PSLVERROR (io_apbSlave_0_PSLVERROR ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign axi_aw_halfPipe_fire = (axi_aw_halfPipe_valid && axi_aw_halfPipe_ready); + assign axi_awready = (! axi_aw_rValid); + assign axi_aw_halfPipe_valid = axi_aw_rValid; + assign axi_aw_halfPipe_payload_addr = axi_aw_rData_addr; + assign axi_aw_halfPipe_payload_len = axi_aw_rData_len; + assign axi_aw_halfPipe_payload_size = axi_aw_rData_size; + assign axi_aw_halfPipe_payload_cache = axi_aw_rData_cache; + assign axi_aw_halfPipe_payload_prot = axi_aw_rData_prot; + assign axi_aw_halfPipe_ready = streamArbiter_io_inputs_1_ready; + assign axi_w_halfPipe_fire = (axi_w_halfPipe_valid && axi_w_halfPipe_ready); + assign axi_wready = (! axi_w_rValid); + assign axi_w_halfPipe_valid = axi_w_rValid; + assign axi_w_halfPipe_payload_data = axi_w_rData_data; + assign axi_w_halfPipe_payload_strb = axi_w_rData_strb; + assign axi_w_halfPipe_payload_last = axi_w_rData_last; + assign axi_w_halfPipe_ready = axiShared_w_ready; + assign _zz_axiShared_b_ready = (! _zz_axi_bvalid_1); + assign _zz_axi_bvalid = _zz_axi_bvalid_1; + assign axi_bvalid = _zz_axi_bvalid; + assign axi_bresp = _zz_axi_bresp; + assign axi_ar_halfPipe_fire = (axi_ar_halfPipe_valid && axi_ar_halfPipe_ready); + assign axi_arready = (! axi_ar_rValid); + assign axi_ar_halfPipe_valid = axi_ar_rValid; + assign axi_ar_halfPipe_payload_addr = axi_ar_rData_addr; + assign axi_ar_halfPipe_payload_len = axi_ar_rData_len; + assign axi_ar_halfPipe_payload_size = axi_ar_rData_size; + assign axi_ar_halfPipe_payload_cache = axi_ar_rData_cache; + assign axi_ar_halfPipe_payload_prot = axi_ar_rData_prot; + assign axi_ar_halfPipe_ready = streamArbiter_io_inputs_0_ready; + assign _zz_axiShared_r_ready = (! _zz_axi_rvalid_1); + assign _zz_axi_rvalid = _zz_axi_rvalid_1; + assign axi_rvalid = _zz_axi_rvalid; + assign axi_rdata = _zz_axi_rdata; + assign axi_rresp = _zz_axi_rresp; + assign axi_rlast = _zz_axi_rlast; + assign axiShared_arw_valid = streamArbiter_io_output_valid; + assign axiShared_arw_payload_addr = streamArbiter_io_output_payload_addr; + assign axiShared_arw_payload_len = streamArbiter_io_output_payload_len; + assign axiShared_arw_payload_size = streamArbiter_io_output_payload_size; + assign axiShared_arw_payload_cache = streamArbiter_io_output_payload_cache; + assign axiShared_arw_payload_prot = streamArbiter_io_output_payload_prot; + assign axiShared_arw_payload_write = streamArbiter_io_chosenOH[1]; + assign axiShared_w_valid = axi_w_halfPipe_valid; + assign axiShared_w_payload_data = axi_w_halfPipe_payload_data; + assign axiShared_w_payload_strb = axi_w_halfPipe_payload_strb; + assign axiShared_w_payload_last = axi_w_halfPipe_payload_last; + assign axiShared_b_ready = _zz_axiShared_b_ready; + assign axiShared_r_ready = _zz_axiShared_r_ready; + assign axiShared_arw_ready = axiToBmb_io_axi_arw_ready; + assign axiShared_w_ready = axiToBmb_io_axi_w_ready; + assign axiShared_b_valid = axiToBmb_io_axi_b_valid; + assign axiShared_b_payload_resp = axiToBmb_io_axi_b_payload_resp; + assign axiShared_r_valid = axiToBmb_io_axi_r_valid; + assign axiShared_r_payload_data = axiToBmb_io_axi_r_payload_data; + assign axiShared_r_payload_last = axiToBmb_io_axi_r_payload_last; + assign axiShared_r_payload_resp = axiToBmb_io_axi_r_payload_resp; + assign bmbPeripheral_bmb_cmd_valid = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = bmbPeripheral_bmb_cmd_ready; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = bmbPeripheral_bmb_rsp_valid; + assign bmbPeripheral_bmb_rsp_ready = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready; + assign bmbPeripheral_bmb_cmd_payload_last = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = bmbPeripheral_bmb_rsp_payload_last; + assign bmbPeripheral_bmb_cmd_payload_fragment_opcode = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_cmd_payload_fragment_address = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_cmd_payload_fragment_length = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_cmd_payload_fragment_data = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_cmd_payload_fragment_mask = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask; + assign bmbPeripheral_bmb_cmd_payload_fragment_context = bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = bmbPeripheral_bmb_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = bmbPeripheral_bmb_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = bmbPeripheral_bmb_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbHandle_unburstify_io_output_cmd_valid; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbHandle_unburstify_io_output_rsp_ready; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbHandle_unburstify_io_output_cmd_payload_last; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbHandle_unburstify_io_output_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbHandle_unburstify_io_output_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbHandle_unburstify_io_output_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbHandle_unburstify_io_output_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_mask = bmbHandle_unburstify_io_output_cmd_payload_fragment_mask; + assign bmbPeripheral_bmb_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbHandle_unburstify_io_output_cmd_payload_fragment_context; + assign bmbPeripheral_bmb_cmd_ready = bmbPeripheral_bmb_decoder_io_input_cmd_ready; + assign bmbPeripheral_bmb_rsp_valid = bmbPeripheral_bmb_decoder_io_input_rsp_valid; + assign bmbPeripheral_bmb_rsp_payload_last = bmbPeripheral_bmb_decoder_io_input_rsp_payload_last; + assign bmbPeripheral_bmb_rsp_payload_fragment_opcode = bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_rsp_payload_fragment_data = bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_rsp_payload_fragment_context = bmbPeripheral_bmb_decoder_io_input_rsp_payload_fragment_context; + assign system_uart_0_io_txd = system_uart_0_io_logic_io_uart_txd; + assign system_i2c_0_io_sda_write = system_i2c_0_io_logic_io_i2c_sda_write; + assign system_i2c_0_io_scl_write = system_i2c_0_io_logic_io_i2c_scl_write; + assign system_gpio_0_io_write = system_gpio_0_io_logic_io_gpio_write; + assign system_gpio_0_io_writeEnable = system_gpio_0_io_logic_io_gpio_writeEnable; + assign system_gpio_0_io_interrupts_0_source = system_gpio_0_io_logic_io_interrupt[0]; + assign system_gpio_0_io_interrupts_1_source = system_gpio_0_io_logic_io_interrupt[1]; + assign system_gpio_0_io_interrupts_2 = system_gpio_0_io_logic_io_interrupt[2]; + assign system_gpio_0_io_interrupts_3 = system_gpio_0_io_logic_io_interrupt[3]; + assign system_watchdog_logic_panics_0_source = system_watchdog_logic_logic_io_panics[0]; + assign io_apbSlave_0_PADDR = io_apbSlave_0_logic_io_output_PADDR; + assign io_apbSlave_0_PSEL = io_apbSlave_0_logic_io_output_PSEL; + assign io_apbSlave_0_PENABLE = io_apbSlave_0_logic_io_output_PENABLE; + assign io_apbSlave_0_PWRITE = io_apbSlave_0_logic_io_output_PWRITE; + assign io_apbSlave_0_PWDATA = io_apbSlave_0_logic_io_output_PWDATA; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_uart_0_io_logic_io_bus_cmd_ready; + assign _zz_io_bus_rsp_ready = (! _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1); + assign _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign system_uart_0_io_interrupt = system_uart_0_io_logic_system_uart_0_io_interrupt_source; + assign system_spi_0_io_interrupt = system_spi_0_io_logic_system_spi_0_io_interrupt_source; + assign system_spi_0_io_sclk_write = system_spi_0_io_logic_io_spi_sclk_write; + assign system_spi_0_io_data_0_writeEnable = system_spi_0_io_logic_io_spi_data_0_writeEnable; + assign system_spi_0_io_data_0_write = system_spi_0_io_logic_io_spi_data_0_write; + assign system_spi_0_io_data_1_writeEnable = system_spi_0_io_logic_io_spi_data_1_writeEnable; + assign system_spi_0_io_data_1_write = system_spi_0_io_logic_io_spi_data_1_write; + assign system_spi_0_io_data_2_writeEnable = system_spi_0_io_logic_io_spi_data_2_writeEnable; + assign system_spi_0_io_data_2_write = system_spi_0_io_logic_io_spi_data_2_write; + assign system_spi_0_io_data_3_writeEnable = system_spi_0_io_logic_io_spi_data_3_writeEnable; + assign system_spi_0_io_data_3_write = system_spi_0_io_logic_io_spi_data_3_write; + assign system_spi_0_io_ss = system_spi_0_io_logic_io_spi_ss; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_spi_0_io_logic_io_ctrl_cmd_ready; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_spi_0_io_logic_io_ctrl_rsp_valid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_spi_0_io_logic_io_ctrl_rsp_payload_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_data; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_spi_0_io_logic_io_ctrl_rsp_payload_fragment_context; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire = (system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid && system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready); + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = (! system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid); + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_valid = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_last = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_opcode = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_address = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_length = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_data = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_payload_fragment_context = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_ready = system_i2c_0_io_logic_io_ctrl_cmd_ready; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_i2c_0_io_logic_io_ctrl_rsp_valid; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_i2c_0_io_logic_io_ctrl_rsp_payload_last; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_opcode; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_data; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_i2c_0_io_logic_io_ctrl_rsp_payload_fragment_context; + assign system_i2c_0_io_interrupt = system_i2c_0_io_logic_system_i2c_0_io_interrupt_source; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_gpio_0_io_logic_io_bus_cmd_ready; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_gpio_0_io_logic_io_bus_rsp_valid; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_gpio_0_io_logic_io_bus_rsp_payload_last; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_gpio_0_io_logic_io_bus_rsp_payload_fragment_opcode; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_gpio_0_io_logic_io_bus_rsp_payload_fragment_data; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_gpio_0_io_logic_io_bus_rsp_payload_fragment_context; + assign system_gpio_0_io_interrupts_0 = system_gpio_0_io_interrupts_0_source; + assign system_gpio_0_io_interrupts_1 = system_gpio_0_io_interrupts_1_source; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = system_watchdog_logic_logic_io_bus_cmd_ready; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = system_watchdog_logic_logic_io_bus_rsp_valid; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = system_watchdog_logic_logic_io_bus_rsp_payload_last; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = system_watchdog_logic_logic_io_bus_rsp_payload_fragment_opcode; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = system_watchdog_logic_logic_io_bus_rsp_payload_fragment_data; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = system_watchdog_logic_logic_io_bus_rsp_payload_fragment_context; + assign system_watchdog_logic_panics_0 = system_watchdog_logic_panics_0_source; + assign system_watchdog_hardPanic_reset = system_watchdog_logic_logic_io_panics[1]; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready = io_apbSlave_0_logic_io_input_cmd_ready; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid = io_apbSlave_0_logic_io_input_rsp_valid; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last = io_apbSlave_0_logic_io_input_rsp_payload_last; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode = io_apbSlave_0_logic_io_input_rsp_payload_fragment_opcode; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data = io_apbSlave_0_logic_io_input_rsp_payload_fragment_data; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context = io_apbSlave_0_logic_io_input_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready = bmbPeripheral_bmb_decoder_io_outputs_0_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context = bmbPeripheral_bmb_decoder_io_outputs_0_cmd_payload_fragment_context; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_cmd_ready = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address[5:0]; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data; + assign system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context = system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready_1 = bmbPeripheral_bmb_decoder_io_outputs_1_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1 = bmbPeripheral_bmb_decoder_io_outputs_1_cmd_payload_fragment_context; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_1; + assign bmbPeripheral_bmb_withoutMask_cmd_ready_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_1; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_1; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_1; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_1[11:0]; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_1; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_1; + assign system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_1; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_1 = system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready_2 = bmbPeripheral_bmb_decoder_io_outputs_2_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2 = bmbPeripheral_bmb_decoder_io_outputs_2_cmd_payload_fragment_context; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_2; + assign bmbPeripheral_bmb_withoutMask_cmd_ready_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_2; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_2; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_2; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_2[7:0]; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_2; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_2; + assign system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_2; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_2 = system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready_3 = bmbPeripheral_bmb_decoder_io_outputs_3_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3 = bmbPeripheral_bmb_decoder_io_outputs_3_cmd_payload_fragment_context; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_3; + assign bmbPeripheral_bmb_withoutMask_cmd_ready_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_3; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_3; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_3; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_3[7:0]; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_3; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_3; + assign system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_3; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_3 = system_gpio_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready_4 = bmbPeripheral_bmb_decoder_io_outputs_4_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4 = bmbPeripheral_bmb_decoder_io_outputs_4_cmd_payload_fragment_context; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_4; + assign bmbPeripheral_bmb_withoutMask_cmd_ready_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_4; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_4; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_4; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_4[7:0]; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_4; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_4; + assign system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_4; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_4 = system_watchdog_logic_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + assign bmbPeripheral_bmb_withoutMask_cmd_valid_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_valid; + assign bmbPeripheral_bmb_withoutMask_rsp_ready_5 = bmbPeripheral_bmb_decoder_io_outputs_5_rsp_ready; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_last_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_last; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_address; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_length; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_5 = bmbPeripheral_bmb_decoder_io_outputs_5_cmd_payload_fragment_context; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid = bmbPeripheral_bmb_withoutMask_cmd_valid_5; + assign bmbPeripheral_bmb_withoutMask_cmd_ready_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready; + assign bmbPeripheral_bmb_withoutMask_rsp_valid_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready = bmbPeripheral_bmb_withoutMask_rsp_ready_5; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last = bmbPeripheral_bmb_withoutMask_cmd_payload_last_5; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_last_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_opcode_5; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_address_5[15:0]; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_length_5; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_data_5; + assign io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context = bmbPeripheral_bmb_withoutMask_cmd_payload_fragment_context_5; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_opcode_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_data_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data; + assign bmbPeripheral_bmb_withoutMask_rsp_payload_fragment_context_5 = io_apbSlave_0_input_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context; + always @(posedge clk) begin + if(reset) begin + axi_aw_rValid <= 1'b0; + axi_w_rValid <= 1'b0; + _zz_axi_bvalid_1 <= 1'b0; + axi_ar_rValid <= 1'b0; + _zz_axi_rvalid_1 <= 1'b0; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end else begin + if(axi_awvalid) begin + axi_aw_rValid <= 1'b1; + end + if(axi_aw_halfPipe_fire) begin + axi_aw_rValid <= 1'b0; + end + if(axi_wvalid) begin + axi_w_rValid <= 1'b1; + end + if(axi_w_halfPipe_fire) begin + axi_w_rValid <= 1'b0; + end + if(axiShared_b_valid) begin + _zz_axi_bvalid_1 <= 1'b1; + end + if((_zz_axi_bvalid && axi_bready)) begin + _zz_axi_bvalid_1 <= 1'b0; + end + if(axi_arvalid) begin + axi_ar_rValid <= 1'b1; + end + if(axi_ar_halfPipe_fire) begin + axi_ar_rValid <= 1'b0; + end + if(axiShared_r_valid) begin + _zz_axi_rvalid_1 <= 1'b1; + end + if((_zz_axi_rvalid && axi_rready)) begin + _zz_axi_rvalid_1 <= 1'b0; + end + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + if(system_uart_0_io_logic_io_bus_rsp_valid) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b1; + end + if((_zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid && system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_ready)) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_valid_1 <= 1'b0; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + if(system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_valid) begin + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b1; + end + if(system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_halfPipe_fire) begin + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rValid <= 1'b0; + end + end + end + + always @(posedge clk) begin + if(axi_awready) begin + axi_aw_rData_addr <= axi_awaddr; + axi_aw_rData_len <= axi_awlen; + axi_aw_rData_size <= axi_awsize; + axi_aw_rData_cache <= axi_awcache; + axi_aw_rData_prot <= axi_awprot; + end + if(axi_wready) begin + axi_w_rData_data <= axi_wdata; + axi_w_rData_strb <= axi_wstrb; + axi_w_rData_last <= axi_wlast; + end + if(_zz_axiShared_b_ready) begin + _zz_axi_bresp <= axiShared_b_payload_resp; + end + if(axi_arready) begin + axi_ar_rData_addr <= axi_araddr; + axi_ar_rData_len <= axi_arlen; + axi_ar_rData_size <= axi_arsize; + axi_ar_rData_cache <= axi_arcache; + axi_ar_rData_prot <= axi_arprot; + end + if(_zz_axiShared_r_ready) begin + _zz_axi_rdata <= axiShared_r_payload_data; + _zz_axi_rresp <= axiShared_r_payload_resp; + _zz_axi_rlast <= axiShared_r_payload_last; + end + if(system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + if(_zz_io_bus_rsp_ready) begin + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_last <= system_uart_0_io_logic_io_bus_rsp_payload_last; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_opcode <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_opcode; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_data <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_data; + _zz_system_uart_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_rsp_payload_fragment_context <= system_uart_0_io_logic_io_bus_rsp_payload_fragment_context; + end + if(system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_spi_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + if(system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_ready) begin + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_last <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_last; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_opcode <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_opcode; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_address <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_address; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_length <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_length; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_data <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_data; + system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_rData_fragment_context <= system_i2c_0_io_ctrl_slaveModel_arbiterGen_oneToOne_arbiter_cmd_payload_fragment_context; + end + end + + +endmodule + +module Axi4PeripheralBmbToApb3Bridge ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [15:0] io_input_cmd_payload_fragment_address, + input wire [1:0] io_input_cmd_payload_fragment_length, + input wire [31:0] io_input_cmd_payload_fragment_data, + input wire [2:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [31:0] io_input_rsp_payload_fragment_data, + output wire [2:0] io_input_rsp_payload_fragment_context, + output wire [15:0] io_output_PADDR, + output wire [0:0] io_output_PSEL, + output wire io_output_PENABLE, + input wire io_output_PREADY, + output wire io_output_PWRITE, + output wire [31:0] io_output_PWDATA, + input wire [31:0] io_output_PRDATA, + input wire io_output_PSLVERROR, + input wire clk, + input wire reset +); + + wire bmbBuffer_cmd_valid; + reg bmbBuffer_cmd_ready; + wire bmbBuffer_cmd_payload_last; + wire [0:0] bmbBuffer_cmd_payload_fragment_opcode; + wire [15:0] bmbBuffer_cmd_payload_fragment_address; + wire [1:0] bmbBuffer_cmd_payload_fragment_length; + wire [31:0] bmbBuffer_cmd_payload_fragment_data; + wire [2:0] bmbBuffer_cmd_payload_fragment_context; + reg bmbBuffer_rsp_valid; + reg bmbBuffer_rsp_ready; + wire bmbBuffer_rsp_payload_last; + reg [0:0] bmbBuffer_rsp_payload_fragment_opcode; + wire [31:0] bmbBuffer_rsp_payload_fragment_data; + wire [2:0] bmbBuffer_rsp_payload_fragment_context; + wire io_input_rsp_isStall; + wire _zz_io_input_cmd_ready; + wire bmbBuffer_rsp_m2sPipe_valid; + wire bmbBuffer_rsp_m2sPipe_ready; + wire bmbBuffer_rsp_m2sPipe_payload_last; + wire [0:0] bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; + wire [31:0] bmbBuffer_rsp_m2sPipe_payload_fragment_data; + wire [2:0] bmbBuffer_rsp_m2sPipe_payload_fragment_context; + reg bmbBuffer_rsp_rValid; + reg bmbBuffer_rsp_rData_last; + reg [0:0] bmbBuffer_rsp_rData_fragment_opcode; + reg [31:0] bmbBuffer_rsp_rData_fragment_data; + reg [2:0] bmbBuffer_rsp_rData_fragment_context; + wire when_Stream_l375; + reg state; + wire when_BmbToApb3Bridge_l46; + + assign io_input_rsp_isStall = (io_input_rsp_valid && (! io_input_rsp_ready)); + assign _zz_io_input_cmd_ready = (! io_input_rsp_isStall); + assign io_input_cmd_ready = (bmbBuffer_cmd_ready && _zz_io_input_cmd_ready); + assign bmbBuffer_cmd_valid = (io_input_cmd_valid && _zz_io_input_cmd_ready); + assign bmbBuffer_cmd_payload_last = io_input_cmd_payload_last; + assign bmbBuffer_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign bmbBuffer_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign bmbBuffer_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign bmbBuffer_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign bmbBuffer_cmd_payload_fragment_context = io_input_cmd_payload_fragment_context; + always @(*) begin + bmbBuffer_rsp_ready = bmbBuffer_rsp_m2sPipe_ready; + if(when_Stream_l375) begin + bmbBuffer_rsp_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! bmbBuffer_rsp_m2sPipe_valid); + assign bmbBuffer_rsp_m2sPipe_valid = bmbBuffer_rsp_rValid; + assign bmbBuffer_rsp_m2sPipe_payload_last = bmbBuffer_rsp_rData_last; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_opcode = bmbBuffer_rsp_rData_fragment_opcode; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_data = bmbBuffer_rsp_rData_fragment_data; + assign bmbBuffer_rsp_m2sPipe_payload_fragment_context = bmbBuffer_rsp_rData_fragment_context; + assign io_input_rsp_valid = bmbBuffer_rsp_m2sPipe_valid; + assign bmbBuffer_rsp_m2sPipe_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = bmbBuffer_rsp_m2sPipe_payload_last; + assign io_input_rsp_payload_fragment_opcode = bmbBuffer_rsp_m2sPipe_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = bmbBuffer_rsp_m2sPipe_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = bmbBuffer_rsp_m2sPipe_payload_fragment_context; + always @(*) begin + bmbBuffer_cmd_ready = 1'b0; + if(!when_BmbToApb3Bridge_l46) begin + if(io_output_PREADY) begin + bmbBuffer_cmd_ready = 1'b1; + end + end + end + + assign io_output_PSEL[0] = bmbBuffer_cmd_valid; + assign io_output_PENABLE = state; + assign io_output_PWRITE = (bmbBuffer_cmd_payload_fragment_opcode == 1'b1); + assign io_output_PADDR = bmbBuffer_cmd_payload_fragment_address; + assign io_output_PWDATA = bmbBuffer_cmd_payload_fragment_data; + always @(*) begin + bmbBuffer_rsp_valid = 1'b0; + if(!when_BmbToApb3Bridge_l46) begin + if(io_output_PREADY) begin + bmbBuffer_rsp_valid = 1'b1; + end + end + end + + assign bmbBuffer_rsp_payload_fragment_data = io_output_PRDATA; + assign when_BmbToApb3Bridge_l46 = (! state); + assign bmbBuffer_rsp_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign bmbBuffer_rsp_payload_last = 1'b1; + always @(*) begin + bmbBuffer_rsp_payload_fragment_opcode = 1'b0; + if(io_output_PSLVERROR) begin + bmbBuffer_rsp_payload_fragment_opcode = 1'b1; + end + end + + always @(posedge clk) begin + if(reset) begin + bmbBuffer_rsp_rValid <= 1'b0; + state <= 1'b0; + end else begin + if(bmbBuffer_rsp_ready) begin + bmbBuffer_rsp_rValid <= bmbBuffer_rsp_valid; + end + if(when_BmbToApb3Bridge_l46) begin + state <= bmbBuffer_cmd_valid; + end else begin + if(io_output_PREADY) begin + state <= 1'b0; + end + end + end + end + + always @(posedge clk) begin + if(bmbBuffer_rsp_ready) begin + bmbBuffer_rsp_rData_last <= bmbBuffer_rsp_payload_last; + bmbBuffer_rsp_rData_fragment_opcode <= bmbBuffer_rsp_payload_fragment_opcode; + bmbBuffer_rsp_rData_fragment_data <= bmbBuffer_rsp_payload_fragment_data; + bmbBuffer_rsp_rData_fragment_context <= bmbBuffer_rsp_payload_fragment_context; + end + end + + +endmodule + +module Axi4PeripheralBmbWatchdog ( + input wire io_bus_cmd_valid, + output wire io_bus_cmd_ready, + input wire io_bus_cmd_payload_last, + input wire [0:0] io_bus_cmd_payload_fragment_opcode, + input wire [7:0] io_bus_cmd_payload_fragment_address, + input wire [1:0] io_bus_cmd_payload_fragment_length, + input wire [31:0] io_bus_cmd_payload_fragment_data, + input wire [2:0] io_bus_cmd_payload_fragment_context, + output wire io_bus_rsp_valid, + input wire io_bus_rsp_ready, + output wire io_bus_rsp_payload_last, + output wire [0:0] io_bus_rsp_payload_fragment_opcode, + output wire [31:0] io_bus_rsp_payload_fragment_data, + output wire [2:0] io_bus_rsp_payload_fragment_context, + output wire [1:0] io_panics, + input wire io_heartBeat, + input wire clk, + input wire reset +); + + wire wd_prescaler_io_clear; + wire wd_prescaler_io_overflow; + wire wd_counters_0_timer_io_full; + wire [15:0] wd_counters_0_timer_io_value; + wire wd_counters_1_timer_io_full; + wire [15:0] wd_counters_1_timer_io_value; + reg [1:0] wd_api_enables; + reg wd_api_heartbeat; + reg [1:0] wd_api_panics; + wire wd_counters_0_clear; + reg wd_counters_0_full; + wire wd_counters_1_clear; + reg wd_counters_1_full; + wire busCtrl_readErrorFlag; + wire busCtrl_writeErrorFlag; + wire busCtrl_readHaltTrigger; + wire busCtrl_writeHaltTrigger; + wire busCtrl_rsp_valid; + wire busCtrl_rsp_ready; + wire busCtrl_rsp_payload_last; + reg [0:0] busCtrl_rsp_payload_fragment_opcode; + reg [31:0] busCtrl_rsp_payload_fragment_data; + wire [2:0] busCtrl_rsp_payload_fragment_context; + wire _zz_busCtrl_rsp_ready; + reg _zz_busCtrl_rsp_ready_1; + wire _zz_io_bus_rsp_valid; + reg _zz_io_bus_rsp_valid_1; + reg _zz_io_bus_rsp_payload_last; + reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_bus_rsp_payload_fragment_data; + reg [2:0] _zz_io_bus_rsp_payload_fragment_context; + wire when_Stream_l375; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire io_bus_cmd_fire; + wire busCtrl_doWrite; + wire busCtrl_doRead; + wire when_BmbSlaveFactory_l33; + wire when_BmbSlaveFactory_l35; + reg driver_unlocked; + reg _zz_when_Watchdog_l42; + wire when_Watchdog_l42; + reg _zz_when_Watchdog_l43; + wire when_Watchdog_l43; + reg _zz_wd_api_heartbeat; + wire [1:0] _zz_when_Watchdog_l52; + reg _zz_when_Watchdog_l50; + wire when_Watchdog_l50; + wire when_Watchdog_l52; + wire when_Watchdog_l52_1; + reg _zz_when_Watchdog_l55; + wire when_Watchdog_l55; + wire when_Watchdog_l57; + wire when_Watchdog_l57_1; + reg [23:0] _zz_io_limit; + reg [15:0] _zz_io_limit_1; + reg [15:0] _zz_io_limit_2; + + Axi4PeripheralPrescaler wd_prescaler ( + .io_clear (wd_prescaler_io_clear ), //i + .io_limit (_zz_io_limit[23:0] ), //i + .io_overflow (wd_prescaler_io_overflow), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralTimer wd_counters_0_timer ( + .io_tick (wd_prescaler_io_overflow ), //i + .io_clear (wd_counters_0_clear ), //i + .io_limit (_zz_io_limit_1[15:0] ), //i + .io_full (wd_counters_0_timer_io_full ), //o + .io_value (wd_counters_0_timer_io_value[15:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralTimer wd_counters_1_timer ( + .io_tick (wd_prescaler_io_overflow ), //i + .io_clear (wd_counters_1_clear ), //i + .io_limit (_zz_io_limit_2[15:0] ), //i + .io_full (wd_counters_1_timer_io_full ), //o + .io_value (wd_counters_1_timer_io_value[15:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + assign wd_prescaler_io_clear = (wd_api_heartbeat || (wd_api_enables == 2'b00)); + assign wd_counters_0_clear = ((! wd_api_enables[0]) || wd_api_heartbeat); + always @(*) begin + wd_api_panics[0] = wd_counters_0_full; + wd_api_panics[1] = wd_counters_1_full; + end + + assign wd_counters_1_clear = ((! wd_api_enables[1]) || wd_api_heartbeat); + assign busCtrl_readErrorFlag = 1'b0; + assign busCtrl_writeErrorFlag = 1'b0; + assign busCtrl_readHaltTrigger = 1'b0; + assign busCtrl_writeHaltTrigger = 1'b0; + assign _zz_busCtrl_rsp_ready = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); + assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready_1 && _zz_busCtrl_rsp_ready); + always @(*) begin + _zz_busCtrl_rsp_ready_1 = io_bus_rsp_ready; + if(when_Stream_l375) begin + _zz_busCtrl_rsp_ready_1 = 1'b1; + end + end + + assign when_Stream_l375 = (! _zz_io_bus_rsp_valid); + assign _zz_io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; + assign io_bus_rsp_valid = _zz_io_bus_rsp_valid; + assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; + assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; + assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; + assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; + assign busCtrl_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign busCtrl_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_doRead = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign busCtrl_rsp_valid = io_bus_cmd_valid; + assign io_bus_cmd_ready = busCtrl_rsp_ready; + assign busCtrl_rsp_payload_last = 1'b1; + assign when_BmbSlaveFactory_l33 = (busCtrl_doWrite && busCtrl_writeErrorFlag); + always @(*) begin + if(when_BmbSlaveFactory_l33) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + if(when_BmbSlaveFactory_l35) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + busCtrl_rsp_payload_fragment_opcode = 1'b0; + end + end + end + + assign when_BmbSlaveFactory_l35 = (busCtrl_doRead && busCtrl_readErrorFlag); + always @(*) begin + busCtrl_rsp_payload_fragment_data = 32'h0; + case(io_bus_cmd_payload_fragment_address) + 8'hc0 : begin + busCtrl_rsp_payload_fragment_data[15 : 0] = wd_counters_0_timer_io_value; + end + 8'hc4 : begin + busCtrl_rsp_payload_fragment_data[15 : 0] = wd_counters_1_timer_io_value; + end + default : begin + end + endcase + end + + assign busCtrl_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; + always @(*) begin + _zz_when_Watchdog_l42 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 8'h0 : begin + if(busCtrl_doWrite) begin + _zz_when_Watchdog_l42 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_Watchdog_l42 = (_zz_when_Watchdog_l42 && (io_bus_cmd_payload_fragment_data[31 : 0] == 32'h3c21b925)); + always @(*) begin + _zz_when_Watchdog_l43 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 8'h0 : begin + if(busCtrl_doWrite) begin + _zz_when_Watchdog_l43 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_Watchdog_l43 = (_zz_when_Watchdog_l43 && (io_bus_cmd_payload_fragment_data[31 : 0] == 32'h3c21b924)); + always @(*) begin + _zz_wd_api_heartbeat = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 8'h0 : begin + if(busCtrl_doWrite) begin + _zz_wd_api_heartbeat = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + wd_api_heartbeat = (_zz_wd_api_heartbeat && (io_bus_cmd_payload_fragment_data[31 : 0] == 32'had68e70d)); + if(io_heartBeat) begin + wd_api_heartbeat = 1'b1; + end + end + + always @(*) begin + _zz_when_Watchdog_l50 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 8'h04 : begin + if(busCtrl_doWrite) begin + _zz_when_Watchdog_l50 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_Watchdog_l50 = (_zz_when_Watchdog_l50 && driver_unlocked); + assign when_Watchdog_l52 = _zz_when_Watchdog_l52[0]; + assign when_Watchdog_l52_1 = _zz_when_Watchdog_l52[1]; + always @(*) begin + _zz_when_Watchdog_l55 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 8'h08 : begin + if(busCtrl_doWrite) begin + _zz_when_Watchdog_l55 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_Watchdog_l55 = (_zz_when_Watchdog_l55 && driver_unlocked); + assign when_Watchdog_l57 = _zz_when_Watchdog_l52[0]; + assign when_Watchdog_l57_1 = _zz_when_Watchdog_l52[1]; + assign io_panics = wd_api_panics; + assign _zz_when_Watchdog_l52 = io_bus_cmd_payload_fragment_data[1 : 0]; + always @(posedge clk) begin + if(reset) begin + wd_counters_0_full <= 1'b0; + wd_counters_1_full <= 1'b0; + _zz_io_bus_rsp_valid_1 <= 1'b0; + driver_unlocked <= 1'b1; + wd_api_enables <= 2'b00; + _zz_io_limit <= 24'h0; + _zz_io_limit_1 <= 16'h0; + _zz_io_limit_2 <= 16'h0; + end else begin + if(wd_counters_0_timer_io_full) begin + wd_counters_0_full <= 1'b1; + end + if(wd_counters_0_clear) begin + wd_counters_0_full <= 1'b0; + end + if(wd_counters_1_timer_io_full) begin + wd_counters_1_full <= 1'b1; + end + if(wd_counters_1_clear) begin + wd_counters_1_full <= 1'b0; + end + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_bus_rsp_valid_1 <= (busCtrl_rsp_valid && _zz_busCtrl_rsp_ready); + end + if(when_Watchdog_l42) begin + driver_unlocked <= 1'b1; + end + if(when_Watchdog_l43) begin + driver_unlocked <= 1'b0; + end + if(when_Watchdog_l50) begin + if(when_Watchdog_l52) begin + wd_api_enables[0] <= 1'b1; + end + if(when_Watchdog_l52_1) begin + wd_api_enables[1] <= 1'b1; + end + end + if(when_Watchdog_l55) begin + if(when_Watchdog_l57) begin + wd_api_enables[0] <= 1'b0; + end + if(when_Watchdog_l57_1) begin + wd_api_enables[1] <= 1'b0; + end + end + case(io_bus_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + if(driver_unlocked) begin + _zz_io_limit <= io_bus_cmd_payload_fragment_data[23 : 0]; + end + end + end + 8'h80 : begin + if(busCtrl_doWrite) begin + if(driver_unlocked) begin + _zz_io_limit_1 <= io_bus_cmd_payload_fragment_data[15 : 0]; + end + end + end + 8'h84 : begin + if(busCtrl_doWrite) begin + if(driver_unlocked) begin + _zz_io_limit_2 <= io_bus_cmd_payload_fragment_data[15 : 0]; + end + end + end + default : begin + end + endcase + end + end + + always @(posedge clk) begin + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_bus_rsp_payload_last <= busCtrl_rsp_payload_last; + _zz_io_bus_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; + _zz_io_bus_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; + _zz_io_bus_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; + end + end + + +endmodule + +module Axi4PeripheralBmbGpio2 ( + input wire [3:0] io_gpio_read, + output reg [3:0] io_gpio_write, + output reg [3:0] io_gpio_writeEnable, + input wire io_bus_cmd_valid, + output wire io_bus_cmd_ready, + input wire io_bus_cmd_payload_last, + input wire [0:0] io_bus_cmd_payload_fragment_opcode, + input wire [7:0] io_bus_cmd_payload_fragment_address, + input wire [1:0] io_bus_cmd_payload_fragment_length, + input wire [31:0] io_bus_cmd_payload_fragment_data, + input wire [2:0] io_bus_cmd_payload_fragment_context, + output wire io_bus_rsp_valid, + input wire io_bus_rsp_ready, + output wire io_bus_rsp_payload_last, + output wire [0:0] io_bus_rsp_payload_fragment_opcode, + output wire [31:0] io_bus_rsp_payload_fragment_data, + output wire [2:0] io_bus_rsp_payload_fragment_context, + output reg [3:0] io_interrupt, + input wire clk, + input wire reset +); + + wire mapper_readErrorFlag; + wire mapper_writeErrorFlag; + wire mapper_readHaltTrigger; + wire mapper_writeHaltTrigger; + wire mapper_rsp_valid; + wire mapper_rsp_ready; + wire mapper_rsp_payload_last; + reg [0:0] mapper_rsp_payload_fragment_opcode; + reg [31:0] mapper_rsp_payload_fragment_data; + wire [2:0] mapper_rsp_payload_fragment_context; + wire _zz_mapper_rsp_ready; + reg _zz_mapper_rsp_ready_1; + wire _zz_io_bus_rsp_valid; + reg _zz_io_bus_rsp_valid_1; + reg _zz_io_bus_rsp_payload_last; + reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_bus_rsp_payload_fragment_data; + reg [2:0] _zz_io_bus_rsp_payload_fragment_context; + wire when_Stream_l375; + wire mapper_askWrite; + wire mapper_askRead; + wire io_bus_cmd_fire; + wire mapper_doWrite; + wire mapper_doRead; + wire when_BmbSlaveFactory_l33; + wire when_BmbSlaveFactory_l35; + reg [3:0] io_gpio_read_delay_1; + reg [3:0] syncronized; + reg [3:0] last; + reg _zz_io_gpio_write; + reg _zz_io_gpio_writeEnable; + reg _zz_io_gpio_write_1; + reg _zz_io_gpio_writeEnable_1; + reg _zz_io_gpio_write_2; + reg _zz_io_gpio_writeEnable_2; + reg _zz_io_gpio_write_3; + reg _zz_io_gpio_writeEnable_3; + reg [3:0] interrupt_enable_high; + reg [3:0] interrupt_enable_low; + reg [3:0] interrupt_enable_rise; + reg [3:0] interrupt_enable_fall; + wire [3:0] interrupt_valid; + reg _zz_mapper_rsp_payload_fragment_data; + reg _zz_mapper_rsp_payload_fragment_data_1; + reg _zz_mapper_rsp_payload_fragment_data_2; + reg _zz_mapper_rsp_payload_fragment_data_3; + reg _zz_mapper_rsp_payload_fragment_data_4; + reg _zz_mapper_rsp_payload_fragment_data_5; + reg _zz_mapper_rsp_payload_fragment_data_6; + reg _zz_mapper_rsp_payload_fragment_data_7; + + assign mapper_readErrorFlag = 1'b0; + assign mapper_writeErrorFlag = 1'b0; + assign mapper_readHaltTrigger = 1'b0; + assign mapper_writeHaltTrigger = 1'b0; + assign _zz_mapper_rsp_ready = (! (mapper_readHaltTrigger || mapper_writeHaltTrigger)); + assign mapper_rsp_ready = (_zz_mapper_rsp_ready_1 && _zz_mapper_rsp_ready); + always @(*) begin + _zz_mapper_rsp_ready_1 = io_bus_rsp_ready; + if(when_Stream_l375) begin + _zz_mapper_rsp_ready_1 = 1'b1; + end + end + + assign when_Stream_l375 = (! _zz_io_bus_rsp_valid); + assign _zz_io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; + assign io_bus_rsp_valid = _zz_io_bus_rsp_valid; + assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; + assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; + assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; + assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; + assign mapper_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign mapper_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign mapper_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign mapper_doRead = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign mapper_rsp_valid = io_bus_cmd_valid; + assign io_bus_cmd_ready = mapper_rsp_ready; + assign mapper_rsp_payload_last = 1'b1; + assign when_BmbSlaveFactory_l33 = (mapper_doWrite && mapper_writeErrorFlag); + always @(*) begin + if(when_BmbSlaveFactory_l33) begin + mapper_rsp_payload_fragment_opcode = 1'b1; + end else begin + if(when_BmbSlaveFactory_l35) begin + mapper_rsp_payload_fragment_opcode = 1'b1; + end else begin + mapper_rsp_payload_fragment_opcode = 1'b0; + end + end + end + + assign when_BmbSlaveFactory_l35 = (mapper_doRead && mapper_readErrorFlag); + always @(*) begin + mapper_rsp_payload_fragment_data = 32'h0; + case(io_bus_cmd_payload_fragment_address) + 8'h0 : begin + mapper_rsp_payload_fragment_data[0 : 0] = syncronized[0]; + mapper_rsp_payload_fragment_data[1 : 1] = syncronized[1]; + mapper_rsp_payload_fragment_data[2 : 2] = syncronized[2]; + mapper_rsp_payload_fragment_data[3 : 3] = syncronized[3]; + end + 8'h04 : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_io_gpio_write; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_io_gpio_write_1; + mapper_rsp_payload_fragment_data[2 : 2] = _zz_io_gpio_write_2; + mapper_rsp_payload_fragment_data[3 : 3] = _zz_io_gpio_write_3; + end + 8'h08 : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_io_gpio_writeEnable; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_io_gpio_writeEnable_1; + mapper_rsp_payload_fragment_data[2 : 2] = _zz_io_gpio_writeEnable_2; + mapper_rsp_payload_fragment_data[3 : 3] = _zz_io_gpio_writeEnable_3; + end + 8'h20 : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_mapper_rsp_payload_fragment_data; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_mapper_rsp_payload_fragment_data_4; + end + 8'h24 : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_mapper_rsp_payload_fragment_data_1; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_mapper_rsp_payload_fragment_data_5; + end + 8'h28 : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_mapper_rsp_payload_fragment_data_2; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_mapper_rsp_payload_fragment_data_6; + end + 8'h2c : begin + mapper_rsp_payload_fragment_data[0 : 0] = _zz_mapper_rsp_payload_fragment_data_3; + mapper_rsp_payload_fragment_data[1 : 1] = _zz_mapper_rsp_payload_fragment_data_7; + end + default : begin + end + endcase + end + + assign mapper_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; + always @(*) begin + io_gpio_write[0] = _zz_io_gpio_write; + io_gpio_write[1] = _zz_io_gpio_write_1; + io_gpio_write[2] = _zz_io_gpio_write_2; + io_gpio_write[3] = _zz_io_gpio_write_3; + end + + always @(*) begin + io_gpio_writeEnable[0] = _zz_io_gpio_writeEnable; + io_gpio_writeEnable[1] = _zz_io_gpio_writeEnable_1; + io_gpio_writeEnable[2] = _zz_io_gpio_writeEnable_2; + io_gpio_writeEnable[3] = _zz_io_gpio_writeEnable_3; + end + + assign interrupt_valid = ((((interrupt_enable_high & syncronized) | (interrupt_enable_low & (~ syncronized))) | (interrupt_enable_rise & (syncronized & (~ last)))) | (interrupt_enable_fall & ((~ syncronized) & last))); + always @(*) begin + io_interrupt[0] = interrupt_valid[0]; + io_interrupt[1] = interrupt_valid[1]; + io_interrupt[2] = 1'b0; + io_interrupt[3] = 1'b0; + end + + always @(*) begin + interrupt_enable_rise[0] = _zz_mapper_rsp_payload_fragment_data; + interrupt_enable_rise[1] = _zz_mapper_rsp_payload_fragment_data_4; + interrupt_enable_rise[2] = 1'b0; + interrupt_enable_rise[3] = 1'b0; + end + + always @(*) begin + interrupt_enable_fall[0] = _zz_mapper_rsp_payload_fragment_data_1; + interrupt_enable_fall[1] = _zz_mapper_rsp_payload_fragment_data_5; + interrupt_enable_fall[2] = 1'b0; + interrupt_enable_fall[3] = 1'b0; + end + + always @(*) begin + interrupt_enable_high[0] = _zz_mapper_rsp_payload_fragment_data_2; + interrupt_enable_high[1] = _zz_mapper_rsp_payload_fragment_data_6; + interrupt_enable_high[2] = 1'b0; + interrupt_enable_high[3] = 1'b0; + end + + always @(*) begin + interrupt_enable_low[0] = _zz_mapper_rsp_payload_fragment_data_3; + interrupt_enable_low[1] = _zz_mapper_rsp_payload_fragment_data_7; + interrupt_enable_low[2] = 1'b0; + interrupt_enable_low[3] = 1'b0; + end + + always @(posedge clk) begin + if(reset) begin + _zz_io_bus_rsp_valid_1 <= 1'b0; + _zz_io_gpio_writeEnable <= 1'b0; + _zz_io_gpio_writeEnable_1 <= 1'b0; + _zz_io_gpio_writeEnable_2 <= 1'b0; + _zz_io_gpio_writeEnable_3 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_1 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_2 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_3 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_4 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_5 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_6 <= 1'b0; + _zz_mapper_rsp_payload_fragment_data_7 <= 1'b0; + end else begin + if(_zz_mapper_rsp_ready_1) begin + _zz_io_bus_rsp_valid_1 <= (mapper_rsp_valid && _zz_mapper_rsp_ready); + end + case(io_bus_cmd_payload_fragment_address) + 8'h08 : begin + if(mapper_doWrite) begin + _zz_io_gpio_writeEnable <= io_bus_cmd_payload_fragment_data[0]; + _zz_io_gpio_writeEnable_1 <= io_bus_cmd_payload_fragment_data[1]; + _zz_io_gpio_writeEnable_2 <= io_bus_cmd_payload_fragment_data[2]; + _zz_io_gpio_writeEnable_3 <= io_bus_cmd_payload_fragment_data[3]; + end + end + 8'h20 : begin + if(mapper_doWrite) begin + _zz_mapper_rsp_payload_fragment_data <= io_bus_cmd_payload_fragment_data[0]; + _zz_mapper_rsp_payload_fragment_data_4 <= io_bus_cmd_payload_fragment_data[1]; + end + end + 8'h24 : begin + if(mapper_doWrite) begin + _zz_mapper_rsp_payload_fragment_data_1 <= io_bus_cmd_payload_fragment_data[0]; + _zz_mapper_rsp_payload_fragment_data_5 <= io_bus_cmd_payload_fragment_data[1]; + end + end + 8'h28 : begin + if(mapper_doWrite) begin + _zz_mapper_rsp_payload_fragment_data_2 <= io_bus_cmd_payload_fragment_data[0]; + _zz_mapper_rsp_payload_fragment_data_6 <= io_bus_cmd_payload_fragment_data[1]; + end + end + 8'h2c : begin + if(mapper_doWrite) begin + _zz_mapper_rsp_payload_fragment_data_3 <= io_bus_cmd_payload_fragment_data[0]; + _zz_mapper_rsp_payload_fragment_data_7 <= io_bus_cmd_payload_fragment_data[1]; + end + end + default : begin + end + endcase + end + end + + always @(posedge clk) begin + if(_zz_mapper_rsp_ready_1) begin + _zz_io_bus_rsp_payload_last <= mapper_rsp_payload_last; + _zz_io_bus_rsp_payload_fragment_opcode <= mapper_rsp_payload_fragment_opcode; + _zz_io_bus_rsp_payload_fragment_data <= mapper_rsp_payload_fragment_data; + _zz_io_bus_rsp_payload_fragment_context <= mapper_rsp_payload_fragment_context; + end + io_gpio_read_delay_1 <= io_gpio_read; + syncronized <= io_gpio_read_delay_1; + last <= syncronized; + case(io_bus_cmd_payload_fragment_address) + 8'h04 : begin + if(mapper_doWrite) begin + _zz_io_gpio_write <= io_bus_cmd_payload_fragment_data[0]; + _zz_io_gpio_write_1 <= io_bus_cmd_payload_fragment_data[1]; + _zz_io_gpio_write_2 <= io_bus_cmd_payload_fragment_data[2]; + _zz_io_gpio_write_3 <= io_bus_cmd_payload_fragment_data[3]; + end + end + default : begin + end + endcase + end + + +endmodule + +module Axi4PeripheralBmbI2cCtrl ( + input wire io_ctrl_cmd_valid, + output wire io_ctrl_cmd_ready, + input wire io_ctrl_cmd_payload_last, + input wire [0:0] io_ctrl_cmd_payload_fragment_opcode, + input wire [7:0] io_ctrl_cmd_payload_fragment_address, + input wire [1:0] io_ctrl_cmd_payload_fragment_length, + input wire [31:0] io_ctrl_cmd_payload_fragment_data, + input wire [2:0] io_ctrl_cmd_payload_fragment_context, + output wire io_ctrl_rsp_valid, + input wire io_ctrl_rsp_ready, + output wire io_ctrl_rsp_payload_last, + output wire [0:0] io_ctrl_rsp_payload_fragment_opcode, + output wire [31:0] io_ctrl_rsp_payload_fragment_data, + output wire [2:0] io_ctrl_rsp_payload_fragment_context, + output wire io_i2c_sda_write, + input wire io_i2c_sda_read, + output wire io_i2c_scl_write, + input wire io_i2c_scl_read, + output wire system_i2c_0_io_interrupt_source, + input wire clk, + input wire reset +); + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT = 4'd0; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE = 4'd1; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 = 4'd2; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 = 4'd3; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 = 4'd4; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW = 4'd5; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH = 4'd6; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART = 4'd7; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 = 4'd8; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 = 4'd9; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 = 4'd10; + localparam Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF = 4'd11; + localparam Axi4PeripheralI2cSlaveCmdMode_NONE = 3'd0; + localparam Axi4PeripheralI2cSlaveCmdMode_START = 3'd1; + localparam Axi4PeripheralI2cSlaveCmdMode_RESTART = 3'd2; + localparam Axi4PeripheralI2cSlaveCmdMode_STOP = 3'd3; + localparam Axi4PeripheralI2cSlaveCmdMode_DROP = 3'd4; + localparam Axi4PeripheralI2cSlaveCmdMode_DRIVE = 3'd5; + localparam Axi4PeripheralI2cSlaveCmdMode_READ = 3'd6; + + reg i2cCtrl_io_config_timeoutClear; + reg i2cCtrl_io_bus_rsp_valid; + reg i2cCtrl_io_bus_rsp_enable; + reg i2cCtrl_io_bus_rsp_data; + wire i2cCtrl_io_i2c_scl_write; + wire i2cCtrl_io_i2c_sda_write; + wire [2:0] i2cCtrl_io_bus_cmd_kind; + wire i2cCtrl_io_bus_cmd_data; + wire i2cCtrl_io_timeout; + wire i2cCtrl_io_internals_inFrame; + wire i2cCtrl_io_internals_sdaRead; + wire i2cCtrl_io_internals_sclRead; + wire [6:0] _zz_bridge_addressFilter_hits_0; + wire [6:0] _zz_bridge_addressFilter_hits_1; + wire [0:0] _zz_bridge_masterLogic_start; + wire [0:0] _zz_bridge_masterLogic_stop; + wire [0:0] _zz_bridge_masterLogic_drop; + wire [0:0] _zz_bridge_masterLogic_recover; + wire [11:0] _zz_bridge_masterLogic_timer_value; + wire [0:0] _zz_bridge_masterLogic_timer_value_1; + wire [0:0] _zz_bridge_masterLogic_fsm_dropped_start; + wire [0:0] _zz_bridge_masterLogic_fsm_dropped_stop; + wire [0:0] _zz_bridge_masterLogic_fsm_dropped_recover; + wire [2:0] _zz_io_bus_rsp_data; + wire [2:0] _zz_bridge_rxData_value; + wire [0:0] _zz_bridge_interruptCtrl_start_flag; + wire [0:0] _zz_bridge_interruptCtrl_restart_flag; + wire [0:0] _zz_bridge_interruptCtrl_end_flag; + wire [0:0] _zz_bridge_interruptCtrl_drop_flag; + wire [0:0] _zz_bridge_interruptCtrl_filterGen_flag; + wire [0:0] _zz_bridge_interruptCtrl_clockGenExit_flag; + wire [0:0] _zz_bridge_interruptCtrl_clockGenEnter_flag; + wire busCtrl_readErrorFlag; + wire busCtrl_writeErrorFlag; + wire busCtrl_readHaltTrigger; + wire busCtrl_writeHaltTrigger; + wire busCtrl_rsp_valid; + wire busCtrl_rsp_ready; + wire busCtrl_rsp_payload_last; + reg [0:0] busCtrl_rsp_payload_fragment_opcode; + reg [31:0] busCtrl_rsp_payload_fragment_data; + wire [2:0] busCtrl_rsp_payload_fragment_context; + wire _zz_busCtrl_rsp_ready; + reg _zz_busCtrl_rsp_ready_1; + wire _zz_io_ctrl_rsp_valid; + reg _zz_io_ctrl_rsp_valid_1; + reg _zz_io_ctrl_rsp_payload_last; + reg [0:0] _zz_io_ctrl_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_ctrl_rsp_payload_fragment_data; + reg [2:0] _zz_io_ctrl_rsp_payload_fragment_context; + wire when_Stream_l375; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire io_ctrl_cmd_fire; + wire busCtrl_doWrite; + wire busCtrl_doRead; + wire when_BmbSlaveFactory_l33; + wire when_BmbSlaveFactory_l35; + wire bridge_busCtrlWithOffset_readErrorFlag; + wire bridge_busCtrlWithOffset_writeErrorFlag; + reg bridge_frameReset; + reg bridge_i2cBuffer_sda_write; + wire bridge_i2cBuffer_sda_read; + reg bridge_i2cBuffer_scl_write; + wire bridge_i2cBuffer_scl_read; + reg bridge_rxData_event; + reg bridge_rxData_listen; + reg bridge_rxData_valid; + reg [7:0] bridge_rxData_value; + reg when_I2cCtrl_l224; + reg bridge_rxAck_listen; + reg bridge_rxAck_valid; + reg bridge_rxAck_value; + reg when_I2cCtrl_l237; + reg bridge_txData_valid; + reg bridge_txData_repeat; + reg bridge_txData_enable; + reg [7:0] bridge_txData_value; + reg bridge_txData_forceDisable; + reg bridge_txData_disableOnDataConflict; + reg bridge_txAck_valid; + reg bridge_txAck_repeat; + reg bridge_txAck_enable; + reg bridge_txAck_value; + reg bridge_txAck_forceAck; + reg bridge_txAck_disableOnDataConflict; + reg bridge_addressFilter_addresses_0_enable; + reg [9:0] bridge_addressFilter_addresses_0_value; + reg bridge_addressFilter_addresses_0_is10Bit; + reg bridge_addressFilter_addresses_1_enable; + reg [9:0] bridge_addressFilter_addresses_1_value; + reg bridge_addressFilter_addresses_1_is10Bit; + reg [1:0] bridge_addressFilter_state; + reg [7:0] bridge_addressFilter_byte0; + reg [7:0] bridge_addressFilter_byte1; + wire bridge_addressFilter_byte0Is10Bit; + wire bridge_addressFilter_hits_0; + wire bridge_addressFilter_hits_1; + wire when_I2cCtrl_l306; + wire _zz_when_I2cCtrl_l310; + reg _zz_when_I2cCtrl_l310_1; + wire when_I2cCtrl_l310; + reg bridge_masterLogic_start; + reg when_BusSlaveFactory_l377; + wire when_BusSlaveFactory_l379; + reg bridge_masterLogic_stop; + reg when_BusSlaveFactory_l377_1; + wire when_BusSlaveFactory_l379_1; + reg bridge_masterLogic_drop; + reg when_BusSlaveFactory_l377_2; + wire when_BusSlaveFactory_l379_2; + reg bridge_masterLogic_recover; + reg when_BusSlaveFactory_l377_3; + wire when_BusSlaveFactory_l379_3; + reg [11:0] bridge_masterLogic_timer_value; + reg [11:0] bridge_masterLogic_timer_tLow; + reg [11:0] bridge_masterLogic_timer_tHigh; + reg [11:0] bridge_masterLogic_timer_tBuf; + wire bridge_masterLogic_timer_done; + wire bridge_masterLogic_txReady; + wire bridge_masterLogic_fsm_wantExit; + reg bridge_masterLogic_fsm_wantStart; + wire bridge_masterLogic_fsm_wantKill; + reg bridge_masterLogic_fsm_dropped_start; + reg bridge_masterLogic_fsm_dropped_stop; + reg bridge_masterLogic_fsm_dropped_recover; + reg bridge_masterLogic_fsm_dropped_trigger; + reg bridge_masterLogic_fsm_inFrameLate; + wire when_I2cCtrl_l363; + wire when_I2cCtrl_l363_1; + wire bridge_masterLogic_fsm_outOfSync; + wire bridge_masterLogic_fsm_isBusy; + reg when_BusSlaveFactory_l341; + wire when_BusSlaveFactory_l347; + reg when_BusSlaveFactory_l341_1; + wire when_BusSlaveFactory_l347_1; + reg when_BusSlaveFactory_l341_2; + wire when_BusSlaveFactory_l347_2; + reg [2:0] bridge_dataCounter; + reg bridge_inAckState; + reg bridge_wasntAck; + wire when_I2cCtrl_l523; + wire when_I2cCtrl_l546; + wire when_I2cCtrl_l566; + wire when_I2cCtrl_l570; + wire when_I2cCtrl_l574; + wire when_I2cCtrl_l578; + wire when_I2cCtrl_l588; + wire when_I2cCtrl_l601; + reg bridge_interruptCtrl_rxDataEnable; + reg bridge_interruptCtrl_rxAckEnable; + reg bridge_interruptCtrl_txDataEnable; + reg bridge_interruptCtrl_txAckEnable; + reg bridge_interruptCtrl_interrupt; + wire when_I2cCtrl_l634; + reg bridge_interruptCtrl_start_enable; + reg bridge_interruptCtrl_start_flag; + wire when_I2cCtrl_l634_1; + reg when_BusSlaveFactory_l341_3; + wire when_BusSlaveFactory_l347_3; + wire when_I2cCtrl_l634_2; + reg bridge_interruptCtrl_restart_enable; + reg bridge_interruptCtrl_restart_flag; + wire when_I2cCtrl_l634_3; + reg when_BusSlaveFactory_l341_4; + wire when_BusSlaveFactory_l347_4; + wire when_I2cCtrl_l634_4; + reg bridge_interruptCtrl_end_enable; + reg bridge_interruptCtrl_end_flag; + wire when_I2cCtrl_l634_5; + reg when_BusSlaveFactory_l341_5; + wire when_BusSlaveFactory_l347_5; + wire when_I2cCtrl_l634_6; + reg bridge_interruptCtrl_drop_enable; + reg bridge_interruptCtrl_drop_flag; + wire when_I2cCtrl_l634_7; + reg when_BusSlaveFactory_l341_6; + wire when_BusSlaveFactory_l347_6; + wire _zz_when_I2cCtrl_l634; + reg _zz_when_I2cCtrl_l634_1; + wire when_I2cCtrl_l634_8; + reg bridge_interruptCtrl_filterGen_enable; + reg bridge_interruptCtrl_filterGen_flag; + wire when_I2cCtrl_l634_9; + reg when_BusSlaveFactory_l341_7; + wire when_BusSlaveFactory_l347_7; + reg bridge_masterLogic_fsm_isBusy_regNext; + wire when_I2cCtrl_l634_10; + reg bridge_interruptCtrl_clockGenExit_enable; + reg bridge_interruptCtrl_clockGenExit_flag; + wire when_I2cCtrl_l634_11; + reg when_BusSlaveFactory_l341_8; + wire when_BusSlaveFactory_l347_8; + reg bridge_masterLogic_fsm_isBusy_regNext_1; + wire when_I2cCtrl_l634_12; + reg bridge_interruptCtrl_clockGenEnter_enable; + reg bridge_interruptCtrl_clockGenEnter_flag; + wire when_I2cCtrl_l634_13; + reg when_BusSlaveFactory_l341_9; + wire when_BusSlaveFactory_l347_9; + reg [9:0] _zz_io_config_samplingClockDivider; + reg [19:0] _zz_io_config_timeout; + reg [5:0] _zz_io_config_tsuData; + reg bridge_timeoutClear; + wire when_I2cCtrl_l659; + reg [3:0] bridge_masterLogic_fsm_stateReg; + reg [3:0] bridge_masterLogic_fsm_stateNext; + reg i2cCtrl_io_internals_inFrame_regNext; + wire when_I2cCtrl_l367; + wire when_I2cCtrl_l369; + wire when_I2cCtrl_l380; + wire when_I2cCtrl_l392; + wire when_I2cCtrl_l418; + wire when_I2cCtrl_l422; + wire when_I2cCtrl_l442; + wire when_I2cCtrl_l450; + wire when_I2cCtrl_l474; + wire when_StateMachine_l253; + wire when_StateMachine_l253_1; + wire when_StateMachine_l253_2; + wire when_StateMachine_l253_3; + wire when_StateMachine_l253_4; + wire when_StateMachine_l253_5; + wire when_I2cCtrl_l350; + reg bridge_slaveOverride_sda; + reg bridge_slaveOverride_scl; + wire when_I2cCtrl_l673; + wire when_I2cCtrl_l674; + reg bridge_i2cBuffer_scl_write_regNext; + reg bridge_i2cBuffer_sda_write_regNext; + `ifndef SYNTHESIS + reg [55:0] bridge_masterLogic_fsm_stateReg_string; + reg [55:0] bridge_masterLogic_fsm_stateNext_string; + `endif + + + assign _zz_bridge_addressFilter_hits_0 = (bridge_addressFilter_byte0 >>> 1'd1); + assign _zz_bridge_addressFilter_hits_1 = (bridge_addressFilter_byte0 >>> 1'd1); + assign _zz_bridge_masterLogic_start = 1'b1; + assign _zz_bridge_masterLogic_stop = 1'b1; + assign _zz_bridge_masterLogic_drop = 1'b1; + assign _zz_bridge_masterLogic_recover = 1'b1; + assign _zz_bridge_masterLogic_timer_value_1 = (! bridge_masterLogic_timer_done); + assign _zz_bridge_masterLogic_timer_value = {11'd0, _zz_bridge_masterLogic_timer_value_1}; + assign _zz_bridge_masterLogic_fsm_dropped_start = 1'b0; + assign _zz_bridge_masterLogic_fsm_dropped_stop = 1'b0; + assign _zz_bridge_masterLogic_fsm_dropped_recover = 1'b0; + assign _zz_io_bus_rsp_data = (3'b111 - bridge_dataCounter); + assign _zz_bridge_rxData_value = (3'b111 - bridge_dataCounter); + assign _zz_bridge_interruptCtrl_start_flag = 1'b0; + assign _zz_bridge_interruptCtrl_restart_flag = 1'b0; + assign _zz_bridge_interruptCtrl_end_flag = 1'b0; + assign _zz_bridge_interruptCtrl_drop_flag = 1'b0; + assign _zz_bridge_interruptCtrl_filterGen_flag = 1'b0; + assign _zz_bridge_interruptCtrl_clockGenExit_flag = 1'b0; + assign _zz_bridge_interruptCtrl_clockGenEnter_flag = 1'b0; + Axi4PeripheralI2cSlave i2cCtrl ( + .io_i2c_sda_write (i2cCtrl_io_i2c_sda_write ), //o + .io_i2c_sda_read (bridge_i2cBuffer_sda_read ), //i + .io_i2c_scl_write (i2cCtrl_io_i2c_scl_write ), //o + .io_i2c_scl_read (bridge_i2cBuffer_scl_read ), //i + .io_config_samplingClockDivider (_zz_io_config_samplingClockDivider[9:0]), //i + .io_config_timeout (_zz_io_config_timeout[19:0] ), //i + .io_config_tsuData (_zz_io_config_tsuData[5:0] ), //i + .io_config_timeoutClear (i2cCtrl_io_config_timeoutClear ), //i + .io_bus_cmd_kind (i2cCtrl_io_bus_cmd_kind[2:0] ), //o + .io_bus_cmd_data (i2cCtrl_io_bus_cmd_data ), //o + .io_bus_rsp_valid (i2cCtrl_io_bus_rsp_valid ), //i + .io_bus_rsp_enable (i2cCtrl_io_bus_rsp_enable ), //i + .io_bus_rsp_data (i2cCtrl_io_bus_rsp_data ), //i + .io_timeout (i2cCtrl_io_timeout ), //o + .io_internals_inFrame (i2cCtrl_io_internals_inFrame ), //o + .io_internals_sdaRead (i2cCtrl_io_internals_sdaRead ), //o + .io_internals_sclRead (i2cCtrl_io_internals_sclRead ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + initial begin + `ifndef SYNTHESIS + _zz_io_config_timeout = {$urandom}; + _zz_io_config_tsuData = {$urandom}; + `endif + end + + `ifndef SYNTHESIS + always @(*) begin + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT : bridge_masterLogic_fsm_stateReg_string = "BOOT "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : bridge_masterLogic_fsm_stateReg_string = "IDLE "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : bridge_masterLogic_fsm_stateReg_string = "START1 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : bridge_masterLogic_fsm_stateReg_string = "START2 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : bridge_masterLogic_fsm_stateReg_string = "START3 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : bridge_masterLogic_fsm_stateReg_string = "LOW "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : bridge_masterLogic_fsm_stateReg_string = "HIGH "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : bridge_masterLogic_fsm_stateReg_string = "RESTART"; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : bridge_masterLogic_fsm_stateReg_string = "STOP1 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : bridge_masterLogic_fsm_stateReg_string = "STOP2 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : bridge_masterLogic_fsm_stateReg_string = "STOP3 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : bridge_masterLogic_fsm_stateReg_string = "TBUF "; + default : bridge_masterLogic_fsm_stateReg_string = "???????"; + endcase + end + always @(*) begin + case(bridge_masterLogic_fsm_stateNext) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT : bridge_masterLogic_fsm_stateNext_string = "BOOT "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : bridge_masterLogic_fsm_stateNext_string = "IDLE "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : bridge_masterLogic_fsm_stateNext_string = "START1 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : bridge_masterLogic_fsm_stateNext_string = "START2 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : bridge_masterLogic_fsm_stateNext_string = "START3 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : bridge_masterLogic_fsm_stateNext_string = "LOW "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : bridge_masterLogic_fsm_stateNext_string = "HIGH "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : bridge_masterLogic_fsm_stateNext_string = "RESTART"; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : bridge_masterLogic_fsm_stateNext_string = "STOP1 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : bridge_masterLogic_fsm_stateNext_string = "STOP2 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : bridge_masterLogic_fsm_stateNext_string = "STOP3 "; + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : bridge_masterLogic_fsm_stateNext_string = "TBUF "; + default : bridge_masterLogic_fsm_stateNext_string = "???????"; + endcase + end + `endif + + assign busCtrl_readErrorFlag = 1'b0; + assign busCtrl_writeErrorFlag = 1'b0; + assign busCtrl_readHaltTrigger = 1'b0; + assign busCtrl_writeHaltTrigger = 1'b0; + assign _zz_busCtrl_rsp_ready = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); + assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready_1 && _zz_busCtrl_rsp_ready); + always @(*) begin + _zz_busCtrl_rsp_ready_1 = io_ctrl_rsp_ready; + if(when_Stream_l375) begin + _zz_busCtrl_rsp_ready_1 = 1'b1; + end + end + + assign when_Stream_l375 = (! _zz_io_ctrl_rsp_valid); + assign _zz_io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid_1; + assign io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid; + assign io_ctrl_rsp_payload_last = _zz_io_ctrl_rsp_payload_last; + assign io_ctrl_rsp_payload_fragment_opcode = _zz_io_ctrl_rsp_payload_fragment_opcode; + assign io_ctrl_rsp_payload_fragment_data = _zz_io_ctrl_rsp_payload_fragment_data; + assign io_ctrl_rsp_payload_fragment_context = _zz_io_ctrl_rsp_payload_fragment_context; + assign busCtrl_askWrite = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_askRead = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign io_ctrl_cmd_fire = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); + assign busCtrl_doWrite = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_doRead = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign busCtrl_rsp_valid = io_ctrl_cmd_valid; + assign io_ctrl_cmd_ready = busCtrl_rsp_ready; + assign busCtrl_rsp_payload_last = 1'b1; + assign when_BmbSlaveFactory_l33 = (busCtrl_doWrite && busCtrl_writeErrorFlag); + always @(*) begin + if(when_BmbSlaveFactory_l33) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + if(when_BmbSlaveFactory_l35) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + busCtrl_rsp_payload_fragment_opcode = 1'b0; + end + end + end + + assign when_BmbSlaveFactory_l35 = (busCtrl_doRead && busCtrl_readErrorFlag); + always @(*) begin + busCtrl_rsp_payload_fragment_data = 32'h0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h08 : begin + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_rxData_valid; + busCtrl_rsp_payload_fragment_data[7 : 0] = bridge_rxData_value; + end + 8'h0c : begin + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_rxAck_valid; + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_rxAck_value; + end + 8'h0 : begin + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_txData_valid; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_txData_enable; + end + 8'h04 : begin + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_txAck_valid; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_txAck_enable; + end + 8'h80 : begin + busCtrl_rsp_payload_fragment_data[1 : 0] = {bridge_addressFilter_hits_1,bridge_addressFilter_hits_0}; + end + 8'h84 : begin + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_addressFilter_byte0[0]; + end + 8'h40 : begin + busCtrl_rsp_payload_fragment_data[4 : 4] = bridge_masterLogic_start; + busCtrl_rsp_payload_fragment_data[5 : 5] = bridge_masterLogic_stop; + busCtrl_rsp_payload_fragment_data[6 : 6] = bridge_masterLogic_drop; + busCtrl_rsp_payload_fragment_data[7 : 7] = bridge_masterLogic_recover; + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_masterLogic_fsm_isBusy; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_masterLogic_fsm_dropped_start; + busCtrl_rsp_payload_fragment_data[10 : 10] = bridge_masterLogic_fsm_dropped_stop; + busCtrl_rsp_payload_fragment_data[11 : 11] = bridge_masterLogic_fsm_dropped_recover; + end + 8'h20 : begin + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_interruptCtrl_rxDataEnable; + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_interruptCtrl_rxAckEnable; + busCtrl_rsp_payload_fragment_data[2 : 2] = bridge_interruptCtrl_txDataEnable; + busCtrl_rsp_payload_fragment_data[3 : 3] = bridge_interruptCtrl_txAckEnable; + busCtrl_rsp_payload_fragment_data[4 : 4] = bridge_interruptCtrl_start_enable; + busCtrl_rsp_payload_fragment_data[5 : 5] = bridge_interruptCtrl_restart_enable; + busCtrl_rsp_payload_fragment_data[6 : 6] = bridge_interruptCtrl_end_enable; + busCtrl_rsp_payload_fragment_data[7 : 7] = bridge_interruptCtrl_drop_enable; + busCtrl_rsp_payload_fragment_data[17 : 17] = bridge_interruptCtrl_filterGen_enable; + busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_interruptCtrl_clockGenExit_enable; + busCtrl_rsp_payload_fragment_data[16 : 16] = bridge_interruptCtrl_clockGenEnter_enable; + end + 8'h24 : begin + busCtrl_rsp_payload_fragment_data[4 : 4] = bridge_interruptCtrl_start_flag; + busCtrl_rsp_payload_fragment_data[5 : 5] = bridge_interruptCtrl_restart_flag; + busCtrl_rsp_payload_fragment_data[6 : 6] = bridge_interruptCtrl_end_flag; + busCtrl_rsp_payload_fragment_data[7 : 7] = bridge_interruptCtrl_drop_flag; + busCtrl_rsp_payload_fragment_data[17 : 17] = bridge_interruptCtrl_filterGen_flag; + busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_interruptCtrl_clockGenExit_flag; + busCtrl_rsp_payload_fragment_data[16 : 16] = bridge_interruptCtrl_clockGenEnter_flag; + end + 8'h44 : begin + busCtrl_rsp_payload_fragment_data[0 : 0] = i2cCtrl_io_internals_inFrame; + busCtrl_rsp_payload_fragment_data[1 : 1] = i2cCtrl_io_internals_sdaRead; + busCtrl_rsp_payload_fragment_data[2 : 2] = i2cCtrl_io_internals_sclRead; + end + 8'h48 : begin + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_slaveOverride_sda; + busCtrl_rsp_payload_fragment_data[2 : 2] = bridge_slaveOverride_scl; + end + default : begin + end + endcase + end + + assign busCtrl_rsp_payload_fragment_context = io_ctrl_cmd_payload_fragment_context; + assign bridge_busCtrlWithOffset_readErrorFlag = 1'b0; + assign bridge_busCtrlWithOffset_writeErrorFlag = 1'b0; + always @(*) begin + bridge_frameReset = 1'b0; + case(i2cCtrl_io_bus_cmd_kind) + Axi4PeripheralI2cSlaveCmdMode_START : begin + bridge_frameReset = 1'b1; + end + Axi4PeripheralI2cSlaveCmdMode_RESTART : begin + bridge_frameReset = 1'b1; + end + Axi4PeripheralI2cSlaveCmdMode_STOP : begin + bridge_frameReset = 1'b1; + end + Axi4PeripheralI2cSlaveCmdMode_DROP : begin + bridge_frameReset = 1'b1; + end + default : begin + end + endcase + end + + always @(*) begin + bridge_i2cBuffer_sda_write = i2cCtrl_io_i2c_sda_write; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + bridge_i2cBuffer_sda_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + bridge_i2cBuffer_sda_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + bridge_i2cBuffer_sda_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + bridge_i2cBuffer_sda_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + end + endcase + if(when_I2cCtrl_l673) begin + bridge_i2cBuffer_sda_write = 1'b0; + end + end + + always @(*) begin + bridge_i2cBuffer_scl_write = i2cCtrl_io_i2c_scl_write; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + bridge_i2cBuffer_scl_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + if(bridge_masterLogic_timer_done) begin + if(when_I2cCtrl_l418) begin + bridge_i2cBuffer_scl_write = 1'b0; + end else begin + if(when_I2cCtrl_l422) begin + bridge_i2cBuffer_scl_write = 1'b0; + end + end + end else begin + bridge_i2cBuffer_scl_write = 1'b0; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + bridge_i2cBuffer_scl_write = 1'b0; + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + end + endcase + if(when_I2cCtrl_l674) begin + bridge_i2cBuffer_scl_write = 1'b0; + end + end + + always @(*) begin + when_I2cCtrl_l224 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h08 : begin + if(busCtrl_doRead) begin + when_I2cCtrl_l224 = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + when_I2cCtrl_l237 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h0c : begin + if(busCtrl_doRead) begin + when_I2cCtrl_l237 = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + bridge_txData_forceDisable = 1'b0; + if(when_I2cCtrl_l601) begin + bridge_txData_forceDisable = 1'b0; + end + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + if(bridge_masterLogic_timer_done) begin + if(when_I2cCtrl_l418) begin + bridge_txData_forceDisable = 1'b1; + end else begin + if(when_I2cCtrl_l422) begin + bridge_txData_forceDisable = 1'b1; + end + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + end + endcase + end + + always @(*) begin + bridge_txAck_forceAck = 1'b0; + if(when_I2cCtrl_l306) begin + bridge_txAck_forceAck = 1'b1; + end + end + + assign bridge_addressFilter_byte0Is10Bit = (bridge_addressFilter_byte0[7 : 3] == 5'h1e); + assign bridge_addressFilter_hits_0 = (bridge_addressFilter_addresses_0_enable && ((! bridge_addressFilter_addresses_0_is10Bit) ? ((_zz_bridge_addressFilter_hits_0 == bridge_addressFilter_addresses_0_value[6 : 0]) && (bridge_addressFilter_state != 2'b00)) : (({bridge_addressFilter_byte0[2 : 1],bridge_addressFilter_byte1} == bridge_addressFilter_addresses_0_value) && (bridge_addressFilter_state == 2'b10)))); + assign bridge_addressFilter_hits_1 = (bridge_addressFilter_addresses_1_enable && ((! bridge_addressFilter_addresses_1_is10Bit) ? ((_zz_bridge_addressFilter_hits_1 == bridge_addressFilter_addresses_1_value[6 : 0]) && (bridge_addressFilter_state != 2'b00)) : (({bridge_addressFilter_byte0[2 : 1],bridge_addressFilter_byte1} == bridge_addressFilter_addresses_1_value) && (bridge_addressFilter_state == 2'b10)))); + assign when_I2cCtrl_l306 = ((bridge_addressFilter_byte0Is10Bit && (bridge_addressFilter_state == 2'b01)) && (|{((bridge_addressFilter_addresses_1_enable && bridge_addressFilter_addresses_1_is10Bit) && (bridge_addressFilter_byte0[2 : 1] == bridge_addressFilter_addresses_1_value[9 : 8])),((bridge_addressFilter_addresses_0_enable && bridge_addressFilter_addresses_0_is10Bit) && (bridge_addressFilter_byte0[2 : 1] == bridge_addressFilter_addresses_0_value[9 : 8]))})); + assign _zz_when_I2cCtrl_l310 = (|{bridge_addressFilter_hits_1,bridge_addressFilter_hits_0}); + assign when_I2cCtrl_l310 = (_zz_when_I2cCtrl_l310 && (! _zz_when_I2cCtrl_l310_1)); + always @(*) begin + when_BusSlaveFactory_l377 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l377 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379 = io_ctrl_cmd_payload_fragment_data[4]; + always @(*) begin + when_BusSlaveFactory_l377_1 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l377_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_1 = io_ctrl_cmd_payload_fragment_data[5]; + always @(*) begin + when_BusSlaveFactory_l377_2 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l377_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_2 = io_ctrl_cmd_payload_fragment_data[6]; + always @(*) begin + when_BusSlaveFactory_l377_3 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l377_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_3 = io_ctrl_cmd_payload_fragment_data[7]; + assign bridge_masterLogic_timer_done = (bridge_masterLogic_timer_value == 12'h0); + assign bridge_masterLogic_fsm_wantExit = 1'b0; + always @(*) begin + bridge_masterLogic_fsm_wantStart = 1'b0; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + bridge_masterLogic_fsm_wantStart = 1'b1; + end + endcase + end + + assign bridge_masterLogic_fsm_wantKill = 1'b0; + always @(*) begin + bridge_masterLogic_fsm_dropped_trigger = 1'b0; + if(when_I2cCtrl_l350) begin + bridge_masterLogic_fsm_dropped_trigger = 1'b1; + end + end + + assign when_I2cCtrl_l363 = (! i2cCtrl_io_internals_sclRead); + assign when_I2cCtrl_l363_1 = (! i2cCtrl_io_internals_inFrame); + assign bridge_masterLogic_fsm_outOfSync = ((! i2cCtrl_io_internals_inFrame) && ((! i2cCtrl_io_internals_sdaRead) || (! i2cCtrl_io_internals_sclRead))); + assign bridge_masterLogic_fsm_isBusy = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE)) && (! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF))); + always @(*) begin + when_BusSlaveFactory_l341 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347 = io_ctrl_cmd_payload_fragment_data[9]; + always @(*) begin + when_BusSlaveFactory_l341_1 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_1 = io_ctrl_cmd_payload_fragment_data[10]; + always @(*) begin + when_BusSlaveFactory_l341_2 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h40 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_2 = io_ctrl_cmd_payload_fragment_data[11]; + assign bridge_masterLogic_txReady = (bridge_inAckState ? bridge_txAck_valid : bridge_txData_valid); + assign when_I2cCtrl_l523 = (! bridge_inAckState); + always @(*) begin + if(when_I2cCtrl_l523) begin + i2cCtrl_io_bus_rsp_valid = ((bridge_txData_valid && (! (bridge_rxData_valid && bridge_rxData_listen))) && (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DRIVE)); + if(bridge_txData_forceDisable) begin + i2cCtrl_io_bus_rsp_valid = 1'b1; + end + end else begin + i2cCtrl_io_bus_rsp_valid = ((bridge_txAck_valid && (! (bridge_rxAck_valid && bridge_rxAck_listen))) && (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DRIVE)); + if(bridge_txAck_forceAck) begin + i2cCtrl_io_bus_rsp_valid = 1'b1; + end + end + if(when_I2cCtrl_l546) begin + i2cCtrl_io_bus_rsp_valid = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DRIVE); + end + end + + always @(*) begin + if(when_I2cCtrl_l523) begin + i2cCtrl_io_bus_rsp_enable = bridge_txData_enable; + if(bridge_txData_forceDisable) begin + i2cCtrl_io_bus_rsp_enable = 1'b0; + end + end else begin + i2cCtrl_io_bus_rsp_enable = bridge_txAck_enable; + if(bridge_txAck_forceAck) begin + i2cCtrl_io_bus_rsp_enable = 1'b1; + end + end + if(when_I2cCtrl_l546) begin + i2cCtrl_io_bus_rsp_enable = 1'b0; + end + end + + always @(*) begin + if(when_I2cCtrl_l523) begin + i2cCtrl_io_bus_rsp_data = bridge_txData_value[_zz_io_bus_rsp_data]; + end else begin + i2cCtrl_io_bus_rsp_data = bridge_txAck_value; + if(bridge_txAck_forceAck) begin + i2cCtrl_io_bus_rsp_data = 1'b0; + end + end + end + + assign when_I2cCtrl_l546 = (bridge_wasntAck && (! bridge_masterLogic_fsm_isBusy)); + assign when_I2cCtrl_l566 = (! bridge_inAckState); + assign when_I2cCtrl_l570 = (i2cCtrl_io_bus_rsp_data != i2cCtrl_io_bus_cmd_data); + assign when_I2cCtrl_l574 = (bridge_dataCounter == 3'b111); + assign when_I2cCtrl_l578 = (bridge_txData_valid && (! bridge_txData_repeat)); + assign when_I2cCtrl_l588 = (bridge_txAck_valid && (! bridge_txAck_repeat)); + assign when_I2cCtrl_l601 = ((i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_STOP) || (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DROP)); + always @(*) begin + bridge_interruptCtrl_interrupt = ((((bridge_interruptCtrl_rxDataEnable && bridge_rxData_valid) || (bridge_interruptCtrl_rxAckEnable && bridge_rxAck_valid)) || (bridge_interruptCtrl_txDataEnable && (! bridge_txData_valid))) || (bridge_interruptCtrl_txAckEnable && (! bridge_txAck_valid))); + if(bridge_interruptCtrl_start_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_restart_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_end_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_drop_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_filterGen_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_clockGenExit_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + if(bridge_interruptCtrl_clockGenEnter_flag) begin + bridge_interruptCtrl_interrupt = 1'b1; + end + end + + assign when_I2cCtrl_l634 = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_START); + assign when_I2cCtrl_l634_1 = (! bridge_interruptCtrl_start_enable); + always @(*) begin + when_BusSlaveFactory_l341_3 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_3 = io_ctrl_cmd_payload_fragment_data[4]; + assign when_I2cCtrl_l634_2 = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_RESTART); + assign when_I2cCtrl_l634_3 = (! bridge_interruptCtrl_restart_enable); + always @(*) begin + when_BusSlaveFactory_l341_4 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_4 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_4 = io_ctrl_cmd_payload_fragment_data[5]; + assign when_I2cCtrl_l634_4 = (i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_STOP); + assign when_I2cCtrl_l634_5 = (! bridge_interruptCtrl_end_enable); + always @(*) begin + when_BusSlaveFactory_l341_5 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_5 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_5 = io_ctrl_cmd_payload_fragment_data[6]; + assign when_I2cCtrl_l634_6 = ((i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DROP) || bridge_masterLogic_fsm_dropped_trigger); + assign when_I2cCtrl_l634_7 = (! bridge_interruptCtrl_drop_enable); + always @(*) begin + when_BusSlaveFactory_l341_6 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_6 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_6 = io_ctrl_cmd_payload_fragment_data[7]; + assign _zz_when_I2cCtrl_l634 = (|{bridge_addressFilter_hits_1,bridge_addressFilter_hits_0}); + assign when_I2cCtrl_l634_8 = (_zz_when_I2cCtrl_l634 && (! _zz_when_I2cCtrl_l634_1)); + assign when_I2cCtrl_l634_9 = (! bridge_interruptCtrl_filterGen_enable); + always @(*) begin + when_BusSlaveFactory_l341_7 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_7 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_7 = io_ctrl_cmd_payload_fragment_data[17]; + assign when_I2cCtrl_l634_10 = ((! bridge_masterLogic_fsm_isBusy) && bridge_masterLogic_fsm_isBusy_regNext); + assign when_I2cCtrl_l634_11 = (! bridge_interruptCtrl_clockGenExit_enable); + always @(*) begin + when_BusSlaveFactory_l341_8 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_8 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_8 = io_ctrl_cmd_payload_fragment_data[15]; + assign when_I2cCtrl_l634_12 = (bridge_masterLogic_fsm_isBusy && (! bridge_masterLogic_fsm_isBusy_regNext_1)); + assign when_I2cCtrl_l634_13 = (! bridge_interruptCtrl_clockGenEnter_enable); + always @(*) begin + when_BusSlaveFactory_l341_9 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 8'h24 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_9 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_9 = io_ctrl_cmd_payload_fragment_data[16]; + always @(*) begin + i2cCtrl_io_config_timeoutClear = bridge_timeoutClear; + if(when_I2cCtrl_l659) begin + i2cCtrl_io_config_timeoutClear = 1'b1; + end + end + + assign when_I2cCtrl_l659 = ((! i2cCtrl_io_internals_inFrame) && (! bridge_masterLogic_fsm_isBusy)); + always @(*) begin + bridge_masterLogic_fsm_stateNext = bridge_masterLogic_fsm_stateReg; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + if(when_I2cCtrl_l367) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF; + end else begin + if(when_I2cCtrl_l369) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1; + end else begin + if(bridge_masterLogic_recover) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW; + end + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + if(when_I2cCtrl_l380) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + if(when_I2cCtrl_l392) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + if(bridge_masterLogic_timer_done) begin + if(when_I2cCtrl_l418) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1; + end else begin + if(when_I2cCtrl_l422) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART; + end else begin + if(i2cCtrl_io_internals_sclRead) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH; + end + end + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + if(when_I2cCtrl_l442) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + if(!when_I2cCtrl_l450) begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1; + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + if(!when_I2cCtrl_l474) begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3; + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + if(i2cCtrl_io_internals_sdaRead) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE; + end + end + default : begin + end + endcase + if(when_I2cCtrl_l350) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF; + end + if(bridge_masterLogic_fsm_wantStart) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE; + end + if(bridge_masterLogic_fsm_wantKill) begin + bridge_masterLogic_fsm_stateNext = Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT; + end + end + + assign when_I2cCtrl_l367 = ((! i2cCtrl_io_internals_inFrame) && i2cCtrl_io_internals_inFrame_regNext); + assign when_I2cCtrl_l369 = (bridge_masterLogic_start && (! bridge_masterLogic_fsm_inFrameLate)); + assign when_I2cCtrl_l380 = (! bridge_masterLogic_fsm_outOfSync); + assign when_I2cCtrl_l392 = (bridge_masterLogic_timer_done || (! i2cCtrl_io_internals_sclRead)); + assign when_I2cCtrl_l418 = ((bridge_masterLogic_stop && (! bridge_inAckState)) || (bridge_masterLogic_recover && i2cCtrl_io_internals_sdaRead)); + assign when_I2cCtrl_l422 = (bridge_masterLogic_start && (! bridge_inAckState)); + assign when_I2cCtrl_l442 = (bridge_masterLogic_timer_done || (! i2cCtrl_io_internals_sclRead)); + assign when_I2cCtrl_l450 = (! i2cCtrl_io_internals_sclRead); + assign when_I2cCtrl_l474 = (! i2cCtrl_io_internals_sclRead); + assign when_StateMachine_l253 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2)); + assign when_StateMachine_l253_1 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3)); + assign when_StateMachine_l253_2 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW)); + assign when_StateMachine_l253_3 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH)); + assign when_StateMachine_l253_4 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1)); + assign when_StateMachine_l253_5 = ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF)) && (bridge_masterLogic_fsm_stateNext == Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF)); + assign when_I2cCtrl_l350 = (bridge_masterLogic_drop || ((! (bridge_masterLogic_fsm_stateReg == Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE)) && ((i2cCtrl_io_bus_cmd_kind == Axi4PeripheralI2cSlaveCmdMode_DROP) || i2cCtrl_io_timeout))); + assign when_I2cCtrl_l673 = (! bridge_slaveOverride_sda); + assign when_I2cCtrl_l674 = (! bridge_slaveOverride_scl); + assign io_i2c_scl_write = bridge_i2cBuffer_scl_write_regNext; + assign io_i2c_sda_write = bridge_i2cBuffer_sda_write_regNext; + assign bridge_i2cBuffer_scl_read = io_i2c_scl_read; + assign bridge_i2cBuffer_sda_read = io_i2c_sda_read; + assign system_i2c_0_io_interrupt_source = bridge_interruptCtrl_interrupt; + always @(posedge clk) begin + if(reset) begin + _zz_io_ctrl_rsp_valid_1 <= 1'b0; + bridge_rxData_event <= 1'b0; + bridge_rxData_listen <= 1'b0; + bridge_rxData_valid <= 1'b0; + bridge_rxAck_listen <= 1'b0; + bridge_rxAck_valid <= 1'b0; + bridge_txData_valid <= 1'b1; + bridge_txData_repeat <= 1'b1; + bridge_txData_enable <= 1'b0; + bridge_txAck_valid <= 1'b1; + bridge_txAck_repeat <= 1'b1; + bridge_txAck_enable <= 1'b0; + bridge_addressFilter_addresses_0_enable <= 1'b0; + bridge_addressFilter_addresses_1_enable <= 1'b0; + bridge_addressFilter_state <= 2'b00; + bridge_masterLogic_start <= 1'b0; + bridge_masterLogic_stop <= 1'b0; + bridge_masterLogic_drop <= 1'b0; + bridge_masterLogic_recover <= 1'b0; + bridge_masterLogic_fsm_dropped_start <= 1'b0; + bridge_masterLogic_fsm_dropped_stop <= 1'b0; + bridge_masterLogic_fsm_dropped_recover <= 1'b0; + bridge_dataCounter <= 3'b000; + bridge_inAckState <= 1'b0; + bridge_wasntAck <= 1'b0; + bridge_interruptCtrl_rxDataEnable <= 1'b0; + bridge_interruptCtrl_rxAckEnable <= 1'b0; + bridge_interruptCtrl_txDataEnable <= 1'b0; + bridge_interruptCtrl_txAckEnable <= 1'b0; + bridge_interruptCtrl_start_enable <= 1'b0; + bridge_interruptCtrl_start_flag <= 1'b0; + bridge_interruptCtrl_restart_enable <= 1'b0; + bridge_interruptCtrl_restart_flag <= 1'b0; + bridge_interruptCtrl_end_enable <= 1'b0; + bridge_interruptCtrl_end_flag <= 1'b0; + bridge_interruptCtrl_drop_enable <= 1'b0; + bridge_interruptCtrl_drop_flag <= 1'b0; + bridge_interruptCtrl_filterGen_enable <= 1'b0; + bridge_interruptCtrl_filterGen_flag <= 1'b0; + bridge_interruptCtrl_clockGenExit_enable <= 1'b0; + bridge_interruptCtrl_clockGenExit_flag <= 1'b0; + bridge_interruptCtrl_clockGenEnter_enable <= 1'b0; + bridge_interruptCtrl_clockGenEnter_flag <= 1'b0; + _zz_io_config_samplingClockDivider <= 10'h0; + bridge_masterLogic_fsm_stateReg <= Axi4Peripheralbridge_masterLogic_fsm_enumDef_BOOT; + bridge_slaveOverride_sda <= 1'b1; + bridge_slaveOverride_scl <= 1'b1; + bridge_i2cBuffer_scl_write_regNext <= 1'b1; + bridge_i2cBuffer_sda_write_regNext <= 1'b1; + end else begin + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_ctrl_rsp_valid_1 <= (busCtrl_rsp_valid && _zz_busCtrl_rsp_ready); + end + bridge_rxData_event <= 1'b0; + if(when_I2cCtrl_l224) begin + bridge_rxData_valid <= 1'b0; + end + if(when_I2cCtrl_l237) begin + bridge_rxAck_valid <= 1'b0; + end + if(bridge_rxData_event) begin + case(bridge_addressFilter_state) + 2'b00 : begin + bridge_addressFilter_state <= 2'b01; + end + 2'b01 : begin + bridge_addressFilter_state <= 2'b10; + end + default : begin + end + endcase + end + if(bridge_frameReset) begin + bridge_addressFilter_state <= 2'b00; + end + if(when_I2cCtrl_l310) begin + bridge_txAck_valid <= 1'b0; + end + if(when_BusSlaveFactory_l377) begin + if(when_BusSlaveFactory_l379) begin + bridge_masterLogic_start <= _zz_bridge_masterLogic_start[0]; + end + end + if(when_BusSlaveFactory_l377_1) begin + if(when_BusSlaveFactory_l379_1) begin + bridge_masterLogic_stop <= _zz_bridge_masterLogic_stop[0]; + end + end + if(when_BusSlaveFactory_l377_2) begin + if(when_BusSlaveFactory_l379_2) begin + bridge_masterLogic_drop <= _zz_bridge_masterLogic_drop[0]; + end + end + if(when_BusSlaveFactory_l377_3) begin + if(when_BusSlaveFactory_l379_3) begin + bridge_masterLogic_recover <= _zz_bridge_masterLogic_recover[0]; + end + end + if(when_BusSlaveFactory_l341) begin + if(when_BusSlaveFactory_l347) begin + bridge_masterLogic_fsm_dropped_start <= _zz_bridge_masterLogic_fsm_dropped_start[0]; + end + end + if(when_BusSlaveFactory_l341_1) begin + if(when_BusSlaveFactory_l347_1) begin + bridge_masterLogic_fsm_dropped_stop <= _zz_bridge_masterLogic_fsm_dropped_stop[0]; + end + end + if(when_BusSlaveFactory_l341_2) begin + if(when_BusSlaveFactory_l347_2) begin + bridge_masterLogic_fsm_dropped_recover <= _zz_bridge_masterLogic_fsm_dropped_recover[0]; + end + end + case(i2cCtrl_io_bus_cmd_kind) + Axi4PeripheralI2cSlaveCmdMode_READ : begin + if(when_I2cCtrl_l566) begin + bridge_dataCounter <= (bridge_dataCounter + 3'b001); + if(when_I2cCtrl_l570) begin + if(bridge_txData_disableOnDataConflict) begin + bridge_txData_enable <= 1'b0; + end + if(bridge_txAck_disableOnDataConflict) begin + bridge_txAck_enable <= 1'b0; + end + end + if(when_I2cCtrl_l574) begin + if(bridge_rxData_listen) begin + bridge_rxData_valid <= 1'b1; + end + bridge_rxData_event <= 1'b1; + bridge_inAckState <= 1'b1; + if(when_I2cCtrl_l578) begin + bridge_txData_valid <= 1'b0; + end + end + end else begin + if(bridge_rxAck_listen) begin + bridge_rxAck_valid <= 1'b1; + end + bridge_inAckState <= 1'b0; + bridge_wasntAck <= i2cCtrl_io_bus_cmd_data; + if(when_I2cCtrl_l588) begin + bridge_txAck_valid <= 1'b0; + end + end + end + default : begin + end + endcase + if(bridge_frameReset) begin + bridge_inAckState <= 1'b0; + bridge_dataCounter <= 3'b000; + bridge_wasntAck <= 1'b0; + end + if(when_I2cCtrl_l601) begin + bridge_txData_valid <= 1'b1; + bridge_txData_enable <= 1'b0; + bridge_txData_repeat <= 1'b1; + bridge_txAck_valid <= 1'b1; + bridge_txAck_enable <= 1'b0; + bridge_txAck_repeat <= 1'b1; + bridge_rxData_listen <= 1'b0; + bridge_rxAck_listen <= 1'b0; + end + if(when_I2cCtrl_l634) begin + bridge_interruptCtrl_start_flag <= 1'b1; + end + if(when_I2cCtrl_l634_1) begin + bridge_interruptCtrl_start_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_3) begin + if(when_BusSlaveFactory_l347_3) begin + bridge_interruptCtrl_start_flag <= _zz_bridge_interruptCtrl_start_flag[0]; + end + end + if(when_I2cCtrl_l634_2) begin + bridge_interruptCtrl_restart_flag <= 1'b1; + end + if(when_I2cCtrl_l634_3) begin + bridge_interruptCtrl_restart_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_4) begin + if(when_BusSlaveFactory_l347_4) begin + bridge_interruptCtrl_restart_flag <= _zz_bridge_interruptCtrl_restart_flag[0]; + end + end + if(when_I2cCtrl_l634_4) begin + bridge_interruptCtrl_end_flag <= 1'b1; + end + if(when_I2cCtrl_l634_5) begin + bridge_interruptCtrl_end_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_5) begin + if(when_BusSlaveFactory_l347_5) begin + bridge_interruptCtrl_end_flag <= _zz_bridge_interruptCtrl_end_flag[0]; + end + end + if(when_I2cCtrl_l634_6) begin + bridge_interruptCtrl_drop_flag <= 1'b1; + end + if(when_I2cCtrl_l634_7) begin + bridge_interruptCtrl_drop_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_6) begin + if(when_BusSlaveFactory_l347_6) begin + bridge_interruptCtrl_drop_flag <= _zz_bridge_interruptCtrl_drop_flag[0]; + end + end + if(when_I2cCtrl_l634_8) begin + bridge_interruptCtrl_filterGen_flag <= 1'b1; + end + if(when_I2cCtrl_l634_9) begin + bridge_interruptCtrl_filterGen_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_7) begin + if(when_BusSlaveFactory_l347_7) begin + bridge_interruptCtrl_filterGen_flag <= _zz_bridge_interruptCtrl_filterGen_flag[0]; + end + end + if(when_I2cCtrl_l634_10) begin + bridge_interruptCtrl_clockGenExit_flag <= 1'b1; + end + if(when_I2cCtrl_l634_11) begin + bridge_interruptCtrl_clockGenExit_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_8) begin + if(when_BusSlaveFactory_l347_8) begin + bridge_interruptCtrl_clockGenExit_flag <= _zz_bridge_interruptCtrl_clockGenExit_flag[0]; + end + end + if(when_I2cCtrl_l634_12) begin + bridge_interruptCtrl_clockGenEnter_flag <= 1'b1; + end + if(when_I2cCtrl_l634_13) begin + bridge_interruptCtrl_clockGenEnter_flag <= 1'b0; + end + if(when_BusSlaveFactory_l341_9) begin + if(when_BusSlaveFactory_l347_9) begin + bridge_interruptCtrl_clockGenEnter_flag <= _zz_bridge_interruptCtrl_clockGenEnter_flag[0]; + end + end + bridge_masterLogic_fsm_stateReg <= bridge_masterLogic_fsm_stateNext; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + if(!when_I2cCtrl_l367) begin + if(when_I2cCtrl_l369) begin + bridge_txData_valid <= 1'b0; + end + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + if(bridge_masterLogic_timer_done) begin + bridge_masterLogic_start <= 1'b0; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + if(i2cCtrl_io_internals_sdaRead) begin + bridge_masterLogic_stop <= 1'b0; + bridge_masterLogic_recover <= 1'b0; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + end + endcase + if(when_I2cCtrl_l350) begin + bridge_masterLogic_start <= 1'b0; + bridge_masterLogic_stop <= 1'b0; + bridge_masterLogic_drop <= 1'b0; + bridge_masterLogic_recover <= 1'b0; + if(bridge_masterLogic_start) begin + bridge_masterLogic_fsm_dropped_start <= 1'b1; + end + if(bridge_masterLogic_stop) begin + bridge_masterLogic_fsm_dropped_stop <= 1'b1; + end + end + bridge_i2cBuffer_scl_write_regNext <= bridge_i2cBuffer_scl_write; + bridge_i2cBuffer_sda_write_regNext <= bridge_i2cBuffer_sda_write; + case(io_ctrl_cmd_payload_fragment_address) + 8'h08 : begin + if(busCtrl_doWrite) begin + bridge_rxData_listen <= io_ctrl_cmd_payload_fragment_data[9]; + end + end + 8'h0c : begin + if(busCtrl_doWrite) begin + bridge_rxAck_listen <= io_ctrl_cmd_payload_fragment_data[9]; + end + end + 8'h0 : begin + if(busCtrl_doWrite) begin + bridge_txData_repeat <= io_ctrl_cmd_payload_fragment_data[10]; + bridge_txData_valid <= io_ctrl_cmd_payload_fragment_data[8]; + bridge_txData_enable <= io_ctrl_cmd_payload_fragment_data[9]; + end + end + 8'h04 : begin + if(busCtrl_doWrite) begin + bridge_txAck_repeat <= io_ctrl_cmd_payload_fragment_data[10]; + bridge_txAck_valid <= io_ctrl_cmd_payload_fragment_data[8]; + bridge_txAck_enable <= io_ctrl_cmd_payload_fragment_data[9]; + end + end + 8'h88 : begin + if(busCtrl_doWrite) begin + bridge_addressFilter_addresses_0_enable <= io_ctrl_cmd_payload_fragment_data[15]; + end + end + 8'h8c : begin + if(busCtrl_doWrite) begin + bridge_addressFilter_addresses_1_enable <= io_ctrl_cmd_payload_fragment_data[15]; + end + end + 8'h20 : begin + if(busCtrl_doWrite) begin + bridge_interruptCtrl_rxDataEnable <= io_ctrl_cmd_payload_fragment_data[0]; + bridge_interruptCtrl_rxAckEnable <= io_ctrl_cmd_payload_fragment_data[1]; + bridge_interruptCtrl_txDataEnable <= io_ctrl_cmd_payload_fragment_data[2]; + bridge_interruptCtrl_txAckEnable <= io_ctrl_cmd_payload_fragment_data[3]; + bridge_interruptCtrl_start_enable <= io_ctrl_cmd_payload_fragment_data[4]; + bridge_interruptCtrl_restart_enable <= io_ctrl_cmd_payload_fragment_data[5]; + bridge_interruptCtrl_end_enable <= io_ctrl_cmd_payload_fragment_data[6]; + bridge_interruptCtrl_drop_enable <= io_ctrl_cmd_payload_fragment_data[7]; + bridge_interruptCtrl_filterGen_enable <= io_ctrl_cmd_payload_fragment_data[17]; + bridge_interruptCtrl_clockGenExit_enable <= io_ctrl_cmd_payload_fragment_data[15]; + bridge_interruptCtrl_clockGenEnter_enable <= io_ctrl_cmd_payload_fragment_data[16]; + end + end + 8'h28 : begin + if(busCtrl_doWrite) begin + _zz_io_config_samplingClockDivider <= io_ctrl_cmd_payload_fragment_data[9 : 0]; + end + end + 8'h48 : begin + if(busCtrl_doWrite) begin + bridge_slaveOverride_sda <= io_ctrl_cmd_payload_fragment_data[1]; + bridge_slaveOverride_scl <= io_ctrl_cmd_payload_fragment_data[2]; + end + end + default : begin + end + endcase + end + end + + always @(posedge clk) begin + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_ctrl_rsp_payload_last <= busCtrl_rsp_payload_last; + _zz_io_ctrl_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; + _zz_io_ctrl_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; + _zz_io_ctrl_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; + end + if(bridge_rxData_event) begin + case(bridge_addressFilter_state) + 2'b00 : begin + bridge_addressFilter_byte0 <= bridge_rxData_value; + end + 2'b01 : begin + bridge_addressFilter_byte1 <= bridge_rxData_value; + end + default : begin + end + endcase + end + _zz_when_I2cCtrl_l310_1 <= _zz_when_I2cCtrl_l310; + bridge_masterLogic_timer_value <= (bridge_masterLogic_timer_value - _zz_bridge_masterLogic_timer_value); + if(when_I2cCtrl_l363) begin + bridge_masterLogic_fsm_inFrameLate <= 1'b1; + end + if(when_I2cCtrl_l363_1) begin + bridge_masterLogic_fsm_inFrameLate <= 1'b0; + end + case(i2cCtrl_io_bus_cmd_kind) + Axi4PeripheralI2cSlaveCmdMode_READ : begin + if(when_I2cCtrl_l566) begin + bridge_rxData_value[_zz_bridge_rxData_value] <= i2cCtrl_io_bus_cmd_data; + end else begin + bridge_rxAck_value <= i2cCtrl_io_bus_cmd_data; + end + end + default : begin + end + endcase + if(when_I2cCtrl_l601) begin + bridge_txData_disableOnDataConflict <= 1'b0; + bridge_txAck_disableOnDataConflict <= 1'b0; + end + _zz_when_I2cCtrl_l634_1 <= _zz_when_I2cCtrl_l634; + bridge_masterLogic_fsm_isBusy_regNext <= bridge_masterLogic_fsm_isBusy; + bridge_masterLogic_fsm_isBusy_regNext_1 <= bridge_masterLogic_fsm_isBusy; + bridge_timeoutClear <= 1'b0; + case(bridge_masterLogic_fsm_stateReg) + Axi4Peripheralbridge_masterLogic_fsm_enumDef_IDLE : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START2 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_START3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_LOW : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_HIGH : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_RESTART : begin + if(when_I2cCtrl_l450) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP1 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP2 : begin + if(when_I2cCtrl_l474) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; + end + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_STOP3 : begin + end + Axi4Peripheralbridge_masterLogic_fsm_enumDef_TBUF : begin + end + default : begin + end + endcase + if(when_StateMachine_l253) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; + end + if(when_StateMachine_l253_1) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tLow; + end + if(when_StateMachine_l253_2) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tLow; + end + if(when_StateMachine_l253_3) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; + end + if(when_StateMachine_l253_4) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tHigh; + end + if(when_StateMachine_l253_5) begin + bridge_masterLogic_timer_value <= bridge_masterLogic_timer_tBuf; + end + case(io_ctrl_cmd_payload_fragment_address) + 8'h0 : begin + if(busCtrl_doWrite) begin + bridge_txData_value <= io_ctrl_cmd_payload_fragment_data[7 : 0]; + bridge_txData_disableOnDataConflict <= io_ctrl_cmd_payload_fragment_data[11]; + end + end + 8'h04 : begin + if(busCtrl_doWrite) begin + bridge_txAck_value <= io_ctrl_cmd_payload_fragment_data[0]; + bridge_txAck_disableOnDataConflict <= io_ctrl_cmd_payload_fragment_data[11]; + end + end + 8'h88 : begin + if(busCtrl_doWrite) begin + bridge_addressFilter_addresses_0_value <= io_ctrl_cmd_payload_fragment_data[9 : 0]; + bridge_addressFilter_addresses_0_is10Bit <= io_ctrl_cmd_payload_fragment_data[14]; + end + end + 8'h8c : begin + if(busCtrl_doWrite) begin + bridge_addressFilter_addresses_1_value <= io_ctrl_cmd_payload_fragment_data[9 : 0]; + bridge_addressFilter_addresses_1_is10Bit <= io_ctrl_cmd_payload_fragment_data[14]; + end + end + 8'h50 : begin + if(busCtrl_doWrite) begin + bridge_masterLogic_timer_tLow <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 8'h54 : begin + if(busCtrl_doWrite) begin + bridge_masterLogic_timer_tHigh <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 8'h58 : begin + if(busCtrl_doWrite) begin + bridge_masterLogic_timer_tBuf <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 8'h2c : begin + if(busCtrl_doWrite) begin + _zz_io_config_timeout <= io_ctrl_cmd_payload_fragment_data[19 : 0]; + bridge_timeoutClear <= 1'b1; + end + end + 8'h30 : begin + if(busCtrl_doWrite) begin + _zz_io_config_tsuData <= io_ctrl_cmd_payload_fragment_data[5 : 0]; + end + end + default : begin + end + endcase + end + + always @(posedge clk) begin + if(reset) begin + i2cCtrl_io_internals_inFrame_regNext <= 1'b0; + end else begin + i2cCtrl_io_internals_inFrame_regNext <= i2cCtrl_io_internals_inFrame; + end + end + + +endmodule + +module Axi4PeripheralBmbSpiXdrMasterCtrl ( + input wire io_ctrl_cmd_valid, + output wire io_ctrl_cmd_ready, + input wire io_ctrl_cmd_payload_last, + input wire [0:0] io_ctrl_cmd_payload_fragment_opcode, + input wire [11:0] io_ctrl_cmd_payload_fragment_address, + input wire [1:0] io_ctrl_cmd_payload_fragment_length, + input wire [31:0] io_ctrl_cmd_payload_fragment_data, + input wire [2:0] io_ctrl_cmd_payload_fragment_context, + output wire io_ctrl_rsp_valid, + input wire io_ctrl_rsp_ready, + output wire io_ctrl_rsp_payload_last, + output wire [0:0] io_ctrl_rsp_payload_fragment_opcode, + output wire [31:0] io_ctrl_rsp_payload_fragment_data, + output wire [2:0] io_ctrl_rsp_payload_fragment_context, + output wire [0:0] io_spi_sclk_write, + output wire io_spi_data_0_writeEnable, + input wire [0:0] io_spi_data_0_read, + output wire [0:0] io_spi_data_0_write, + output wire io_spi_data_1_writeEnable, + input wire [0:0] io_spi_data_1_read, + output wire [0:0] io_spi_data_1_write, + output wire io_spi_data_2_writeEnable, + input wire [0:0] io_spi_data_2_read, + output wire [0:0] io_spi_data_2_write, + output wire io_spi_data_3_writeEnable, + input wire [0:0] io_spi_data_3_read, + output wire [0:0] io_spi_data_3_write, + output wire [3:0] io_spi_ss, + output wire system_spi_0_io_interrupt_source, + input wire clk, + input wire reset +); + + wire ctrl_io_rsp_queueWithOccupancy_io_pop_ready; + wire ctrl_io_cmd_ready; + wire ctrl_io_rsp_valid; + wire [7:0] ctrl_io_rsp_payload_data; + wire [0:0] ctrl_io_spi_sclk_write; + wire [3:0] ctrl_io_spi_ss; + wire [0:0] ctrl_io_spi_data_0_write; + wire ctrl_io_spi_data_0_writeEnable; + wire [0:0] ctrl_io_spi_data_1_write; + wire ctrl_io_spi_data_1_writeEnable; + wire [0:0] ctrl_io_spi_data_2_write; + wire ctrl_io_spi_data_2_writeEnable; + wire [0:0] ctrl_io_spi_data_3_write; + wire ctrl_io_spi_data_3_writeEnable; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; + wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy; + wire [8:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; + wire ctrl_io_rsp_queueWithOccupancy_io_push_ready; + wire ctrl_io_rsp_queueWithOccupancy_io_pop_valid; + wire [7:0] ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_occupancy; + wire [8:0] ctrl_io_rsp_queueWithOccupancy_io_availability; + wire factory_readErrorFlag; + wire factory_writeErrorFlag; + wire factory_readHaltTrigger; + wire factory_writeHaltTrigger; + wire factory_rsp_valid; + wire factory_rsp_ready; + wire factory_rsp_payload_last; + reg [0:0] factory_rsp_payload_fragment_opcode; + reg [31:0] factory_rsp_payload_fragment_data; + wire [2:0] factory_rsp_payload_fragment_context; + wire _zz_factory_rsp_ready; + reg _zz_factory_rsp_ready_1; + wire _zz_io_ctrl_rsp_valid; + reg _zz_io_ctrl_rsp_valid_1; + reg _zz_io_ctrl_rsp_payload_last; + reg [0:0] _zz_io_ctrl_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_ctrl_rsp_payload_fragment_data; + reg [2:0] _zz_io_ctrl_rsp_payload_fragment_context; + wire when_Stream_l375; + wire factory_askWrite; + wire factory_askRead; + wire io_ctrl_cmd_fire; + wire factory_doWrite; + wire factory_doRead; + wire when_BmbSlaveFactory_l33; + wire when_BmbSlaveFactory_l35; + wire [31:0] mapping_cmdLogic_writeData; + reg mapping_cmdLogic_doRegular; + reg mapping_cmdLogic_doWriteLarge; + reg mapping_cmdLogic_doReadWriteLarge; + wire mapping_cmdLogic_streamUnbuffered_valid; + wire mapping_cmdLogic_streamUnbuffered_ready; + wire mapping_cmdLogic_streamUnbuffered_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_payload_read; + wire mapping_cmdLogic_streamUnbuffered_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_payload_data; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write; + reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read; + wire mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write; + wire [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; + reg mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; + reg [7:0] mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; + wire when_Stream_l375_1; + wire ctrl_io_rsp_toStream_valid; + wire ctrl_io_rsp_toStream_ready; + wire [7:0] ctrl_io_rsp_toStream_payload_data; + reg _zz_io_pop_ready; + reg _zz_io_pop_ready_1; + reg mapping_interruptCtrl_cmdIntEnable; + reg mapping_interruptCtrl_rspIntEnable; + wire mapping_interruptCtrl_cmdInt; + wire mapping_interruptCtrl_rspInt; + wire mapping_interruptCtrl_interrupt; + reg _zz_io_config_kind_cpol; + reg _zz_io_config_kind_cpha; + reg [1:0] _zz_io_config_mod; + reg [11:0] _zz_io_config_sclkToggle; + reg [11:0] _zz_io_config_ss_setup; + reg [11:0] _zz_io_config_ss_hold; + reg [11:0] _zz_io_config_ss_disable; + reg [3:0] _zz_io_config_ss_activeHigh; + wire [1:0] _zz_io_config_kind_cpol_1; + + Axi4PeripheralTopLevel ctrl ( + .io_config_kind_cpol (_zz_io_config_kind_cpol ), //i + .io_config_kind_cpha (_zz_io_config_kind_cpha ), //i + .io_config_sclkToggle (_zz_io_config_sclkToggle[11:0] ), //i + .io_config_mod (_zz_io_config_mod[1:0] ), //i + .io_config_ss_activeHigh (_zz_io_config_ss_activeHigh[3:0] ), //i + .io_config_ss_setup (_zz_io_config_ss_setup[11:0] ), //i + .io_config_ss_hold (_zz_io_config_ss_hold[11:0] ), //i + .io_config_ss_disable (_zz_io_config_ss_disable[11:0] ), //i + .io_cmd_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid ), //i + .io_cmd_ready (ctrl_io_cmd_ready ), //o + .io_cmd_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind ), //i + .io_cmd_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read ), //i + .io_cmd_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write ), //i + .io_cmd_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data[7:0]), //i + .io_rsp_valid (ctrl_io_rsp_valid ), //o + .io_rsp_payload_data (ctrl_io_rsp_payload_data[7:0] ), //o + .io_spi_sclk_write (ctrl_io_spi_sclk_write ), //o + .io_spi_data_0_writeEnable (ctrl_io_spi_data_0_writeEnable ), //o + .io_spi_data_0_read (io_spi_data_0_read ), //i + .io_spi_data_0_write (ctrl_io_spi_data_0_write ), //o + .io_spi_data_1_writeEnable (ctrl_io_spi_data_1_writeEnable ), //o + .io_spi_data_1_read (io_spi_data_1_read ), //i + .io_spi_data_1_write (ctrl_io_spi_data_1_write ), //o + .io_spi_data_2_writeEnable (ctrl_io_spi_data_2_writeEnable ), //o + .io_spi_data_2_read (io_spi_data_2_read ), //i + .io_spi_data_2_write (ctrl_io_spi_data_2_write ), //o + .io_spi_data_3_writeEnable (ctrl_io_spi_data_3_writeEnable ), //o + .io_spi_data_3_read (io_spi_data_3_read ), //i + .io_spi_data_3_write (ctrl_io_spi_data_3_write ), //o + .io_spi_ss (ctrl_io_spi_ss[3:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralStreamFifo_2 mapping_cmdLogic_streamUnbuffered_queueWithAvailability ( + .io_push_valid (mapping_cmdLogic_streamUnbuffered_valid ), //i + .io_push_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready ), //o + .io_push_payload_kind (mapping_cmdLogic_streamUnbuffered_payload_kind ), //i + .io_push_payload_read (mapping_cmdLogic_streamUnbuffered_payload_read ), //i + .io_push_payload_write (mapping_cmdLogic_streamUnbuffered_payload_write ), //i + .io_push_payload_data (mapping_cmdLogic_streamUnbuffered_payload_data[7:0] ), //i + .io_pop_valid (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid ), //o + .io_pop_ready (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ), //i + .io_pop_payload_kind (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind ), //o + .io_pop_payload_read (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read ), //o + .io_pop_payload_write (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write ), //o + .io_pop_payload_data (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data[7:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_occupancy[8:0] ), //o + .io_availability (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability[8:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralStreamFifo_3 ctrl_io_rsp_queueWithOccupancy ( + .io_push_valid (ctrl_io_rsp_toStream_valid ), //i + .io_push_ready (ctrl_io_rsp_queueWithOccupancy_io_push_ready ), //o + .io_push_payload_data (ctrl_io_rsp_toStream_payload_data[7:0] ), //i + .io_pop_valid (ctrl_io_rsp_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (ctrl_io_rsp_queueWithOccupancy_io_pop_ready ), //i + .io_pop_payload_data (ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data[7:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (ctrl_io_rsp_queueWithOccupancy_io_occupancy[8:0] ), //o + .io_availability (ctrl_io_rsp_queueWithOccupancy_io_availability[8:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + assign factory_readErrorFlag = 1'b0; + assign factory_writeErrorFlag = 1'b0; + assign factory_readHaltTrigger = 1'b0; + assign factory_writeHaltTrigger = 1'b0; + assign _zz_factory_rsp_ready = (! (factory_readHaltTrigger || factory_writeHaltTrigger)); + assign factory_rsp_ready = (_zz_factory_rsp_ready_1 && _zz_factory_rsp_ready); + always @(*) begin + _zz_factory_rsp_ready_1 = io_ctrl_rsp_ready; + if(when_Stream_l375) begin + _zz_factory_rsp_ready_1 = 1'b1; + end + end + + assign when_Stream_l375 = (! _zz_io_ctrl_rsp_valid); + assign _zz_io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid_1; + assign io_ctrl_rsp_valid = _zz_io_ctrl_rsp_valid; + assign io_ctrl_rsp_payload_last = _zz_io_ctrl_rsp_payload_last; + assign io_ctrl_rsp_payload_fragment_opcode = _zz_io_ctrl_rsp_payload_fragment_opcode; + assign io_ctrl_rsp_payload_fragment_data = _zz_io_ctrl_rsp_payload_fragment_data; + assign io_ctrl_rsp_payload_fragment_context = _zz_io_ctrl_rsp_payload_fragment_context; + assign factory_askWrite = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign factory_askRead = (io_ctrl_cmd_valid && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign io_ctrl_cmd_fire = (io_ctrl_cmd_valid && io_ctrl_cmd_ready); + assign factory_doWrite = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b1)); + assign factory_doRead = (io_ctrl_cmd_fire && (io_ctrl_cmd_payload_fragment_opcode == 1'b0)); + assign factory_rsp_valid = io_ctrl_cmd_valid; + assign io_ctrl_cmd_ready = factory_rsp_ready; + assign factory_rsp_payload_last = 1'b1; + assign when_BmbSlaveFactory_l33 = (factory_doWrite && factory_writeErrorFlag); + always @(*) begin + if(when_BmbSlaveFactory_l33) begin + factory_rsp_payload_fragment_opcode = 1'b1; + end else begin + if(when_BmbSlaveFactory_l35) begin + factory_rsp_payload_fragment_opcode = 1'b1; + end else begin + factory_rsp_payload_fragment_opcode = 1'b0; + end + end + end + + assign when_BmbSlaveFactory_l35 = (factory_doRead && factory_readErrorFlag); + always @(*) begin + factory_rsp_payload_fragment_data = 32'h0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + factory_rsp_payload_fragment_data[31 : 31] = (! ctrl_io_rsp_queueWithOccupancy_io_pop_valid); + factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + end + 12'h004 : begin + factory_rsp_payload_fragment_data[8 : 0] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_availability; + factory_rsp_payload_fragment_data[24 : 16] = ctrl_io_rsp_queueWithOccupancy_io_occupancy; + end + 12'h00c : begin + factory_rsp_payload_fragment_data[16 : 16] = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid; + factory_rsp_payload_fragment_data[0 : 0] = mapping_interruptCtrl_cmdIntEnable; + factory_rsp_payload_fragment_data[1 : 1] = mapping_interruptCtrl_rspIntEnable; + factory_rsp_payload_fragment_data[8 : 8] = mapping_interruptCtrl_cmdInt; + factory_rsp_payload_fragment_data[9 : 9] = mapping_interruptCtrl_rspInt; + end + 12'h058 : begin + factory_rsp_payload_fragment_data[7 : 0] = ctrl_io_rsp_queueWithOccupancy_io_pop_payload_data; + end + default : begin + end + endcase + end + + assign factory_rsp_payload_fragment_context = io_ctrl_cmd_payload_fragment_context; + always @(*) begin + mapping_cmdLogic_doRegular = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doRegular = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + mapping_cmdLogic_doWriteLarge = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h050 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doWriteLarge = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + mapping_cmdLogic_doReadWriteLarge = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h054 : begin + if(factory_doWrite) begin + mapping_cmdLogic_doReadWriteLarge = 1'b1; + end + end + default : begin + end + endcase + end + + assign mapping_cmdLogic_streamUnbuffered_valid = ((mapping_cmdLogic_doRegular || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_write = (((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[8]) || mapping_cmdLogic_doWriteLarge) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_read = ((mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[9]) || mapping_cmdLogic_doReadWriteLarge); + assign mapping_cmdLogic_streamUnbuffered_payload_kind = (mapping_cmdLogic_doRegular && mapping_cmdLogic_writeData[11]); + assign mapping_cmdLogic_streamUnbuffered_payload_data = mapping_cmdLogic_writeData[7:0]; + assign mapping_cmdLogic_streamUnbuffered_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_push_ready; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid || (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN)); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data = (mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN ? mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data : mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data); + always @(*) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready; + if(when_Stream_l375_1) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375_1 = (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid); + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_valid = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_kind = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_read = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_write = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_payload_data = mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data; + assign mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_m2sPipe_ready = ctrl_io_cmd_ready; + assign ctrl_io_rsp_toStream_valid = ctrl_io_rsp_valid; + assign ctrl_io_rsp_toStream_payload_data = ctrl_io_rsp_payload_data; + assign ctrl_io_rsp_toStream_ready = ctrl_io_rsp_queueWithOccupancy_io_push_ready; + always @(*) begin + _zz_io_pop_ready = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h0 : begin + if(factory_doRead) begin + _zz_io_pop_ready = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + _zz_io_pop_ready_1 = 1'b0; + case(io_ctrl_cmd_payload_fragment_address) + 12'h058 : begin + if(factory_doRead) begin + _zz_io_pop_ready_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign ctrl_io_rsp_queueWithOccupancy_io_pop_ready = (_zz_io_pop_ready || _zz_io_pop_ready_1); + assign mapping_interruptCtrl_cmdInt = (mapping_interruptCtrl_cmdIntEnable && (! mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid)); + assign mapping_interruptCtrl_rspInt = (mapping_interruptCtrl_rspIntEnable && ctrl_io_rsp_queueWithOccupancy_io_pop_valid); + assign mapping_interruptCtrl_interrupt = (mapping_interruptCtrl_rspInt || mapping_interruptCtrl_cmdInt); + assign io_spi_sclk_write = ctrl_io_spi_sclk_write; + assign io_spi_data_0_writeEnable = ctrl_io_spi_data_0_writeEnable; + assign io_spi_data_0_write = ctrl_io_spi_data_0_write; + assign io_spi_data_1_writeEnable = ctrl_io_spi_data_1_writeEnable; + assign io_spi_data_1_write = ctrl_io_spi_data_1_write; + assign io_spi_data_2_writeEnable = ctrl_io_spi_data_2_writeEnable; + assign io_spi_data_2_write = ctrl_io_spi_data_2_write; + assign io_spi_data_3_writeEnable = ctrl_io_spi_data_3_writeEnable; + assign io_spi_data_3_write = ctrl_io_spi_data_3_write; + assign io_spi_ss = ctrl_io_spi_ss; + assign system_spi_0_io_interrupt_source = mapping_interruptCtrl_interrupt; + assign mapping_cmdLogic_writeData = io_ctrl_cmd_payload_fragment_data[31 : 0]; + assign _zz_io_config_kind_cpol_1 = io_ctrl_cmd_payload_fragment_data[1 : 0]; + always @(posedge clk) begin + if(reset) begin + _zz_io_ctrl_rsp_valid_1 <= 1'b0; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN <= 1'b1; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= 1'b0; + mapping_interruptCtrl_cmdIntEnable <= 1'b0; + mapping_interruptCtrl_rspIntEnable <= 1'b0; + _zz_io_config_ss_activeHigh <= 4'b0000; + end else begin + if(_zz_factory_rsp_ready_1) begin + _zz_io_ctrl_rsp_valid_1 <= (factory_rsp_valid && _zz_factory_rsp_ready); + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_valid) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN <= 1'b0; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN <= 1'b1; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rValid <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_valid; + end + case(io_ctrl_cmd_payload_fragment_address) + 12'h00c : begin + if(factory_doWrite) begin + mapping_interruptCtrl_cmdIntEnable <= io_ctrl_cmd_payload_fragment_data[0]; + mapping_interruptCtrl_rspIntEnable <= io_ctrl_cmd_payload_fragment_data[1]; + end + end + 12'h030 : begin + if(factory_doWrite) begin + _zz_io_config_ss_activeHigh <= io_ctrl_cmd_payload_fragment_data[3 : 0]; + end + end + default : begin + end + endcase + end + end + + always @(posedge clk) begin + if(_zz_factory_rsp_ready_1) begin + _zz_io_ctrl_rsp_payload_last <= factory_rsp_payload_last; + _zz_io_ctrl_rsp_payload_fragment_opcode <= factory_rsp_payload_fragment_opcode; + _zz_io_ctrl_rsp_payload_fragment_data <= factory_rsp_payload_fragment_data; + _zz_io_ctrl_rsp_payload_fragment_context <= factory_rsp_payload_fragment_context; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rValidN) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_kind; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_read; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_write; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_payload_data; + end + if(mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_ready) begin + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_kind <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_kind; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_read <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_read; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_write <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_write; + mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_rData_data <= mapping_cmdLogic_streamUnbuffered_queueWithAvailability_io_pop_s2mPipe_payload_data; + end + case(io_ctrl_cmd_payload_fragment_address) + 12'h008 : begin + if(factory_doWrite) begin + _zz_io_config_kind_cpol <= _zz_io_config_kind_cpol_1[0]; + _zz_io_config_kind_cpha <= _zz_io_config_kind_cpol_1[1]; + _zz_io_config_mod <= io_ctrl_cmd_payload_fragment_data[5 : 4]; + end + end + 12'h020 : begin + if(factory_doWrite) begin + _zz_io_config_sclkToggle <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h024 : begin + if(factory_doWrite) begin + _zz_io_config_ss_setup <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h028 : begin + if(factory_doWrite) begin + _zz_io_config_ss_hold <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + 12'h02c : begin + if(factory_doWrite) begin + _zz_io_config_ss_disable <= io_ctrl_cmd_payload_fragment_data[11 : 0]; + end + end + default : begin + end + endcase + end + + +endmodule + +module Axi4PeripheralBmbUartCtrl ( + input wire io_bus_cmd_valid, + output wire io_bus_cmd_ready, + input wire io_bus_cmd_payload_last, + input wire [0:0] io_bus_cmd_payload_fragment_opcode, + input wire [5:0] io_bus_cmd_payload_fragment_address, + input wire [1:0] io_bus_cmd_payload_fragment_length, + input wire [31:0] io_bus_cmd_payload_fragment_data, + input wire [2:0] io_bus_cmd_payload_fragment_context, + output wire io_bus_rsp_valid, + input wire io_bus_rsp_ready, + output wire io_bus_rsp_payload_last, + output wire [0:0] io_bus_rsp_payload_fragment_opcode, + output wire [31:0] io_bus_rsp_payload_fragment_data, + output wire [2:0] io_bus_rsp_payload_fragment_context, + output wire io_uart_txd, + input wire io_uart_rxd, + output wire system_uart_0_io_interrupt_source, + input wire clk, + input wire reset +); + localparam Axi4PeripheralUartStopType_ONE = 1'd0; + localparam Axi4PeripheralUartStopType_TWO = 1'd1; + localparam Axi4PeripheralUartParityType_NONE = 2'd0; + localparam Axi4PeripheralUartParityType_EVEN = 2'd1; + localparam Axi4PeripheralUartParityType_ODD = 2'd2; + + reg uartCtrl_io_read_queueWithOccupancy_io_pop_ready; + wire uartCtrl_io_write_ready; + wire uartCtrl_io_read_valid; + wire [7:0] uartCtrl_io_read_payload; + wire uartCtrl_io_uart_txd; + wire uartCtrl_io_readError; + wire uartCtrl_io_readBreak; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + wire bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy; + wire [7:0] bridge_write_streamUnbuffered_queueWithOccupancy_io_availability; + wire uartCtrl_io_read_queueWithOccupancy_io_push_ready; + wire uartCtrl_io_read_queueWithOccupancy_io_pop_valid; + wire [7:0] uartCtrl_io_read_queueWithOccupancy_io_pop_payload; + wire [7:0] uartCtrl_io_read_queueWithOccupancy_io_occupancy; + wire [7:0] uartCtrl_io_read_queueWithOccupancy_io_availability; + wire [0:0] _zz_bridge_misc_readError; + wire [0:0] _zz_bridge_misc_readOverflowError; + wire [0:0] _zz_bridge_misc_breakDetected; + wire [0:0] _zz_bridge_misc_doBreak; + wire [0:0] _zz_bridge_misc_doBreak_1; + wire [7:0] _zz_busCtrl_rsp_payload_fragment_data; + wire busCtrl_readErrorFlag; + wire busCtrl_writeErrorFlag; + wire busCtrl_readHaltTrigger; + wire busCtrl_writeHaltTrigger; + wire busCtrl_rsp_valid; + wire busCtrl_rsp_ready; + wire busCtrl_rsp_payload_last; + reg [0:0] busCtrl_rsp_payload_fragment_opcode; + reg [31:0] busCtrl_rsp_payload_fragment_data; + wire [2:0] busCtrl_rsp_payload_fragment_context; + wire _zz_busCtrl_rsp_ready; + reg _zz_busCtrl_rsp_ready_1; + wire _zz_io_bus_rsp_valid; + reg _zz_io_bus_rsp_valid_1; + reg _zz_io_bus_rsp_payload_last; + reg [0:0] _zz_io_bus_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_bus_rsp_payload_fragment_data; + reg [2:0] _zz_io_bus_rsp_payload_fragment_context; + wire when_Stream_l375; + wire busCtrl_askWrite; + wire busCtrl_askRead; + wire io_bus_cmd_fire; + wire busCtrl_doWrite; + wire busCtrl_doRead; + wire when_BmbSlaveFactory_l33; + wire when_BmbSlaveFactory_l35; + wire bridge_busCtrlWrapped_readErrorFlag; + wire bridge_busCtrlWrapped_writeErrorFlag; + reg [2:0] bridge_uartConfigReg_frame_dataLength; + reg [0:0] bridge_uartConfigReg_frame_stop; + reg [1:0] bridge_uartConfigReg_frame_parity; + reg [19:0] bridge_uartConfigReg_clockDivider; + reg _zz_bridge_write_streamUnbuffered_valid; + wire bridge_write_streamUnbuffered_valid; + wire bridge_write_streamUnbuffered_ready; + wire [7:0] bridge_write_streamUnbuffered_payload; + reg bridge_read_streamBreaked_valid; + reg bridge_read_streamBreaked_ready; + wire [7:0] bridge_read_streamBreaked_payload; + reg bridge_interruptCtrl_writeIntEnable; + reg bridge_interruptCtrl_readIntEnable; + wire bridge_interruptCtrl_readInt; + wire bridge_interruptCtrl_writeInt; + wire bridge_interruptCtrl_interrupt; + reg bridge_misc_readError; + reg when_BusSlaveFactory_l341; + wire when_BusSlaveFactory_l347; + reg bridge_misc_readOverflowError; + reg when_BusSlaveFactory_l341_1; + wire when_BusSlaveFactory_l347_1; + wire uartCtrl_io_read_isStall; + reg bridge_misc_breakDetected; + reg uartCtrl_io_readBreak_regNext; + wire when_UartCtrl_l155; + reg when_BusSlaveFactory_l341_2; + wire when_BusSlaveFactory_l347_2; + reg bridge_misc_doBreak; + reg when_BusSlaveFactory_l377; + wire when_BusSlaveFactory_l379; + reg when_BusSlaveFactory_l341_3; + wire when_BusSlaveFactory_l347_3; + wire [1:0] _zz_bridge_uartConfigReg_frame_parity; + wire [0:0] _zz_bridge_uartConfigReg_frame_stop; + wire when_BmbSlaveFactory_l77; + `ifndef SYNTHESIS + reg [23:0] bridge_uartConfigReg_frame_stop_string; + reg [31:0] bridge_uartConfigReg_frame_parity_string; + reg [31:0] _zz_bridge_uartConfigReg_frame_parity_string; + reg [23:0] _zz_bridge_uartConfigReg_frame_stop_string; + `endif + + + assign _zz_bridge_misc_readError = 1'b0; + assign _zz_bridge_misc_readOverflowError = 1'b0; + assign _zz_bridge_misc_breakDetected = 1'b0; + assign _zz_bridge_misc_doBreak = 1'b1; + assign _zz_bridge_misc_doBreak_1 = 1'b0; + assign _zz_busCtrl_rsp_payload_fragment_data = (8'h80 - bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy); + Axi4PeripheralUartCtrl uartCtrl ( + .io_config_frame_dataLength (bridge_uartConfigReg_frame_dataLength[2:0] ), //i + .io_config_frame_stop (bridge_uartConfigReg_frame_stop ), //i + .io_config_frame_parity (bridge_uartConfigReg_frame_parity[1:0] ), //i + .io_config_clockDivider (bridge_uartConfigReg_clockDivider[19:0] ), //i + .io_write_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //i + .io_write_ready (uartCtrl_io_write_ready ), //o + .io_write_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0]), //i + .io_read_valid (uartCtrl_io_read_valid ), //o + .io_read_ready (uartCtrl_io_read_queueWithOccupancy_io_push_ready ), //i + .io_read_payload (uartCtrl_io_read_payload[7:0] ), //o + .io_uart_txd (uartCtrl_io_uart_txd ), //o + .io_uart_rxd (io_uart_rxd ), //i + .io_readError (uartCtrl_io_readError ), //o + .io_writeBreak (bridge_misc_doBreak ), //i + .io_readBreak (uartCtrl_io_readBreak ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralStreamFifo bridge_write_streamUnbuffered_queueWithOccupancy ( + .io_push_valid (bridge_write_streamUnbuffered_valid ), //i + .io_push_ready (bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready ), //o + .io_push_payload (bridge_write_streamUnbuffered_payload[7:0] ), //i + .io_pop_valid (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (uartCtrl_io_write_ready ), //i + .io_pop_payload (bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_payload[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (bridge_write_streamUnbuffered_queueWithOccupancy_io_occupancy[7:0] ), //o + .io_availability (bridge_write_streamUnbuffered_queueWithOccupancy_io_availability[7:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralStreamFifo uartCtrl_io_read_queueWithOccupancy ( + .io_push_valid (uartCtrl_io_read_valid ), //i + .io_push_ready (uartCtrl_io_read_queueWithOccupancy_io_push_ready ), //o + .io_push_payload (uartCtrl_io_read_payload[7:0] ), //i + .io_pop_valid (uartCtrl_io_read_queueWithOccupancy_io_pop_valid ), //o + .io_pop_ready (uartCtrl_io_read_queueWithOccupancy_io_pop_ready ), //i + .io_pop_payload (uartCtrl_io_read_queueWithOccupancy_io_pop_payload[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (uartCtrl_io_read_queueWithOccupancy_io_occupancy[7:0] ), //o + .io_availability (uartCtrl_io_read_queueWithOccupancy_io_availability[7:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(bridge_uartConfigReg_frame_stop) + Axi4PeripheralUartStopType_ONE : bridge_uartConfigReg_frame_stop_string = "ONE"; + Axi4PeripheralUartStopType_TWO : bridge_uartConfigReg_frame_stop_string = "TWO"; + default : bridge_uartConfigReg_frame_stop_string = "???"; + endcase + end + always @(*) begin + case(bridge_uartConfigReg_frame_parity) + Axi4PeripheralUartParityType_NONE : bridge_uartConfigReg_frame_parity_string = "NONE"; + Axi4PeripheralUartParityType_EVEN : bridge_uartConfigReg_frame_parity_string = "EVEN"; + Axi4PeripheralUartParityType_ODD : bridge_uartConfigReg_frame_parity_string = "ODD "; + default : bridge_uartConfigReg_frame_parity_string = "????"; + endcase + end + always @(*) begin + case(_zz_bridge_uartConfigReg_frame_parity) + Axi4PeripheralUartParityType_NONE : _zz_bridge_uartConfigReg_frame_parity_string = "NONE"; + Axi4PeripheralUartParityType_EVEN : _zz_bridge_uartConfigReg_frame_parity_string = "EVEN"; + Axi4PeripheralUartParityType_ODD : _zz_bridge_uartConfigReg_frame_parity_string = "ODD "; + default : _zz_bridge_uartConfigReg_frame_parity_string = "????"; + endcase + end + always @(*) begin + case(_zz_bridge_uartConfigReg_frame_stop) + Axi4PeripheralUartStopType_ONE : _zz_bridge_uartConfigReg_frame_stop_string = "ONE"; + Axi4PeripheralUartStopType_TWO : _zz_bridge_uartConfigReg_frame_stop_string = "TWO"; + default : _zz_bridge_uartConfigReg_frame_stop_string = "???"; + endcase + end + `endif + + assign io_uart_txd = uartCtrl_io_uart_txd; + assign busCtrl_readErrorFlag = 1'b0; + assign busCtrl_writeErrorFlag = 1'b0; + assign busCtrl_readHaltTrigger = 1'b0; + assign busCtrl_writeHaltTrigger = 1'b0; + assign _zz_busCtrl_rsp_ready = (! (busCtrl_readHaltTrigger || busCtrl_writeHaltTrigger)); + assign busCtrl_rsp_ready = (_zz_busCtrl_rsp_ready_1 && _zz_busCtrl_rsp_ready); + always @(*) begin + _zz_busCtrl_rsp_ready_1 = io_bus_rsp_ready; + if(when_Stream_l375) begin + _zz_busCtrl_rsp_ready_1 = 1'b1; + end + end + + assign when_Stream_l375 = (! _zz_io_bus_rsp_valid); + assign _zz_io_bus_rsp_valid = _zz_io_bus_rsp_valid_1; + assign io_bus_rsp_valid = _zz_io_bus_rsp_valid; + assign io_bus_rsp_payload_last = _zz_io_bus_rsp_payload_last; + assign io_bus_rsp_payload_fragment_opcode = _zz_io_bus_rsp_payload_fragment_opcode; + assign io_bus_rsp_payload_fragment_data = _zz_io_bus_rsp_payload_fragment_data; + assign io_bus_rsp_payload_fragment_context = _zz_io_bus_rsp_payload_fragment_context; + assign busCtrl_askWrite = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_askRead = (io_bus_cmd_valid && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign io_bus_cmd_fire = (io_bus_cmd_valid && io_bus_cmd_ready); + assign busCtrl_doWrite = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b1)); + assign busCtrl_doRead = (io_bus_cmd_fire && (io_bus_cmd_payload_fragment_opcode == 1'b0)); + assign busCtrl_rsp_valid = io_bus_cmd_valid; + assign io_bus_cmd_ready = busCtrl_rsp_ready; + assign busCtrl_rsp_payload_last = 1'b1; + assign when_BmbSlaveFactory_l33 = (busCtrl_doWrite && busCtrl_writeErrorFlag); + always @(*) begin + if(when_BmbSlaveFactory_l33) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + if(when_BmbSlaveFactory_l35) begin + busCtrl_rsp_payload_fragment_opcode = 1'b1; + end else begin + busCtrl_rsp_payload_fragment_opcode = 1'b0; + end + end + end + + assign when_BmbSlaveFactory_l35 = (busCtrl_doRead && busCtrl_readErrorFlag); + always @(*) begin + busCtrl_rsp_payload_fragment_data = 32'h0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + busCtrl_rsp_payload_fragment_data[16 : 16] = (bridge_read_streamBreaked_valid ^ 1'b0); + busCtrl_rsp_payload_fragment_data[7 : 0] = bridge_read_streamBreaked_payload; + end + 6'h04 : begin + busCtrl_rsp_payload_fragment_data[23 : 16] = _zz_busCtrl_rsp_payload_fragment_data; + busCtrl_rsp_payload_fragment_data[15 : 15] = bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid; + busCtrl_rsp_payload_fragment_data[31 : 24] = uartCtrl_io_read_queueWithOccupancy_io_occupancy; + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_interruptCtrl_writeIntEnable; + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_interruptCtrl_readIntEnable; + busCtrl_rsp_payload_fragment_data[8 : 8] = bridge_interruptCtrl_writeInt; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_interruptCtrl_readInt; + end + 6'h10 : begin + busCtrl_rsp_payload_fragment_data[0 : 0] = bridge_misc_readError; + busCtrl_rsp_payload_fragment_data[1 : 1] = bridge_misc_readOverflowError; + busCtrl_rsp_payload_fragment_data[8 : 8] = uartCtrl_io_readBreak; + busCtrl_rsp_payload_fragment_data[9 : 9] = bridge_misc_breakDetected; + end + default : begin + end + endcase + end + + assign busCtrl_rsp_payload_fragment_context = io_bus_cmd_payload_fragment_context; + assign bridge_busCtrlWrapped_readErrorFlag = 1'b0; + assign bridge_busCtrlWrapped_writeErrorFlag = 1'b0; + always @(*) begin + _zz_bridge_write_streamUnbuffered_valid = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + if(busCtrl_doWrite) begin + _zz_bridge_write_streamUnbuffered_valid = 1'b1; + end + end + default : begin + end + endcase + end + + assign bridge_write_streamUnbuffered_valid = _zz_bridge_write_streamUnbuffered_valid; + assign bridge_write_streamUnbuffered_payload = io_bus_cmd_payload_fragment_data[7 : 0]; + assign bridge_write_streamUnbuffered_ready = bridge_write_streamUnbuffered_queueWithOccupancy_io_push_ready; + always @(*) begin + bridge_read_streamBreaked_valid = uartCtrl_io_read_queueWithOccupancy_io_pop_valid; + if(uartCtrl_io_readBreak) begin + bridge_read_streamBreaked_valid = 1'b0; + end + end + + always @(*) begin + uartCtrl_io_read_queueWithOccupancy_io_pop_ready = bridge_read_streamBreaked_ready; + if(uartCtrl_io_readBreak) begin + uartCtrl_io_read_queueWithOccupancy_io_pop_ready = 1'b1; + end + end + + assign bridge_read_streamBreaked_payload = uartCtrl_io_read_queueWithOccupancy_io_pop_payload; + always @(*) begin + bridge_read_streamBreaked_ready = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h0 : begin + if(busCtrl_doRead) begin + bridge_read_streamBreaked_ready = 1'b1; + end + end + default : begin + end + endcase + end + + assign bridge_interruptCtrl_readInt = (bridge_interruptCtrl_readIntEnable && bridge_read_streamBreaked_valid); + assign bridge_interruptCtrl_writeInt = (bridge_interruptCtrl_writeIntEnable && (! bridge_write_streamUnbuffered_queueWithOccupancy_io_pop_valid)); + assign bridge_interruptCtrl_interrupt = (bridge_interruptCtrl_readInt || bridge_interruptCtrl_writeInt); + always @(*) begin + when_BusSlaveFactory_l341 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347 = io_bus_cmd_payload_fragment_data[0]; + always @(*) begin + when_BusSlaveFactory_l341_1 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_1 = io_bus_cmd_payload_fragment_data[1]; + assign uartCtrl_io_read_isStall = (uartCtrl_io_read_valid && (! uartCtrl_io_read_queueWithOccupancy_io_push_ready)); + assign when_UartCtrl_l155 = (uartCtrl_io_readBreak && (! uartCtrl_io_readBreak_regNext)); + always @(*) begin + when_BusSlaveFactory_l341_2 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_2 = io_bus_cmd_payload_fragment_data[9]; + always @(*) begin + when_BusSlaveFactory_l377 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l377 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379 = io_bus_cmd_payload_fragment_data[10]; + always @(*) begin + when_BusSlaveFactory_l341_3 = 1'b0; + case(io_bus_cmd_payload_fragment_address) + 6'h10 : begin + if(busCtrl_doWrite) begin + when_BusSlaveFactory_l341_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_3 = io_bus_cmd_payload_fragment_data[11]; + assign system_uart_0_io_interrupt_source = bridge_interruptCtrl_interrupt; + assign _zz_bridge_uartConfigReg_frame_parity = io_bus_cmd_payload_fragment_data[9 : 8]; + assign _zz_bridge_uartConfigReg_frame_stop = io_bus_cmd_payload_fragment_data[16 : 16]; + assign when_BmbSlaveFactory_l77 = ((io_bus_cmd_payload_fragment_address & (~ 6'h03)) == 6'h08); + always @(posedge clk) begin + if(reset) begin + _zz_io_bus_rsp_valid_1 <= 1'b0; + bridge_uartConfigReg_clockDivider <= 20'h0; + bridge_uartConfigReg_clockDivider <= 20'h000d8; + bridge_uartConfigReg_frame_dataLength <= 3'b111; + bridge_uartConfigReg_frame_parity <= Axi4PeripheralUartParityType_NONE; + bridge_uartConfigReg_frame_stop <= Axi4PeripheralUartStopType_ONE; + bridge_interruptCtrl_writeIntEnable <= 1'b0; + bridge_interruptCtrl_readIntEnable <= 1'b0; + bridge_misc_readError <= 1'b0; + bridge_misc_readOverflowError <= 1'b0; + bridge_misc_breakDetected <= 1'b0; + bridge_misc_doBreak <= 1'b0; + end else begin + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_bus_rsp_valid_1 <= (busCtrl_rsp_valid && _zz_busCtrl_rsp_ready); + end + if(when_BusSlaveFactory_l341) begin + if(when_BusSlaveFactory_l347) begin + bridge_misc_readError <= _zz_bridge_misc_readError[0]; + end + end + if(uartCtrl_io_readError) begin + bridge_misc_readError <= 1'b1; + end + if(when_BusSlaveFactory_l341_1) begin + if(when_BusSlaveFactory_l347_1) begin + bridge_misc_readOverflowError <= _zz_bridge_misc_readOverflowError[0]; + end + end + if(uartCtrl_io_read_isStall) begin + bridge_misc_readOverflowError <= 1'b1; + end + if(when_UartCtrl_l155) begin + bridge_misc_breakDetected <= 1'b1; + end + if(when_BusSlaveFactory_l341_2) begin + if(when_BusSlaveFactory_l347_2) begin + bridge_misc_breakDetected <= _zz_bridge_misc_breakDetected[0]; + end + end + if(when_BusSlaveFactory_l377) begin + if(when_BusSlaveFactory_l379) begin + bridge_misc_doBreak <= _zz_bridge_misc_doBreak[0]; + end + end + if(when_BusSlaveFactory_l341_3) begin + if(when_BusSlaveFactory_l347_3) begin + bridge_misc_doBreak <= _zz_bridge_misc_doBreak_1[0]; + end + end + case(io_bus_cmd_payload_fragment_address) + 6'h0c : begin + if(busCtrl_doWrite) begin + bridge_uartConfigReg_frame_dataLength <= io_bus_cmd_payload_fragment_data[2 : 0]; + bridge_uartConfigReg_frame_parity <= _zz_bridge_uartConfigReg_frame_parity; + bridge_uartConfigReg_frame_stop <= _zz_bridge_uartConfigReg_frame_stop; + end + end + 6'h04 : begin + if(busCtrl_doWrite) begin + bridge_interruptCtrl_writeIntEnable <= io_bus_cmd_payload_fragment_data[0]; + bridge_interruptCtrl_readIntEnable <= io_bus_cmd_payload_fragment_data[1]; + end + end + default : begin + end + endcase + if(when_BmbSlaveFactory_l77) begin + if(busCtrl_doWrite) begin + bridge_uartConfigReg_clockDivider[19 : 0] <= io_bus_cmd_payload_fragment_data[19 : 0]; + end + end + end + end + + always @(posedge clk) begin + if(_zz_busCtrl_rsp_ready_1) begin + _zz_io_bus_rsp_payload_last <= busCtrl_rsp_payload_last; + _zz_io_bus_rsp_payload_fragment_opcode <= busCtrl_rsp_payload_fragment_opcode; + _zz_io_bus_rsp_payload_fragment_data <= busCtrl_rsp_payload_fragment_data; + _zz_io_bus_rsp_payload_fragment_context <= busCtrl_rsp_payload_fragment_context; + end + uartCtrl_io_readBreak_regNext <= uartCtrl_io_readBreak; + end + + +endmodule + +module Axi4PeripheralBmbDecoder_1 ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [23:0] io_input_cmd_payload_fragment_address, + input wire [1:0] io_input_cmd_payload_fragment_length, + input wire [31:0] io_input_cmd_payload_fragment_data, + input wire [3:0] io_input_cmd_payload_fragment_mask, + input wire [2:0] io_input_cmd_payload_fragment_context, + output reg io_input_rsp_valid, + input wire io_input_rsp_ready, + output reg io_input_rsp_payload_last, + output reg [0:0] io_input_rsp_payload_fragment_opcode, + output wire [31:0] io_input_rsp_payload_fragment_data, + output reg [2:0] io_input_rsp_payload_fragment_context, + output reg io_outputs_0_cmd_valid, + input wire io_outputs_0_cmd_ready, + output wire io_outputs_0_cmd_payload_last, + output wire [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_0_cmd_payload_fragment_address, + output wire [1:0] io_outputs_0_cmd_payload_fragment_length, + output wire [31:0] io_outputs_0_cmd_payload_fragment_data, + output wire [3:0] io_outputs_0_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_0_cmd_payload_fragment_context, + input wire io_outputs_0_rsp_valid, + output wire io_outputs_0_rsp_ready, + input wire io_outputs_0_rsp_payload_last, + input wire [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_0_rsp_payload_fragment_data, + input wire [2:0] io_outputs_0_rsp_payload_fragment_context, + output reg io_outputs_1_cmd_valid, + input wire io_outputs_1_cmd_ready, + output wire io_outputs_1_cmd_payload_last, + output wire [0:0] io_outputs_1_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_1_cmd_payload_fragment_address, + output wire [1:0] io_outputs_1_cmd_payload_fragment_length, + output wire [31:0] io_outputs_1_cmd_payload_fragment_data, + output wire [3:0] io_outputs_1_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_1_cmd_payload_fragment_context, + input wire io_outputs_1_rsp_valid, + output wire io_outputs_1_rsp_ready, + input wire io_outputs_1_rsp_payload_last, + input wire [0:0] io_outputs_1_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_1_rsp_payload_fragment_data, + input wire [2:0] io_outputs_1_rsp_payload_fragment_context, + output reg io_outputs_2_cmd_valid, + input wire io_outputs_2_cmd_ready, + output wire io_outputs_2_cmd_payload_last, + output wire [0:0] io_outputs_2_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_2_cmd_payload_fragment_address, + output wire [1:0] io_outputs_2_cmd_payload_fragment_length, + output wire [31:0] io_outputs_2_cmd_payload_fragment_data, + output wire [3:0] io_outputs_2_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_2_cmd_payload_fragment_context, + input wire io_outputs_2_rsp_valid, + output wire io_outputs_2_rsp_ready, + input wire io_outputs_2_rsp_payload_last, + input wire [0:0] io_outputs_2_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_2_rsp_payload_fragment_data, + input wire [2:0] io_outputs_2_rsp_payload_fragment_context, + output reg io_outputs_3_cmd_valid, + input wire io_outputs_3_cmd_ready, + output wire io_outputs_3_cmd_payload_last, + output wire [0:0] io_outputs_3_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_3_cmd_payload_fragment_address, + output wire [1:0] io_outputs_3_cmd_payload_fragment_length, + output wire [31:0] io_outputs_3_cmd_payload_fragment_data, + output wire [3:0] io_outputs_3_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_3_cmd_payload_fragment_context, + input wire io_outputs_3_rsp_valid, + output wire io_outputs_3_rsp_ready, + input wire io_outputs_3_rsp_payload_last, + input wire [0:0] io_outputs_3_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_3_rsp_payload_fragment_data, + input wire [2:0] io_outputs_3_rsp_payload_fragment_context, + output reg io_outputs_4_cmd_valid, + input wire io_outputs_4_cmd_ready, + output wire io_outputs_4_cmd_payload_last, + output wire [0:0] io_outputs_4_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_4_cmd_payload_fragment_address, + output wire [1:0] io_outputs_4_cmd_payload_fragment_length, + output wire [31:0] io_outputs_4_cmd_payload_fragment_data, + output wire [3:0] io_outputs_4_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_4_cmd_payload_fragment_context, + input wire io_outputs_4_rsp_valid, + output wire io_outputs_4_rsp_ready, + input wire io_outputs_4_rsp_payload_last, + input wire [0:0] io_outputs_4_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_4_rsp_payload_fragment_data, + input wire [2:0] io_outputs_4_rsp_payload_fragment_context, + output reg io_outputs_5_cmd_valid, + input wire io_outputs_5_cmd_ready, + output wire io_outputs_5_cmd_payload_last, + output wire [0:0] io_outputs_5_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_5_cmd_payload_fragment_address, + output wire [1:0] io_outputs_5_cmd_payload_fragment_length, + output wire [31:0] io_outputs_5_cmd_payload_fragment_data, + output wire [3:0] io_outputs_5_cmd_payload_fragment_mask, + output wire [2:0] io_outputs_5_cmd_payload_fragment_context, + input wire io_outputs_5_rsp_valid, + output wire io_outputs_5_rsp_ready, + input wire io_outputs_5_rsp_payload_last, + input wire [0:0] io_outputs_5_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_5_rsp_payload_fragment_data, + input wire [2:0] io_outputs_5_rsp_payload_fragment_context, + input wire clk, + input wire reset +); + + wire [6:0] _zz_logic_rspPendingCounter; + wire [6:0] _zz_logic_rspPendingCounter_1; + wire [0:0] _zz_logic_rspPendingCounter_2; + wire [6:0] _zz_logic_rspPendingCounter_3; + wire [0:0] _zz_logic_rspPendingCounter_4; + reg _zz_io_input_rsp_payload_last_4; + reg [0:0] _zz_io_input_rsp_payload_fragment_opcode; + reg [31:0] _zz_io_input_rsp_payload_fragment_data; + reg [2:0] _zz_io_input_rsp_payload_fragment_context; + wire logic_input_valid; + reg logic_input_ready; + wire logic_input_payload_last; + wire [0:0] logic_input_payload_fragment_opcode; + wire [23:0] logic_input_payload_fragment_address; + wire [1:0] logic_input_payload_fragment_length; + wire [31:0] logic_input_payload_fragment_data; + wire [3:0] logic_input_payload_fragment_mask; + wire [2:0] logic_input_payload_fragment_context; + wire logic_hitsS0_0; + wire logic_hitsS0_1; + wire logic_hitsS0_2; + wire logic_hitsS0_3; + wire logic_hitsS0_4; + wire logic_hitsS0_5; + wire logic_noHitS0; + wire _zz_io_outputs_0_cmd_payload_last; + wire _zz_io_outputs_1_cmd_payload_last; + wire _zz_io_outputs_2_cmd_payload_last; + wire _zz_io_outputs_3_cmd_payload_last; + wire _zz_io_outputs_4_cmd_payload_last; + wire _zz_io_outputs_5_cmd_payload_last; + reg [6:0] logic_rspPendingCounter; + wire logic_input_fire; + wire io_input_rsp_fire; + wire logic_cmdWait; + wire when_BmbDecoder_l56; + reg logic_rspHits_0; + reg logic_rspHits_1; + reg logic_rspHits_2; + reg logic_rspHits_3; + reg logic_rspHits_4; + reg logic_rspHits_5; + wire logic_rspPending; + wire logic_rspNoHitValid; + reg logic_rspNoHit_doIt; + wire when_BmbDecoder_l60; + wire when_BmbDecoder_l60_1; + reg logic_rspNoHit_singleBeatRsp; + reg [2:0] logic_rspNoHit_context; + wire _zz_io_input_rsp_payload_last; + wire _zz_io_input_rsp_payload_last_1; + wire _zz_io_input_rsp_payload_last_2; + wire [2:0] _zz_io_input_rsp_payload_last_3; + + assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); + assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); + assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; + assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; + always @(*) begin + case(_zz_io_input_rsp_payload_last_3) + 3'b000 : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_0_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_0_rsp_payload_fragment_context; + end + 3'b001 : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_1_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_1_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_1_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_1_rsp_payload_fragment_context; + end + 3'b010 : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_2_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_2_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_2_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_2_rsp_payload_fragment_context; + end + 3'b011 : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_3_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_3_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_3_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_3_rsp_payload_fragment_context; + end + 3'b100 : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_4_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_4_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_4_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_4_rsp_payload_fragment_context; + end + default : begin + _zz_io_input_rsp_payload_last_4 = io_outputs_5_rsp_payload_last; + _zz_io_input_rsp_payload_fragment_opcode = io_outputs_5_rsp_payload_fragment_opcode; + _zz_io_input_rsp_payload_fragment_data = io_outputs_5_rsp_payload_fragment_data; + _zz_io_input_rsp_payload_fragment_context = io_outputs_5_rsp_payload_fragment_context; + end + endcase + end + + assign logic_input_valid = io_input_cmd_valid; + assign io_input_cmd_ready = logic_input_ready; + assign logic_input_payload_last = io_input_cmd_payload_last; + assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign logic_input_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign logic_noHitS0 = (! (|{logic_hitsS0_5,{logic_hitsS0_4,{logic_hitsS0_3,{logic_hitsS0_2,{logic_hitsS0_1,logic_hitsS0_0}}}}})); + assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 24'h00003f)) == 24'h010000); + always @(*) begin + io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); + if(logic_cmdWait) begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; + assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; + assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_0_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_1 = ((io_input_cmd_payload_fragment_address & (~ 24'h000fff)) == 24'h030000); + always @(*) begin + io_outputs_1_cmd_valid = (logic_input_valid && logic_hitsS0_1); + if(logic_cmdWait) begin + io_outputs_1_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_1_cmd_payload_last = logic_input_payload_last; + assign io_outputs_1_cmd_payload_last = _zz_io_outputs_1_cmd_payload_last; + assign io_outputs_1_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_1_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_1_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_1_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_1_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_1_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_2 = ((io_input_cmd_payload_fragment_address & (~ 24'h0000ff)) == 24'h020000); + always @(*) begin + io_outputs_2_cmd_valid = (logic_input_valid && logic_hitsS0_2); + if(logic_cmdWait) begin + io_outputs_2_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_2_cmd_payload_last = logic_input_payload_last; + assign io_outputs_2_cmd_payload_last = _zz_io_outputs_2_cmd_payload_last; + assign io_outputs_2_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_2_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_2_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_2_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_2_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_2_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_3 = ((io_input_cmd_payload_fragment_address & (~ 24'h0000ff)) == 24'h040000); + always @(*) begin + io_outputs_3_cmd_valid = (logic_input_valid && logic_hitsS0_3); + if(logic_cmdWait) begin + io_outputs_3_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_3_cmd_payload_last = logic_input_payload_last; + assign io_outputs_3_cmd_payload_last = _zz_io_outputs_3_cmd_payload_last; + assign io_outputs_3_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_3_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_3_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_3_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_3_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_3_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_4 = ((io_input_cmd_payload_fragment_address & (~ 24'h0000ff)) == 24'h050000); + always @(*) begin + io_outputs_4_cmd_valid = (logic_input_valid && logic_hitsS0_4); + if(logic_cmdWait) begin + io_outputs_4_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_4_cmd_payload_last = logic_input_payload_last; + assign io_outputs_4_cmd_payload_last = _zz_io_outputs_4_cmd_payload_last; + assign io_outputs_4_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_4_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_4_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_4_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_4_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_4_cmd_payload_fragment_context = logic_input_payload_fragment_context; + assign logic_hitsS0_5 = ((io_input_cmd_payload_fragment_address & (~ 24'h00ffff)) == 24'h100000); + always @(*) begin + io_outputs_5_cmd_valid = (logic_input_valid && logic_hitsS0_5); + if(logic_cmdWait) begin + io_outputs_5_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_5_cmd_payload_last = logic_input_payload_last; + assign io_outputs_5_cmd_payload_last = _zz_io_outputs_5_cmd_payload_last; + assign io_outputs_5_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_5_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_5_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_5_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_5_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + assign io_outputs_5_cmd_payload_fragment_context = logic_input_payload_fragment_context; + always @(*) begin + logic_input_ready = ((|{(logic_hitsS0_5 && io_outputs_5_cmd_ready),{(logic_hitsS0_4 && io_outputs_4_cmd_ready),{(logic_hitsS0_3 && io_outputs_3_cmd_ready),{(logic_hitsS0_2 && io_outputs_2_cmd_ready),{(logic_hitsS0_1 && io_outputs_1_cmd_ready),(logic_hitsS0_0 && io_outputs_0_cmd_ready)}}}}}) || logic_noHitS0); + if(logic_cmdWait) begin + logic_input_ready = 1'b0; + end + end + + assign logic_input_fire = (logic_input_valid && logic_input_ready); + assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); + assign logic_rspPending = (logic_rspPendingCounter != 7'h0); + assign logic_rspNoHitValid = (! (|{logic_rspHits_5,{logic_rspHits_4,{logic_rspHits_3,{logic_rspHits_2,{logic_rspHits_1,logic_rspHits_0}}}}})); + assign when_BmbDecoder_l60 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign when_BmbDecoder_l60_1 = ((logic_input_fire && logic_noHitS0) && logic_input_payload_last); + always @(*) begin + io_input_rsp_valid = ((|{io_outputs_5_rsp_valid,{io_outputs_4_rsp_valid,{io_outputs_3_rsp_valid,{io_outputs_2_rsp_valid,{io_outputs_1_rsp_valid,io_outputs_0_rsp_valid}}}}}) || (logic_rspPending && logic_rspNoHitValid)); + if(logic_rspNoHit_doIt) begin + io_input_rsp_valid = 1'b1; + end + end + + assign _zz_io_input_rsp_payload_last = ((logic_rspHits_1 || logic_rspHits_3) || logic_rspHits_5); + assign _zz_io_input_rsp_payload_last_1 = (logic_rspHits_2 || logic_rspHits_3); + assign _zz_io_input_rsp_payload_last_2 = (logic_rspHits_4 || logic_rspHits_5); + assign _zz_io_input_rsp_payload_last_3 = {_zz_io_input_rsp_payload_last_2,{_zz_io_input_rsp_payload_last_1,_zz_io_input_rsp_payload_last}}; + always @(*) begin + io_input_rsp_payload_last = _zz_io_input_rsp_payload_last_4; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_last = 1'b1; + end + end + + always @(*) begin + io_input_rsp_payload_fragment_opcode = _zz_io_input_rsp_payload_fragment_opcode; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_opcode = 1'b1; + end + end + + assign io_input_rsp_payload_fragment_data = _zz_io_input_rsp_payload_fragment_data; + always @(*) begin + io_input_rsp_payload_fragment_context = _zz_io_input_rsp_payload_fragment_context; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_context = logic_rspNoHit_context; + end + end + + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign io_outputs_1_rsp_ready = io_input_rsp_ready; + assign io_outputs_2_rsp_ready = io_input_rsp_ready; + assign io_outputs_3_rsp_ready = io_input_rsp_ready; + assign io_outputs_4_rsp_ready = io_input_rsp_ready; + assign io_outputs_5_rsp_ready = io_input_rsp_ready; + assign logic_cmdWait = ((logic_rspPending && (((((((logic_hitsS0_0 != logic_rspHits_0) || (logic_hitsS0_1 != logic_rspHits_1)) || (logic_hitsS0_2 != logic_rspHits_2)) || (logic_hitsS0_3 != logic_rspHits_3)) || (logic_hitsS0_4 != logic_rspHits_4)) || (logic_hitsS0_5 != logic_rspHits_5)) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); + always @(posedge clk) begin + if(reset) begin + logic_rspPendingCounter <= 7'h0; + logic_rspNoHit_doIt <= 1'b0; + end else begin + logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); + if(when_BmbDecoder_l60) begin + logic_rspNoHit_doIt <= 1'b0; + end + if(when_BmbDecoder_l60_1) begin + logic_rspNoHit_doIt <= 1'b1; + end + end + end + + always @(posedge clk) begin + if(when_BmbDecoder_l56) begin + logic_rspHits_0 <= logic_hitsS0_0; + logic_rspHits_1 <= logic_hitsS0_1; + logic_rspHits_2 <= logic_hitsS0_2; + logic_rspHits_3 <= logic_hitsS0_3; + logic_rspHits_4 <= logic_hitsS0_4; + logic_rspHits_5 <= logic_hitsS0_5; + end + if(logic_input_fire) begin + logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); + end + if(logic_input_fire) begin + logic_rspNoHit_context <= logic_input_payload_fragment_context; + end + end + + +endmodule + +module Axi4PeripheralBmbUnburstify ( + input wire io_input_cmd_valid, + output reg io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_source, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [23:0] io_input_cmd_payload_fragment_address, + input wire [9:0] io_input_cmd_payload_fragment_length, + input wire [31:0] io_input_cmd_payload_fragment_data, + input wire [3:0] io_input_cmd_payload_fragment_mask, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_source, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [31:0] io_input_rsp_payload_fragment_data, + output reg io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output reg [0:0] io_output_cmd_payload_fragment_opcode, + output reg [23:0] io_output_cmd_payload_fragment_address, + output reg [1:0] io_output_cmd_payload_fragment_length, + output wire [31:0] io_output_cmd_payload_fragment_data, + output wire [3:0] io_output_cmd_payload_fragment_mask, + output wire [2:0] io_output_cmd_payload_fragment_context, + input wire io_output_rsp_valid, + output reg io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [31:0] io_output_rsp_payload_fragment_data, + input wire [2:0] io_output_rsp_payload_fragment_context, + input wire clk, + input wire reset +); + + wire [7:0] _zz_buffer_last; + wire [0:0] _zz_buffer_last_1; + wire [11:0] _zz_buffer_addressIncr; + wire doResult; + reg buffer_valid; + reg [0:0] buffer_opcode; + reg [0:0] buffer_source; + reg [23:0] buffer_address; + reg [7:0] buffer_beat; + wire buffer_last; + wire [23:0] buffer_addressIncr; + wire buffer_isWrite; + wire io_output_cmd_fire; + wire [7:0] cmdTransferBeatCount; + wire requireBuffer; + reg cmdContext_drop; + reg cmdContext_last; + reg [0:0] cmdContext_source; + wire rspContext_drop; + wire rspContext_last; + wire [0:0] rspContext_source; + wire [2:0] _zz_rspContext_drop; + wire when_Stream_l445; + reg io_output_rsp_thrown_valid; + wire io_output_rsp_thrown_ready; + wire io_output_rsp_thrown_payload_last; + wire [0:0] io_output_rsp_thrown_payload_fragment_opcode; + wire [31:0] io_output_rsp_thrown_payload_fragment_data; + wire [2:0] io_output_rsp_thrown_payload_fragment_context; + + assign _zz_buffer_last_1 = 1'b1; + assign _zz_buffer_last = {7'd0, _zz_buffer_last_1}; + assign _zz_buffer_addressIncr = (buffer_address[11 : 0] + 12'h004); + assign buffer_last = (buffer_beat == _zz_buffer_last); + assign buffer_addressIncr = {buffer_address[23 : 12],(_zz_buffer_addressIncr & (~ 12'h003))}; + assign buffer_isWrite = (buffer_opcode == 1'b1); + assign io_output_cmd_fire = (io_output_cmd_valid && io_output_cmd_ready); + assign cmdTransferBeatCount = io_input_cmd_payload_fragment_length[9 : 2]; + assign requireBuffer = (cmdTransferBeatCount != 8'h0); + assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign io_output_cmd_payload_last = 1'b1; + assign io_output_cmd_payload_fragment_context = {cmdContext_source,{cmdContext_last,cmdContext_drop}}; + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_address = buffer_addressIncr; + end else begin + io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + if(requireBuffer) begin + io_output_cmd_payload_fragment_address[1 : 0] = 2'b00; + end + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_opcode = buffer_opcode; + end else begin + io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_payload_fragment_length = 2'b11; + end else begin + if(requireBuffer) begin + io_output_cmd_payload_fragment_length = 2'b11; + end else begin + io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length[1:0]; + end + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_source = buffer_source; + end else begin + cmdContext_source = io_input_cmd_payload_fragment_source; + end + end + + always @(*) begin + io_input_cmd_ready = 1'b0; + if(buffer_valid) begin + io_input_cmd_ready = (buffer_isWrite && io_output_cmd_ready); + end else begin + io_input_cmd_ready = io_output_cmd_ready; + end + end + + always @(*) begin + if(buffer_valid) begin + io_output_cmd_valid = (! (buffer_isWrite && (! io_input_cmd_valid))); + end else begin + io_output_cmd_valid = io_input_cmd_valid; + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_last = buffer_last; + end else begin + cmdContext_last = (! requireBuffer); + end + end + + always @(*) begin + if(buffer_valid) begin + cmdContext_drop = buffer_isWrite; + end else begin + cmdContext_drop = (io_input_cmd_payload_fragment_opcode == 1'b1); + end + end + + assign _zz_rspContext_drop = io_output_rsp_payload_fragment_context; + assign rspContext_drop = _zz_rspContext_drop[0]; + assign rspContext_last = _zz_rspContext_drop[1]; + assign rspContext_source = _zz_rspContext_drop[2 : 2]; + assign when_Stream_l445 = (! (rspContext_last || (! rspContext_drop))); + always @(*) begin + io_output_rsp_thrown_valid = io_output_rsp_valid; + if(when_Stream_l445) begin + io_output_rsp_thrown_valid = 1'b0; + end + end + + always @(*) begin + io_output_rsp_ready = io_output_rsp_thrown_ready; + if(when_Stream_l445) begin + io_output_rsp_ready = 1'b1; + end + end + + assign io_output_rsp_thrown_payload_last = io_output_rsp_payload_last; + assign io_output_rsp_thrown_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_output_rsp_thrown_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_output_rsp_thrown_payload_fragment_context = io_output_rsp_payload_fragment_context; + assign io_input_rsp_valid = io_output_rsp_thrown_valid; + assign io_output_rsp_thrown_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = rspContext_last; + assign io_input_rsp_payload_fragment_source = rspContext_source; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + always @(posedge clk) begin + if(reset) begin + buffer_valid <= 1'b0; + end else begin + if(io_output_cmd_fire) begin + if(buffer_last) begin + buffer_valid <= 1'b0; + end + end + if(!buffer_valid) begin + buffer_valid <= (requireBuffer && io_output_cmd_fire); + end + end + end + + always @(posedge clk) begin + if(io_output_cmd_fire) begin + buffer_beat <= (buffer_beat - 8'h01); + buffer_address[11 : 0] <= buffer_addressIncr[11 : 0]; + end + if(!buffer_valid) begin + buffer_opcode <= io_input_cmd_payload_fragment_opcode; + buffer_source <= io_input_cmd_payload_fragment_source; + buffer_address <= io_input_cmd_payload_fragment_address; + buffer_beat <= cmdTransferBeatCount; + end + end + + +endmodule + +module Axi4PeripheralBmbDecoder ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_source, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [23:0] io_input_cmd_payload_fragment_address, + input wire [9:0] io_input_cmd_payload_fragment_length, + input wire [31:0] io_input_cmd_payload_fragment_data, + input wire [3:0] io_input_cmd_payload_fragment_mask, + output reg io_input_rsp_valid, + input wire io_input_rsp_ready, + output reg io_input_rsp_payload_last, + output reg [0:0] io_input_rsp_payload_fragment_source, + output reg [0:0] io_input_rsp_payload_fragment_opcode, + output wire [31:0] io_input_rsp_payload_fragment_data, + output reg io_outputs_0_cmd_valid, + input wire io_outputs_0_cmd_ready, + output wire io_outputs_0_cmd_payload_last, + output wire [0:0] io_outputs_0_cmd_payload_fragment_source, + output wire [0:0] io_outputs_0_cmd_payload_fragment_opcode, + output wire [23:0] io_outputs_0_cmd_payload_fragment_address, + output wire [9:0] io_outputs_0_cmd_payload_fragment_length, + output wire [31:0] io_outputs_0_cmd_payload_fragment_data, + output wire [3:0] io_outputs_0_cmd_payload_fragment_mask, + input wire io_outputs_0_rsp_valid, + output wire io_outputs_0_rsp_ready, + input wire io_outputs_0_rsp_payload_last, + input wire [0:0] io_outputs_0_rsp_payload_fragment_source, + input wire [0:0] io_outputs_0_rsp_payload_fragment_opcode, + input wire [31:0] io_outputs_0_rsp_payload_fragment_data, + input wire clk, + input wire reset +); + + wire [6:0] _zz_logic_rspPendingCounter; + wire [6:0] _zz_logic_rspPendingCounter_1; + wire [0:0] _zz_logic_rspPendingCounter_2; + wire [6:0] _zz_logic_rspPendingCounter_3; + wire [0:0] _zz_logic_rspPendingCounter_4; + wire logic_input_valid; + reg logic_input_ready; + wire logic_input_payload_last; + wire [0:0] logic_input_payload_fragment_source; + wire [0:0] logic_input_payload_fragment_opcode; + wire [23:0] logic_input_payload_fragment_address; + wire [9:0] logic_input_payload_fragment_length; + wire [31:0] logic_input_payload_fragment_data; + wire [3:0] logic_input_payload_fragment_mask; + wire logic_hitsS0_0; + wire logic_noHitS0; + wire _zz_io_outputs_0_cmd_payload_last; + reg [6:0] logic_rspPendingCounter; + wire logic_input_fire; + wire io_input_rsp_fire; + wire logic_cmdWait; + wire when_BmbDecoder_l56; + reg logic_rspHits_0; + wire logic_rspPending; + wire logic_rspNoHitValid; + reg logic_rspNoHit_doIt; + wire when_BmbDecoder_l60; + wire when_BmbDecoder_l60_1; + reg logic_rspNoHit_singleBeatRsp; + reg [0:0] logic_rspNoHit_source; + reg [7:0] logic_rspNoHit_counter; + wire when_BmbDecoder_l81; + + assign _zz_logic_rspPendingCounter = (logic_rspPendingCounter + _zz_logic_rspPendingCounter_1); + assign _zz_logic_rspPendingCounter_2 = (logic_input_fire && logic_input_payload_last); + assign _zz_logic_rspPendingCounter_1 = {6'd0, _zz_logic_rspPendingCounter_2}; + assign _zz_logic_rspPendingCounter_4 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign _zz_logic_rspPendingCounter_3 = {6'd0, _zz_logic_rspPendingCounter_4}; + assign logic_input_valid = io_input_cmd_valid; + assign io_input_cmd_ready = logic_input_ready; + assign logic_input_payload_last = io_input_cmd_payload_last; + assign logic_input_payload_fragment_source = io_input_cmd_payload_fragment_source; + assign logic_input_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign logic_input_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign logic_input_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign logic_input_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign logic_input_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign logic_noHitS0 = (! (|logic_hitsS0_0)); + assign logic_hitsS0_0 = ((io_input_cmd_payload_fragment_address & (~ 24'hffffff)) == 24'h0); + always @(*) begin + io_outputs_0_cmd_valid = (logic_input_valid && logic_hitsS0_0); + if(logic_cmdWait) begin + io_outputs_0_cmd_valid = 1'b0; + end + end + + assign _zz_io_outputs_0_cmd_payload_last = logic_input_payload_last; + assign io_outputs_0_cmd_payload_last = _zz_io_outputs_0_cmd_payload_last; + assign io_outputs_0_cmd_payload_fragment_source = logic_input_payload_fragment_source; + assign io_outputs_0_cmd_payload_fragment_opcode = logic_input_payload_fragment_opcode; + assign io_outputs_0_cmd_payload_fragment_address = logic_input_payload_fragment_address; + assign io_outputs_0_cmd_payload_fragment_length = logic_input_payload_fragment_length; + assign io_outputs_0_cmd_payload_fragment_data = logic_input_payload_fragment_data; + assign io_outputs_0_cmd_payload_fragment_mask = logic_input_payload_fragment_mask; + always @(*) begin + logic_input_ready = ((|(logic_hitsS0_0 && io_outputs_0_cmd_ready)) || logic_noHitS0); + if(logic_cmdWait) begin + logic_input_ready = 1'b0; + end + end + + assign logic_input_fire = (logic_input_valid && logic_input_ready); + assign io_input_rsp_fire = (io_input_rsp_valid && io_input_rsp_ready); + assign when_BmbDecoder_l56 = (logic_input_valid && (! logic_cmdWait)); + assign logic_rspPending = (logic_rspPendingCounter != 7'h0); + assign logic_rspNoHitValid = (! (|logic_rspHits_0)); + assign when_BmbDecoder_l60 = (io_input_rsp_fire && io_input_rsp_payload_last); + assign when_BmbDecoder_l60_1 = ((logic_input_fire && logic_noHitS0) && logic_input_payload_last); + always @(*) begin + io_input_rsp_valid = ((|io_outputs_0_rsp_valid) || (logic_rspPending && logic_rspNoHitValid)); + if(logic_rspNoHit_doIt) begin + io_input_rsp_valid = 1'b1; + end + end + + always @(*) begin + io_input_rsp_payload_last = io_outputs_0_rsp_payload_last; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_last = 1'b0; + if(when_BmbDecoder_l81) begin + io_input_rsp_payload_last = 1'b1; + end + if(logic_rspNoHit_singleBeatRsp) begin + io_input_rsp_payload_last = 1'b1; + end + end + end + + always @(*) begin + io_input_rsp_payload_fragment_source = io_outputs_0_rsp_payload_fragment_source; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_source = logic_rspNoHit_source; + end + end + + always @(*) begin + io_input_rsp_payload_fragment_opcode = io_outputs_0_rsp_payload_fragment_opcode; + if(logic_rspNoHit_doIt) begin + io_input_rsp_payload_fragment_opcode = 1'b1; + end + end + + assign io_input_rsp_payload_fragment_data = io_outputs_0_rsp_payload_fragment_data; + assign when_BmbDecoder_l81 = (logic_rspNoHit_counter == 8'h0); + assign io_outputs_0_rsp_ready = io_input_rsp_ready; + assign logic_cmdWait = ((logic_rspPending && ((logic_hitsS0_0 != logic_rspHits_0) || logic_rspNoHitValid)) || (logic_rspPendingCounter == 7'h40)); + always @(posedge clk) begin + if(reset) begin + logic_rspPendingCounter <= 7'h0; + logic_rspNoHit_doIt <= 1'b0; + end else begin + logic_rspPendingCounter <= (_zz_logic_rspPendingCounter - _zz_logic_rspPendingCounter_3); + if(when_BmbDecoder_l60) begin + logic_rspNoHit_doIt <= 1'b0; + end + if(when_BmbDecoder_l60_1) begin + logic_rspNoHit_doIt <= 1'b1; + end + end + end + + always @(posedge clk) begin + if(when_BmbDecoder_l56) begin + logic_rspHits_0 <= logic_hitsS0_0; + end + if(logic_input_fire) begin + logic_rspNoHit_singleBeatRsp <= (logic_input_payload_fragment_opcode == 1'b1); + end + if(logic_input_fire) begin + logic_rspNoHit_source <= logic_input_payload_fragment_source; + end + if(logic_input_fire) begin + logic_rspNoHit_counter <= logic_input_payload_fragment_length[9 : 2]; + end + if(logic_rspNoHit_doIt) begin + if(io_input_rsp_fire) begin + logic_rspNoHit_counter <= (logic_rspNoHit_counter - 8'h01); + end + end + end + + +endmodule + +module Axi4PeripheralAxi4SharedToBmb ( + input wire io_axi_arw_valid, + output wire io_axi_arw_ready, + input wire [23:0] io_axi_arw_payload_addr, + input wire [7:0] io_axi_arw_payload_len, + input wire [2:0] io_axi_arw_payload_size, + input wire [3:0] io_axi_arw_payload_cache, + input wire [2:0] io_axi_arw_payload_prot, + input wire io_axi_arw_payload_write, + input wire io_axi_w_valid, + output wire io_axi_w_ready, + input wire [31:0] io_axi_w_payload_data, + input wire [3:0] io_axi_w_payload_strb, + input wire io_axi_w_payload_last, + output wire io_axi_b_valid, + input wire io_axi_b_ready, + output reg [1:0] io_axi_b_payload_resp, + output wire io_axi_r_valid, + input wire io_axi_r_ready, + output wire [31:0] io_axi_r_payload_data, + output reg [1:0] io_axi_r_payload_resp, + output wire io_axi_r_payload_last, + output wire io_bmb_cmd_valid, + input wire io_bmb_cmd_ready, + output wire io_bmb_cmd_payload_last, + output wire [0:0] io_bmb_cmd_payload_fragment_source, + output wire [0:0] io_bmb_cmd_payload_fragment_opcode, + output wire [23:0] io_bmb_cmd_payload_fragment_address, + output wire [9:0] io_bmb_cmd_payload_fragment_length, + output wire [31:0] io_bmb_cmd_payload_fragment_data, + output wire [3:0] io_bmb_cmd_payload_fragment_mask, + input wire io_bmb_rsp_valid, + output wire io_bmb_rsp_ready, + input wire io_bmb_rsp_payload_last, + input wire [0:0] io_bmb_rsp_payload_fragment_source, + input wire [0:0] io_bmb_rsp_payload_fragment_opcode, + input wire [31:0] io_bmb_rsp_payload_fragment_data +); + + wire [9:0] _zz_io_bmb_cmd_payload_fragment_length; + wire hazard; + wire io_bmb_cmd_fire; + wire rspIsWrite; + wire when_Axi4SharedToBmb_l42; + wire when_Axi4SharedToBmb_l49; + + assign _zz_io_bmb_cmd_payload_fragment_length = ({2'd0,io_axi_arw_payload_len} <<< 2'd2); + assign hazard = (io_axi_arw_payload_write && (! io_axi_w_valid)); + assign io_bmb_cmd_valid = (io_axi_arw_valid && (! hazard)); + assign io_bmb_cmd_payload_fragment_source = io_axi_arw_payload_write; + assign io_bmb_cmd_payload_fragment_opcode = io_axi_arw_payload_write; + assign io_bmb_cmd_payload_fragment_address = io_axi_arw_payload_addr; + assign io_bmb_cmd_payload_fragment_length = (_zz_io_bmb_cmd_payload_fragment_length | 10'h003); + assign io_bmb_cmd_payload_fragment_data = io_axi_w_payload_data; + assign io_bmb_cmd_payload_fragment_mask = io_axi_w_payload_strb; + assign io_bmb_cmd_payload_last = ((! io_axi_arw_payload_write) || io_axi_w_payload_last); + assign io_bmb_cmd_fire = (io_bmb_cmd_valid && io_bmb_cmd_ready); + assign io_axi_arw_ready = (io_bmb_cmd_fire && io_bmb_cmd_payload_last); + assign io_axi_w_ready = (io_bmb_cmd_fire && (io_bmb_cmd_payload_fragment_opcode == 1'b1)); + assign rspIsWrite = io_bmb_rsp_payload_fragment_source[0]; + assign io_axi_b_valid = (io_bmb_rsp_valid && rspIsWrite); + always @(*) begin + io_axi_b_payload_resp = 2'b00; + if(when_Axi4SharedToBmb_l42) begin + io_axi_b_payload_resp = 2'b11; + end + end + + assign when_Axi4SharedToBmb_l42 = (io_bmb_rsp_payload_fragment_opcode == 1'b1); + assign io_axi_r_valid = (io_bmb_rsp_valid && (! rspIsWrite)); + assign io_axi_r_payload_data = io_bmb_rsp_payload_fragment_data; + assign io_axi_r_payload_last = io_bmb_rsp_payload_last; + always @(*) begin + io_axi_r_payload_resp = 2'b00; + if(when_Axi4SharedToBmb_l49) begin + io_axi_r_payload_resp = 2'b11; + end + end + + assign when_Axi4SharedToBmb_l49 = (io_bmb_rsp_payload_fragment_opcode == 1'b1); + assign io_bmb_rsp_ready = (rspIsWrite ? io_axi_b_ready : io_axi_r_ready); + +endmodule + +module Axi4PeripheralStreamArbiter ( + input wire io_inputs_0_valid, + output wire io_inputs_0_ready, + input wire [23:0] io_inputs_0_payload_addr, + input wire [7:0] io_inputs_0_payload_len, + input wire [2:0] io_inputs_0_payload_size, + input wire [3:0] io_inputs_0_payload_cache, + input wire [2:0] io_inputs_0_payload_prot, + input wire io_inputs_1_valid, + output wire io_inputs_1_ready, + input wire [23:0] io_inputs_1_payload_addr, + input wire [7:0] io_inputs_1_payload_len, + input wire [2:0] io_inputs_1_payload_size, + input wire [3:0] io_inputs_1_payload_cache, + input wire [2:0] io_inputs_1_payload_prot, + output wire io_output_valid, + input wire io_output_ready, + output wire [23:0] io_output_payload_addr, + output wire [7:0] io_output_payload_len, + output wire [2:0] io_output_payload_size, + output wire [3:0] io_output_payload_cache, + output wire [2:0] io_output_payload_prot, + output wire [0:0] io_chosen, + output wire [1:0] io_chosenOH, + input wire clk, + input wire reset +); + + wire [3:0] _zz__zz_maskProposal_0_2; + wire [3:0] _zz__zz_maskProposal_0_2_1; + wire [1:0] _zz__zz_maskProposal_0_2_2; + reg locked; + wire maskProposal_0; + wire maskProposal_1; + reg maskLocked_0; + reg maskLocked_1; + wire maskRouted_0; + wire maskRouted_1; + wire [1:0] _zz_maskProposal_0; + wire [3:0] _zz_maskProposal_0_1; + wire [3:0] _zz_maskProposal_0_2; + wire [1:0] _zz_maskProposal_0_3; + wire io_output_fire; + wire _zz_io_chosen; + + assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); + assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; + assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; + assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); + assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); + assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; + assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; + assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); + assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); + assign maskProposal_0 = _zz_maskProposal_0_3[0]; + assign maskProposal_1 = _zz_maskProposal_0_3[1]; + assign io_output_fire = (io_output_valid && io_output_ready); + assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); + assign io_output_payload_addr = (maskRouted_0 ? io_inputs_0_payload_addr : io_inputs_1_payload_addr); + assign io_output_payload_len = (maskRouted_0 ? io_inputs_0_payload_len : io_inputs_1_payload_len); + assign io_output_payload_size = (maskRouted_0 ? io_inputs_0_payload_size : io_inputs_1_payload_size); + assign io_output_payload_cache = (maskRouted_0 ? io_inputs_0_payload_cache : io_inputs_1_payload_cache); + assign io_output_payload_prot = (maskRouted_0 ? io_inputs_0_payload_prot : io_inputs_1_payload_prot); + assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); + assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); + assign io_chosenOH = {maskRouted_1,maskRouted_0}; + assign _zz_io_chosen = io_chosenOH[1]; + assign io_chosen = _zz_io_chosen; + always @(posedge clk) begin + if(reset) begin + locked <= 1'b0; + maskLocked_0 <= 1'b0; + maskLocked_1 <= 1'b1; + end else begin + if(io_output_valid) begin + maskLocked_0 <= maskRouted_0; + maskLocked_1 <= maskRouted_1; + end + if(io_output_valid) begin + locked <= 1'b1; + end + if(io_output_fire) begin + locked <= 1'b0; + end + end + end + + +endmodule + +//Axi4PeripheralTimer_1 replaced by Axi4PeripheralTimer + +module Axi4PeripheralTimer ( + input wire io_tick, + input wire io_clear, + input wire [15:0] io_limit, + output wire io_full, + output wire [15:0] io_value, + input wire clk, + input wire reset +); + + wire [15:0] _zz_counter; + wire [0:0] _zz_counter_1; + reg [15:0] counter; + wire limitHit; + reg inhibitFull; + + assign _zz_counter_1 = (! limitHit); + assign _zz_counter = {15'd0, _zz_counter_1}; + assign limitHit = (counter == io_limit); + assign io_full = ((limitHit && io_tick) && (! inhibitFull)); + assign io_value = counter; + always @(posedge clk) begin + if(reset) begin + inhibitFull <= 1'b0; + end else begin + if(io_tick) begin + inhibitFull <= limitHit; + end + if(io_clear) begin + inhibitFull <= 1'b0; + end + end + end + + always @(posedge clk) begin + if(io_tick) begin + counter <= (counter + _zz_counter); + end + if(io_clear) begin + counter <= 16'h0; + end + end + + +endmodule + +module Axi4PeripheralPrescaler ( + input wire io_clear, + input wire [23:0] io_limit, + output wire io_overflow, + input wire clk, + input wire reset +); + + reg [23:0] counter; + wire when_Prescaler_l17; + + assign when_Prescaler_l17 = (io_clear || io_overflow); + assign io_overflow = (counter == io_limit); + always @(posedge clk) begin + counter <= (counter + 24'h000001); + if(when_Prescaler_l17) begin + counter <= 24'h0; + end + end + + +endmodule + +module Axi4PeripheralI2cSlave ( + output wire io_i2c_sda_write, + input wire io_i2c_sda_read, + output wire io_i2c_scl_write, + input wire io_i2c_scl_read, + input wire [9:0] io_config_samplingClockDivider, + input wire [19:0] io_config_timeout, + input wire [5:0] io_config_tsuData, + input wire io_config_timeoutClear, + output reg [2:0] io_bus_cmd_kind, + output wire io_bus_cmd_data, + input wire io_bus_rsp_valid, + input wire io_bus_rsp_enable, + input wire io_bus_rsp_data, + output wire io_timeout, + output wire io_internals_inFrame, + output wire io_internals_sdaRead, + output wire io_internals_sclRead, + input wire clk, + input wire reset +); + localparam Axi4PeripheralI2cSlaveCmdMode_NONE = 3'd0; + localparam Axi4PeripheralI2cSlaveCmdMode_START = 3'd1; + localparam Axi4PeripheralI2cSlaveCmdMode_RESTART = 3'd2; + localparam Axi4PeripheralI2cSlaveCmdMode_STOP = 3'd3; + localparam Axi4PeripheralI2cSlaveCmdMode_DROP = 3'd4; + localparam Axi4PeripheralI2cSlaveCmdMode_DRIVE = 3'd5; + localparam Axi4PeripheralI2cSlaveCmdMode_READ = 3'd6; + + wire io_i2c_scl_read_buffercc_io_dataOut; + wire io_i2c_sda_read_buffercc_io_dataOut; + reg [9:0] filter_timer_counter; + wire filter_timer_tick; + wire filter_sampler_sclSync; + wire filter_sampler_sdaSync; + wire filter_sampler_sclSamples_0; + wire filter_sampler_sclSamples_1; + wire filter_sampler_sclSamples_2; + wire _zz_filter_sampler_sclSamples_0; + reg _zz_filter_sampler_sclSamples_1; + reg _zz_filter_sampler_sclSamples_2; + wire filter_sampler_sdaSamples_0; + wire filter_sampler_sdaSamples_1; + wire filter_sampler_sdaSamples_2; + wire _zz_filter_sampler_sdaSamples_0; + reg _zz_filter_sampler_sdaSamples_1; + reg _zz_filter_sampler_sdaSamples_2; + reg filter_sda; + reg filter_scl; + wire when_Misc_l82; + wire when_Misc_l85; + wire sclEdge_rise; + wire sclEdge_fall; + wire sclEdge_toggle; + reg filter_scl_regNext; + wire sdaEdge_rise; + wire sdaEdge_fall; + wire sdaEdge_toggle; + reg filter_sda_regNext; + wire detector_start; + wire detector_stop; + reg [5:0] tsuData_counter; + wire tsuData_done; + reg tsuData_reset; + wire when_I2CSlave_l191; + reg ctrl_inFrame; + reg ctrl_inFrameData; + reg ctrl_sdaWrite; + reg ctrl_sclWrite; + wire ctrl_rspBufferIn_valid; + reg ctrl_rspBufferIn_ready; + wire ctrl_rspBufferIn_payload_enable; + wire ctrl_rspBufferIn_payload_data; + wire ctrl_rspBuffer_valid; + reg ctrl_rspBuffer_ready; + wire ctrl_rspBuffer_payload_enable; + wire ctrl_rspBuffer_payload_data; + reg ctrl_rspBufferIn_rValid; + reg ctrl_rspBufferIn_rData_enable; + reg ctrl_rspBufferIn_rData_data; + wire when_Stream_l375; + wire ctrl_rspAhead_valid; + wire ctrl_rspAhead_payload_enable; + wire ctrl_rspAhead_payload_data; + wire when_I2CSlave_l241; + wire when_I2CSlave_l245; + wire when_I2CSlave_l251; + wire [2:0] _zz_io_bus_cmd_kind; + reg timeout_enabled; + reg [19:0] timeout_counter; + wire timeout_tick; + wire when_I2CSlave_l270; + wire when_I2CSlave_l276; + wire [2:0] _zz_io_bus_cmd_kind_1; + `ifndef SYNTHESIS + reg [55:0] io_bus_cmd_kind_string; + reg [55:0] _zz_io_bus_cmd_kind_string; + reg [55:0] _zz_io_bus_cmd_kind_1_string; + `endif + + + (* keep_hierarchy = "TRUE" *) Axi4PeripheralBufferCC_1 io_i2c_scl_read_buffercc ( + .io_dataIn (io_i2c_scl_read ), //i + .io_dataOut (io_i2c_scl_read_buffercc_io_dataOut), //o + .clk (clk ), //i + .reset (reset ) //i + ); + (* keep_hierarchy = "TRUE" *) Axi4PeripheralBufferCC_1 io_i2c_sda_read_buffercc ( + .io_dataIn (io_i2c_sda_read ), //i + .io_dataOut (io_i2c_sda_read_buffercc_io_dataOut), //o + .clk (clk ), //i + .reset (reset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_bus_cmd_kind) + Axi4PeripheralI2cSlaveCmdMode_NONE : io_bus_cmd_kind_string = "NONE "; + Axi4PeripheralI2cSlaveCmdMode_START : io_bus_cmd_kind_string = "START "; + Axi4PeripheralI2cSlaveCmdMode_RESTART : io_bus_cmd_kind_string = "RESTART"; + Axi4PeripheralI2cSlaveCmdMode_STOP : io_bus_cmd_kind_string = "STOP "; + Axi4PeripheralI2cSlaveCmdMode_DROP : io_bus_cmd_kind_string = "DROP "; + Axi4PeripheralI2cSlaveCmdMode_DRIVE : io_bus_cmd_kind_string = "DRIVE "; + Axi4PeripheralI2cSlaveCmdMode_READ : io_bus_cmd_kind_string = "READ "; + default : io_bus_cmd_kind_string = "???????"; + endcase + end + always @(*) begin + case(_zz_io_bus_cmd_kind) + Axi4PeripheralI2cSlaveCmdMode_NONE : _zz_io_bus_cmd_kind_string = "NONE "; + Axi4PeripheralI2cSlaveCmdMode_START : _zz_io_bus_cmd_kind_string = "START "; + Axi4PeripheralI2cSlaveCmdMode_RESTART : _zz_io_bus_cmd_kind_string = "RESTART"; + Axi4PeripheralI2cSlaveCmdMode_STOP : _zz_io_bus_cmd_kind_string = "STOP "; + Axi4PeripheralI2cSlaveCmdMode_DROP : _zz_io_bus_cmd_kind_string = "DROP "; + Axi4PeripheralI2cSlaveCmdMode_DRIVE : _zz_io_bus_cmd_kind_string = "DRIVE "; + Axi4PeripheralI2cSlaveCmdMode_READ : _zz_io_bus_cmd_kind_string = "READ "; + default : _zz_io_bus_cmd_kind_string = "???????"; + endcase + end + always @(*) begin + case(_zz_io_bus_cmd_kind_1) + Axi4PeripheralI2cSlaveCmdMode_NONE : _zz_io_bus_cmd_kind_1_string = "NONE "; + Axi4PeripheralI2cSlaveCmdMode_START : _zz_io_bus_cmd_kind_1_string = "START "; + Axi4PeripheralI2cSlaveCmdMode_RESTART : _zz_io_bus_cmd_kind_1_string = "RESTART"; + Axi4PeripheralI2cSlaveCmdMode_STOP : _zz_io_bus_cmd_kind_1_string = "STOP "; + Axi4PeripheralI2cSlaveCmdMode_DROP : _zz_io_bus_cmd_kind_1_string = "DROP "; + Axi4PeripheralI2cSlaveCmdMode_DRIVE : _zz_io_bus_cmd_kind_1_string = "DRIVE "; + Axi4PeripheralI2cSlaveCmdMode_READ : _zz_io_bus_cmd_kind_1_string = "READ "; + default : _zz_io_bus_cmd_kind_1_string = "???????"; + endcase + end + `endif + + assign filter_timer_tick = (filter_timer_counter == 10'h0); + assign filter_sampler_sclSync = io_i2c_scl_read_buffercc_io_dataOut; + assign filter_sampler_sdaSync = io_i2c_sda_read_buffercc_io_dataOut; + assign _zz_filter_sampler_sclSamples_0 = filter_sampler_sclSync; + assign filter_sampler_sclSamples_0 = _zz_filter_sampler_sclSamples_0; + assign filter_sampler_sclSamples_1 = _zz_filter_sampler_sclSamples_1; + assign filter_sampler_sclSamples_2 = _zz_filter_sampler_sclSamples_2; + assign _zz_filter_sampler_sdaSamples_0 = filter_sampler_sdaSync; + assign filter_sampler_sdaSamples_0 = _zz_filter_sampler_sdaSamples_0; + assign filter_sampler_sdaSamples_1 = _zz_filter_sampler_sdaSamples_1; + assign filter_sampler_sdaSamples_2 = _zz_filter_sampler_sdaSamples_2; + assign when_Misc_l82 = (&{(filter_sampler_sdaSamples_2 != filter_sda),{(filter_sampler_sdaSamples_1 != filter_sda),(filter_sampler_sdaSamples_0 != filter_sda)}}); + assign when_Misc_l85 = (&{(filter_sampler_sclSamples_2 != filter_scl),{(filter_sampler_sclSamples_1 != filter_scl),(filter_sampler_sclSamples_0 != filter_scl)}}); + assign sclEdge_rise = ((! filter_scl_regNext) && filter_scl); + assign sclEdge_fall = (filter_scl_regNext && (! filter_scl)); + assign sclEdge_toggle = (filter_scl_regNext != filter_scl); + assign sdaEdge_rise = ((! filter_sda_regNext) && filter_sda); + assign sdaEdge_fall = (filter_sda_regNext && (! filter_sda)); + assign sdaEdge_toggle = (filter_sda_regNext != filter_sda); + assign detector_start = (filter_scl && sdaEdge_fall); + assign detector_stop = (filter_scl && sdaEdge_rise); + assign tsuData_done = (tsuData_counter == 6'h0); + always @(*) begin + tsuData_reset = 1'b0; + if(ctrl_inFrameData) begin + tsuData_reset = (! ctrl_rspAhead_valid); + end + end + + assign when_I2CSlave_l191 = (! tsuData_done); + always @(*) begin + ctrl_sdaWrite = 1'b1; + if(ctrl_inFrameData) begin + if(when_I2CSlave_l251) begin + ctrl_sdaWrite = ctrl_rspAhead_payload_data; + end + end + end + + always @(*) begin + ctrl_sclWrite = 1'b1; + if(ctrl_inFrameData) begin + if(when_I2CSlave_l245) begin + ctrl_sclWrite = 1'b0; + end + end + end + + always @(*) begin + ctrl_rspBufferIn_ready = ctrl_rspBuffer_ready; + if(when_Stream_l375) begin + ctrl_rspBufferIn_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! ctrl_rspBuffer_valid); + assign ctrl_rspBuffer_valid = ctrl_rspBufferIn_rValid; + assign ctrl_rspBuffer_payload_enable = ctrl_rspBufferIn_rData_enable; + assign ctrl_rspBuffer_payload_data = ctrl_rspBufferIn_rData_data; + assign ctrl_rspAhead_valid = (ctrl_rspBuffer_valid ? ctrl_rspBuffer_valid : ctrl_rspBufferIn_valid); + assign ctrl_rspAhead_payload_enable = (ctrl_rspBuffer_valid ? ctrl_rspBuffer_payload_enable : ctrl_rspBufferIn_payload_enable); + assign ctrl_rspAhead_payload_data = (ctrl_rspBuffer_valid ? ctrl_rspBuffer_payload_data : ctrl_rspBufferIn_payload_data); + assign ctrl_rspBufferIn_valid = io_bus_rsp_valid; + assign ctrl_rspBufferIn_payload_enable = io_bus_rsp_enable; + assign ctrl_rspBufferIn_payload_data = io_bus_rsp_data; + always @(*) begin + ctrl_rspBuffer_ready = 1'b0; + if(ctrl_inFrame) begin + if(sclEdge_fall) begin + ctrl_rspBuffer_ready = 1'b1; + end + end + end + + always @(*) begin + io_bus_cmd_kind = Axi4PeripheralI2cSlaveCmdMode_NONE; + if(ctrl_inFrame) begin + if(sclEdge_rise) begin + io_bus_cmd_kind = Axi4PeripheralI2cSlaveCmdMode_READ; + end + end + if(ctrl_inFrameData) begin + if(when_I2CSlave_l241) begin + io_bus_cmd_kind = Axi4PeripheralI2cSlaveCmdMode_DRIVE; + end + end + if(detector_start) begin + io_bus_cmd_kind = _zz_io_bus_cmd_kind; + end + if(when_I2CSlave_l276) begin + if(ctrl_inFrame) begin + io_bus_cmd_kind = _zz_io_bus_cmd_kind_1; + end + end + end + + assign io_bus_cmd_data = filter_sda; + assign when_I2CSlave_l241 = ((! ctrl_rspBuffer_valid) || ctrl_rspBuffer_ready); + assign when_I2CSlave_l245 = ((! ctrl_rspAhead_valid) || (ctrl_rspAhead_payload_enable && (! tsuData_done))); + assign when_I2CSlave_l251 = (ctrl_rspAhead_valid && ctrl_rspAhead_payload_enable); + assign _zz_io_bus_cmd_kind = (ctrl_inFrame ? Axi4PeripheralI2cSlaveCmdMode_RESTART : Axi4PeripheralI2cSlaveCmdMode_START); + assign timeout_tick = (timeout_enabled && (timeout_counter == 20'h0)); + assign when_I2CSlave_l270 = (((timeout_tick || sclEdge_toggle) || (((! ctrl_inFrame) && filter_scl) && filter_sda)) || io_config_timeoutClear); + assign io_timeout = timeout_tick; + assign when_I2CSlave_l276 = (detector_stop || timeout_tick); + assign _zz_io_bus_cmd_kind_1 = (timeout_tick ? Axi4PeripheralI2cSlaveCmdMode_DROP : Axi4PeripheralI2cSlaveCmdMode_STOP); + assign io_internals_inFrame = ctrl_inFrame; + assign io_internals_sdaRead = filter_sda; + assign io_internals_sclRead = filter_scl; + assign io_i2c_scl_write = ctrl_sclWrite; + assign io_i2c_sda_write = ctrl_sdaWrite; + always @(posedge clk) begin + if(reset) begin + filter_timer_counter <= 10'h0; + _zz_filter_sampler_sclSamples_1 <= 1'b1; + _zz_filter_sampler_sclSamples_2 <= 1'b1; + _zz_filter_sampler_sdaSamples_1 <= 1'b1; + _zz_filter_sampler_sdaSamples_2 <= 1'b1; + filter_sda <= 1'b1; + filter_scl <= 1'b1; + filter_scl_regNext <= 1'b1; + filter_sda_regNext <= 1'b1; + tsuData_counter <= 6'h0; + ctrl_inFrame <= 1'b0; + ctrl_inFrameData <= 1'b0; + ctrl_rspBufferIn_rValid <= 1'b0; + timeout_counter <= 20'h0; + end else begin + filter_timer_counter <= (filter_timer_counter - 10'h001); + if(filter_timer_tick) begin + filter_timer_counter <= io_config_samplingClockDivider; + end + if(filter_timer_tick) begin + _zz_filter_sampler_sclSamples_1 <= _zz_filter_sampler_sclSamples_0; + end + if(filter_timer_tick) begin + _zz_filter_sampler_sclSamples_2 <= _zz_filter_sampler_sclSamples_1; + end + if(filter_timer_tick) begin + _zz_filter_sampler_sdaSamples_1 <= _zz_filter_sampler_sdaSamples_0; + end + if(filter_timer_tick) begin + _zz_filter_sampler_sdaSamples_2 <= _zz_filter_sampler_sdaSamples_1; + end + if(filter_timer_tick) begin + if(when_Misc_l82) begin + filter_sda <= filter_sampler_sdaSamples_2; + end + if(when_Misc_l85) begin + filter_scl <= filter_sampler_sclSamples_2; + end + end + filter_scl_regNext <= filter_scl; + filter_sda_regNext <= filter_sda; + if(when_I2CSlave_l191) begin + tsuData_counter <= (tsuData_counter - 6'h01); + end + if(tsuData_reset) begin + tsuData_counter <= io_config_tsuData; + end + if(ctrl_rspBufferIn_ready) begin + ctrl_rspBufferIn_rValid <= ctrl_rspBufferIn_valid; + end + if(ctrl_inFrame) begin + if(sclEdge_fall) begin + ctrl_inFrameData <= 1'b1; + end + end + if(detector_start) begin + ctrl_inFrame <= 1'b1; + ctrl_inFrameData <= 1'b0; + end + timeout_counter <= (timeout_counter - 20'h00001); + if(when_I2CSlave_l270) begin + timeout_counter <= io_config_timeout; + end + if(when_I2CSlave_l276) begin + ctrl_inFrame <= 1'b0; + ctrl_inFrameData <= 1'b0; + end + end + end + + always @(posedge clk) begin + if(ctrl_rspBufferIn_ready) begin + ctrl_rspBufferIn_rData_enable <= ctrl_rspBufferIn_payload_enable; + ctrl_rspBufferIn_rData_data <= ctrl_rspBufferIn_payload_data; + end + timeout_enabled <= (io_config_timeout != 20'h0); + end + + +endmodule + +module Axi4PeripheralStreamFifo_3 ( + input wire io_push_valid, + output wire io_push_ready, + input wire [7:0] io_push_payload_data, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [7:0] io_pop_payload_data, + input wire io_flush, + output wire [8:0] io_occupancy, + output wire [8:0] io_availability, + input wire clk, + input wire reset +); + + reg [7:0] logic_ram_spinal_port1; + reg _zz_1; + wire logic_ptr_doPush; + wire logic_ptr_doPop; + wire logic_ptr_full; + wire logic_ptr_empty; + reg [8:0] logic_ptr_push; + reg [8:0] logic_ptr_pop; + wire [8:0] logic_ptr_occupancy; + wire [8:0] logic_ptr_popOnIo; + wire when_Stream_l1248; + reg logic_ptr_wentUp; + wire io_push_fire; + wire logic_push_onRam_write_valid; + wire [7:0] logic_push_onRam_write_payload_address; + wire [7:0] logic_push_onRam_write_payload_data_data; + wire logic_pop_addressGen_valid; + reg logic_pop_addressGen_ready; + wire [7:0] logic_pop_addressGen_payload; + wire logic_pop_addressGen_fire; + wire logic_pop_sync_readArbitation_valid; + wire logic_pop_sync_readArbitation_ready; + wire [7:0] logic_pop_sync_readArbitation_payload; + reg logic_pop_addressGen_rValid; + reg [7:0] logic_pop_addressGen_rData; + wire when_Stream_l375; + wire logic_pop_sync_readPort_cmd_valid; + wire [7:0] logic_pop_sync_readPort_cmd_payload; + wire [7:0] logic_pop_sync_readPort_rsp_data; + wire logic_pop_sync_readArbitation_translated_valid; + wire logic_pop_sync_readArbitation_translated_ready; + wire [7:0] logic_pop_sync_readArbitation_translated_payload_data; + wire logic_pop_sync_readArbitation_fire; + reg [8:0] logic_pop_sync_popReg; + reg [7:0] logic_ram [0:255]; + + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data_data; + end + end + + always @(posedge clk) begin + if(logic_pop_sync_readPort_cmd_valid) begin + logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_push_onRam_write_valid) begin + _zz_1 = 1'b1; + end + end + + assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); + assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 9'h100) == 9'h0); + assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop); + assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo); + assign io_push_ready = (! logic_ptr_full); + assign io_push_fire = (io_push_valid && io_push_ready); + assign logic_ptr_doPush = io_push_fire; + assign logic_push_onRam_write_valid = io_push_fire; + assign logic_push_onRam_write_payload_address = logic_ptr_push[7:0]; + assign logic_push_onRam_write_payload_data_data = io_push_payload_data; + assign logic_pop_addressGen_valid = (! logic_ptr_empty); + assign logic_pop_addressGen_payload = logic_ptr_pop[7:0]; + assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); + assign logic_ptr_doPop = logic_pop_addressGen_fire; + always @(*) begin + logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; + if(when_Stream_l375) begin + logic_pop_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); + assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; + assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; + assign logic_pop_sync_readPort_rsp_data = logic_ram_spinal_port1[7 : 0]; + assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; + assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; + assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; + assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; + assign logic_pop_sync_readArbitation_translated_payload_data = logic_pop_sync_readPort_rsp_data; + assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; + assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_data = logic_pop_sync_readArbitation_translated_payload_data; + assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); + assign logic_ptr_popOnIo = logic_pop_sync_popReg; + assign io_occupancy = logic_ptr_occupancy; + assign io_availability = (9'h100 - logic_ptr_occupancy); + always @(posedge clk) begin + if(reset) begin + logic_ptr_push <= 9'h0; + logic_ptr_pop <= 9'h0; + logic_ptr_wentUp <= 1'b0; + logic_pop_addressGen_rValid <= 1'b0; + logic_pop_sync_popReg <= 9'h0; + end else begin + if(when_Stream_l1248) begin + logic_ptr_wentUp <= logic_ptr_doPush; + end + if(io_flush) begin + logic_ptr_wentUp <= 1'b0; + end + if(logic_ptr_doPush) begin + logic_ptr_push <= (logic_ptr_push + 9'h001); + end + if(logic_ptr_doPop) begin + logic_ptr_pop <= (logic_ptr_pop + 9'h001); + end + if(io_flush) begin + logic_ptr_push <= 9'h0; + logic_ptr_pop <= 9'h0; + end + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; + end + if(io_flush) begin + logic_pop_addressGen_rValid <= 1'b0; + end + if(logic_pop_sync_readArbitation_fire) begin + logic_pop_sync_popReg <= logic_ptr_pop; + end + if(io_flush) begin + logic_pop_sync_popReg <= 9'h0; + end + end + end + + always @(posedge clk) begin + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rData <= logic_pop_addressGen_payload; + end + end + + +endmodule + +module Axi4PeripheralStreamFifo_2 ( + input wire io_push_valid, + output wire io_push_ready, + input wire io_push_payload_kind, + input wire io_push_payload_read, + input wire io_push_payload_write, + input wire [7:0] io_push_payload_data, + output wire io_pop_valid, + input wire io_pop_ready, + output wire io_pop_payload_kind, + output wire io_pop_payload_read, + output wire io_pop_payload_write, + output wire [7:0] io_pop_payload_data, + input wire io_flush, + output wire [8:0] io_occupancy, + output wire [8:0] io_availability, + input wire clk, + input wire reset +); + + reg [10:0] logic_ram_spinal_port1; + wire [10:0] _zz_logic_ram_port; + reg _zz_1; + wire logic_ptr_doPush; + wire logic_ptr_doPop; + wire logic_ptr_full; + wire logic_ptr_empty; + reg [8:0] logic_ptr_push; + reg [8:0] logic_ptr_pop; + wire [8:0] logic_ptr_occupancy; + wire [8:0] logic_ptr_popOnIo; + wire when_Stream_l1248; + reg logic_ptr_wentUp; + wire io_push_fire; + wire logic_push_onRam_write_valid; + wire [7:0] logic_push_onRam_write_payload_address; + wire logic_push_onRam_write_payload_data_kind; + wire logic_push_onRam_write_payload_data_read; + wire logic_push_onRam_write_payload_data_write; + wire [7:0] logic_push_onRam_write_payload_data_data; + wire logic_pop_addressGen_valid; + reg logic_pop_addressGen_ready; + wire [7:0] logic_pop_addressGen_payload; + wire logic_pop_addressGen_fire; + wire logic_pop_sync_readArbitation_valid; + wire logic_pop_sync_readArbitation_ready; + wire [7:0] logic_pop_sync_readArbitation_payload; + reg logic_pop_addressGen_rValid; + reg [7:0] logic_pop_addressGen_rData; + wire when_Stream_l375; + wire logic_pop_sync_readPort_cmd_valid; + wire [7:0] logic_pop_sync_readPort_cmd_payload; + wire logic_pop_sync_readPort_rsp_kind; + wire logic_pop_sync_readPort_rsp_read; + wire logic_pop_sync_readPort_rsp_write; + wire [7:0] logic_pop_sync_readPort_rsp_data; + wire [10:0] _zz_logic_pop_sync_readPort_rsp_kind; + wire logic_pop_sync_readArbitation_translated_valid; + wire logic_pop_sync_readArbitation_translated_ready; + wire logic_pop_sync_readArbitation_translated_payload_kind; + wire logic_pop_sync_readArbitation_translated_payload_read; + wire logic_pop_sync_readArbitation_translated_payload_write; + wire [7:0] logic_pop_sync_readArbitation_translated_payload_data; + wire logic_pop_sync_readArbitation_fire; + reg [8:0] logic_pop_sync_popReg; + reg [10:0] logic_ram [0:255]; + + assign _zz_logic_ram_port = {logic_push_onRam_write_payload_data_data,{logic_push_onRam_write_payload_data_write,{logic_push_onRam_write_payload_data_read,logic_push_onRam_write_payload_data_kind}}}; + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_push_onRam_write_payload_address] <= _zz_logic_ram_port; + end + end + + always @(posedge clk) begin + if(logic_pop_sync_readPort_cmd_valid) begin + logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_push_onRam_write_valid) begin + _zz_1 = 1'b1; + end + end + + assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); + assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 9'h100) == 9'h0); + assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop); + assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo); + assign io_push_ready = (! logic_ptr_full); + assign io_push_fire = (io_push_valid && io_push_ready); + assign logic_ptr_doPush = io_push_fire; + assign logic_push_onRam_write_valid = io_push_fire; + assign logic_push_onRam_write_payload_address = logic_ptr_push[7:0]; + assign logic_push_onRam_write_payload_data_kind = io_push_payload_kind; + assign logic_push_onRam_write_payload_data_read = io_push_payload_read; + assign logic_push_onRam_write_payload_data_write = io_push_payload_write; + assign logic_push_onRam_write_payload_data_data = io_push_payload_data; + assign logic_pop_addressGen_valid = (! logic_ptr_empty); + assign logic_pop_addressGen_payload = logic_ptr_pop[7:0]; + assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); + assign logic_ptr_doPop = logic_pop_addressGen_fire; + always @(*) begin + logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; + if(when_Stream_l375) begin + logic_pop_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); + assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; + assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; + assign _zz_logic_pop_sync_readPort_rsp_kind = logic_ram_spinal_port1; + assign logic_pop_sync_readPort_rsp_kind = _zz_logic_pop_sync_readPort_rsp_kind[0]; + assign logic_pop_sync_readPort_rsp_read = _zz_logic_pop_sync_readPort_rsp_kind[1]; + assign logic_pop_sync_readPort_rsp_write = _zz_logic_pop_sync_readPort_rsp_kind[2]; + assign logic_pop_sync_readPort_rsp_data = _zz_logic_pop_sync_readPort_rsp_kind[10 : 3]; + assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; + assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; + assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; + assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; + assign logic_pop_sync_readArbitation_translated_payload_kind = logic_pop_sync_readPort_rsp_kind; + assign logic_pop_sync_readArbitation_translated_payload_read = logic_pop_sync_readPort_rsp_read; + assign logic_pop_sync_readArbitation_translated_payload_write = logic_pop_sync_readPort_rsp_write; + assign logic_pop_sync_readArbitation_translated_payload_data = logic_pop_sync_readPort_rsp_data; + assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; + assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_kind = logic_pop_sync_readArbitation_translated_payload_kind; + assign io_pop_payload_read = logic_pop_sync_readArbitation_translated_payload_read; + assign io_pop_payload_write = logic_pop_sync_readArbitation_translated_payload_write; + assign io_pop_payload_data = logic_pop_sync_readArbitation_translated_payload_data; + assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); + assign logic_ptr_popOnIo = logic_pop_sync_popReg; + assign io_occupancy = logic_ptr_occupancy; + assign io_availability = (9'h100 - logic_ptr_occupancy); + always @(posedge clk) begin + if(reset) begin + logic_ptr_push <= 9'h0; + logic_ptr_pop <= 9'h0; + logic_ptr_wentUp <= 1'b0; + logic_pop_addressGen_rValid <= 1'b0; + logic_pop_sync_popReg <= 9'h0; + end else begin + if(when_Stream_l1248) begin + logic_ptr_wentUp <= logic_ptr_doPush; + end + if(io_flush) begin + logic_ptr_wentUp <= 1'b0; + end + if(logic_ptr_doPush) begin + logic_ptr_push <= (logic_ptr_push + 9'h001); + end + if(logic_ptr_doPop) begin + logic_ptr_pop <= (logic_ptr_pop + 9'h001); + end + if(io_flush) begin + logic_ptr_push <= 9'h0; + logic_ptr_pop <= 9'h0; + end + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; + end + if(io_flush) begin + logic_pop_addressGen_rValid <= 1'b0; + end + if(logic_pop_sync_readArbitation_fire) begin + logic_pop_sync_popReg <= logic_ptr_pop; + end + if(io_flush) begin + logic_pop_sync_popReg <= 9'h0; + end + end + end + + always @(posedge clk) begin + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rData <= logic_pop_addressGen_payload; + end + end + + +endmodule + +module Axi4PeripheralTopLevel ( + input wire io_config_kind_cpol, + input wire io_config_kind_cpha, + input wire [11:0] io_config_sclkToggle, + input wire [1:0] io_config_mod, + input wire [3:0] io_config_ss_activeHigh, + input wire [11:0] io_config_ss_setup, + input wire [11:0] io_config_ss_hold, + input wire [11:0] io_config_ss_disable, + input wire io_cmd_valid, + output reg io_cmd_ready, + input wire io_cmd_payload_kind, + input wire io_cmd_payload_read, + input wire io_cmd_payload_write, + input wire [7:0] io_cmd_payload_data, + output wire io_rsp_valid, + output wire [7:0] io_rsp_payload_data, + output wire [0:0] io_spi_sclk_write, + output reg io_spi_data_0_writeEnable, + input wire [0:0] io_spi_data_0_read, + output reg [0:0] io_spi_data_0_write, + output reg io_spi_data_1_writeEnable, + input wire [0:0] io_spi_data_1_read, + output reg [0:0] io_spi_data_1_write, + output reg io_spi_data_2_writeEnable, + input wire [0:0] io_spi_data_2_read, + output reg [0:0] io_spi_data_2_write, + output reg io_spi_data_3_writeEnable, + input wire [0:0] io_spi_data_3_read, + output reg [0:0] io_spi_data_3_write, + output wire [3:0] io_spi_ss, + input wire clk, + input wire reset +); + + reg [0:0] _zz_outputPhy_dataWrite_3; + wire [2:0] _zz_outputPhy_dataWrite_4; + reg [1:0] _zz_outputPhy_dataWrite_5; + wire [1:0] _zz_outputPhy_dataWrite_6; + wire [2:0] _zz_outputPhy_dataWrite_7; + reg [3:0] _zz_outputPhy_dataWrite_8; + wire [0:0] _zz_outputPhy_dataWrite_9; + wire [2:0] _zz_outputPhy_dataWrite_10; + wire [3:0] _zz_inputPhy_dataRead; + wire [3:0] _zz_inputPhy_dataRead_1; + wire [3:0] _zz_inputPhy_dataRead_2; + wire [3:0] _zz_inputPhy_dataRead_3; + wire [3:0] _zz_inputPhy_dataRead_4; + wire [3:0] _zz_inputPhy_dataRead_5; + wire [3:0] _zz_inputPhy_dataRead_6; + wire [8:0] _zz_inputPhy_bufferNext; + wire [10:0] _zz_inputPhy_bufferNext_1; + reg [11:0] timer_counter; + reg timer_reset; + wire timer_ss_setupHit; + wire timer_ss_holdHit; + wire timer_ss_disableHit; + wire timer_sclkToggleHit; + reg fsm_state; + reg [2:0] fsm_counter; + reg [2:0] _zz_fsm_counterPlus; + wire [2:0] fsm_counterPlus; + reg fsm_fastRate; + reg fsm_isDdr; + reg [2:0] fsm_counterMax; + reg fsm_lateSampling; + reg fsm_readFill; + reg fsm_readDone; + reg [3:0] fsm_ss; + wire when_SpiXdrMasterCtrl_l741; + wire when_SpiXdrMasterCtrl_l744; + wire when_SpiXdrMasterCtrl_l751; + wire when_SpiXdrMasterCtrl_l753; + wire when_SpiXdrMasterCtrl_l760; + wire when_SpiXdrMasterCtrl_l766; + wire when_SpiXdrMasterCtrl_l783; + reg [0:0] outputPhy_sclkWrite; + wire [0:0] _zz_io_spi_sclk_write; + wire when_SpiXdrMasterCtrl_l798; + reg [3:0] outputPhy_dataWrite; + reg [2:0] outputPhy_widthSel; + reg [2:0] outputPhy_offset; + wire [7:0] _zz_outputPhy_dataWrite; + wire [7:0] _zz_outputPhy_dataWrite_1; + wire [7:0] _zz_outputPhy_dataWrite_2; + wire when_SpiXdrMasterCtrl_l841; + wire when_SpiXdrMasterCtrl_l841_1; + reg [1:0] io_config_mod_delay_1; + reg [1:0] inputPhy_mod; + reg fsm_readFill_delay_1; + reg inputPhy_readFill; + reg fsm_readDone_delay_1; + reg inputPhy_readDone; + reg [6:0] inputPhy_buffer; + reg [7:0] inputPhy_bufferNext; + reg [2:0] inputPhy_widthSel; + wire [3:0] inputPhy_dataWrite; + reg [3:0] inputPhy_dataRead; + reg fsm_state_delay_1; + reg fsm_state_delay_2; + wire when_SpiXdrMasterCtrl_l863; + reg [3:0] inputPhy_dataReadBuffer; + + assign _zz_outputPhy_dataWrite_4 = (outputPhy_offset - fsm_counter); + assign _zz_outputPhy_dataWrite_6 = (_zz_outputPhy_dataWrite_7 >>> 1'd1); + assign _zz_outputPhy_dataWrite_7 = (outputPhy_offset - fsm_counter); + assign _zz_outputPhy_dataWrite_9 = (_zz_outputPhy_dataWrite_10 >>> 2'd2); + assign _zz_outputPhy_dataWrite_10 = (outputPhy_offset - fsm_counter); + assign _zz_inputPhy_dataRead = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_1 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_2 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_3 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_4 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_5 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_dataRead_6 = {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + assign _zz_inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[1 : 0]}; + assign _zz_inputPhy_bufferNext_1 = {inputPhy_buffer,inputPhy_dataRead[3 : 0]}; + always @(*) begin + case(_zz_outputPhy_dataWrite_4) + 3'b000 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[0 : 0]; + 3'b001 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[1 : 1]; + 3'b010 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[2 : 2]; + 3'b011 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[3 : 3]; + 3'b100 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[4 : 4]; + 3'b101 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[5 : 5]; + 3'b110 : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[6 : 6]; + default : _zz_outputPhy_dataWrite_3 = _zz_outputPhy_dataWrite[7 : 7]; + endcase + end + + always @(*) begin + case(_zz_outputPhy_dataWrite_6) + 2'b00 : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[1 : 0]; + 2'b01 : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[3 : 2]; + 2'b10 : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[5 : 4]; + default : _zz_outputPhy_dataWrite_5 = _zz_outputPhy_dataWrite_1[7 : 6]; + endcase + end + + always @(*) begin + case(_zz_outputPhy_dataWrite_9) + 1'b0 : _zz_outputPhy_dataWrite_8 = _zz_outputPhy_dataWrite_2[3 : 0]; + default : _zz_outputPhy_dataWrite_8 = _zz_outputPhy_dataWrite_2[7 : 4]; + endcase + end + + always @(*) begin + timer_reset = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l741) begin + timer_reset = timer_sclkToggleHit; + end else begin + if(!when_SpiXdrMasterCtrl_l760) begin + if(when_SpiXdrMasterCtrl_l766) begin + if(timer_ss_holdHit) begin + timer_reset = 1'b1; + end + end + end + end + end + if(when_SpiXdrMasterCtrl_l783) begin + timer_reset = 1'b1; + end + end + + assign timer_ss_setupHit = (timer_counter == io_config_ss_setup); + assign timer_ss_holdHit = (timer_counter == io_config_ss_hold); + assign timer_ss_disableHit = (timer_counter == io_config_ss_disable); + assign timer_sclkToggleHit = (timer_counter == io_config_sclkToggle); + always @(*) begin + _zz_fsm_counterPlus = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + _zz_fsm_counterPlus = 3'b001; + end + 2'b01 : begin + _zz_fsm_counterPlus = 3'b010; + end + 2'b10 : begin + _zz_fsm_counterPlus = 3'b100; + end + default : begin + end + endcase + end + + assign fsm_counterPlus = (fsm_counter + _zz_fsm_counterPlus); + always @(*) begin + fsm_fastRate = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_fastRate = 1'b0; + end + 2'b01 : begin + fsm_fastRate = 1'b0; + end + 2'b10 : begin + fsm_fastRate = 1'b0; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_isDdr = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_isDdr = 1'b0; + end + 2'b01 : begin + fsm_isDdr = 1'b0; + end + 2'b10 : begin + fsm_isDdr = 1'b0; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_counterMax = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + fsm_counterMax = 3'b111; + end + 2'b01 : begin + fsm_counterMax = 3'b110; + end + 2'b10 : begin + fsm_counterMax = 3'b100; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_lateSampling = 1'bx; + case(io_config_mod) + 2'b00 : begin + fsm_lateSampling = 1'b1; + end + 2'b01 : begin + fsm_lateSampling = 1'b1; + end + 2'b10 : begin + fsm_lateSampling = 1'b1; + end + default : begin + end + endcase + end + + always @(*) begin + fsm_readFill = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l741) begin + if(when_SpiXdrMasterCtrl_l744) begin + fsm_readFill = 1'b1; + end + end + end + end + + always @(*) begin + fsm_readDone = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l741) begin + if(when_SpiXdrMasterCtrl_l744) begin + fsm_readDone = (io_cmd_payload_read && (fsm_counter == fsm_counterMax)); + end + end + end + end + + assign io_spi_ss = (~ (fsm_ss ^ io_config_ss_activeHigh)); + always @(*) begin + io_cmd_ready = 1'b0; + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l741) begin + if(when_SpiXdrMasterCtrl_l751) begin + if(when_SpiXdrMasterCtrl_l753) begin + io_cmd_ready = 1'b1; + end + end + end else begin + if(when_SpiXdrMasterCtrl_l760) begin + if(timer_ss_setupHit) begin + io_cmd_ready = 1'b1; + end + end else begin + if(!when_SpiXdrMasterCtrl_l766) begin + if(timer_ss_disableHit) begin + io_cmd_ready = 1'b1; + end + end + end + end + end + end + + assign when_SpiXdrMasterCtrl_l741 = (! io_cmd_payload_kind); + assign when_SpiXdrMasterCtrl_l744 = ((timer_sclkToggleHit && (((! fsm_state) ^ fsm_lateSampling) || fsm_isDdr)) || fsm_fastRate); + assign when_SpiXdrMasterCtrl_l751 = ((timer_sclkToggleHit && (fsm_state || fsm_isDdr)) || fsm_fastRate); + assign when_SpiXdrMasterCtrl_l753 = (fsm_counter == fsm_counterMax); + assign when_SpiXdrMasterCtrl_l760 = io_cmd_payload_data[7]; + assign when_SpiXdrMasterCtrl_l766 = (! fsm_state); + assign when_SpiXdrMasterCtrl_l783 = ((! io_cmd_valid) || io_cmd_ready); + always @(*) begin + outputPhy_sclkWrite = 1'b0; + if(when_SpiXdrMasterCtrl_l798) begin + case(io_config_mod) + 2'b00 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + 2'b01 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + 2'b10 : begin + outputPhy_sclkWrite = ((fsm_state ^ io_config_kind_cpha) ? 1'b1 : 1'b0); + end + default : begin + end + endcase + end + end + + assign _zz_io_spi_sclk_write[0] = io_config_kind_cpol; + assign io_spi_sclk_write = (outputPhy_sclkWrite ^ _zz_io_spi_sclk_write); + assign when_SpiXdrMasterCtrl_l798 = (io_cmd_valid && (! io_cmd_payload_kind)); + always @(*) begin + outputPhy_widthSel = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + outputPhy_widthSel = 3'b000; + end + 2'b01 : begin + outputPhy_widthSel = 3'b001; + end + 2'b10 : begin + outputPhy_widthSel = 3'b010; + end + default : begin + end + endcase + end + + always @(*) begin + outputPhy_offset = 3'bxxx; + case(io_config_mod) + 2'b00 : begin + outputPhy_offset = 3'b111; + end + 2'b01 : begin + outputPhy_offset = 3'b111; + end + 2'b10 : begin + outputPhy_offset = 3'b111; + end + default : begin + end + endcase + end + + always @(*) begin + outputPhy_dataWrite = 4'bxxxx; + case(outputPhy_widthSel) + 3'b000 : begin + outputPhy_dataWrite[0 : 0] = _zz_outputPhy_dataWrite_3; + end + 3'b001 : begin + outputPhy_dataWrite[1 : 0] = _zz_outputPhy_dataWrite_5; + end + 3'b010 : begin + outputPhy_dataWrite[3 : 0] = _zz_outputPhy_dataWrite_8; + end + default : begin + end + endcase + end + + assign _zz_outputPhy_dataWrite = io_cmd_payload_data; + assign _zz_outputPhy_dataWrite_1 = io_cmd_payload_data; + assign _zz_outputPhy_dataWrite_2 = io_cmd_payload_data; + always @(*) begin + io_spi_data_0_writeEnable = 1'b0; + case(io_config_mod) + 2'b00 : begin + io_spi_data_0_writeEnable = 1'b1; + end + 2'b01 : begin + if(when_SpiXdrMasterCtrl_l841) begin + io_spi_data_0_writeEnable = 1'b1; + end + end + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l841_1) begin + io_spi_data_0_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_1_writeEnable = 1'b0; + case(io_config_mod) + 2'b01 : begin + if(when_SpiXdrMasterCtrl_l841) begin + io_spi_data_1_writeEnable = 1'b1; + end + end + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l841_1) begin + io_spi_data_1_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_2_writeEnable = 1'b0; + case(io_config_mod) + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l841_1) begin + io_spi_data_2_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_3_writeEnable = 1'b0; + case(io_config_mod) + 2'b10 : begin + if(when_SpiXdrMasterCtrl_l841_1) begin + io_spi_data_3_writeEnable = 1'b1; + end + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_0_write = 1'bx; + case(io_config_mod) + 2'b00 : begin + io_spi_data_0_write[0] = (outputPhy_dataWrite[0] || (! (io_cmd_valid && io_cmd_payload_write))); + end + 2'b01 : begin + io_spi_data_0_write[0] = outputPhy_dataWrite[0]; + end + 2'b10 : begin + io_spi_data_0_write[0] = outputPhy_dataWrite[0]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_1_write = 1'bx; + case(io_config_mod) + 2'b01 : begin + io_spi_data_1_write[0] = outputPhy_dataWrite[1]; + end + 2'b10 : begin + io_spi_data_1_write[0] = outputPhy_dataWrite[1]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_2_write = 1'bx; + case(io_config_mod) + 2'b10 : begin + io_spi_data_2_write[0] = outputPhy_dataWrite[2]; + end + default : begin + end + endcase + end + + always @(*) begin + io_spi_data_3_write = 1'bx; + case(io_config_mod) + 2'b10 : begin + io_spi_data_3_write[0] = outputPhy_dataWrite[3]; + end + default : begin + end + endcase + end + + assign when_SpiXdrMasterCtrl_l841 = (io_cmd_valid && io_cmd_payload_write); + assign when_SpiXdrMasterCtrl_l841_1 = (io_cmd_valid && io_cmd_payload_write); + always @(*) begin + inputPhy_bufferNext = 8'bxxxxxxxx; + case(inputPhy_widthSel) + 3'b000 : begin + inputPhy_bufferNext = {inputPhy_buffer,inputPhy_dataRead[0 : 0]}; + end + 3'b001 : begin + inputPhy_bufferNext = _zz_inputPhy_bufferNext[7:0]; + end + 3'b010 : begin + inputPhy_bufferNext = _zz_inputPhy_bufferNext_1[7:0]; + end + default : begin + end + endcase + end + + always @(*) begin + inputPhy_widthSel = 3'bxxx; + case(inputPhy_mod) + 2'b00 : begin + inputPhy_widthSel = 3'b000; + end + 2'b01 : begin + inputPhy_widthSel = 3'b001; + end + 2'b10 : begin + inputPhy_widthSel = 3'b010; + end + default : begin + end + endcase + end + + assign when_SpiXdrMasterCtrl_l863 = (! fsm_state_delay_2); + always @(*) begin + inputPhy_dataRead = 4'bxxxx; + case(inputPhy_mod) + 2'b00 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead[1]; + end + 2'b01 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead_1[0]; + inputPhy_dataRead[1] = _zz_inputPhy_dataRead_2[1]; + end + 2'b10 : begin + inputPhy_dataRead[0] = _zz_inputPhy_dataRead_3[0]; + inputPhy_dataRead[1] = _zz_inputPhy_dataRead_4[1]; + inputPhy_dataRead[2] = _zz_inputPhy_dataRead_5[2]; + inputPhy_dataRead[3] = _zz_inputPhy_dataRead_6[3]; + end + default : begin + end + endcase + end + + assign io_rsp_valid = inputPhy_readDone; + assign io_rsp_payload_data = inputPhy_bufferNext; + always @(posedge clk) begin + timer_counter <= (timer_counter + 12'h001); + if(timer_reset) begin + timer_counter <= 12'h0; + end + io_config_mod_delay_1 <= io_config_mod; + inputPhy_mod <= io_config_mod_delay_1; + fsm_state_delay_1 <= fsm_state; + fsm_state_delay_2 <= fsm_state_delay_1; + if(when_SpiXdrMasterCtrl_l863) begin + inputPhy_dataReadBuffer <= {io_spi_data_3_read[0],{io_spi_data_2_read[0],{io_spi_data_1_read[0],io_spi_data_0_read[0]}}}; + end + case(inputPhy_widthSel) + 3'b000 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + 3'b001 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + 3'b010 : begin + if(inputPhy_readFill) begin + inputPhy_buffer <= inputPhy_bufferNext[6:0]; + end + end + default : begin + end + endcase + end + + always @(posedge clk) begin + if(reset) begin + fsm_state <= 1'b0; + fsm_counter <= 3'b000; + fsm_ss <= 4'b0000; + fsm_readFill_delay_1 <= 1'b0; + inputPhy_readFill <= 1'b0; + fsm_readDone_delay_1 <= 1'b0; + inputPhy_readDone <= 1'b0; + end else begin + if(io_cmd_valid) begin + if(when_SpiXdrMasterCtrl_l741) begin + if(timer_sclkToggleHit) begin + fsm_state <= (! fsm_state); + end + if(when_SpiXdrMasterCtrl_l751) begin + fsm_counter <= fsm_counterPlus; + if(when_SpiXdrMasterCtrl_l753) begin + fsm_state <= 1'b0; + end + end + end else begin + if(when_SpiXdrMasterCtrl_l760) begin + fsm_ss[io_cmd_payload_data[1 : 0]] <= 1'b1; + end else begin + if(when_SpiXdrMasterCtrl_l766) begin + if(timer_ss_holdHit) begin + fsm_state <= 1'b1; + end + end else begin + fsm_ss[io_cmd_payload_data[1 : 0]] <= 1'b0; + end + end + end + end + if(when_SpiXdrMasterCtrl_l783) begin + fsm_state <= 1'b0; + fsm_counter <= 3'b000; + end + fsm_readFill_delay_1 <= fsm_readFill; + inputPhy_readFill <= fsm_readFill_delay_1; + fsm_readDone_delay_1 <= fsm_readDone; + inputPhy_readDone <= fsm_readDone_delay_1; + end + end + + +endmodule + +//Axi4PeripheralStreamFifo_1 replaced by Axi4PeripheralStreamFifo + +module Axi4PeripheralStreamFifo ( + input wire io_push_valid, + output wire io_push_ready, + input wire [7:0] io_push_payload, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [7:0] io_pop_payload, + input wire io_flush, + output wire [7:0] io_occupancy, + output wire [7:0] io_availability, + input wire clk, + input wire reset +); + + reg [7:0] logic_ram_spinal_port1; + reg _zz_1; + wire logic_ptr_doPush; + wire logic_ptr_doPop; + wire logic_ptr_full; + wire logic_ptr_empty; + reg [7:0] logic_ptr_push; + reg [7:0] logic_ptr_pop; + wire [7:0] logic_ptr_occupancy; + wire [7:0] logic_ptr_popOnIo; + wire when_Stream_l1248; + reg logic_ptr_wentUp; + wire io_push_fire; + wire logic_push_onRam_write_valid; + wire [6:0] logic_push_onRam_write_payload_address; + wire [7:0] logic_push_onRam_write_payload_data; + wire logic_pop_addressGen_valid; + reg logic_pop_addressGen_ready; + wire [6:0] logic_pop_addressGen_payload; + wire logic_pop_addressGen_fire; + wire logic_pop_sync_readArbitation_valid; + wire logic_pop_sync_readArbitation_ready; + wire [6:0] logic_pop_sync_readArbitation_payload; + reg logic_pop_addressGen_rValid; + reg [6:0] logic_pop_addressGen_rData; + wire when_Stream_l375; + wire logic_pop_sync_readPort_cmd_valid; + wire [6:0] logic_pop_sync_readPort_cmd_payload; + wire [7:0] logic_pop_sync_readPort_rsp; + wire logic_pop_sync_readArbitation_translated_valid; + wire logic_pop_sync_readArbitation_translated_ready; + wire [7:0] logic_pop_sync_readArbitation_translated_payload; + wire logic_pop_sync_readArbitation_fire; + reg [7:0] logic_pop_sync_popReg; + reg [7:0] logic_ram [0:127]; + + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data; + end + end + + always @(posedge clk) begin + if(logic_pop_sync_readPort_cmd_valid) begin + logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_push_onRam_write_valid) begin + _zz_1 = 1'b1; + end + end + + assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); + assign logic_ptr_full = (((logic_ptr_push ^ logic_ptr_popOnIo) ^ 8'h80) == 8'h0); + assign logic_ptr_empty = (logic_ptr_push == logic_ptr_pop); + assign logic_ptr_occupancy = (logic_ptr_push - logic_ptr_popOnIo); + assign io_push_ready = (! logic_ptr_full); + assign io_push_fire = (io_push_valid && io_push_ready); + assign logic_ptr_doPush = io_push_fire; + assign logic_push_onRam_write_valid = io_push_fire; + assign logic_push_onRam_write_payload_address = logic_ptr_push[6:0]; + assign logic_push_onRam_write_payload_data = io_push_payload; + assign logic_pop_addressGen_valid = (! logic_ptr_empty); + assign logic_pop_addressGen_payload = logic_ptr_pop[6:0]; + assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); + assign logic_ptr_doPop = logic_pop_addressGen_fire; + always @(*) begin + logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; + if(when_Stream_l375) begin + logic_pop_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); + assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; + assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; + assign logic_pop_sync_readPort_rsp = logic_ram_spinal_port1; + assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; + assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; + assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; + assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; + assign logic_pop_sync_readArbitation_translated_payload = logic_pop_sync_readPort_rsp; + assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; + assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload = logic_pop_sync_readArbitation_translated_payload; + assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); + assign logic_ptr_popOnIo = logic_pop_sync_popReg; + assign io_occupancy = logic_ptr_occupancy; + assign io_availability = (8'h80 - logic_ptr_occupancy); + always @(posedge clk) begin + if(reset) begin + logic_ptr_push <= 8'h0; + logic_ptr_pop <= 8'h0; + logic_ptr_wentUp <= 1'b0; + logic_pop_addressGen_rValid <= 1'b0; + logic_pop_sync_popReg <= 8'h0; + end else begin + if(when_Stream_l1248) begin + logic_ptr_wentUp <= logic_ptr_doPush; + end + if(io_flush) begin + logic_ptr_wentUp <= 1'b0; + end + if(logic_ptr_doPush) begin + logic_ptr_push <= (logic_ptr_push + 8'h01); + end + if(logic_ptr_doPop) begin + logic_ptr_pop <= (logic_ptr_pop + 8'h01); + end + if(io_flush) begin + logic_ptr_push <= 8'h0; + logic_ptr_pop <= 8'h0; + end + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; + end + if(io_flush) begin + logic_pop_addressGen_rValid <= 1'b0; + end + if(logic_pop_sync_readArbitation_fire) begin + logic_pop_sync_popReg <= logic_ptr_pop; + end + if(io_flush) begin + logic_pop_sync_popReg <= 8'h0; + end + end + end + + always @(posedge clk) begin + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rData <= logic_pop_addressGen_payload; + end + end + + +endmodule + +module Axi4PeripheralUartCtrl ( + input wire [2:0] io_config_frame_dataLength, + input wire [0:0] io_config_frame_stop, + input wire [1:0] io_config_frame_parity, + input wire [19:0] io_config_clockDivider, + input wire io_write_valid, + output reg io_write_ready, + input wire [7:0] io_write_payload, + output wire io_read_valid, + input wire io_read_ready, + output wire [7:0] io_read_payload, + output wire io_uart_txd, + input wire io_uart_rxd, + output wire io_readError, + input wire io_writeBreak, + output wire io_readBreak, + input wire clk, + input wire reset +); + localparam Axi4PeripheralUartStopType_ONE = 1'd0; + localparam Axi4PeripheralUartStopType_TWO = 1'd1; + localparam Axi4PeripheralUartParityType_NONE = 2'd0; + localparam Axi4PeripheralUartParityType_EVEN = 2'd1; + localparam Axi4PeripheralUartParityType_ODD = 2'd2; + + wire tx_io_write_ready; + wire tx_io_txd; + wire rx_io_read_valid; + wire [7:0] rx_io_read_payload; + wire rx_io_rts; + wire rx_io_error; + wire rx_io_break; + reg [19:0] clockDivider_counter; + wire clockDivider_tick; + reg clockDivider_tickReg; + reg io_write_thrown_valid; + wire io_write_thrown_ready; + wire [7:0] io_write_thrown_payload; + `ifndef SYNTHESIS + reg [23:0] io_config_frame_stop_string; + reg [31:0] io_config_frame_parity_string; + `endif + + + Axi4PeripheralUartCtrlTx tx ( + .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i + .io_configFrame_stop (io_config_frame_stop ), //i + .io_configFrame_parity (io_config_frame_parity[1:0] ), //i + .io_samplingTick (clockDivider_tickReg ), //i + .io_write_valid (io_write_thrown_valid ), //i + .io_write_ready (tx_io_write_ready ), //o + .io_write_payload (io_write_thrown_payload[7:0] ), //i + .io_cts (1'b0 ), //i + .io_txd (tx_io_txd ), //o + .io_break (io_writeBreak ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Axi4PeripheralUartCtrlRx rx ( + .io_configFrame_dataLength (io_config_frame_dataLength[2:0]), //i + .io_configFrame_stop (io_config_frame_stop ), //i + .io_configFrame_parity (io_config_frame_parity[1:0] ), //i + .io_samplingTick (clockDivider_tickReg ), //i + .io_read_valid (rx_io_read_valid ), //o + .io_read_ready (io_read_ready ), //i + .io_read_payload (rx_io_read_payload[7:0] ), //o + .io_rxd (io_uart_rxd ), //i + .io_rts (rx_io_rts ), //o + .io_error (rx_io_error ), //o + .io_break (rx_io_break ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_config_frame_stop) + Axi4PeripheralUartStopType_ONE : io_config_frame_stop_string = "ONE"; + Axi4PeripheralUartStopType_TWO : io_config_frame_stop_string = "TWO"; + default : io_config_frame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_config_frame_parity) + Axi4PeripheralUartParityType_NONE : io_config_frame_parity_string = "NONE"; + Axi4PeripheralUartParityType_EVEN : io_config_frame_parity_string = "EVEN"; + Axi4PeripheralUartParityType_ODD : io_config_frame_parity_string = "ODD "; + default : io_config_frame_parity_string = "????"; + endcase + end + `endif + + assign clockDivider_tick = (clockDivider_counter == 20'h0); + always @(*) begin + io_write_thrown_valid = io_write_valid; + if(rx_io_break) begin + io_write_thrown_valid = 1'b0; + end + end + + always @(*) begin + io_write_ready = io_write_thrown_ready; + if(rx_io_break) begin + io_write_ready = 1'b1; + end + end + + assign io_write_thrown_payload = io_write_payload; + assign io_write_thrown_ready = tx_io_write_ready; + assign io_read_valid = rx_io_read_valid; + assign io_read_payload = rx_io_read_payload; + assign io_uart_txd = tx_io_txd; + assign io_readError = rx_io_error; + assign io_readBreak = rx_io_break; + always @(posedge clk) begin + if(reset) begin + clockDivider_counter <= 20'h0; + clockDivider_tickReg <= 1'b0; + end else begin + clockDivider_tickReg <= clockDivider_tick; + clockDivider_counter <= (clockDivider_counter - 20'h00001); + if(clockDivider_tick) begin + clockDivider_counter <= io_config_clockDivider; + end + end + end + + +endmodule + +//Axi4PeripheralBufferCC_2 replaced by Axi4PeripheralBufferCC_1 + +module Axi4PeripheralBufferCC_1 ( + input wire io_dataIn, + output wire io_dataOut, + input wire clk, + input wire reset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge clk) begin + if(reset) begin + buffers_0 <= 1'b1; + buffers_1 <= 1'b1; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module Axi4PeripheralUartCtrlRx ( + input wire [2:0] io_configFrame_dataLength, + input wire [0:0] io_configFrame_stop, + input wire [1:0] io_configFrame_parity, + input wire io_samplingTick, + output wire io_read_valid, + input wire io_read_ready, + output wire [7:0] io_read_payload, + input wire io_rxd, + output wire io_rts, + output reg io_error, + output wire io_break, + input wire clk, + input wire reset +); + localparam Axi4PeripheralUartStopType_ONE = 1'd0; + localparam Axi4PeripheralUartStopType_TWO = 1'd1; + localparam Axi4PeripheralUartParityType_NONE = 2'd0; + localparam Axi4PeripheralUartParityType_EVEN = 2'd1; + localparam Axi4PeripheralUartParityType_ODD = 2'd2; + localparam Axi4PeripheralUartCtrlRxState_IDLE = 3'd0; + localparam Axi4PeripheralUartCtrlRxState_START = 3'd1; + localparam Axi4PeripheralUartCtrlRxState_DATA = 3'd2; + localparam Axi4PeripheralUartCtrlRxState_PARITY = 3'd3; + localparam Axi4PeripheralUartCtrlRxState_STOP = 3'd4; + + wire io_rxd_buffercc_io_dataOut; + wire _zz_sampler_value; + wire _zz_sampler_value_1; + wire _zz_sampler_value_2; + wire _zz_sampler_value_3; + wire _zz_sampler_value_4; + wire _zz_sampler_value_5; + wire _zz_sampler_value_6; + wire [2:0] _zz_when_UartCtrlRx_l139; + wire [0:0] _zz_when_UartCtrlRx_l139_1; + reg _zz_io_rts; + wire sampler_synchroniser; + wire sampler_samples_0; + reg sampler_samples_1; + reg sampler_samples_2; + reg sampler_samples_3; + reg sampler_samples_4; + reg sampler_value; + reg sampler_tick; + reg [2:0] bitTimer_counter; + reg bitTimer_tick; + wire when_UartCtrlRx_l43; + reg [2:0] bitCounter_value; + reg [6:0] break_counter; + wire break_valid; + wire when_UartCtrlRx_l69; + reg [2:0] stateMachine_state; + reg stateMachine_parity; + reg [7:0] stateMachine_shifter; + reg stateMachine_validReg; + wire when_UartCtrlRx_l93; + wire when_UartCtrlRx_l103; + wire when_UartCtrlRx_l111; + wire when_UartCtrlRx_l113; + wire when_UartCtrlRx_l125; + wire when_UartCtrlRx_l136; + wire when_UartCtrlRx_l139; + `ifndef SYNTHESIS + reg [23:0] io_configFrame_stop_string; + reg [31:0] io_configFrame_parity_string; + reg [47:0] stateMachine_state_string; + `endif + + + assign _zz_when_UartCtrlRx_l139_1 = ((io_configFrame_stop == Axi4PeripheralUartStopType_ONE) ? 1'b0 : 1'b1); + assign _zz_when_UartCtrlRx_l139 = {2'd0, _zz_when_UartCtrlRx_l139_1}; + assign _zz_sampler_value = ((((1'b0 || ((_zz_sampler_value_1 && sampler_samples_1) && sampler_samples_2)) || (((_zz_sampler_value_2 && sampler_samples_0) && sampler_samples_1) && sampler_samples_3)) || (((1'b1 && sampler_samples_0) && sampler_samples_2) && sampler_samples_3)) || (((1'b1 && sampler_samples_1) && sampler_samples_2) && sampler_samples_3)); + assign _zz_sampler_value_3 = (((1'b1 && sampler_samples_0) && sampler_samples_1) && sampler_samples_4); + assign _zz_sampler_value_4 = ((1'b1 && sampler_samples_0) && sampler_samples_2); + assign _zz_sampler_value_5 = (1'b1 && sampler_samples_1); + assign _zz_sampler_value_6 = 1'b1; + assign _zz_sampler_value_1 = (1'b1 && sampler_samples_0); + assign _zz_sampler_value_2 = 1'b1; + (* keep_hierarchy = "TRUE" *) Axi4PeripheralBufferCC io_rxd_buffercc ( + .io_dataIn (io_rxd ), //i + .io_dataOut (io_rxd_buffercc_io_dataOut), //o + .clk (clk ), //i + .reset (reset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(io_configFrame_stop) + Axi4PeripheralUartStopType_ONE : io_configFrame_stop_string = "ONE"; + Axi4PeripheralUartStopType_TWO : io_configFrame_stop_string = "TWO"; + default : io_configFrame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_configFrame_parity) + Axi4PeripheralUartParityType_NONE : io_configFrame_parity_string = "NONE"; + Axi4PeripheralUartParityType_EVEN : io_configFrame_parity_string = "EVEN"; + Axi4PeripheralUartParityType_ODD : io_configFrame_parity_string = "ODD "; + default : io_configFrame_parity_string = "????"; + endcase + end + always @(*) begin + case(stateMachine_state) + Axi4PeripheralUartCtrlRxState_IDLE : stateMachine_state_string = "IDLE "; + Axi4PeripheralUartCtrlRxState_START : stateMachine_state_string = "START "; + Axi4PeripheralUartCtrlRxState_DATA : stateMachine_state_string = "DATA "; + Axi4PeripheralUartCtrlRxState_PARITY : stateMachine_state_string = "PARITY"; + Axi4PeripheralUartCtrlRxState_STOP : stateMachine_state_string = "STOP "; + default : stateMachine_state_string = "??????"; + endcase + end + `endif + + always @(*) begin + io_error = 1'b0; + case(stateMachine_state) + Axi4PeripheralUartCtrlRxState_IDLE : begin + end + Axi4PeripheralUartCtrlRxState_START : begin + end + Axi4PeripheralUartCtrlRxState_DATA : begin + end + Axi4PeripheralUartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + if(!when_UartCtrlRx_l125) begin + io_error = 1'b1; + end + end + end + default : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l136) begin + io_error = 1'b1; + end + end + end + endcase + end + + assign io_rts = _zz_io_rts; + assign sampler_synchroniser = io_rxd_buffercc_io_dataOut; + assign sampler_samples_0 = sampler_synchroniser; + always @(*) begin + bitTimer_tick = 1'b0; + if(sampler_tick) begin + if(when_UartCtrlRx_l43) begin + bitTimer_tick = 1'b1; + end + end + end + + assign when_UartCtrlRx_l43 = (bitTimer_counter == 3'b000); + assign break_valid = (break_counter == 7'h68); + assign when_UartCtrlRx_l69 = (io_samplingTick && (! break_valid)); + assign io_break = break_valid; + assign io_read_valid = stateMachine_validReg; + assign when_UartCtrlRx_l93 = ((sampler_tick && (! sampler_value)) && (! break_valid)); + assign when_UartCtrlRx_l103 = (sampler_value == 1'b1); + assign when_UartCtrlRx_l111 = (bitCounter_value == io_configFrame_dataLength); + assign when_UartCtrlRx_l113 = (io_configFrame_parity == Axi4PeripheralUartParityType_NONE); + assign when_UartCtrlRx_l125 = (stateMachine_parity == sampler_value); + assign when_UartCtrlRx_l136 = (! sampler_value); + assign when_UartCtrlRx_l139 = (bitCounter_value == _zz_when_UartCtrlRx_l139); + assign io_read_payload = stateMachine_shifter; + always @(posedge clk) begin + if(reset) begin + _zz_io_rts <= 1'b0; + sampler_samples_1 <= 1'b1; + sampler_samples_2 <= 1'b1; + sampler_samples_3 <= 1'b1; + sampler_samples_4 <= 1'b1; + sampler_value <= 1'b1; + sampler_tick <= 1'b0; + break_counter <= 7'h0; + stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; + stateMachine_validReg <= 1'b0; + end else begin + _zz_io_rts <= (! io_read_ready); + if(io_samplingTick) begin + sampler_samples_1 <= sampler_samples_0; + end + if(io_samplingTick) begin + sampler_samples_2 <= sampler_samples_1; + end + if(io_samplingTick) begin + sampler_samples_3 <= sampler_samples_2; + end + if(io_samplingTick) begin + sampler_samples_4 <= sampler_samples_3; + end + sampler_value <= ((((((_zz_sampler_value || _zz_sampler_value_3) || (_zz_sampler_value_4 && sampler_samples_4)) || ((_zz_sampler_value_5 && sampler_samples_2) && sampler_samples_4)) || (((_zz_sampler_value_6 && sampler_samples_0) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_1) && sampler_samples_3) && sampler_samples_4)) || (((1'b1 && sampler_samples_2) && sampler_samples_3) && sampler_samples_4)); + sampler_tick <= io_samplingTick; + if(sampler_value) begin + break_counter <= 7'h0; + end else begin + if(when_UartCtrlRx_l69) begin + break_counter <= (break_counter + 7'h01); + end + end + stateMachine_validReg <= 1'b0; + case(stateMachine_state) + Axi4PeripheralUartCtrlRxState_IDLE : begin + if(when_UartCtrlRx_l93) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_START; + end + end + Axi4PeripheralUartCtrlRxState_START : begin + if(bitTimer_tick) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_DATA; + if(when_UartCtrlRx_l103) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; + end + end + end + Axi4PeripheralUartCtrlRxState_DATA : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l111) begin + if(when_UartCtrlRx_l113) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_STOP; + stateMachine_validReg <= 1'b1; + end else begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_PARITY; + end + end + end + end + Axi4PeripheralUartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l125) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_STOP; + stateMachine_validReg <= 1'b1; + end else begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; + end + end + end + default : begin + if(bitTimer_tick) begin + if(when_UartCtrlRx_l136) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; + end else begin + if(when_UartCtrlRx_l139) begin + stateMachine_state <= Axi4PeripheralUartCtrlRxState_IDLE; + end + end + end + end + endcase + end + end + + always @(posedge clk) begin + if(sampler_tick) begin + bitTimer_counter <= (bitTimer_counter - 3'b001); + end + if(bitTimer_tick) begin + bitCounter_value <= (bitCounter_value + 3'b001); + end + if(bitTimer_tick) begin + stateMachine_parity <= (stateMachine_parity ^ sampler_value); + end + case(stateMachine_state) + Axi4PeripheralUartCtrlRxState_IDLE : begin + if(when_UartCtrlRx_l93) begin + bitTimer_counter <= 3'b010; + end + end + Axi4PeripheralUartCtrlRxState_START : begin + if(bitTimer_tick) begin + bitCounter_value <= 3'b000; + stateMachine_parity <= (io_configFrame_parity == Axi4PeripheralUartParityType_ODD); + end + end + Axi4PeripheralUartCtrlRxState_DATA : begin + if(bitTimer_tick) begin + stateMachine_shifter[bitCounter_value] <= sampler_value; + if(when_UartCtrlRx_l111) begin + bitCounter_value <= 3'b000; + end + end + end + Axi4PeripheralUartCtrlRxState_PARITY : begin + if(bitTimer_tick) begin + bitCounter_value <= 3'b000; + end + end + default : begin + end + endcase + end + + +endmodule + +module Axi4PeripheralUartCtrlTx ( + input wire [2:0] io_configFrame_dataLength, + input wire [0:0] io_configFrame_stop, + input wire [1:0] io_configFrame_parity, + input wire io_samplingTick, + input wire io_write_valid, + output reg io_write_ready, + input wire [7:0] io_write_payload, + input wire io_cts, + output wire io_txd, + input wire io_break, + input wire clk, + input wire reset +); + localparam Axi4PeripheralUartStopType_ONE = 1'd0; + localparam Axi4PeripheralUartStopType_TWO = 1'd1; + localparam Axi4PeripheralUartParityType_NONE = 2'd0; + localparam Axi4PeripheralUartParityType_EVEN = 2'd1; + localparam Axi4PeripheralUartParityType_ODD = 2'd2; + localparam Axi4PeripheralUartCtrlTxState_IDLE = 3'd0; + localparam Axi4PeripheralUartCtrlTxState_START = 3'd1; + localparam Axi4PeripheralUartCtrlTxState_DATA = 3'd2; + localparam Axi4PeripheralUartCtrlTxState_PARITY = 3'd3; + localparam Axi4PeripheralUartCtrlTxState_STOP = 3'd4; + + wire [2:0] _zz_clockDivider_counter_valueNext; + wire [0:0] _zz_clockDivider_counter_valueNext_1; + wire [2:0] _zz_when_UartCtrlTx_l93; + wire [0:0] _zz_when_UartCtrlTx_l93_1; + reg clockDivider_counter_willIncrement; + wire clockDivider_counter_willClear; + reg [2:0] clockDivider_counter_valueNext; + reg [2:0] clockDivider_counter_value; + wire clockDivider_counter_willOverflowIfInc; + wire clockDivider_counter_willOverflow; + reg [2:0] tickCounter_value; + reg [2:0] stateMachine_state; + reg stateMachine_parity; + reg stateMachine_txd; + wire when_UartCtrlTx_l58; + wire when_UartCtrlTx_l73; + wire when_UartCtrlTx_l76; + wire when_UartCtrlTx_l93; + wire [2:0] _zz_stateMachine_state; + reg _zz_io_txd; + `ifndef SYNTHESIS + reg [23:0] io_configFrame_stop_string; + reg [31:0] io_configFrame_parity_string; + reg [47:0] stateMachine_state_string; + reg [47:0] _zz_stateMachine_state_string; + `endif + + + assign _zz_clockDivider_counter_valueNext_1 = clockDivider_counter_willIncrement; + assign _zz_clockDivider_counter_valueNext = {2'd0, _zz_clockDivider_counter_valueNext_1}; + assign _zz_when_UartCtrlTx_l93_1 = ((io_configFrame_stop == Axi4PeripheralUartStopType_ONE) ? 1'b0 : 1'b1); + assign _zz_when_UartCtrlTx_l93 = {2'd0, _zz_when_UartCtrlTx_l93_1}; + `ifndef SYNTHESIS + always @(*) begin + case(io_configFrame_stop) + Axi4PeripheralUartStopType_ONE : io_configFrame_stop_string = "ONE"; + Axi4PeripheralUartStopType_TWO : io_configFrame_stop_string = "TWO"; + default : io_configFrame_stop_string = "???"; + endcase + end + always @(*) begin + case(io_configFrame_parity) + Axi4PeripheralUartParityType_NONE : io_configFrame_parity_string = "NONE"; + Axi4PeripheralUartParityType_EVEN : io_configFrame_parity_string = "EVEN"; + Axi4PeripheralUartParityType_ODD : io_configFrame_parity_string = "ODD "; + default : io_configFrame_parity_string = "????"; + endcase + end + always @(*) begin + case(stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : stateMachine_state_string = "IDLE "; + Axi4PeripheralUartCtrlTxState_START : stateMachine_state_string = "START "; + Axi4PeripheralUartCtrlTxState_DATA : stateMachine_state_string = "DATA "; + Axi4PeripheralUartCtrlTxState_PARITY : stateMachine_state_string = "PARITY"; + Axi4PeripheralUartCtrlTxState_STOP : stateMachine_state_string = "STOP "; + default : stateMachine_state_string = "??????"; + endcase + end + always @(*) begin + case(_zz_stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : _zz_stateMachine_state_string = "IDLE "; + Axi4PeripheralUartCtrlTxState_START : _zz_stateMachine_state_string = "START "; + Axi4PeripheralUartCtrlTxState_DATA : _zz_stateMachine_state_string = "DATA "; + Axi4PeripheralUartCtrlTxState_PARITY : _zz_stateMachine_state_string = "PARITY"; + Axi4PeripheralUartCtrlTxState_STOP : _zz_stateMachine_state_string = "STOP "; + default : _zz_stateMachine_state_string = "??????"; + endcase + end + `endif + + always @(*) begin + clockDivider_counter_willIncrement = 1'b0; + if(io_samplingTick) begin + clockDivider_counter_willIncrement = 1'b1; + end + end + + assign clockDivider_counter_willClear = 1'b0; + assign clockDivider_counter_willOverflowIfInc = (clockDivider_counter_value == 3'b111); + assign clockDivider_counter_willOverflow = (clockDivider_counter_willOverflowIfInc && clockDivider_counter_willIncrement); + always @(*) begin + clockDivider_counter_valueNext = (clockDivider_counter_value + _zz_clockDivider_counter_valueNext); + if(clockDivider_counter_willClear) begin + clockDivider_counter_valueNext = 3'b000; + end + end + + always @(*) begin + stateMachine_txd = 1'b1; + case(stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : begin + end + Axi4PeripheralUartCtrlTxState_START : begin + stateMachine_txd = 1'b0; + end + Axi4PeripheralUartCtrlTxState_DATA : begin + stateMachine_txd = io_write_payload[tickCounter_value]; + end + Axi4PeripheralUartCtrlTxState_PARITY : begin + stateMachine_txd = stateMachine_parity; + end + default : begin + end + endcase + end + + always @(*) begin + io_write_ready = io_break; + case(stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : begin + end + Axi4PeripheralUartCtrlTxState_START : begin + end + Axi4PeripheralUartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + io_write_ready = 1'b1; + end + end + end + Axi4PeripheralUartCtrlTxState_PARITY : begin + end + default : begin + end + endcase + end + + assign when_UartCtrlTx_l58 = ((io_write_valid && (! io_cts)) && clockDivider_counter_willOverflow); + assign when_UartCtrlTx_l73 = (tickCounter_value == io_configFrame_dataLength); + assign when_UartCtrlTx_l76 = (io_configFrame_parity == Axi4PeripheralUartParityType_NONE); + assign when_UartCtrlTx_l93 = (tickCounter_value == _zz_when_UartCtrlTx_l93); + assign _zz_stateMachine_state = (io_write_valid ? Axi4PeripheralUartCtrlTxState_START : Axi4PeripheralUartCtrlTxState_IDLE); + assign io_txd = _zz_io_txd; + always @(posedge clk) begin + if(reset) begin + clockDivider_counter_value <= 3'b000; + stateMachine_state <= Axi4PeripheralUartCtrlTxState_IDLE; + _zz_io_txd <= 1'b1; + end else begin + clockDivider_counter_value <= clockDivider_counter_valueNext; + case(stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : begin + if(when_UartCtrlTx_l58) begin + stateMachine_state <= Axi4PeripheralUartCtrlTxState_START; + end + end + Axi4PeripheralUartCtrlTxState_START : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_state <= Axi4PeripheralUartCtrlTxState_DATA; + end + end + Axi4PeripheralUartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + if(when_UartCtrlTx_l76) begin + stateMachine_state <= Axi4PeripheralUartCtrlTxState_STOP; + end else begin + stateMachine_state <= Axi4PeripheralUartCtrlTxState_PARITY; + end + end + end + end + Axi4PeripheralUartCtrlTxState_PARITY : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_state <= Axi4PeripheralUartCtrlTxState_STOP; + end + end + default : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l93) begin + stateMachine_state <= _zz_stateMachine_state; + end + end + end + endcase + _zz_io_txd <= (stateMachine_txd && (! io_break)); + end + end + + always @(posedge clk) begin + if(clockDivider_counter_willOverflow) begin + tickCounter_value <= (tickCounter_value + 3'b001); + end + if(clockDivider_counter_willOverflow) begin + stateMachine_parity <= (stateMachine_parity ^ stateMachine_txd); + end + case(stateMachine_state) + Axi4PeripheralUartCtrlTxState_IDLE : begin + end + Axi4PeripheralUartCtrlTxState_START : begin + if(clockDivider_counter_willOverflow) begin + stateMachine_parity <= (io_configFrame_parity == Axi4PeripheralUartParityType_ODD); + tickCounter_value <= 3'b000; + end + end + Axi4PeripheralUartCtrlTxState_DATA : begin + if(clockDivider_counter_willOverflow) begin + if(when_UartCtrlTx_l73) begin + tickCounter_value <= 3'b000; + end + end + end + Axi4PeripheralUartCtrlTxState_PARITY : begin + if(clockDivider_counter_willOverflow) begin + tickCounter_value <= 3'b000; + end + end + default : begin + end + endcase + end + + +endmodule + +module Axi4PeripheralBufferCC ( + input wire io_dataIn, + output wire io_dataOut, + input wire clk, + input wire reset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge clk) begin + if(reset) begin + buffers_0 <= 1'b0; + buffers_1 <= 1'b0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule diff --git a/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/source/peri_config b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/source/peri_config new file mode 100644 index 0000000..571f0ba --- /dev/null +++ b/Ti375C529_devkit/ip/EfxSapphireHpSoc_slb/source/peri_config @@ -0,0 +1,8 @@ +--apbSlave name=io_apbSlave_0,address=0x100000,size=65536 +--uart name=system_uart_0_io,address=0x10000,interruptId=0 +--peripheralFrequency 200000000 +--PeripheralClock true +--i2c name=system_i2c_0_io,address=0x20000,interruptId=6 +--watchdog name=system_watchdog,address=0x50000,interruptId=13,prescalerWidth=24,counters=2,countersWidth=16 +--spi name=system_spi_0_io,address=0x30000,interruptId=3,width=8,ssCount=4 +--gpio name=system_gpio_0_io,address=0x40000,width=4,interrupts="0->9;1->10" diff --git a/Ti375C529_devkit/ip/gAXIM_2to1_switch/axi_interconnect.vh b/Ti375C529_devkit/ip/gAXIM_2to1_switch/axi_interconnect.vh new file mode 100644 index 0000000..cf9993c --- /dev/null +++ b/Ti375C529_devkit/ip/gAXIM_2to1_switch/axi_interconnect.vh @@ -0,0 +1,2 @@ +localparam M_BASE_ADDR = {32'h41000000,32'h40000000,32'h30000000,32'h20000000,32'h11100000,32'h11000000,32'h10000000,32'h0}; +localparam M_ADDR_WIDTH = {32'd20,32'd24,32'd28,32'd28,32'd20,32'd12,32'd24,32'd32}; \ No newline at end of file diff --git a/Ti375C529_devkit/ip/gAXIM_2to1_switch/gAXIM_2to1_switch.v b/Ti375C529_devkit/ip/gAXIM_2to1_switch/gAXIM_2to1_switch.v new file mode 100644 index 0000000..35c79f3 --- /dev/null +++ b/Ti375C529_devkit/ip/gAXIM_2to1_switch/gAXIM_2to1_switch.v @@ -0,0 +1,1361 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2026.1.132 +// IP Version: 5.6 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2026 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _ec96b3fb89244203bb74a6d5d477a76b +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module gAXIM_2to1_switch +( + input rst_n, + input clk, + input [1:0] s_axi_awvalid, + input [63:0] s_axi_awaddr, + input [3:0] s_axi_awlock, + output [1:0] s_axi_awready, + input [1:0] s_axi_arvalid, + input [63:0] s_axi_araddr, + input [3:0] s_axi_arlock, + output [1:0] s_axi_arready, + input [1:0] s_axi_wvalid, + input [1:0] s_axi_wlast, + input [15:0] s_axi_wid, + input [1:0] s_axi_bready, + output [3:0] s_axi_bresp, + input [1:0] s_axi_rready, + output [15:0] s_axi_bid, + output [15:0] s_axi_rid, + input [255:0] s_axi_wdata, + output [255:0] s_axi_rdata, + output [3:0] s_axi_rresp, + output [1:0] s_axi_bvalid, + output [1:0] s_axi_rvalid, + output [1:0] s_axi_rlast, + input [31:0] s_axi_wstrb, + output [0:0] m_axi_awvalid, + output [31:0] m_axi_awaddr, + output [1:0] m_axi_awlock, + input [0:0] m_axi_awready, + output [0:0] m_axi_arvalid, + output [31:0] m_axi_araddr, + output [1:0] m_axi_arlock, + input [0:0] m_axi_arready, + output [0:0] m_axi_wvalid, + output [0:0] m_axi_wlast, + output [0:0] m_axi_bready, + input [1:0] m_axi_bresp, + output [0:0] m_axi_rready, + input [7:0] m_axi_bid, + input [7:0] m_axi_rid, + output [127:0] m_axi_wdata, + input [127:0] m_axi_rdata, + input [1:0] m_axi_rresp, + input [0:0] m_axi_bvalid, + input [0:0] m_axi_rvalid, + input [0:0] m_axi_rlast, + output [15:0] m_axi_wstrb, + input [0:0] m_axi_wready, + output [1:0] s_axi_wready, + input [5:0] s_axi_awprot, + input [7:0] s_axi_awcache, + input [7:0] s_axi_awqos, + input [5:0] s_axi_awuser, + input [7:0] s_axi_arqos, + input [7:0] s_axi_arcache, + output [2:0] m_axi_awprot, + input [15:0] s_axi_arid, + input [5:0] s_axi_arsize, + input [15:0] s_axi_arlen, + input [3:0] s_axi_arburst, + input [5:0] s_axi_arprot, + input [15:0] s_axi_awid, + input [3:0] s_axi_awburst, + input [15:0] s_axi_awlen, + input [5:0] s_axi_awsize, + output [7:0] m_axi_awid, + output [1:0] m_axi_awburst, + output [7:0] m_axi_awlen, + output [2:0] m_axi_awsize, + output [3:0] m_axi_awcache, + output [3:0] m_axi_awqos, + output [2:0] m_axi_awuser, + output [2:0] m_axi_arprot, + output [1:0] m_axi_arburst, + output [7:0] m_axi_arlen, + output [2:0] m_axi_arsize, + output [3:0] m_axi_arcache, + output [3:0] m_axi_arqos, + output [2:0] m_axi_aruser, + output [3:0] m_axi_awregion, + output [3:0] m_axi_arregion, + output [7:0] m_axi_arid, + output [2:0] m_axi_wuser, + input [2:0] m_axi_ruser, + input [2:0] m_axi_buser, + input [5:0] s_axi_aruser, + input [5:0] s_axi_wuser, + output [5:0] s_axi_buser, + output [5:0] s_axi_ruser +); +`IP_MODULE_NAME(efx_axi_interconnect) +#( + .ARB_MODE ("ROUND_ROBIN_1"), + .S_PORTS (2), + .DATA_WIDTH (128), + .ADDR_WIDTH (32), + .M_PORTS (1), + .ID_WIDTH (8), + .USER_WIDTH (3), + .PROTOCOL ("AXI4") +) +u_efx_axi_interconnect +( + .rst_n ( rst_n ), + .clk ( clk ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awlock ( s_axi_awlock ), + .s_axi_awready ( s_axi_awready ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arlock ( s_axi_arlock ), + .s_axi_arready ( s_axi_arready ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_wlast ( s_axi_wlast ), + .s_axi_wid ( s_axi_wid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_rready ( s_axi_rready ), + .s_axi_bid ( s_axi_bid ), + .s_axi_rid ( s_axi_rid ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rlast ( s_axi_rlast ), + .s_axi_wstrb ( s_axi_wstrb ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awready ( m_axi_awready ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arready ( m_axi_arready ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_bready ( m_axi_bready ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_rready ( m_axi_rready ), + .m_axi_bid ( m_axi_bid ), + .m_axi_rid ( m_axi_rid ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_rdata ( m_axi_rdata ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_wready ( m_axi_wready ), + .s_axi_wready ( s_axi_wready ), + .s_axi_awprot ( s_axi_awprot ), + .s_axi_awcache ( s_axi_awcache ), + .s_axi_awqos ( s_axi_awqos ), + .s_axi_awuser ( s_axi_awuser ), + .s_axi_arqos ( s_axi_arqos ), + .s_axi_arcache ( s_axi_arcache ), + .m_axi_awprot ( m_axi_awprot ), + .s_axi_arid ( s_axi_arid ), + .s_axi_arsize ( s_axi_arsize ), + .s_axi_arlen ( s_axi_arlen ), + .s_axi_arburst ( s_axi_arburst ), + .s_axi_arprot ( s_axi_arprot ), + .s_axi_awid ( s_axi_awid ), + .s_axi_awburst ( s_axi_awburst ), + .s_axi_awlen ( s_axi_awlen ), + .s_axi_awsize ( s_axi_awsize ), + .m_axi_awid ( m_axi_awid ), + .m_axi_awburst ( m_axi_awburst ), + .m_axi_awlen ( m_axi_awlen ), + .m_axi_awsize ( m_axi_awsize ), + .m_axi_awcache ( m_axi_awcache ), + .m_axi_awqos ( m_axi_awqos ), + .m_axi_awuser ( m_axi_awuser ), + .m_axi_arprot ( m_axi_arprot ), + .m_axi_arburst ( m_axi_arburst ), + .m_axi_arlen ( m_axi_arlen ), + .m_axi_arsize ( m_axi_arsize ), + .m_axi_arcache ( m_axi_arcache ), + .m_axi_arqos ( m_axi_arqos ), + .m_axi_aruser ( m_axi_aruser ), + .m_axi_awregion ( m_axi_awregion ), + .m_axi_arregion ( m_axi_arregion ), + .m_axi_arid ( m_axi_arid ), + .m_axi_wuser ( m_axi_wuser ), + .m_axi_ruser ( m_axi_ruser ), + .m_axi_buser ( m_axi_buser ), + .s_axi_aruser ( s_axi_aruser ), + .s_axi_wuser ( s_axi_wuser ), + .s_axi_buser ( s_axi_buser ), + .s_axi_ruser ( s_axi_ruser ) +); +endmodule + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +BSiclTfEX07oDTPwvSfmqSh37gsGawnAkFDdQtfz2b2aPAbkkOIevgA5jmAEpk8Z +jmjFoTAnEUNBHxHADHQl29GtYYLQLcTt1dvsb1L8xXXbyd41mZnW9qxR1yEXo2Km +PmHE4/laDDFnEAn08I7oinDvTWN/plGfuIWWaEXC4z7ls9W1O5jNY2gj1ZC0oyT4 +iwzQ3cMmgvMMfqkgA6T8wMNFL1jvPdUxnuGh8qa0Q5zso+v2lpzszj4ytZLI8JZz +ZeX/ipjz/4hUHkihXJPjFD+MetXdYJTpzRO3ZbxTOlyD1Ln8yDvo0qNPrgbzN9qq +YropxHtLb22q5bZxY+vKMw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 9552 ) +`pragma protect data_block ++Vo70GbdNusghssxCh548dyMR2SkpjbMNAhuQNohK03MZPtslM2VcFXDSMs/E4I3 +A0tJBsXs6xJPmnI2dRa4m1jbkpAyspc0YB55NAgJLYdmR9j6FyHXqlpTZEcftxHN +U0jtFOoa18GEMGSCMB1hS59vfrr8WKoVGK2KMx8ZvAuWlQ0YHQjLkE8WQjVMM55l +aP/cENky21pfv/q9aoe1Ku3NLdbDqb8Mf/xcXYVJFJaMRBTujuRBZkvEBDhdz78t +J6irEqM5Esiu61ol7FyudRxQ9CyuB9hXVb40puIOcvjK6w4R5IFdJtzamLms4rEo +ttyRNF4nJVzvrjJErNRuCjJeWgYZGt7SXTDXpHvc/U8J03YrUq//wH9tuvfylFAb +bEasWeYHPxRKeJhZAyvxrsqltj0kDrJuaq1crK/jBem8w2mtGvkYNWTSw/Atty// +XOvqYjH8Lv1IBse+lGx5BUvPW2v9Mklu7s94aket2iIVqh6nVqt3dDC8ttJAA86u +o/wzbF0knyVABaBp8P1cYpjr346wDkAcB6FA1zTweqEsJbzezxvHQWZUuJvtpzrD +6WJJnp5e/9Ky/QdN7rMxioe+hn9rlAjyVazKEtypSZME9YaCXF5xv6Nm68s75QzP +WDEXiCA/MHoKMwovdWzYV8TnQmf1xnU/3KlKAEr3rnLvI5rIf5Sq1RHANvD2rQIw +huUjwsyE+Cy8BrBit89Y5eDgmlc/rlMgWwIfeJKwaHsg4kuDPFUbLV8GBgtD5+L8 +VqiVrOqvPX58wuiR6KJzyUPxXFMd7sxzpjrbe+qIIFvooqMqUeIhZFMzDT477uBF +nOWbpGGLV/uZTq0/nYl5raL9cu7/H5s0K1L0fFJPEkgTRN0sfTeWss5bjNjge0oy +mXpp2W5BhRDGPYszKDzFMl3dWwIKeDyolnsLhp1I80hDszRgEbdTO8qxoyDHRE/8 +7L7Wzj8cBZaQuyJTOdewJEjEOWESJx28Wr+24AqhjMPzM3Oy6QSfC0s0dGX+uLIN +DlepkOWfa1bGnK7EKh+QMw2Y+Hnxwdije+wgquoUNtLjCNB6rPh1qzJSccc7aHh/ +U1bAswc4wnpHqwqKP8bwg8A8C1xW5UW7/D/72SaGhNnfGOQ3BT9d5JFOdo08Rkrn +94ui9eHQlp1Pkpez3kz9Ow4KgTKz9qKk5KE2veb5Yf/jipoT1OXlHbPxelULfn8p +0+XRV85tGcJC0bdjGMMEJA2IXeOAZve0NgBojKtvDOD1jJCLekrfE+40nJvT7GdX ++0rpWydBkbVbKGiRgRUmoDJ9fPvYjrgXPfNZkzj2OuDy5UCeeVUnpKa9eYiCq698 +W1LH4LYjXXtjfzrRPMG6XW+sYkkLami4Ddmchxkkrtmom5f0aV1lzOow9hJVMuQT +ReMoUz6UamLLCoVItZghjS277HIPlv24hwR2WgaS8I4lXvWrUctSIkCPoWudlTE3 +WAy8RJrFGrov4uqTOe+uQISgnW6nxAXZ4wbsGZyJSPaHbFPFpN1ica6KQHRSCMdH +MOjwmMpHtaQ6hfsxP/rL4LiLP5TX9hzvEY++Sfy3TnkxpkBb8JDoIQkg419g1G0g +loYxnF79qgRIRiPYVyCg94Fvjb39r6GBy5sjPAUBnpFQnCUZfEtvEXPn2ff83wJ+ +KFAK5jPLXKq5TR4UxCWES/9MjrzpXX9Q5ZW3afh5gLY/i7Eld2aFuoJ7Yw0Wg0/P +0t+89+widhpOU+Vtj0VhZPPEHGAM7pIAI8BEAIyy+t01V3ELjbGQwLB4FmHh1K6h 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+mD470LuP9+f5Ud307Xx4F6AM71/FGZrha/rJxjluETxdHCy5bAx/oXWQo31VURq7 +3q6UCh0ymGPD837xKYyUYceQRZff4/xlTF/OEQdZPNtbBVE8IsHMp2mfFfSDxq+C +axB5ar3/7/HrmzJElpSIOoSceJQXYo0L9scIrPSF8jNRRB2TxDReT/yjiQsCkww1 +fGF62e7DC0HnyHPBQrRlj9JQC34pW2K2ZTTgQYZhrhwQwTzaoIHBb45KPMMUuBHp +v82gEe/pW9K++sUDQK/W7wgO1NeiS5NHJmtaqv/uH5AOxE1XMLrXPsYiw7p2QJOq +1bmbF7c4TMfs9iT1KNHz2p1mqo4wOo0tHgDdPmL8PXLMm7POrz0rKoBS6lDTid35 +`pragma protect end_protected + +//pragma protect end + + +module `IP_MODULE_NAME(efx_axi_interconnect) #( + parameter PROTOCOL = "AXI4", + parameter ARB_MODE = "PRIORITY", + parameter S_PORTS = 1, + parameter M_PORTS = 8, + parameter ID_WIDTH = 8, + parameter DATA_WIDTH = 32, + parameter USER_WIDTH = 3, + parameter ADDR_WIDTH = 32, + parameter M_REGIONS = 1, + parameter M_CONNECT_READ = {M_PORTS{{S_PORTS{1'b1}}}}, + parameter M_CONNECT_WRITE = {M_PORTS{{S_PORTS{1'b1}}}}, + parameter STRB_WIDTH = DATA_WIDTH/8 +) ( + input wire clk, + input wire rst_n, + input wire [S_PORTS-1:0] s_axi_awvalid, + input wire [S_PORTS*ADDR_WIDTH-1:0] s_axi_awaddr, + input wire [S_PORTS*3-1:0] s_axi_awprot, + input wire [S_PORTS*ID_WIDTH-1:0] s_axi_awid, + input wire [S_PORTS*2-1:0] s_axi_awburst, + input wire [S_PORTS*8-1:0] s_axi_awlen, + input wire [S_PORTS*3-1:0] s_axi_awsize, + input wire [S_PORTS*4-1:0] s_axi_awcache, + input wire [S_PORTS*4-1:0] s_axi_awqos, + input wire [S_PORTS*USER_WIDTH-1:0] s_axi_awuser, + input wire [S_PORTS*2-1:0] s_axi_awlock, + output reg [S_PORTS-1:0] s_axi_awready, + input wire [S_PORTS-1:0] s_axi_wvalid, + input wire [S_PORTS*DATA_WIDTH-1:0] s_axi_wdata, + input wire [S_PORTS*STRB_WIDTH-1:0] s_axi_wstrb, + input wire [S_PORTS-1:0] s_axi_wlast, + input wire [S_PORTS*USER_WIDTH-1:0] s_axi_wuser, + input wire [S_PORTS*ID_WIDTH-1:0] s_axi_wid, + output wire [S_PORTS-1:0] s_axi_wready, + input wire [S_PORTS-1:0] s_axi_bready, + output wire [S_PORTS*2-1:0] s_axi_bresp, + output reg [S_PORTS-1:0] s_axi_bvalid, + output wire [S_PORTS*ID_WIDTH-1:0] s_axi_bid, + output wire [S_PORTS*USER_WIDTH-1:0] s_axi_buser, + input wire [S_PORTS-1:0] s_axi_arvalid, + input wire [S_PORTS*ADDR_WIDTH-1:0] s_axi_araddr, + input wire [S_PORTS*3-1:0] s_axi_arprot, + input wire [S_PORTS*ID_WIDTH-1:0] s_axi_arid, + input wire [S_PORTS*2-1:0] s_axi_arburst, + input wire [S_PORTS*8-1:0] s_axi_arlen, + input wire [S_PORTS*3-1:0] s_axi_arsize, + input wire [S_PORTS*4-1:0] s_axi_arcache, + input wire [S_PORTS*4-1:0] s_axi_arqos, + input wire [S_PORTS*USER_WIDTH-1:0] s_axi_aruser, + input wire [S_PORTS*2-1:0] s_axi_arlock, + output reg [S_PORTS-1:0] s_axi_arready, + input wire [S_PORTS-1:0] s_axi_rready, + output wire [S_PORTS*ID_WIDTH-1:0] s_axi_rid, + output wire [S_PORTS*DATA_WIDTH-1:0] s_axi_rdata, + output wire [S_PORTS*2-1:0] s_axi_rresp, + output wire [S_PORTS-1:0] s_axi_rvalid, + output wire [S_PORTS-1:0] s_axi_rlast, + output wire [S_PORTS*USER_WIDTH-1:0] s_axi_ruser, + output reg [M_PORTS-1:0] m_axi_awvalid, + output wire [M_PORTS*ID_WIDTH-1:0] m_axi_awid, + output wire [M_PORTS*2-1:0] m_axi_awburst, + output wire [M_PORTS*8-1:0] m_axi_awlen, + output wire [M_PORTS*3-1:0] m_axi_awsize, + output wire [M_PORTS*4-1:0] m_axi_awcache, + output wire [M_PORTS*4-1:0] m_axi_awqos, + output wire [M_PORTS*4-1:0] m_axi_awregion, + output wire [M_PORTS*USER_WIDTH-1:0] m_axi_awuser, + output wire [M_PORTS*ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [M_PORTS*3-1:0] m_axi_awprot, + output wire [M_PORTS*2-1:0] m_axi_awlock, + input wire [M_PORTS-1:0] m_axi_awready, + output wire [M_PORTS*DATA_WIDTH-1:0] m_axi_wdata, + output wire [M_PORTS*STRB_WIDTH-1:0] m_axi_wstrb, + output wire [M_PORTS-1:0] m_axi_wvalid, + output wire [M_PORTS-1:0] m_axi_wlast, + output wire [M_PORTS*USER_WIDTH-1:0] m_axi_wuser, + output wire [M_PORTS*ID_WIDTH-1:0] m_axi_wid, + input wire [M_PORTS-1:0] m_axi_wready, + input wire [M_PORTS*2-1:0] m_axi_bresp, + input wire [M_PORTS-1:0] m_axi_bvalid, + input wire [M_PORTS*ID_WIDTH-1:0] m_axi_bid, + input wire [M_PORTS*USER_WIDTH-1:0] m_axi_buser, + output reg [M_PORTS-1:0] m_axi_bready, + output reg [M_PORTS-1:0] m_axi_arvalid, + output wire [M_PORTS*ID_WIDTH-1:0] m_axi_arid, + output wire [M_PORTS*2-1:0] m_axi_arburst, + output wire [M_PORTS*8-1:0] m_axi_arlen, + output wire [M_PORTS*3-1:0] m_axi_arsize, + output wire [M_PORTS*4-1:0] m_axi_arcache, + output wire [M_PORTS*4-1:0] m_axi_arqos, + output wire [M_PORTS*4-1:0] m_axi_arregion, + output wire [M_PORTS*USER_WIDTH-1:0] m_axi_aruser, + output wire [M_PORTS*ADDR_WIDTH-1:0] m_axi_araddr, + output wire [M_PORTS*3-1:0] m_axi_arprot, + output wire [M_PORTS*2-1:0] m_axi_arlock, + input wire [M_PORTS-1:0] m_axi_arready, + input wire [M_PORTS*ID_WIDTH-1:0] m_axi_rid, + input wire [M_PORTS*DATA_WIDTH-1:0] m_axi_rdata, + input wire [M_PORTS*2-1:0] m_axi_rresp, + input wire [M_PORTS-1:0] m_axi_rvalid, + input wire [M_PORTS-1:0] m_axi_rlast, + input wire [M_PORTS*USER_WIDTH-1:0] m_axi_ruser, + output wire [M_PORTS-1:0] m_axi_rready +); +`include "axi_interconnect.vh" +parameter S_PORTS_WIDTH = clog2(S_PORTS); +parameter M_PORTS_WIDTH = clog2(M_PORTS); +parameter M_BASE_ADDR_INT = M_BASE_ADDR ? M_BASE_ADDR : calcBaseAddrs(0); +parameter IDLE = 0, + PORT_GRANT = 1, + ADDR_DECODE = 2, + WR_FORWARD = 3, + WR_RESPONSE = 4, + RD_REQUEST = 5, + RD_RETURN = 6, + DRP_REQUEST = 7, + DRP_WAIT = 8, + END_WAIT = 9; +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +h798DEoPCCw6eC93sfxnz8ZJ5DmYibE3rGjjhE+YK5a3RIfjyfpuQmm+Qi6hiWsS +h21ZC3p98i4VCoRgq9ttjdMjEUVk6R1INC59AvJ35jeq6cjGdiMiIPwnlnHEAIqa +kQUAn5DZG6XDT0Q74iMGbdiR7Uqpt242DlxQT/RPahxewbF7bTMwF22aKiwUymVQ +WL77YlV9D3RHdY6gVwH+r4vNibfPRFoNglrFWdWkXgAM3QCILfTmCmNOrDP+tU67 +Sp1AnVUQDUfoMreLqPv9PxJK3wnCugVdw08bgxzbxycLpfzcQbzXtVTNLzpE9m/C +m4DQ47zqQmz4Zj4f/JVRfg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 25024 ) +`pragma protect data_block +YwM6jjCriz1M+FDJXSN2LeXck/ZAaH8JuIXMxJq2uSTQniMJPx1HUHKK0h6e+ADy +nOpy4Npr3RCHDdf751Af8iOf0C8dZcMs3a1GYK43f9lfLJ4Am1BOEiaKGIMLoNoP +3/ezGIbxr0ugu0861FRZvKAC9ByuIi2/kp4W3oQ7m7vZVqigNx/Z+Lw30JD+Tdof +nd9fbmhRCCJW3RaeEuI7sGkqxIGkRp9Ypju2a3+UmaW00MJNt8bCRmHGNKebapN2 +4iVEq1eRDz+FLHYVirgJupc+ujLQGmDcYUtfEv75/zbfhbnSF2Tzy4KWhMa/eqDt +JdYj2al2m3yH2PEUGOEg/lmK4ufxcT7uAskU+0OCNTLvSk3xxzqGDoUTwqKX5Ln0 +JIDW8HetHVJZFTLmXuKbPHS6O+HyLuJ7Zxymn+Fjne6idZqUL/nzh8AJkD5MeD46 +devUK2qciMx2VyWCOynEzLIDQuLhf4HjJnSRV9ZjArs+ihs/aN5AaI98MfMmwjWS +KFKPxBp0tjRn2JUO0XR81ueXaQ9p/dLA1gbRJm7u3ADC4VBKoZXEWjeKWQe3/n1Q +mbN+x2KwcKG8XtTQY0BO2biWZo3QqJH1PH6ghVrcaM0KAEj3eBYyVZNVRgEB9Zrw +RRFhPPGhGTYcaC0TDtPS2EToJT5P23Ql13VFSHg3/OojCJpJcY0k1dryK52hqUyY +DiWhs5ZXPNHotTcdv5rTTZ/yPkW4CMHMJsuqWMpMzkQfRWTLiLfPZCs059UxzGNu +ZxxVrqi2QvhQEvWGbqnY4nFNZv20Zg/gjBNxOZGImfOZ0Y9dhYEcbRA76Ygnpw5G +vGVtZG8zdpoUvm5EKdyPpCtMRRphbRSJOtfS4HuKv/+VOGCmZaOiM6orgILxnDj4 +cJZcAvsaKNPUkQBZl1SdTWoZQ/ju+qYxeH5r6aZLkNlAg8wxRWRLF60dr2HZjer8 +evhWNI1sXa3DYfXmrbwUlrRlNScBbch6nExhqbPvdWtVWN8FLcA2450xz3EqLC0v +feI7zE+5RTFKHrFinkDsvLSssGe1F2TqSwgHq8wjB3wBMKoGATMrdcoUI2WYRzps +sP8fhHOW81v0p8J6cL8JSFTmnDD1QjgxYc0UHXrK5RNr2TSldF9Ou5BBhkAPViVR +FIKcFlaVe+RGEazKhck1nsf1xUSGwWx23yq4cIsyQCPXWKRDTKXWeM8FkbOfsB4h +jOLT4/44scAugcFmRTk0QLiz01X/qCE92lXw1/DWYkPkpJjEtgNyZ5sRAiPCoGx5 +pjLXzx8g4oS8KrEfdGhIfSMf/ac/7nnoML7Lw4+QkXMvIwOHLreX7f2b6xoi6H6p ++t5vR0AOmFGBcGCE3exjIyI46ho1XyuDGrY+67zNn1N9b1Ub6o/nuaUwVLWk1eHm +f0M2FtnsAKYziyMLe1virFt1be8XoHB+ZhDjV03xpiT41vjH/O+V83gcInEzBy2W +QyCLM+ma98sPP7eg1+vROdya3CBGdPYImWLsfomVwFR5DUkqPBV/Yvxtux7DejoT +41Z1oqJ+rHnSnzlQ0XxPrcfPu4tfNYWle9kqizkAVtjZSa3uG1S8mSnhcizugnge +MgqTyqZyJP6rQjbTxAOQV8iOpQ7KkHcFDdsN6CNIt3qOAPaWUIruqhvdNTdr+MgM +ttM3ciN7ddW4EFINq4hVaZiwOPsUyx7kFABzxWCy/lm9iu97+ujhpDbdgDgl3N6G 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+Yg3bb+MZBoJSx1bubJg+o5E3BkL40S/fAkj6c2uWPgCdl3r5BRCx1ucpBt0L7X2D +/l6T3GJAxPypfc4TzBOOQqOCDujGOV5ODMj1vMgngzz7owxpOiGCTjiHCvy49kqE +IqgNCgdBxm6ouv9UyqJKrMQrLiyUG1ZZknZxjWnvv9ISJ4AjuhkypSbY3v+ngPOK +hwivM16i4BPI2dfzEb0PIb7g2Y9jcOzteqjm5n3oypdyR+zpDT+hvqA3BPi25W0B +JPYxtbm4M1TPfEmgrkNbchX/D0U91Stwyv+qf4JqYYdaQXNdd449kc+NEnwTYsrq +imyaZXGkE+l6ED8peKJutbb1ccZHoZh+/itLOVb5jLrfCXLeDI2LUxittjCamfW5 +lt+O642jvKoWfacQoGHaq/AIPlwNqftmR49MtYZZMsDzfB+T4+2WoI60nL+OmMcu +GL3mI8jrE/W3gbgmLujiGP/0Ma1zJd1rqZufxTlCa61cMnpkieSrmehFshtQ2ONG +nsHziIMfVHv/ubGOxOvWWA6ESxhyq4Bb7YE6fnyfk4YwwpVD/QDv/+P9eOklQa1I +cQRQmNo/vwzwS1nfA0mc3wtdW3m0qIjV/PaogQuODlY1TLbydqB4H+lhbwXvhHZ5 +60YjPDLerHojlSKgOWBz35r7fbZqJOCKnTC6LE/2BzjB7GewxnTJsjWRJmkLaHmF +i6BmBm4m78KsKEJZgToH/UJ++X5fhUQ+SG+hz+h0i7xxyC/cnU/PigQ3vZ/SUkN6 +7zg/hdWRcuGmho0aVNUfw1w5Wdd1RwXdUYbYfG8RWeYIqQ6OWqhjLOK/B+Yy3r/n +JNwvRqtuUZFoPNH2FzMv2pdxZm5CvcOuJOMBcvVpgxktn57SwIk367E1srFwQw/j +VhTvV5MqNhAZpXfPbkZ0rQ== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +RwZLaWoAKLBm11tcUo3zg7WK2hPcNJvetUS0HcngH1N+uqVkxItkonJwS2nHozet +PZ4e0pcL7oMHU+YSSKFGF0HZtDLJ6ggz9Tjk65W4OruIfJxIuyYdw9nbusKhaJTz +khXz5VPO6s2gfnVif+az5zjoe7kudgxlxU7jmvaX9sbur5cFMS2KnJogDMLJcl1s +ZlLL+9F5h5+8PKCF6eoiFm6TtkD7MrBiDjMDu9eLqZ5t8VgWYRMKduwEQ9J2M3t/ +JcbjL7GG+1h3LkL6WEKxF8zVIpKiu3k7UC98wKI8mhEpZ8bChW07nVCr4PHLn2IX +BU9Qy5kOLqe8sKbl6LYs7g== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1312 ) +`pragma protect data_block +p0bIW99zYvQA4u0XRWnQ90s6MugNpXe6l31pFNyBhuxQU67mS/BBRtYtc25nySM/ +yHwfDVEt2eeSh2xZ2Kv1d8VWucKTg8lXrK+ooXsXcYiy61IB12mnjuKPa/FUxFS4 +JM2AiESAcF0ks9YGnHz5atWTSPAnEYKTqIrZDoYqJkbgClLiRdrZY+N2hC5jdZeW +cR1EkHw0PZqw6S2eCHL5hUi6ryPKMkre1oH3Xdag2DJT8qQxbuNqhhrm/L+8L8lX +f5F3asZ05yCB1pnJRqVPESYDajoN8u1lWD18RYsWX60ld2PcwCxsHkPOyoBvAV1u +PgCYq2l6s5FitBJR9RvIIWQXgYcJnkvvctXAE4sHkA/8YmzJKAUlmADFxObHh7nH +B9Tr9F5MMMItWtOlRVOB7r7GpKZ4CIu9H0pG8rHeitdTJzb//0sRPwO4Ifpq00gF +PYpm2+uw1qrcWOBG9wrbOEUMiFlt1c1y6CM7W0HiQg/FK+4Y4JiB7uaAlzUejTOI +zOL6no+QbQSWHIEVAYNpQGNcTG+AuFlhiSI5DitSGvW5yCLRLs7Fv5AnqLM6z1Qg +nRTXEKDaR/AFlAFB16izDRH4FYwpXtH01JTfdxvrFbPDjE2B07qlVwewnCVApXy1 +GNPPzEat9SO3vQ9t7PCKFzQV6OGGAn/dyMwguU6EDW8mcNxemcFiHUdiSfhhZpeH +IcnqAMISo7J5oznEHRV6eZ2t27p8fCR6kY+/9tdw+mhgfM47E9D+jOa2LZcvRNK0 +IxKxNWtgUL0KlYtkFTGEhG+p36IePpoZOlbFukyAkrvx2uvJdjDKNhR7fljgKZp9 +ntpSnYfXJhwQrP8yTvoXUhnLpaxBTrh8cyLUFVm+2UtqRrz/+WA/Du8u19N0NmoU +4Z65V0tXF/tW4DpeElKcg5Z9g3Srjon+LpuobgvaptlZ3rG7pXXklUAdxNfJ+4mu +g8S64RYvfLamt1za0XyFbePfAbEPHUNKbKIqzGRB92kxJ6jYjgC9RQHp35SL3T55 +2DhArYHiRs4HAieVOggerJ2mFKRe1jgXpNH28cIvReVtjhPSR0h2/N1kktJoFN9j +pAwsBXcE20H2DgeDq7MOl5klQOQIZqq2NOi/TtiDykzXOq9c52KT5YQDUiFYqQvD +H29baw+SyQUZTso78q8DVb5S1dB3XyHStAKgoGq93+Wz/B1RLpKYack4xd4rdS5s +pwx6XbBMdp7aDqOyz2KgKWf+dspEnt1aZSkLPUfnK1QqEuwBFSip0++f8lsYJwt6 +h2RR9rfNZmd8nt+mXhbGkKeiOagijsA/5zVB+4MgI0KR9sujHhdd3ikiYUTRDpcb +AA7w3mFn6w2oiAcHGimR/cBGrmo7m6L0USsPGqFYBLIQfdAn5dEBlb2BCoA5VFZj +jXKJF/jua7Y+DrPzh66goMGjpF9lBpoEP1rWQA/7bSpIp6mTsXcqppKrJq4X3UzK +fnxoXMOzyXak8Q0RLDFj9NSgAWzr4VmwVpFWnocoXpsQlisCkXdTJvGnor8LLZr9 +sDZmzgcSix39SaRGPrUkPl4jLdocSaImMFvFf75Ln2LkiFK2PwLHbdxu5OHmQoCw +7wBcsGkL2gXd3tYL2ns54yYSqMYHrxBbag+ndd5VaJnjZK34JNDCSh65qkKE7y7v +Behj6SqW7qWtdmufzd16RndX/9C4+tnd6CZRltVVSxqHORQEFpJfBX3qZLp11vTQ +Pib5SMqM0nVbJDVpqDeCAA== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +V7fazAcYfn/upNWI2MrDSQamEge7Y8sqGyEbHWTTDvIkXpdIuRisL8LJjvy83vue +ZgYLruqRxsDQR/Wu7PMlj65sb/NkxpSPTHfwdQcOEP3MsixExszjuA1HqHtg+aNQ +uFOiuMhxVPj6PMHq/Hqrqa85QcEVSbWPuLxSaFzY0ndkgyErZck8cU+0bbs6pFmr +tNIeglsOu6Am3uxBT62KHdsx5/dbyBFUXzyoeMcVqVN/dSwFJEWKXykd+OnIo8cg +TAWc+EOAJ6ExmKO/aLU8Un5EpThP6h/F+4FSrXQ8+zAfJHLLmWelIILCIn9r270y +7CUxtRRDMVrzxeZaHx87Jw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1200 ) +`pragma protect data_block +0H3ui++saKA3Qim7nBCnYyJXuXUUae6AJ4LYf9uQIt7dDyl6C5Q3z+wohgm7l6P/ +puE1YIk57wYrhZfaxaOZbQEeQcTD5dhNWYlNGXkVD3n3ordUMQqbpossg6k8GBbL +hcT5AJLRLWp1fmFYHU/sChpXsLIvsw4ylUF+kPCiM/E2Qrxqk+h6yKLdH/qUhhl9 +SFhgQaFfWNjj6ajZXfTXAeH01G9YVoXQTrTURK7LCmy8Exrca33pvD2n8qRjNHVC +SMvlBAlMyB9GhVbgRH5g1J3eexKd42EKVG1OYkkLmaw/2mYb6XQBYWGV+JPCs/lf +iK57mI1tmXdY1dZroI+VNNMZ2ERNO1xPtSdY84zkg7t8kqVOzrKucAQtG6cbtv1M +zOk4T1+sHwfHB5B0MAQxfUujCPIx48x0ucEJPziWVe4xGSV7Y/CdKWRJKyu1t9Fd +RrGJ90FB8JcoftYS17u1PRbcM0J+K9rYOujMCI2wOiGLeakIZUzeUlYgu3AhwJ+p +rFTdyQbZfeR1hJMbKn0z9kiVI7O//BPB79Ovy0ckHGOWpsznVPMik4mcftaUGBo/ +SKRhNP5RZ7ADTWwNcGVQ50K6Uk/FWRH/LjkzUDgrlN+BL9CVLgTUzw4n7TXZLYO1 +UUMwg1Abr+r4azUlV2lllRgjlWSPEmPeuWdkmDLE1kzi81/3MG9dkGcEzpCjQn1g +wlq08l1m/9D6ssj9X+L9zWestpPbK8KKA36LM44lR7JM48DHZp/GFFbwyCyfem5J +Yk9dQrVMSLDeQfsKUdIRfzsLFIcVo9j9nAjaOh5icY9Ju14nqLljzJxMSLXwpRpN +pHlAUZkLKZ81BR2lNUcueWoYr1mNO5wt/8ZXKNAe4baXyx5pQlkEoPhDAu/MmaoV +IQmRsNZAJw70Y6wneeDDkHad2vIHrOElxrM5Lnlhdq1qO4G2CjQ03nmLodMZn/cu +JhstoiAqinvEClsBGQAEn59Mk5wMvMergihuxdt6qTvztnpZTBcB2JqJyHkCY2xR +XYx3muggMb4QtLLic31NtDmfG8SMy5jpSvmNNdDUrcWI5vOaLo+t2/mVb5p6U/Z8 +WsFN6j8TpdcSc+yFYrWVYf/mabwUsQccMAaYaGcHwQTAXW/zRUxCfgK2BtB9AUG3 +Kwe4fuqZPo1NDmSSdATNh7Ls+wMag23tKAtoVCW+TQ3lLpto8vUWhWKQTH1PsQRx ++KWcJaJK96bA+80M/q4HUzR+yC6IUVQ9VRvWhgG0ygZTLKmQmJ/DKIzlw1lxCkA3 +JF0FRPBrpi2n+UOIXtU6FUAnUoSUl8Eeuwpycld1aaAI++CWVpk0pdWCRD85nBNb +vAQ7vQzvYravu3V0bHTVB/w+yyy05bUUjf1aVui34DyQ1QLLkq3XQF2v9st57JGH +egpS3SZqHPJ0AZAJJvkOXoxVRMHu48i9M6Wx9Qjtrh9EJee4xLdxqYrF04J9h9ck +AvKxciqIeVCjtaleTRBLEWnwUKa6wADHB0WNBFNEidDe8gAcwWkZyKkh/VaUiupU +5Cv90Shsjvie3xvNr1QXSLjEkUzHLYrvPv6IGVvcwtPvJNwajthWm4H1o8D7rdfK +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +idlb0ipwgIc0hiUfW9lCBvIc27j+O1T55dJ3BL9eUyC3AmELfvx2LyGUfXvUfYTf +8sHVL37lgxYwkxIH4ZSSZQ1GK2zLKlNHYUEmXZIR/WoNIg7U3rYo+/OAX5LDNWz3 +I3htHfdktV9gYc7iVdI9VNrqBa0Gg55NmIOrO+wM2ME4dVbdMJVDfW+oOu9rTeme +KOonn0oR5/zNCWcqkhf2z6BLLm49S0wwKQJc9Tn8j8aAVVAS5PR4HM/UAt+Pm5Qw +qUaeukXs5OImR86WKmCfOXrROtxYmBZ//zwyzxGdjene5Dzf1Lue74V7vg9Yy8Es +kofIx1Iiwvl5uhKqK0ZywQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1984 ) +`pragma protect data_block +W5IcpMWeZEmcNKazNSseGe/SkDOlgncKe6xygU4WozXer89CE7H74/gQ3yQQ4LCo +YC8yuYKcjPKApcXYJYuOgpsab8uIQGftqOoDnHHE/TFo5sK5ih7BYybPWYaaZIfN +U42fSf3IGBc/VJJMqP+4YGf2p7Dp5YE+Wy7VkeYE9mZmjDlwds+pPKcijo5Rgpy4 +aylibzsZkO5+oK4Olfl1/eP949zocOLdn828ECpQrR+1rd90XEST7JJU34+5nQR0 +iYx3aHjOcfjFetECQ73ZAYN9xqbs+aqjzeLBFzT66wgcNopyNE3rPObBjFm/FlMY +NJuj22N2AvkTuG1FfuBr5E5/i9RjA+BTgZPyYvLaoLqprEm8CWiFhmozo0TuSThV +oxsGKZXYjCpb3zoOzL++RaNuogj+rTHHnB4sjSyjcQXyW9FHyxQ9ou3pB0HSnVv9 +mmlv1FlvuwmXWRcsAbk9MN5Bu1XDI5gL7Ipu6jQGD76fGfDk5YZNwHHplmC9Hxoo +14fkoUi/IGM4yaR9gsmZ4/V39IhpdKS0TO3LMyFgBX1m9J69gD3agPTxpHvmjGBF +iBeClMI2X+GOMbRoQ7MTuRI/wsqqHaKZFnqG2JrdQ5jH4KCWRqJG4uuYi7J1i9bs +xY16r9KjF+6f0MFsxcK3KibLp7s5dEDpsw2XIf00NhedOsMfk9w9HgMaBIhHDYko +R9z9VCyALLVSnoVdMfGtgRCz9L0ZTjxm9XhyXpCWP2dQQ5YHyD+cFxCRM2u+sbOa +XCcYDb1UlKsoUKPrA6upaDj3TlNdAdCre4HET9kn0PDrdWIRz9my1VexCrOwQ/4v +/AGqqMzOkN1K3GiLhBjp7mc32jSK9Xwlf04J/O25O257w8YWwGgCDGh0YcXBAP9P +dRzMnjs3Uk7xrEq2VCihUs7MsFR2dplgxIVe/f4i6d9mLLp/cVw1tY4mO7GQJJL+ +NJxQNxDTfheXoNHxcaGlEvOWL2b3J/OVNbr/wJPsNPO3JZmZWUpP8CsvLDnb13uy +iNwDj4gZpR9546m0yEFGqGJTEKCKJEKdLC6E6Gdr4yH+RNK3GQAtivmlYR1RQi50 +PKxXgfvCk7ALJB0/AJ3VKJanssU7Hy6k/ihsWnMeUmW60hSGVcI7H4Dc2LD/zqWt +hTHS+BRPB55N1E551ExGrUEM85MWlZDv876GiCWMXvhRqs9srCM9ecVIL7dQAs33 +eEmvppS+tTUufZM9oZTu42ShCYqUVMSqeUy/xzqnGhbXu4Q7GBe6tQ22Qrny4jVx +0oqenju9rIFJylCiiAE55m3dRqcpZ/BW8zJT9E5xqywiyk2hKjD3cBa8sFQk4o0L +Q8sbZOGGnwkBiq09qANjvGvlkm1v9FDgC5FRhvdDYVbDc5kwRgkXw2C5yGo8ATdo +PBCMK39Rit7ogQUspBMSRycdQEknqdzSNQE/bSr+sFg7NtFexRxi9+4sFCfzdOdH ++cDNk2jJ3o5Pt3cxiWI+66BF+lGKauggjRt6wxcGgXxd1mAGo0E3ZAxv0Yzqu5pw +DiX9Ub+lowoE+P03j9ORmbT4fPh1vCZqOweT5yq4msNhPgF5yTiyJxa1f/nW/871 +YIJppXKMqggxL4xvTBLMFRRq5hyIaGUvjNRoml49I2/e1TeW/m4txLIR28P5W3g5 +XlPYaCFV3Q6BFDTb6hzglWO0MdX0htcU794klHzIjr9es0VaPjbGbgJwq13D3F/0 +Wq8j0HPafBZpvWLerjIfQntl7kZCuc2V2cANOqkVpbyXIWRCbZ7tsWyxylvndsWT +6E4JutWqIlD9ScB+1qz5I5aMLznRt/6iauVApWrYxEUIHKCY2O4d0GeF6lI4gTr2 +Ff4x1GYqVXjRfQ14+0Q/UVGYnaif0luhvPGRrZVCGBn5bYgic6aYLLVr39G/Bw5V +zhXtqIf1ISZtmmzRBJTn+QdkE1Rw+SrJcH8BdWjLo5Q4VpHvSX4wlw9lt2zjHr1g +Gw3jvpOsK0lFtMbrT1TOkk5TIAVkSEti7VAGeaycfKxXTfXsQcEdeTjsx/z+7E4s +5LmeTE6BUDvniF9TMGxAh8UNoorK/9h7raa/mc6UP1Ap0sVsn6FAnB5a3hp8AcfO +YyUI/+rE3uvbY7eV0TjnPlB2a4bKmip2sUnzCtjxk38a70NoSwvSF5fHD/gmb2Kt +In3bRGhQ51Ou8wyYtPtzpRKl9lfBj579kv2ljgctkPOCPxJ0qOO5U7vH9UVhyH4V +8Q6lGkKpbY+oJSEyXkd22SgAuuLMTQzychAeCZrzurKRTCJEkybeqpnHeMDZF144 +yT/sjynj+V1VANU1CW6cQPulbZj2svXukJupVa/ZhMF/Y2G5v2JIVKMZvprQfUMy +xrTAArhmrRjDrUfSaRBsr2icFO6IfrS7qjcKaFF4e7O/jDKLppha19sW6TL25Rzm +Ahjf7mc7/2mJeA/0ayik5t4ZP/xwgvgOII8quhw7Vrm37O9aT6wkCL/5JIKv6tpA +nWE/0iwIWwBWPYliaqFvsEcfMuowM9WrIG4B7EkD5jyS0Lwo/CezIdysfC7/rgBy +x3ZrJCp51uVHU3kT5JLDk0pb0CBXd7O/pLb7bpfJmQZYLmzXM7a6D32ZvJzsMxDq +M6eR/VTYArPQbA4OoPqXhQ== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +kjevziVpR4HNp6ABOs1UfEhnb+dX0JPweI6S3+LX30C9LF3xx7Xd/zMszyIOAsff +hodfZOinnjjXzBncB8lZ/iwEBQcN9AOUuJkxqHw0xEX9lKugu7WOxROcH+yiXxDJ +yy9yDzS1F865ocB3xO9FWkMnml1XZRqox2FTUI5GMVk0MxMQPCoaWPmG40cuqt8H +oNSQWIvbZ0bwp2zXvC4BQlkXD2oWWu6JxxVIVspZ7XmHHSfSB+gK8bmQIk2JZPQd +nB3A0s+SLUanWE/u+Muh6A5t3kkuvJ5Fy1rRHEwle6WO6L5S2arPlksoYEp7hfDo +eW9+LO7WnZdnt0b3dQw5Mw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1104 ) +`pragma protect data_block +LX5Dxt8B2z9u2haDN6HkGNj1Nxa2zeRWxlMLLnbgcY2+2ueKKYern04T7l3DicpU +GAgNW7GQnUadJWzOBc5yfD2Z7DyC1zg+m258ATNxkXP9Ag8Pfl4MhmlpUpmkc23o +YSNVfWttcQespNGB+Kj9g+/b/Ltzb/Pp1dgaxi5NIlG7FsWis/B/nSO/Vd0xLa8l +gdvKVbsSlGSB1tT5WBnrVIsaLuvPuUdgdvXFHzLrEscW/eC28+m22DdewgK9tHYj +l4yaTKwJ+7R2jtaFZr8jMmcRudxesBNt1kTJeA9U1nitqtdHVp23JcdwKc05jnrW +tx2+meDVE/d5vcxlhTdpO8sz2YOw2Z0bAN+ieJFfUDfTuopqPBMc5GBfsrD40ELk +H3q+hGhS+dIM3hrqhKDRW3tPFmcE5szwJbmOAxflm1SvQmlOnQVePLGdCuOZUUiI +tz++pZ5FH+uAdkA40yZWh5MnKo5IcfFxWM2Jsum3JZvmVMjnI7N1x8f70kUe3UgZ +KEcI12J/dpNLgdFOl+74xfjhKGoKm/BgN6Eb01T1RtdX6u5xQtgGCuv62jDE/Yt3 +eJjRnF/x+Ay39zeCLP9UQvypybEe14bN7gfHfWoAQe9HIG87Fm2nKjAzASr6QFRV +DL1jo931/n1Lv9oZuWMfaF7ZCTxH6A9fBYglk+u3TWHi+TkymppU4hV3XjEHw3B7 +wrSwISGJRMUoCJ0wh/W9Iqj3EDcLmFUIHicsgmfrUkpdpcDqQYIKmCedP/+uQ37E +hBOgLdq2ET/+T377dhiMAvLWIMnT6X9iEzqdVEMfkuPgbBZetAoTzb7IozmdA14+ +3PCjcT9XV5Hxvw1vyLKchF3xGFPaDFJgGJtzSIMeyTd9yK/++OeT1TQ0HFPfjjqB +LI0xhfRlEGqOj1YzmolIUWRdGapI6Ywt79vK6KTeqg9K4jHGe3R1t2SJUnNELlNy +Ju1RcPdn+2rNasE/ecNNfcArJ3ReZiWkO6Urua3WtmUiTzAVXd6UD4GUf3QUw0J5 +AefzuP3tFE5IfHRFmTZWTm7Y/JLAztWyBuag+6TRZLBlyPJDyNieFGTz4SEyTkAc +CyJ51RLW7x5j/8mo5k2anYrG7q1YYjOUQHyaLPL/RwYcBBJS38HGPAl44N6KsB9m +PGaS88rOnKmcVDest/nmsVi5/wR7C0xrMTpo2i2v7wOVW53j3SANDy4UhRYGQ75m +9+CZTXcObV1oXJW0me53hFtEJ+qHc7eFGKyCVwTNanP47XH3aJey3ulpiTKXp9iD +rurNoDvwMo1/Wv8495pWfGIS50V6wFEVgh2p6gt3S7meUf9sdMYrrKeQAKEna1ne +Rf8O+xm0FaLvKNBVaPV3ISnRU2qTxpWhaUb3vTQN4TODsKco29kkHPqYRTREwU5p +4ExJ23nclyx/By+ugg0UnN5jZ/DGDMK6ZJ2abjL+WrT31jFUNXgt+rmb/8ViJNIm +`pragma protect end_protected + +//pragma protect end + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Ti375C529_devkit/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_define.vh b/Ti375C529_devkit/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_define.vh new file mode 100644 index 0000000..cacbc6f --- /dev/null +++ b/Ti375C529_devkit/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_define.vh @@ -0,0 +1,53 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2026.1.132 +// IP Version: 5.6 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2026 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam ARB_MODE = "ROUND_ROBIN_1"; +localparam S_PORTS = 2; +localparam DATA_WIDTH = 128; +localparam ADDR_WIDTH = 32; +localparam M_PORTS = 1; +localparam ID_WIDTH = 8; +localparam USER_WIDTH = 3; +localparam PROTOCOL = "AXI4"; diff --git a/Ti375C529_devkit/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_tmpl.v b/Ti375C529_devkit/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_tmpl.v new file mode 100644 index 0000000..59e2d33 --- /dev/null +++ b/Ti375C529_devkit/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_tmpl.v @@ -0,0 +1,137 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2026.1.132 +// IP Version: 5.6 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2026 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +gAXIM_2to1_switch u_gAXIM_2to1_switch +( + .rst_n ( rst_n ), + .clk ( clk ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awlock ( s_axi_awlock ), + .s_axi_awready ( s_axi_awready ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arlock ( s_axi_arlock ), + .s_axi_arready ( s_axi_arready ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_wlast ( s_axi_wlast ), + .s_axi_wid ( s_axi_wid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_rready ( s_axi_rready ), + .s_axi_bid ( s_axi_bid ), + .s_axi_rid ( s_axi_rid ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rlast ( s_axi_rlast ), + .s_axi_wstrb ( s_axi_wstrb ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awready ( m_axi_awready ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arready ( m_axi_arready ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_bready ( m_axi_bready ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_rready ( m_axi_rready ), + .m_axi_bid ( m_axi_bid ), + .m_axi_rid ( m_axi_rid ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_rdata ( m_axi_rdata ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_wready ( m_axi_wready ), + .s_axi_wready ( s_axi_wready ), + .s_axi_awprot ( s_axi_awprot ), + .s_axi_awcache ( s_axi_awcache ), + .s_axi_awqos ( s_axi_awqos ), + .s_axi_awuser ( s_axi_awuser ), + .s_axi_arqos ( s_axi_arqos ), + .s_axi_arcache ( s_axi_arcache ), + .m_axi_awprot ( m_axi_awprot ), + .s_axi_arid ( s_axi_arid ), + .s_axi_arsize ( s_axi_arsize ), + .s_axi_arlen ( s_axi_arlen ), + .s_axi_arburst ( s_axi_arburst ), + .s_axi_arprot ( s_axi_arprot ), + .s_axi_awid ( s_axi_awid ), + .s_axi_awburst ( s_axi_awburst ), + .s_axi_awlen ( s_axi_awlen ), + .s_axi_awsize ( s_axi_awsize ), + .m_axi_awid ( m_axi_awid ), + .m_axi_awburst ( m_axi_awburst ), + .m_axi_awlen ( m_axi_awlen ), + .m_axi_awsize ( m_axi_awsize ), + .m_axi_awcache ( m_axi_awcache ), + .m_axi_awqos ( m_axi_awqos ), + .m_axi_awuser ( m_axi_awuser ), + .m_axi_arprot ( m_axi_arprot ), + .m_axi_arburst ( m_axi_arburst ), + .m_axi_arlen ( m_axi_arlen ), + .m_axi_arsize ( m_axi_arsize ), + .m_axi_arcache ( m_axi_arcache ), + .m_axi_arqos ( m_axi_arqos ), + .m_axi_aruser ( m_axi_aruser ), + .m_axi_awregion ( m_axi_awregion ), + .m_axi_arregion ( m_axi_arregion ), + .m_axi_arid ( m_axi_arid ), + .m_axi_wuser ( m_axi_wuser ), + .m_axi_ruser ( m_axi_ruser ), + .m_axi_buser ( m_axi_buser ), + .s_axi_aruser ( s_axi_aruser ), + .s_axi_wuser ( s_axi_wuser ), + .s_axi_buser ( s_axi_buser ), + .s_axi_ruser ( s_axi_ruser ) +); diff --git a/Ti375C529_devkit/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_tmpl.vhd b/Ti375C529_devkit/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_tmpl.vhd new file mode 100644 index 0000000..bced8de --- /dev/null +++ b/Ti375C529_devkit/ip/gAXIM_2to1_switch/gAXIM_2to1_switch_tmpl.vhd @@ -0,0 +1,229 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2026 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +component gAXIM_2to1_switch is +port ( + rst_n : in std_logic; + clk : in std_logic; + s_axi_awvalid : in std_logic_vector(1 downto 0); + s_axi_awaddr : in std_logic_vector(63 downto 0); + s_axi_awlock : in std_logic_vector(3 downto 0); + s_axi_awready : out std_logic_vector(1 downto 0); + s_axi_arvalid : in std_logic_vector(1 downto 0); + s_axi_araddr : in std_logic_vector(63 downto 0); + s_axi_arlock : in std_logic_vector(3 downto 0); + s_axi_arready : out std_logic_vector(1 downto 0); + s_axi_wvalid : in std_logic_vector(1 downto 0); + s_axi_wlast : in std_logic_vector(1 downto 0); + s_axi_wid : in std_logic_vector(15 downto 0); + s_axi_bready : in std_logic_vector(1 downto 0); + s_axi_bresp : out std_logic_vector(3 downto 0); + s_axi_rready : in std_logic_vector(1 downto 0); + s_axi_bid : out std_logic_vector(15 downto 0); + s_axi_rid : out std_logic_vector(15 downto 0); + s_axi_wdata : in std_logic_vector(255 downto 0); + s_axi_rdata : out std_logic_vector(255 downto 0); + s_axi_rresp : out std_logic_vector(3 downto 0); + s_axi_bvalid : out std_logic_vector(1 downto 0); + s_axi_rvalid : out std_logic_vector(1 downto 0); + s_axi_rlast : out std_logic_vector(1 downto 0); + s_axi_wstrb : in std_logic_vector(31 downto 0); + m_axi_awvalid : out std_logic_vector(0 to 0); + m_axi_awaddr : out std_logic_vector(31 downto 0); + m_axi_awlock : out std_logic_vector(1 downto 0); + m_axi_awready : in std_logic_vector(0 to 0); + m_axi_arvalid : out std_logic_vector(0 to 0); + m_axi_araddr : out std_logic_vector(31 downto 0); + m_axi_arlock : out std_logic_vector(1 downto 0); + m_axi_arready : in std_logic_vector(0 to 0); + m_axi_wvalid : out std_logic_vector(0 to 0); + m_axi_wlast : out std_logic_vector(0 to 0); + m_axi_bready : out std_logic_vector(0 to 0); + m_axi_bresp : in std_logic_vector(1 downto 0); + m_axi_rready : out std_logic_vector(0 to 0); + m_axi_bid : in std_logic_vector(7 downto 0); + m_axi_rid : in std_logic_vector(7 downto 0); + m_axi_wdata : out std_logic_vector(127 downto 0); + m_axi_rdata : in std_logic_vector(127 downto 0); + m_axi_rresp : in std_logic_vector(1 downto 0); + m_axi_bvalid : in std_logic_vector(0 to 0); + m_axi_rvalid : in std_logic_vector(0 to 0); + m_axi_rlast : in std_logic_vector(0 to 0); + m_axi_wstrb : out std_logic_vector(15 downto 0); + m_axi_wready : in std_logic_vector(0 to 0); + s_axi_wready : out std_logic_vector(1 downto 0); + s_axi_awprot : in std_logic_vector(5 downto 0); + s_axi_awcache : in std_logic_vector(7 downto 0); + s_axi_awqos : in std_logic_vector(7 downto 0); + s_axi_awuser : in std_logic_vector(5 downto 0); + s_axi_arqos : in std_logic_vector(7 downto 0); + s_axi_arcache : in std_logic_vector(7 downto 0); + m_axi_awprot : out std_logic_vector(2 downto 0); + s_axi_arid : in std_logic_vector(15 downto 0); + s_axi_arsize : in std_logic_vector(5 downto 0); + s_axi_arlen : in std_logic_vector(15 downto 0); + s_axi_arburst : in std_logic_vector(3 downto 0); + s_axi_arprot : in std_logic_vector(5 downto 0); + s_axi_awid : in std_logic_vector(15 downto 0); + s_axi_awburst : in std_logic_vector(3 downto 0); + s_axi_awlen : in std_logic_vector(15 downto 0); + s_axi_awsize : in std_logic_vector(5 downto 0); + m_axi_awid : out std_logic_vector(7 downto 0); + m_axi_awburst : out std_logic_vector(1 downto 0); + m_axi_awlen : out std_logic_vector(7 downto 0); + m_axi_awsize : out std_logic_vector(2 downto 0); + m_axi_awcache : out std_logic_vector(3 downto 0); + m_axi_awqos : out std_logic_vector(3 downto 0); + m_axi_awuser : out std_logic_vector(2 downto 0); + m_axi_arprot : out std_logic_vector(2 downto 0); + m_axi_arburst : out std_logic_vector(1 downto 0); + m_axi_arlen : out std_logic_vector(7 downto 0); + m_axi_arsize : out std_logic_vector(2 downto 0); + m_axi_arcache : out std_logic_vector(3 downto 0); + m_axi_arqos : out std_logic_vector(3 downto 0); + m_axi_aruser : out std_logic_vector(2 downto 0); + m_axi_awregion : out std_logic_vector(3 downto 0); + m_axi_arregion : out std_logic_vector(3 downto 0); + m_axi_arid : out std_logic_vector(7 downto 0); + m_axi_wuser : out std_logic_vector(2 downto 0); + m_axi_ruser : in std_logic_vector(2 downto 0); + m_axi_buser : in std_logic_vector(2 downto 0); + s_axi_aruser : in std_logic_vector(5 downto 0); + s_axi_wuser : in std_logic_vector(5 downto 0); + s_axi_buser : out std_logic_vector(5 downto 0); + s_axi_ruser : out std_logic_vector(5 downto 0) +); +end component gAXIM_2to1_switch; + +---------------------- End COMPONENT Declaration ------------ +------------- Begin Cut here for INSTANTIATION Template ----- +u_gAXIM_2to1_switch : gAXIM_2to1_switch +port map ( + rst_n => rst_n, + clk => clk, + s_axi_awvalid => s_axi_awvalid, + s_axi_awaddr => s_axi_awaddr, + s_axi_awlock => s_axi_awlock, + s_axi_awready => s_axi_awready, + s_axi_arvalid => s_axi_arvalid, + s_axi_araddr => s_axi_araddr, + s_axi_arlock => s_axi_arlock, + s_axi_arready => s_axi_arready, + s_axi_wvalid => s_axi_wvalid, + s_axi_wlast => s_axi_wlast, + s_axi_wid => s_axi_wid, + s_axi_bready => s_axi_bready, + s_axi_bresp => s_axi_bresp, + s_axi_rready => s_axi_rready, + s_axi_bid => s_axi_bid, + s_axi_rid => s_axi_rid, + s_axi_wdata => s_axi_wdata, + s_axi_rdata => s_axi_rdata, + s_axi_rresp => s_axi_rresp, + s_axi_bvalid => s_axi_bvalid, + s_axi_rvalid => s_axi_rvalid, + s_axi_rlast => s_axi_rlast, + s_axi_wstrb => s_axi_wstrb, + m_axi_awvalid => m_axi_awvalid, + m_axi_awaddr => m_axi_awaddr, + m_axi_awlock => m_axi_awlock, + m_axi_awready => m_axi_awready, + m_axi_arvalid => m_axi_arvalid, + m_axi_araddr => m_axi_araddr, + m_axi_arlock => m_axi_arlock, + m_axi_arready => m_axi_arready, + m_axi_wvalid => m_axi_wvalid, + m_axi_wlast => m_axi_wlast, + m_axi_bready => m_axi_bready, + m_axi_bresp => m_axi_bresp, + m_axi_rready => m_axi_rready, + m_axi_bid => m_axi_bid, + m_axi_rid => m_axi_rid, + m_axi_wdata => m_axi_wdata, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_rvalid => m_axi_rvalid, + m_axi_rlast => m_axi_rlast, + m_axi_wstrb => m_axi_wstrb, + m_axi_wready => m_axi_wready, + s_axi_wready => s_axi_wready, + s_axi_awprot => s_axi_awprot, + s_axi_awcache => s_axi_awcache, + s_axi_awqos => s_axi_awqos, + s_axi_awuser => s_axi_awuser, + s_axi_arqos => s_axi_arqos, + s_axi_arcache => s_axi_arcache, + m_axi_awprot => m_axi_awprot, + s_axi_arid => s_axi_arid, + s_axi_arsize => s_axi_arsize, + s_axi_arlen => s_axi_arlen, + s_axi_arburst => s_axi_arburst, + s_axi_arprot => s_axi_arprot, + s_axi_awid => s_axi_awid, + s_axi_awburst => s_axi_awburst, + s_axi_awlen => s_axi_awlen, + s_axi_awsize => s_axi_awsize, + m_axi_awid => m_axi_awid, + m_axi_awburst => m_axi_awburst, + m_axi_awlen => m_axi_awlen, + m_axi_awsize => m_axi_awsize, + m_axi_awcache => m_axi_awcache, + m_axi_awqos => m_axi_awqos, + m_axi_awuser => m_axi_awuser, + m_axi_arprot => m_axi_arprot, + m_axi_arburst => m_axi_arburst, + m_axi_arlen => m_axi_arlen, + m_axi_arsize => m_axi_arsize, + m_axi_arcache => m_axi_arcache, + m_axi_arqos => m_axi_arqos, + m_axi_aruser => m_axi_aruser, + m_axi_awregion => m_axi_awregion, + m_axi_arregion => m_axi_arregion, + m_axi_arid => m_axi_arid, + m_axi_wuser => m_axi_wuser, + m_axi_ruser => m_axi_ruser, + m_axi_buser => m_axi_buser, + s_axi_aruser => s_axi_aruser, + s_axi_wuser => s_axi_wuser, + s_axi_buser => s_axi_buser, + s_axi_ruser => s_axi_ruser +); + +------------------------ End INSTANTIATION Template --------- diff --git a/Ti375C529_devkit/ip/gAXIM_2to1_switch/ipm/component.pickle b/Ti375C529_devkit/ip/gAXIM_2to1_switch/ipm/component.pickle new file mode 100644 index 0000000..4f29ee4 Binary files /dev/null and b/Ti375C529_devkit/ip/gAXIM_2to1_switch/ipm/component.pickle differ diff --git a/Ti375C529_devkit/ip/gAXIM_2to1_switch/ipm/graph.pickle b/Ti375C529_devkit/ip/gAXIM_2to1_switch/ipm/graph.pickle new file mode 100644 index 0000000..0e78302 Binary files /dev/null and b/Ti375C529_devkit/ip/gAXIM_2to1_switch/ipm/graph.pickle differ diff --git a/Ti375C529_devkit/ip/gAXIM_2to1_switch/settings.json b/Ti375C529_devkit/ip/gAXIM_2to1_switch/settings.json new file mode 100644 index 0000000..481a3b7 --- /dev/null +++ b/Ti375C529_devkit/ip/gAXIM_2to1_switch/settings.json @@ -0,0 +1,54 @@ +{ + "args": [ + "-o", + "gAXIM_2to1_switch", + "--base_path", + "ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "axi_infra", + "name": "efx_axi_interconnect", + "version": "5.6" + } + ], + "conf": { + "ARB_MODE": "\"ROUND_ROBIN_1\"", + "S_PORTS": "1", + "TABLE0_AXI_S0__MIN": "32'd0", + "TABLE0_AXI_S1__MIN": "32'd512", + "TABLE0_AXI_S2__MIN": "32'd285212672", + "TABLE0_AXI_S3__MIN": "32'd286261248", + "TABLE0_AXI_S4__MIN": "32'd536870912", + "TABLE0_AXI_S5__MIN": "32'd805306368", + "TABLE0_AXI_S6__MIN": "32'd1073741824", + "TABLE0_AXI_S7__MIN": "32'd1090519040", + "TABLE0_AXI_S0__MAX": "32'd9", + "TABLE0_AXI_S1__MAX": "32'd8", + "TABLE0_AXI_S2__MAX": "32'd12", + "TABLE0_AXI_S3__MAX": "32'd20", + "TABLE0_AXI_S4__MAX": "32'd28", + "TABLE0_AXI_S5__MAX": "32'd28", + "TABLE0_AXI_S6__MAX": "32'd24", + "TABLE0_AXI_S7__MAX": "32'd20", + "DATA_WIDTH": "32", + "ADDR_WIDTH": "32", + "M_PORTS": "2", + "ID_WIDTH": "8", + "USER_WIDTH": "3", + "PROTOCOL": "\"AXI4_LITE\"" + }, + "output": { + "external_script_generator": [], + "external_source_source": [], + "external_example_example": [], + "external_testbench_synopsys": [], + "external_testbench_modelsim": [], + "external_testbench_ncsim": [], + "external_testbench_aldec": [], + "external_testbench_testbench": [] + }, + "ooc_synthesis": {}, + "sw_version": "2026.1.132", + "external_path_option": "RELATIVE_PATH" +} \ No newline at end of file diff --git a/Ti375C529_devkit/ip/gAXIS_1to3_switch/axi_interconnect.vh b/Ti375C529_devkit/ip/gAXIS_1to3_switch/axi_interconnect.vh new file mode 100644 index 0000000..9ccec85 --- /dev/null +++ b/Ti375C529_devkit/ip/gAXIS_1to3_switch/axi_interconnect.vh @@ -0,0 +1,2 @@ +localparam M_BASE_ADDR = {32'h41000000,32'h40000000,32'h30000000,32'h20000000,32'h11100000,32'h1100000,32'h1000000,32'h0}; +localparam M_ADDR_WIDTH = {32'd20,32'd24,32'd28,32'd28,32'd20,32'd16,32'd16,32'd24}; \ No newline at end of file diff --git a/Ti375C529_devkit/ip/gAXIS_1to3_switch/gAXIS_1to3_switch.v b/Ti375C529_devkit/ip/gAXIS_1to3_switch/gAXIS_1to3_switch.v new file mode 100644 index 0000000..94fe678 --- /dev/null +++ b/Ti375C529_devkit/ip/gAXIS_1to3_switch/gAXIS_1to3_switch.v @@ -0,0 +1,1361 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2026.1.132 +// IP Version: 5.6 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2026 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _b2d21181e3e64b0ab27cd3f4ca0a3529 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module gAXIS_1to3_switch +( + input rst_n, + input clk, + input [0:0] s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [1:0] s_axi_awlock, + output [0:0] s_axi_awready, + input [0:0] s_axi_arvalid, + input [31:0] s_axi_araddr, + input [1:0] s_axi_arlock, + output [0:0] s_axi_arready, + input [0:0] s_axi_wvalid, + input [0:0] s_axi_wlast, + input [7:0] s_axi_wid, + input [0:0] s_axi_bready, + output [1:0] s_axi_bresp, + input [0:0] s_axi_rready, + output [7:0] s_axi_bid, + output [7:0] s_axi_rid, + input [31:0] s_axi_wdata, + output [31:0] s_axi_rdata, + output [1:0] s_axi_rresp, + output [0:0] s_axi_bvalid, + output [0:0] s_axi_rvalid, + output [0:0] s_axi_rlast, + input [3:0] s_axi_wstrb, + output [2:0] m_axi_awvalid, + output [95:0] m_axi_awaddr, + output [5:0] m_axi_awlock, + input [2:0] m_axi_awready, + output [2:0] m_axi_arvalid, + output [95:0] m_axi_araddr, + output [5:0] m_axi_arlock, + input [2:0] m_axi_arready, + output [2:0] m_axi_wvalid, + output [2:0] m_axi_wlast, + output [2:0] m_axi_bready, + input [5:0] m_axi_bresp, + output [2:0] m_axi_rready, + input [23:0] m_axi_bid, + input [23:0] m_axi_rid, + output [95:0] m_axi_wdata, + input [95:0] m_axi_rdata, + input [5:0] m_axi_rresp, + input [2:0] m_axi_bvalid, + input [2:0] m_axi_rvalid, + input [2:0] m_axi_rlast, + output [11:0] m_axi_wstrb, + input [2:0] m_axi_wready, + output [0:0] s_axi_wready, + input [2:0] s_axi_awprot, + input [3:0] s_axi_awcache, + input [3:0] s_axi_awqos, + input [2:0] s_axi_awuser, + input [3:0] s_axi_arqos, + input [3:0] s_axi_arcache, + output [8:0] m_axi_awprot, + input [7:0] s_axi_arid, + input [2:0] s_axi_arsize, + input [7:0] s_axi_arlen, + input [1:0] s_axi_arburst, + input [2:0] s_axi_arprot, + input [7:0] s_axi_awid, + input [1:0] s_axi_awburst, + input [7:0] s_axi_awlen, + input [2:0] s_axi_awsize, + output [23:0] m_axi_awid, + output [5:0] m_axi_awburst, + output [23:0] m_axi_awlen, + output [8:0] m_axi_awsize, + output [11:0] m_axi_awcache, + output [11:0] m_axi_awqos, + output [8:0] m_axi_awuser, + output [8:0] m_axi_arprot, + output [5:0] m_axi_arburst, + output [23:0] m_axi_arlen, + output [8:0] m_axi_arsize, + output [11:0] m_axi_arcache, + output [11:0] m_axi_arqos, + output [8:0] m_axi_aruser, + output [11:0] m_axi_awregion, + output [11:0] m_axi_arregion, + output [23:0] m_axi_arid, + output [8:0] m_axi_wuser, + input [8:0] m_axi_ruser, + input [8:0] m_axi_buser, + input [2:0] s_axi_aruser, + input [2:0] s_axi_wuser, + output [2:0] s_axi_buser, + output [2:0] s_axi_ruser +); +`IP_MODULE_NAME(efx_axi_interconnect) +#( + .ARB_MODE ("ROUND_ROBIN_1"), + .S_PORTS (1), + .DATA_WIDTH (32), + .ADDR_WIDTH (32), + .M_PORTS (3), + .ID_WIDTH (8), + .USER_WIDTH (3), + .PROTOCOL ("AXI4") +) +u_efx_axi_interconnect +( + .rst_n ( rst_n ), + .clk ( clk ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awlock ( s_axi_awlock ), + .s_axi_awready ( s_axi_awready ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arlock ( s_axi_arlock ), + .s_axi_arready ( s_axi_arready ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_wlast ( s_axi_wlast ), + .s_axi_wid ( s_axi_wid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_rready ( s_axi_rready ), + .s_axi_bid ( s_axi_bid ), + .s_axi_rid ( s_axi_rid ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rlast ( s_axi_rlast ), + .s_axi_wstrb ( s_axi_wstrb ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awready ( m_axi_awready ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arready ( m_axi_arready ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_bready ( m_axi_bready ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_rready ( m_axi_rready ), + .m_axi_bid ( m_axi_bid ), + .m_axi_rid ( m_axi_rid ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_rdata ( m_axi_rdata ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_wready ( m_axi_wready ), + .s_axi_wready ( s_axi_wready ), + .s_axi_awprot ( s_axi_awprot ), + .s_axi_awcache ( s_axi_awcache ), + .s_axi_awqos ( s_axi_awqos ), + .s_axi_awuser ( s_axi_awuser ), + .s_axi_arqos ( s_axi_arqos ), + .s_axi_arcache ( s_axi_arcache ), + .m_axi_awprot ( m_axi_awprot ), + .s_axi_arid ( s_axi_arid ), + .s_axi_arsize ( s_axi_arsize ), + .s_axi_arlen ( s_axi_arlen ), + .s_axi_arburst ( s_axi_arburst ), + .s_axi_arprot ( s_axi_arprot ), + .s_axi_awid ( s_axi_awid ), + .s_axi_awburst ( s_axi_awburst ), + .s_axi_awlen ( s_axi_awlen ), + .s_axi_awsize ( s_axi_awsize ), + .m_axi_awid ( m_axi_awid ), + .m_axi_awburst ( m_axi_awburst ), + .m_axi_awlen ( m_axi_awlen ), + .m_axi_awsize ( m_axi_awsize ), + .m_axi_awcache ( m_axi_awcache ), + .m_axi_awqos ( m_axi_awqos ), + .m_axi_awuser ( m_axi_awuser ), + .m_axi_arprot ( m_axi_arprot ), + .m_axi_arburst ( m_axi_arburst ), + .m_axi_arlen ( m_axi_arlen ), + .m_axi_arsize ( m_axi_arsize ), + .m_axi_arcache ( m_axi_arcache ), + .m_axi_arqos ( m_axi_arqos ), + .m_axi_aruser ( m_axi_aruser ), + .m_axi_awregion ( m_axi_awregion ), + .m_axi_arregion ( m_axi_arregion ), + .m_axi_arid ( m_axi_arid ), + .m_axi_wuser ( m_axi_wuser ), + .m_axi_ruser ( m_axi_ruser ), + .m_axi_buser ( m_axi_buser ), + .s_axi_aruser ( s_axi_aruser ), + .s_axi_wuser ( s_axi_wuser ), + .s_axi_buser ( s_axi_buser ), + .s_axi_ruser ( s_axi_ruser ) +); +endmodule + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +BSiclTfEX07oDTPwvSfmqSh37gsGawnAkFDdQtfz2b2aPAbkkOIevgA5jmAEpk8Z +jmjFoTAnEUNBHxHADHQl29GtYYLQLcTt1dvsb1L8xXXbyd41mZnW9qxR1yEXo2Km +PmHE4/laDDFnEAn08I7oinDvTWN/plGfuIWWaEXC4z7ls9W1O5jNY2gj1ZC0oyT4 +iwzQ3cMmgvMMfqkgA6T8wMNFL1jvPdUxnuGh8qa0Q5zso+v2lpzszj4ytZLI8JZz +ZeX/ipjz/4hUHkihXJPjFD+MetXdYJTpzRO3ZbxTOlyD1Ln8yDvo0qNPrgbzN9qq +YropxHtLb22q5bZxY+vKMw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 9552 ) +`pragma protect data_block ++Vo70GbdNusghssxCh548dyMR2SkpjbMNAhuQNohK03MZPtslM2VcFXDSMs/E4I3 +A0tJBsXs6xJPmnI2dRa4m1jbkpAyspc0YB55NAgJLYdmR9j6FyHXqlpTZEcftxHN +U0jtFOoa18GEMGSCMB1hS59vfrr8WKoVGK2KMx8ZvAuWlQ0YHQjLkE8WQjVMM55l +aP/cENky21pfv/q9aoe1Ku3NLdbDqb8Mf/xcXYVJFJaMRBTujuRBZkvEBDhdz78t +J6irEqM5Esiu61ol7FyudRxQ9CyuB9hXVb40puIOcvjK6w4R5IFdJtzamLms4rEo +ttyRNF4nJVzvrjJErNRuCjJeWgYZGt7SXTDXpHvc/U8J03YrUq//wH9tuvfylFAb +bEasWeYHPxRKeJhZAyvxrsqltj0kDrJuaq1crK/jBem8w2mtGvkYNWTSw/Atty// +XOvqYjH8Lv1IBse+lGx5BUvPW2v9Mklu7s94aket2iIVqh6nVqt3dDC8ttJAA86u +o/wzbF0knyVABaBp8P1cYpjr346wDkAcB6FA1zTweqEsJbzezxvHQWZUuJvtpzrD +6WJJnp5e/9Ky/QdN7rMxioe+hn9rlAjyVazKEtypSZME9YaCXF5xv6Nm68s75QzP +WDEXiCA/MHoKMwovdWzYV8TnQmf1xnU/3KlKAEr3rnLvI5rIf5Sq1RHANvD2rQIw +huUjwsyE+Cy8BrBit89Y5eDgmlc/rlMgWwIfeJKwaHsg4kuDPFUbLV8GBgtD5+L8 +VqiVrOqvPX58wuiR6KJzyUPxXFMd7sxzpjrbe+qIIFvooqMqUeIhZFMzDT477uBF +nOWbpGGLV/uZTq0/nYl5raL9cu7/H5s0K1L0fFJPEkgTRN0sfTeWss5bjNjge0oy +mXpp2W5BhRDGPYszKDzFMl3dWwIKeDyolnsLhp1I80hDszRgEbdTO8qxoyDHRE/8 +7L7Wzj8cBZaQuyJTOdewJEjEOWESJx28Wr+24AqhjMPzM3Oy6QSfC0s0dGX+uLIN +DlepkOWfa1bGnK7EKh+QMw2Y+Hnxwdije+wgquoUNtLjCNB6rPh1qzJSccc7aHh/ +U1bAswc4wnpHqwqKP8bwg8A8C1xW5UW7/D/72SaGhNnfGOQ3BT9d5JFOdo08Rkrn +94ui9eHQlp1Pkpez3kz9Ow4KgTKz9qKk5KE2veb5Yf/jipoT1OXlHbPxelULfn8p +0+XRV85tGcJC0bdjGMMEJA2IXeOAZve0NgBojKtvDOD1jJCLekrfE+40nJvT7GdX ++0rpWydBkbVbKGiRgRUmoDJ9fPvYjrgXPfNZkzj2OuDy5UCeeVUnpKa9eYiCq698 +W1LH4LYjXXtjfzrRPMG6XW+sYkkLami4Ddmchxkkrtmom5f0aV1lzOow9hJVMuQT +ReMoUz6UamLLCoVItZghjS277HIPlv24hwR2WgaS8I4lXvWrUctSIkCPoWudlTE3 +WAy8RJrFGrov4uqTOe+uQISgnW6nxAXZ4wbsGZyJSPaHbFPFpN1ica6KQHRSCMdH +MOjwmMpHtaQ6hfsxP/rL4LiLP5TX9hzvEY++Sfy3TnkxpkBb8JDoIQkg419g1G0g +loYxnF79qgRIRiPYVyCg94Fvjb39r6GBy5sjPAUBnpFQnCUZfEtvEXPn2ff83wJ+ +KFAK5jPLXKq5TR4UxCWES/9MjrzpXX9Q5ZW3afh5gLY/i7Eld2aFuoJ7Yw0Wg0/P +0t+89+widhpOU+Vtj0VhZPPEHGAM7pIAI8BEAIyy+t01V3ELjbGQwLB4FmHh1K6h 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+mD470LuP9+f5Ud307Xx4F6AM71/FGZrha/rJxjluETxdHCy5bAx/oXWQo31VURq7 +3q6UCh0ymGPD837xKYyUYceQRZff4/xlTF/OEQdZPNtbBVE8IsHMp2mfFfSDxq+C +axB5ar3/7/HrmzJElpSIOoSceJQXYo0L9scIrPSF8jNRRB2TxDReT/yjiQsCkww1 +fGF62e7DC0HnyHPBQrRlj9JQC34pW2K2ZTTgQYZhrhwQwTzaoIHBb45KPMMUuBHp +v82gEe/pW9K++sUDQK/W7wgO1NeiS5NHJmtaqv/uH5AOxE1XMLrXPsYiw7p2QJOq +1bmbF7c4TMfs9iT1KNHz2p1mqo4wOo0tHgDdPmL8PXLMm7POrz0rKoBS6lDTid35 +`pragma protect end_protected + +//pragma protect end + + +module `IP_MODULE_NAME(efx_axi_interconnect) #( + parameter PROTOCOL = "AXI4", + parameter ARB_MODE = "PRIORITY", + parameter S_PORTS = 1, + parameter M_PORTS = 8, + parameter ID_WIDTH = 8, + parameter DATA_WIDTH = 32, + parameter USER_WIDTH = 3, + parameter ADDR_WIDTH = 32, + parameter M_REGIONS = 1, + parameter M_CONNECT_READ = {M_PORTS{{S_PORTS{1'b1}}}}, + parameter M_CONNECT_WRITE = {M_PORTS{{S_PORTS{1'b1}}}}, + parameter STRB_WIDTH = DATA_WIDTH/8 +) ( + input wire clk, + input wire rst_n, + input wire [S_PORTS-1:0] s_axi_awvalid, + input wire [S_PORTS*ADDR_WIDTH-1:0] s_axi_awaddr, + input wire [S_PORTS*3-1:0] s_axi_awprot, + input wire [S_PORTS*ID_WIDTH-1:0] s_axi_awid, + input wire [S_PORTS*2-1:0] s_axi_awburst, + input wire [S_PORTS*8-1:0] s_axi_awlen, + input wire [S_PORTS*3-1:0] s_axi_awsize, + input wire [S_PORTS*4-1:0] s_axi_awcache, + input wire [S_PORTS*4-1:0] s_axi_awqos, + input wire [S_PORTS*USER_WIDTH-1:0] s_axi_awuser, + input wire [S_PORTS*2-1:0] s_axi_awlock, + output reg [S_PORTS-1:0] s_axi_awready, + input wire [S_PORTS-1:0] s_axi_wvalid, + input wire [S_PORTS*DATA_WIDTH-1:0] s_axi_wdata, + input wire [S_PORTS*STRB_WIDTH-1:0] s_axi_wstrb, + input wire [S_PORTS-1:0] s_axi_wlast, + input wire [S_PORTS*USER_WIDTH-1:0] s_axi_wuser, + input wire [S_PORTS*ID_WIDTH-1:0] s_axi_wid, + output wire [S_PORTS-1:0] s_axi_wready, + input wire [S_PORTS-1:0] s_axi_bready, + output wire [S_PORTS*2-1:0] s_axi_bresp, + output reg [S_PORTS-1:0] s_axi_bvalid, + output wire [S_PORTS*ID_WIDTH-1:0] s_axi_bid, + output wire [S_PORTS*USER_WIDTH-1:0] s_axi_buser, + input wire [S_PORTS-1:0] s_axi_arvalid, + input wire [S_PORTS*ADDR_WIDTH-1:0] s_axi_araddr, + input wire [S_PORTS*3-1:0] s_axi_arprot, + input wire [S_PORTS*ID_WIDTH-1:0] s_axi_arid, + input wire [S_PORTS*2-1:0] s_axi_arburst, + input wire [S_PORTS*8-1:0] s_axi_arlen, + input wire [S_PORTS*3-1:0] s_axi_arsize, + input wire [S_PORTS*4-1:0] s_axi_arcache, + input wire [S_PORTS*4-1:0] s_axi_arqos, + input wire [S_PORTS*USER_WIDTH-1:0] s_axi_aruser, + input wire [S_PORTS*2-1:0] s_axi_arlock, + output reg [S_PORTS-1:0] s_axi_arready, + input wire [S_PORTS-1:0] s_axi_rready, + output wire [S_PORTS*ID_WIDTH-1:0] s_axi_rid, + output wire [S_PORTS*DATA_WIDTH-1:0] s_axi_rdata, + output wire [S_PORTS*2-1:0] s_axi_rresp, + output wire [S_PORTS-1:0] s_axi_rvalid, + output wire [S_PORTS-1:0] s_axi_rlast, + output wire [S_PORTS*USER_WIDTH-1:0] s_axi_ruser, + output reg [M_PORTS-1:0] m_axi_awvalid, + output wire [M_PORTS*ID_WIDTH-1:0] m_axi_awid, + output wire [M_PORTS*2-1:0] m_axi_awburst, + output wire [M_PORTS*8-1:0] m_axi_awlen, + output wire [M_PORTS*3-1:0] m_axi_awsize, + output wire [M_PORTS*4-1:0] m_axi_awcache, + output wire [M_PORTS*4-1:0] m_axi_awqos, + output wire [M_PORTS*4-1:0] m_axi_awregion, + output wire [M_PORTS*USER_WIDTH-1:0] m_axi_awuser, + output wire [M_PORTS*ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [M_PORTS*3-1:0] m_axi_awprot, + output wire [M_PORTS*2-1:0] m_axi_awlock, + input wire [M_PORTS-1:0] m_axi_awready, + output wire [M_PORTS*DATA_WIDTH-1:0] m_axi_wdata, + output wire [M_PORTS*STRB_WIDTH-1:0] m_axi_wstrb, + output wire [M_PORTS-1:0] m_axi_wvalid, + output wire [M_PORTS-1:0] m_axi_wlast, + output wire [M_PORTS*USER_WIDTH-1:0] m_axi_wuser, + output wire [M_PORTS*ID_WIDTH-1:0] m_axi_wid, + input wire [M_PORTS-1:0] m_axi_wready, + input wire [M_PORTS*2-1:0] m_axi_bresp, + input wire [M_PORTS-1:0] m_axi_bvalid, + input wire [M_PORTS*ID_WIDTH-1:0] m_axi_bid, + input wire [M_PORTS*USER_WIDTH-1:0] m_axi_buser, + output reg [M_PORTS-1:0] m_axi_bready, + output reg [M_PORTS-1:0] m_axi_arvalid, + output wire [M_PORTS*ID_WIDTH-1:0] m_axi_arid, + output wire [M_PORTS*2-1:0] m_axi_arburst, + output wire [M_PORTS*8-1:0] m_axi_arlen, + output wire [M_PORTS*3-1:0] m_axi_arsize, + output wire [M_PORTS*4-1:0] m_axi_arcache, + output wire [M_PORTS*4-1:0] m_axi_arqos, + output wire [M_PORTS*4-1:0] m_axi_arregion, + output wire [M_PORTS*USER_WIDTH-1:0] m_axi_aruser, + output wire [M_PORTS*ADDR_WIDTH-1:0] m_axi_araddr, + output wire [M_PORTS*3-1:0] m_axi_arprot, + output wire [M_PORTS*2-1:0] m_axi_arlock, + input wire [M_PORTS-1:0] m_axi_arready, + input wire [M_PORTS*ID_WIDTH-1:0] m_axi_rid, + input wire [M_PORTS*DATA_WIDTH-1:0] m_axi_rdata, + input wire [M_PORTS*2-1:0] m_axi_rresp, + input wire [M_PORTS-1:0] m_axi_rvalid, + input wire [M_PORTS-1:0] m_axi_rlast, + input wire [M_PORTS*USER_WIDTH-1:0] m_axi_ruser, + output wire [M_PORTS-1:0] m_axi_rready +); +`include "axi_interconnect.vh" +parameter S_PORTS_WIDTH = clog2(S_PORTS); +parameter M_PORTS_WIDTH = clog2(M_PORTS); +parameter M_BASE_ADDR_INT = M_BASE_ADDR ? M_BASE_ADDR : calcBaseAddrs(0); +parameter IDLE = 0, + PORT_GRANT = 1, + ADDR_DECODE = 2, + WR_FORWARD = 3, + WR_RESPONSE = 4, + RD_REQUEST = 5, + RD_RETURN = 6, + DRP_REQUEST = 7, + DRP_WAIT = 8, + END_WAIT = 9; +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +h798DEoPCCw6eC93sfxnz8ZJ5DmYibE3rGjjhE+YK5a3RIfjyfpuQmm+Qi6hiWsS +h21ZC3p98i4VCoRgq9ttjdMjEUVk6R1INC59AvJ35jeq6cjGdiMiIPwnlnHEAIqa +kQUAn5DZG6XDT0Q74iMGbdiR7Uqpt242DlxQT/RPahxewbF7bTMwF22aKiwUymVQ +WL77YlV9D3RHdY6gVwH+r4vNibfPRFoNglrFWdWkXgAM3QCILfTmCmNOrDP+tU67 +Sp1AnVUQDUfoMreLqPv9PxJK3wnCugVdw08bgxzbxycLpfzcQbzXtVTNLzpE9m/C +m4DQ47zqQmz4Zj4f/JVRfg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 25024 ) +`pragma protect data_block +YwM6jjCriz1M+FDJXSN2LeXck/ZAaH8JuIXMxJq2uSTQniMJPx1HUHKK0h6e+ADy +nOpy4Npr3RCHDdf751Af8iOf0C8dZcMs3a1GYK43f9lfLJ4Am1BOEiaKGIMLoNoP +3/ezGIbxr0ugu0861FRZvKAC9ByuIi2/kp4W3oQ7m7vZVqigNx/Z+Lw30JD+Tdof +nd9fbmhRCCJW3RaeEuI7sGkqxIGkRp9Ypju2a3+UmaW00MJNt8bCRmHGNKebapN2 +4iVEq1eRDz+FLHYVirgJupc+ujLQGmDcYUtfEv75/zbfhbnSF2Tzy4KWhMa/eqDt +JdYj2al2m3yH2PEUGOEg/lmK4ufxcT7uAskU+0OCNTLvSk3xxzqGDoUTwqKX5Ln0 +JIDW8HetHVJZFTLmXuKbPHS6O+HyLuJ7Zxymn+Fjne6idZqUL/nzh8AJkD5MeD46 +devUK2qciMx2VyWCOynEzLIDQuLhf4HjJnSRV9ZjArs+ihs/aN5AaI98MfMmwjWS +KFKPxBp0tjRn2JUO0XR81ueXaQ9p/dLA1gbRJm7u3ADC4VBKoZXEWjeKWQe3/n1Q +mbN+x2KwcKG8XtTQY0BO2biWZo3QqJH1PH6ghVrcaM0KAEj3eBYyVZNVRgEB9Zrw +RRFhPPGhGTYcaC0TDtPS2EToJT5P23Ql13VFSHg3/OojCJpJcY0k1dryK52hqUyY +DiWhs5ZXPNHotTcdv5rTTZ/yPkW4CMHMJsuqWMpMzkQfRWTLiLfPZCs059UxzGNu +ZxxVrqi2QvhQEvWGbqnY4nFNZv20Zg/gjBNxOZGImfOZ0Y9dhYEcbRA76Ygnpw5G +vGVtZG8zdpoUvm5EKdyPpCtMRRphbRSJOtfS4HuKv/+VOGCmZaOiM6orgILxnDj4 +cJZcAvsaKNPUkQBZl1SdTWoZQ/ju+qYxeH5r6aZLkNlAg8wxRWRLF60dr2HZjer8 +evhWNI1sXa3DYfXmrbwUlrRlNScBbch6nExhqbPvdWtVWN8FLcA2450xz3EqLC0v +feI7zE+5RTFKHrFinkDsvLSssGe1F2TqSwgHq8wjB3wBMKoGATMrdcoUI2WYRzps +sP8fhHOW81v0p8J6cL8JSFTmnDD1QjgxYc0UHXrK5RNr2TSldF9Ou5BBhkAPViVR +FIKcFlaVe+RGEazKhck1nsf1xUSGwWx23yq4cIsyQCPXWKRDTKXWeM8FkbOfsB4h +jOLT4/44scAugcFmRTk0QLiz01X/qCE92lXw1/DWYkPkpJjEtgNyZ5sRAiPCoGx5 +pjLXzx8g4oS8KrEfdGhIfSMf/ac/7nnoML7Lw4+QkXMvIwOHLreX7f2b6xoi6H6p ++t5vR0AOmFGBcGCE3exjIyI46ho1XyuDGrY+67zNn1N9b1Ub6o/nuaUwVLWk1eHm +f0M2FtnsAKYziyMLe1virFt1be8XoHB+ZhDjV03xpiT41vjH/O+V83gcInEzBy2W +QyCLM+ma98sPP7eg1+vROdya3CBGdPYImWLsfomVwFR5DUkqPBV/Yvxtux7DejoT +41Z1oqJ+rHnSnzlQ0XxPrcfPu4tfNYWle9kqizkAVtjZSa3uG1S8mSnhcizugnge +MgqTyqZyJP6rQjbTxAOQV8iOpQ7KkHcFDdsN6CNIt3qOAPaWUIruqhvdNTdr+MgM +ttM3ciN7ddW4EFINq4hVaZiwOPsUyx7kFABzxWCy/lm9iu97+ujhpDbdgDgl3N6G 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+Yg3bb+MZBoJSx1bubJg+o5E3BkL40S/fAkj6c2uWPgCdl3r5BRCx1ucpBt0L7X2D +/l6T3GJAxPypfc4TzBOOQqOCDujGOV5ODMj1vMgngzz7owxpOiGCTjiHCvy49kqE +IqgNCgdBxm6ouv9UyqJKrMQrLiyUG1ZZknZxjWnvv9ISJ4AjuhkypSbY3v+ngPOK +hwivM16i4BPI2dfzEb0PIb7g2Y9jcOzteqjm5n3oypdyR+zpDT+hvqA3BPi25W0B +JPYxtbm4M1TPfEmgrkNbchX/D0U91Stwyv+qf4JqYYdaQXNdd449kc+NEnwTYsrq +imyaZXGkE+l6ED8peKJutbb1ccZHoZh+/itLOVb5jLrfCXLeDI2LUxittjCamfW5 +lt+O642jvKoWfacQoGHaq/AIPlwNqftmR49MtYZZMsDzfB+T4+2WoI60nL+OmMcu +GL3mI8jrE/W3gbgmLujiGP/0Ma1zJd1rqZufxTlCa61cMnpkieSrmehFshtQ2ONG +nsHziIMfVHv/ubGOxOvWWA6ESxhyq4Bb7YE6fnyfk4YwwpVD/QDv/+P9eOklQa1I +cQRQmNo/vwzwS1nfA0mc3wtdW3m0qIjV/PaogQuODlY1TLbydqB4H+lhbwXvhHZ5 +60YjPDLerHojlSKgOWBz35r7fbZqJOCKnTC6LE/2BzjB7GewxnTJsjWRJmkLaHmF +i6BmBm4m78KsKEJZgToH/UJ++X5fhUQ+SG+hz+h0i7xxyC/cnU/PigQ3vZ/SUkN6 +7zg/hdWRcuGmho0aVNUfw1w5Wdd1RwXdUYbYfG8RWeYIqQ6OWqhjLOK/B+Yy3r/n +JNwvRqtuUZFoPNH2FzMv2pdxZm5CvcOuJOMBcvVpgxktn57SwIk367E1srFwQw/j +VhTvV5MqNhAZpXfPbkZ0rQ== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +RwZLaWoAKLBm11tcUo3zg7WK2hPcNJvetUS0HcngH1N+uqVkxItkonJwS2nHozet +PZ4e0pcL7oMHU+YSSKFGF0HZtDLJ6ggz9Tjk65W4OruIfJxIuyYdw9nbusKhaJTz +khXz5VPO6s2gfnVif+az5zjoe7kudgxlxU7jmvaX9sbur5cFMS2KnJogDMLJcl1s +ZlLL+9F5h5+8PKCF6eoiFm6TtkD7MrBiDjMDu9eLqZ5t8VgWYRMKduwEQ9J2M3t/ +JcbjL7GG+1h3LkL6WEKxF8zVIpKiu3k7UC98wKI8mhEpZ8bChW07nVCr4PHLn2IX +BU9Qy5kOLqe8sKbl6LYs7g== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1312 ) +`pragma protect data_block +p0bIW99zYvQA4u0XRWnQ90s6MugNpXe6l31pFNyBhuxQU67mS/BBRtYtc25nySM/ +yHwfDVEt2eeSh2xZ2Kv1d8VWucKTg8lXrK+ooXsXcYiy61IB12mnjuKPa/FUxFS4 +JM2AiESAcF0ks9YGnHz5atWTSPAnEYKTqIrZDoYqJkbgClLiRdrZY+N2hC5jdZeW +cR1EkHw0PZqw6S2eCHL5hUi6ryPKMkre1oH3Xdag2DJT8qQxbuNqhhrm/L+8L8lX +f5F3asZ05yCB1pnJRqVPESYDajoN8u1lWD18RYsWX60ld2PcwCxsHkPOyoBvAV1u +PgCYq2l6s5FitBJR9RvIIWQXgYcJnkvvctXAE4sHkA/8YmzJKAUlmADFxObHh7nH +B9Tr9F5MMMItWtOlRVOB7r7GpKZ4CIu9H0pG8rHeitdTJzb//0sRPwO4Ifpq00gF +PYpm2+uw1qrcWOBG9wrbOEUMiFlt1c1y6CM7W0HiQg/FK+4Y4JiB7uaAlzUejTOI +zOL6no+QbQSWHIEVAYNpQGNcTG+AuFlhiSI5DitSGvW5yCLRLs7Fv5AnqLM6z1Qg +nRTXEKDaR/AFlAFB16izDRH4FYwpXtH01JTfdxvrFbPDjE2B07qlVwewnCVApXy1 +GNPPzEat9SO3vQ9t7PCKFzQV6OGGAn/dyMwguU6EDW8mcNxemcFiHUdiSfhhZpeH +IcnqAMISo7J5oznEHRV6eZ2t27p8fCR6kY+/9tdw+mhgfM47E9D+jOa2LZcvRNK0 +IxKxNWtgUL0KlYtkFTGEhG+p36IePpoZOlbFukyAkrvx2uvJdjDKNhR7fljgKZp9 +ntpSnYfXJhwQrP8yTvoXUhnLpaxBTrh8cyLUFVm+2UtqRrz/+WA/Du8u19N0NmoU +4Z65V0tXF/tW4DpeElKcg5Z9g3Srjon+LpuobgvaptlZ3rG7pXXklUAdxNfJ+4mu +g8S64RYvfLamt1za0XyFbePfAbEPHUNKbKIqzGRB92kxJ6jYjgC9RQHp35SL3T55 +2DhArYHiRs4HAieVOggerJ2mFKRe1jgXpNH28cIvReVtjhPSR0h2/N1kktJoFN9j +pAwsBXcE20H2DgeDq7MOl5klQOQIZqq2NOi/TtiDykzXOq9c52KT5YQDUiFYqQvD +H29baw+SyQUZTso78q8DVb5S1dB3XyHStAKgoGq93+Wz/B1RLpKYack4xd4rdS5s +pwx6XbBMdp7aDqOyz2KgKWf+dspEnt1aZSkLPUfnK1QqEuwBFSip0++f8lsYJwt6 +h2RR9rfNZmd8nt+mXhbGkKeiOagijsA/5zVB+4MgI0KR9sujHhdd3ikiYUTRDpcb +AA7w3mFn6w2oiAcHGimR/cBGrmo7m6L0USsPGqFYBLIQfdAn5dEBlb2BCoA5VFZj +jXKJF/jua7Y+DrPzh66goMGjpF9lBpoEP1rWQA/7bSpIp6mTsXcqppKrJq4X3UzK +fnxoXMOzyXak8Q0RLDFj9NSgAWzr4VmwVpFWnocoXpsQlisCkXdTJvGnor8LLZr9 +sDZmzgcSix39SaRGPrUkPl4jLdocSaImMFvFf75Ln2LkiFK2PwLHbdxu5OHmQoCw +7wBcsGkL2gXd3tYL2ns54yYSqMYHrxBbag+ndd5VaJnjZK34JNDCSh65qkKE7y7v +Behj6SqW7qWtdmufzd16RndX/9C4+tnd6CZRltVVSxqHORQEFpJfBX3qZLp11vTQ +Pib5SMqM0nVbJDVpqDeCAA== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +V7fazAcYfn/upNWI2MrDSQamEge7Y8sqGyEbHWTTDvIkXpdIuRisL8LJjvy83vue +ZgYLruqRxsDQR/Wu7PMlj65sb/NkxpSPTHfwdQcOEP3MsixExszjuA1HqHtg+aNQ +uFOiuMhxVPj6PMHq/Hqrqa85QcEVSbWPuLxSaFzY0ndkgyErZck8cU+0bbs6pFmr +tNIeglsOu6Am3uxBT62KHdsx5/dbyBFUXzyoeMcVqVN/dSwFJEWKXykd+OnIo8cg +TAWc+EOAJ6ExmKO/aLU8Un5EpThP6h/F+4FSrXQ8+zAfJHLLmWelIILCIn9r270y +7CUxtRRDMVrzxeZaHx87Jw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1200 ) +`pragma protect data_block +0H3ui++saKA3Qim7nBCnYyJXuXUUae6AJ4LYf9uQIt7dDyl6C5Q3z+wohgm7l6P/ +puE1YIk57wYrhZfaxaOZbQEeQcTD5dhNWYlNGXkVD3n3ordUMQqbpossg6k8GBbL +hcT5AJLRLWp1fmFYHU/sChpXsLIvsw4ylUF+kPCiM/E2Qrxqk+h6yKLdH/qUhhl9 +SFhgQaFfWNjj6ajZXfTXAeH01G9YVoXQTrTURK7LCmy8Exrca33pvD2n8qRjNHVC +SMvlBAlMyB9GhVbgRH5g1J3eexKd42EKVG1OYkkLmaw/2mYb6XQBYWGV+JPCs/lf +iK57mI1tmXdY1dZroI+VNNMZ2ERNO1xPtSdY84zkg7t8kqVOzrKucAQtG6cbtv1M +zOk4T1+sHwfHB5B0MAQxfUujCPIx48x0ucEJPziWVe4xGSV7Y/CdKWRJKyu1t9Fd +RrGJ90FB8JcoftYS17u1PRbcM0J+K9rYOujMCI2wOiGLeakIZUzeUlYgu3AhwJ+p +rFTdyQbZfeR1hJMbKn0z9kiVI7O//BPB79Ovy0ckHGOWpsznVPMik4mcftaUGBo/ +SKRhNP5RZ7ADTWwNcGVQ50K6Uk/FWRH/LjkzUDgrlN+BL9CVLgTUzw4n7TXZLYO1 +UUMwg1Abr+r4azUlV2lllRgjlWSPEmPeuWdkmDLE1kzi81/3MG9dkGcEzpCjQn1g +wlq08l1m/9D6ssj9X+L9zWestpPbK8KKA36LM44lR7JM48DHZp/GFFbwyCyfem5J +Yk9dQrVMSLDeQfsKUdIRfzsLFIcVo9j9nAjaOh5icY9Ju14nqLljzJxMSLXwpRpN +pHlAUZkLKZ81BR2lNUcueWoYr1mNO5wt/8ZXKNAe4baXyx5pQlkEoPhDAu/MmaoV +IQmRsNZAJw70Y6wneeDDkHad2vIHrOElxrM5Lnlhdq1qO4G2CjQ03nmLodMZn/cu +JhstoiAqinvEClsBGQAEn59Mk5wMvMergihuxdt6qTvztnpZTBcB2JqJyHkCY2xR +XYx3muggMb4QtLLic31NtDmfG8SMy5jpSvmNNdDUrcWI5vOaLo+t2/mVb5p6U/Z8 +WsFN6j8TpdcSc+yFYrWVYf/mabwUsQccMAaYaGcHwQTAXW/zRUxCfgK2BtB9AUG3 +Kwe4fuqZPo1NDmSSdATNh7Ls+wMag23tKAtoVCW+TQ3lLpto8vUWhWKQTH1PsQRx ++KWcJaJK96bA+80M/q4HUzR+yC6IUVQ9VRvWhgG0ygZTLKmQmJ/DKIzlw1lxCkA3 +JF0FRPBrpi2n+UOIXtU6FUAnUoSUl8Eeuwpycld1aaAI++CWVpk0pdWCRD85nBNb +vAQ7vQzvYravu3V0bHTVB/w+yyy05bUUjf1aVui34DyQ1QLLkq3XQF2v9st57JGH +egpS3SZqHPJ0AZAJJvkOXoxVRMHu48i9M6Wx9Qjtrh9EJee4xLdxqYrF04J9h9ck +AvKxciqIeVCjtaleTRBLEWnwUKa6wADHB0WNBFNEidDe8gAcwWkZyKkh/VaUiupU +5Cv90Shsjvie3xvNr1QXSLjEkUzHLYrvPv6IGVvcwtPvJNwajthWm4H1o8D7rdfK +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +idlb0ipwgIc0hiUfW9lCBvIc27j+O1T55dJ3BL9eUyC3AmELfvx2LyGUfXvUfYTf +8sHVL37lgxYwkxIH4ZSSZQ1GK2zLKlNHYUEmXZIR/WoNIg7U3rYo+/OAX5LDNWz3 +I3htHfdktV9gYc7iVdI9VNrqBa0Gg55NmIOrO+wM2ME4dVbdMJVDfW+oOu9rTeme +KOonn0oR5/zNCWcqkhf2z6BLLm49S0wwKQJc9Tn8j8aAVVAS5PR4HM/UAt+Pm5Qw +qUaeukXs5OImR86WKmCfOXrROtxYmBZ//zwyzxGdjene5Dzf1Lue74V7vg9Yy8Es +kofIx1Iiwvl5uhKqK0ZywQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1984 ) +`pragma protect data_block +W5IcpMWeZEmcNKazNSseGe/SkDOlgncKe6xygU4WozXer89CE7H74/gQ3yQQ4LCo +YC8yuYKcjPKApcXYJYuOgpsab8uIQGftqOoDnHHE/TFo5sK5ih7BYybPWYaaZIfN +U42fSf3IGBc/VJJMqP+4YGf2p7Dp5YE+Wy7VkeYE9mZmjDlwds+pPKcijo5Rgpy4 +aylibzsZkO5+oK4Olfl1/eP949zocOLdn828ECpQrR+1rd90XEST7JJU34+5nQR0 +iYx3aHjOcfjFetECQ73ZAYN9xqbs+aqjzeLBFzT66wgcNopyNE3rPObBjFm/FlMY +NJuj22N2AvkTuG1FfuBr5E5/i9RjA+BTgZPyYvLaoLqprEm8CWiFhmozo0TuSThV +oxsGKZXYjCpb3zoOzL++RaNuogj+rTHHnB4sjSyjcQXyW9FHyxQ9ou3pB0HSnVv9 +mmlv1FlvuwmXWRcsAbk9MN5Bu1XDI5gL7Ipu6jQGD76fGfDk5YZNwHHplmC9Hxoo +14fkoUi/IGM4yaR9gsmZ4/V39IhpdKS0TO3LMyFgBX1m9J69gD3agPTxpHvmjGBF +iBeClMI2X+GOMbRoQ7MTuRI/wsqqHaKZFnqG2JrdQ5jH4KCWRqJG4uuYi7J1i9bs +xY16r9KjF+6f0MFsxcK3KibLp7s5dEDpsw2XIf00NhedOsMfk9w9HgMaBIhHDYko +R9z9VCyALLVSnoVdMfGtgRCz9L0ZTjxm9XhyXpCWP2dQQ5YHyD+cFxCRM2u+sbOa +XCcYDb1UlKsoUKPrA6upaDj3TlNdAdCre4HET9kn0PDrdWIRz9my1VexCrOwQ/4v +/AGqqMzOkN1K3GiLhBjp7mc32jSK9Xwlf04J/O25O257w8YWwGgCDGh0YcXBAP9P +dRzMnjs3Uk7xrEq2VCihUs7MsFR2dplgxIVe/f4i6d9mLLp/cVw1tY4mO7GQJJL+ +NJxQNxDTfheXoNHxcaGlEvOWL2b3J/OVNbr/wJPsNPO3JZmZWUpP8CsvLDnb13uy +iNwDj4gZpR9546m0yEFGqGJTEKCKJEKdLC6E6Gdr4yH+RNK3GQAtivmlYR1RQi50 +PKxXgfvCk7ALJB0/AJ3VKJanssU7Hy6k/ihsWnMeUmW60hSGVcI7H4Dc2LD/zqWt +hTHS+BRPB55N1E551ExGrUEM85MWlZDv876GiCWMXvhRqs9srCM9ecVIL7dQAs33 +eEmvppS+tTUufZM9oZTu42ShCYqUVMSqeUy/xzqnGhbXu4Q7GBe6tQ22Qrny4jVx +0oqenju9rIFJylCiiAE55m3dRqcpZ/BW8zJT9E5xqywiyk2hKjD3cBa8sFQk4o0L +Q8sbZOGGnwkBiq09qANjvGvlkm1v9FDgC5FRhvdDYVbDc5kwRgkXw2C5yGo8ATdo +PBCMK39Rit7ogQUspBMSRycdQEknqdzSNQE/bSr+sFg7NtFexRxi9+4sFCfzdOdH ++cDNk2jJ3o5Pt3cxiWI+66BF+lGKauggjRt6wxcGgXxd1mAGo0E3ZAxv0Yzqu5pw +DiX9Ub+lowoE+P03j9ORmbT4fPh1vCZqOweT5yq4msNhPgF5yTiyJxa1f/nW/871 +YIJppXKMqggxL4xvTBLMFRRq5hyIaGUvjNRoml49I2/e1TeW/m4txLIR28P5W3g5 +XlPYaCFV3Q6BFDTb6hzglWO0MdX0htcU794klHzIjr9es0VaPjbGbgJwq13D3F/0 +Wq8j0HPafBZpvWLerjIfQntl7kZCuc2V2cANOqkVpbyXIWRCbZ7tsWyxylvndsWT +6E4JutWqIlD9ScB+1qz5I5aMLznRt/6iauVApWrYxEUIHKCY2O4d0GeF6lI4gTr2 +Ff4x1GYqVXjRfQ14+0Q/UVGYnaif0luhvPGRrZVCGBn5bYgic6aYLLVr39G/Bw5V +zhXtqIf1ISZtmmzRBJTn+QdkE1Rw+SrJcH8BdWjLo5Q4VpHvSX4wlw9lt2zjHr1g +Gw3jvpOsK0lFtMbrT1TOkk5TIAVkSEti7VAGeaycfKxXTfXsQcEdeTjsx/z+7E4s +5LmeTE6BUDvniF9TMGxAh8UNoorK/9h7raa/mc6UP1Ap0sVsn6FAnB5a3hp8AcfO +YyUI/+rE3uvbY7eV0TjnPlB2a4bKmip2sUnzCtjxk38a70NoSwvSF5fHD/gmb2Kt +In3bRGhQ51Ou8wyYtPtzpRKl9lfBj579kv2ljgctkPOCPxJ0qOO5U7vH9UVhyH4V +8Q6lGkKpbY+oJSEyXkd22SgAuuLMTQzychAeCZrzurKRTCJEkybeqpnHeMDZF144 +yT/sjynj+V1VANU1CW6cQPulbZj2svXukJupVa/ZhMF/Y2G5v2JIVKMZvprQfUMy +xrTAArhmrRjDrUfSaRBsr2icFO6IfrS7qjcKaFF4e7O/jDKLppha19sW6TL25Rzm +Ahjf7mc7/2mJeA/0ayik5t4ZP/xwgvgOII8quhw7Vrm37O9aT6wkCL/5JIKv6tpA +nWE/0iwIWwBWPYliaqFvsEcfMuowM9WrIG4B7EkD5jyS0Lwo/CezIdysfC7/rgBy +x3ZrJCp51uVHU3kT5JLDk0pb0CBXd7O/pLb7bpfJmQZYLmzXM7a6D32ZvJzsMxDq +M6eR/VTYArPQbA4OoPqXhQ== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +kjevziVpR4HNp6ABOs1UfEhnb+dX0JPweI6S3+LX30C9LF3xx7Xd/zMszyIOAsff +hodfZOinnjjXzBncB8lZ/iwEBQcN9AOUuJkxqHw0xEX9lKugu7WOxROcH+yiXxDJ +yy9yDzS1F865ocB3xO9FWkMnml1XZRqox2FTUI5GMVk0MxMQPCoaWPmG40cuqt8H +oNSQWIvbZ0bwp2zXvC4BQlkXD2oWWu6JxxVIVspZ7XmHHSfSB+gK8bmQIk2JZPQd +nB3A0s+SLUanWE/u+Muh6A5t3kkuvJ5Fy1rRHEwle6WO6L5S2arPlksoYEp7hfDo +eW9+LO7WnZdnt0b3dQw5Mw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1104 ) +`pragma protect data_block +LX5Dxt8B2z9u2haDN6HkGNj1Nxa2zeRWxlMLLnbgcY2+2ueKKYern04T7l3DicpU +GAgNW7GQnUadJWzOBc5yfD2Z7DyC1zg+m258ATNxkXP9Ag8Pfl4MhmlpUpmkc23o +YSNVfWttcQespNGB+Kj9g+/b/Ltzb/Pp1dgaxi5NIlG7FsWis/B/nSO/Vd0xLa8l +gdvKVbsSlGSB1tT5WBnrVIsaLuvPuUdgdvXFHzLrEscW/eC28+m22DdewgK9tHYj +l4yaTKwJ+7R2jtaFZr8jMmcRudxesBNt1kTJeA9U1nitqtdHVp23JcdwKc05jnrW +tx2+meDVE/d5vcxlhTdpO8sz2YOw2Z0bAN+ieJFfUDfTuopqPBMc5GBfsrD40ELk +H3q+hGhS+dIM3hrqhKDRW3tPFmcE5szwJbmOAxflm1SvQmlOnQVePLGdCuOZUUiI +tz++pZ5FH+uAdkA40yZWh5MnKo5IcfFxWM2Jsum3JZvmVMjnI7N1x8f70kUe3UgZ +KEcI12J/dpNLgdFOl+74xfjhKGoKm/BgN6Eb01T1RtdX6u5xQtgGCuv62jDE/Yt3 +eJjRnF/x+Ay39zeCLP9UQvypybEe14bN7gfHfWoAQe9HIG87Fm2nKjAzASr6QFRV +DL1jo931/n1Lv9oZuWMfaF7ZCTxH6A9fBYglk+u3TWHi+TkymppU4hV3XjEHw3B7 +wrSwISGJRMUoCJ0wh/W9Iqj3EDcLmFUIHicsgmfrUkpdpcDqQYIKmCedP/+uQ37E +hBOgLdq2ET/+T377dhiMAvLWIMnT6X9iEzqdVEMfkuPgbBZetAoTzb7IozmdA14+ +3PCjcT9XV5Hxvw1vyLKchF3xGFPaDFJgGJtzSIMeyTd9yK/++OeT1TQ0HFPfjjqB +LI0xhfRlEGqOj1YzmolIUWRdGapI6Ywt79vK6KTeqg9K4jHGe3R1t2SJUnNELlNy +Ju1RcPdn+2rNasE/ecNNfcArJ3ReZiWkO6Urua3WtmUiTzAVXd6UD4GUf3QUw0J5 +AefzuP3tFE5IfHRFmTZWTm7Y/JLAztWyBuag+6TRZLBlyPJDyNieFGTz4SEyTkAc +CyJ51RLW7x5j/8mo5k2anYrG7q1YYjOUQHyaLPL/RwYcBBJS38HGPAl44N6KsB9m +PGaS88rOnKmcVDest/nmsVi5/wR7C0xrMTpo2i2v7wOVW53j3SANDy4UhRYGQ75m +9+CZTXcObV1oXJW0me53hFtEJ+qHc7eFGKyCVwTNanP47XH3aJey3ulpiTKXp9iD +rurNoDvwMo1/Wv8495pWfGIS50V6wFEVgh2p6gt3S7meUf9sdMYrrKeQAKEna1ne +Rf8O+xm0FaLvKNBVaPV3ISnRU2qTxpWhaUb3vTQN4TODsKco29kkHPqYRTREwU5p +4ExJ23nclyx/By+ugg0UnN5jZ/DGDMK6ZJ2abjL+WrT31jFUNXgt+rmb/8ViJNIm +`pragma protect end_protected + +//pragma protect end + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Ti375C529_devkit/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_define.vh b/Ti375C529_devkit/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_define.vh new file mode 100644 index 0000000..9a37056 --- /dev/null +++ b/Ti375C529_devkit/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_define.vh @@ -0,0 +1,53 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2026.1.132 +// IP Version: 5.6 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2026 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam ARB_MODE = "ROUND_ROBIN_1"; +localparam S_PORTS = 1; +localparam DATA_WIDTH = 32; +localparam ADDR_WIDTH = 32; +localparam M_PORTS = 3; +localparam ID_WIDTH = 8; +localparam USER_WIDTH = 3; +localparam PROTOCOL = "AXI4"; diff --git a/Ti375C529_devkit/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_tmpl.v b/Ti375C529_devkit/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_tmpl.v new file mode 100644 index 0000000..2917172 --- /dev/null +++ b/Ti375C529_devkit/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_tmpl.v @@ -0,0 +1,137 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2026.1.132 +// IP Version: 5.6 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2026 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +gAXIS_1to3_switch u_gAXIS_1to3_switch +( + .rst_n ( rst_n ), + .clk ( clk ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awlock ( s_axi_awlock ), + .s_axi_awready ( s_axi_awready ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arlock ( s_axi_arlock ), + .s_axi_arready ( s_axi_arready ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_wlast ( s_axi_wlast ), + .s_axi_wid ( s_axi_wid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_rready ( s_axi_rready ), + .s_axi_bid ( s_axi_bid ), + .s_axi_rid ( s_axi_rid ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rlast ( s_axi_rlast ), + .s_axi_wstrb ( s_axi_wstrb ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awready ( m_axi_awready ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arready ( m_axi_arready ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_bready ( m_axi_bready ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_rready ( m_axi_rready ), + .m_axi_bid ( m_axi_bid ), + .m_axi_rid ( m_axi_rid ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_rdata ( m_axi_rdata ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_wready ( m_axi_wready ), + .s_axi_wready ( s_axi_wready ), + .s_axi_awprot ( s_axi_awprot ), + .s_axi_awcache ( s_axi_awcache ), + .s_axi_awqos ( s_axi_awqos ), + .s_axi_awuser ( s_axi_awuser ), + .s_axi_arqos ( s_axi_arqos ), + .s_axi_arcache ( s_axi_arcache ), + .m_axi_awprot ( m_axi_awprot ), + .s_axi_arid ( s_axi_arid ), + .s_axi_arsize ( s_axi_arsize ), + .s_axi_arlen ( s_axi_arlen ), + .s_axi_arburst ( s_axi_arburst ), + .s_axi_arprot ( s_axi_arprot ), + .s_axi_awid ( s_axi_awid ), + .s_axi_awburst ( s_axi_awburst ), + .s_axi_awlen ( s_axi_awlen ), + .s_axi_awsize ( s_axi_awsize ), + .m_axi_awid ( m_axi_awid ), + .m_axi_awburst ( m_axi_awburst ), + .m_axi_awlen ( m_axi_awlen ), + .m_axi_awsize ( m_axi_awsize ), + .m_axi_awcache ( m_axi_awcache ), + .m_axi_awqos ( m_axi_awqos ), + .m_axi_awuser ( m_axi_awuser ), + .m_axi_arprot ( m_axi_arprot ), + .m_axi_arburst ( m_axi_arburst ), + .m_axi_arlen ( m_axi_arlen ), + .m_axi_arsize ( m_axi_arsize ), + .m_axi_arcache ( m_axi_arcache ), + .m_axi_arqos ( m_axi_arqos ), + .m_axi_aruser ( m_axi_aruser ), + .m_axi_awregion ( m_axi_awregion ), + .m_axi_arregion ( m_axi_arregion ), + .m_axi_arid ( m_axi_arid ), + .m_axi_wuser ( m_axi_wuser ), + .m_axi_ruser ( m_axi_ruser ), + .m_axi_buser ( m_axi_buser ), + .s_axi_aruser ( s_axi_aruser ), + .s_axi_wuser ( s_axi_wuser ), + .s_axi_buser ( s_axi_buser ), + .s_axi_ruser ( s_axi_ruser ) +); diff --git a/Ti375C529_devkit/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_tmpl.vhd b/Ti375C529_devkit/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_tmpl.vhd new file mode 100644 index 0000000..e5cbfdb --- /dev/null +++ b/Ti375C529_devkit/ip/gAXIS_1to3_switch/gAXIS_1to3_switch_tmpl.vhd @@ -0,0 +1,229 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2026 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +component gAXIS_1to3_switch is +port ( + rst_n : in std_logic; + clk : in std_logic; + s_axi_awvalid : in std_logic_vector(0 to 0); + s_axi_awaddr : in std_logic_vector(31 downto 0); + s_axi_awlock : in std_logic_vector(1 downto 0); + s_axi_awready : out std_logic_vector(0 to 0); + s_axi_arvalid : in std_logic_vector(0 to 0); + s_axi_araddr : in std_logic_vector(31 downto 0); + s_axi_arlock : in std_logic_vector(1 downto 0); + s_axi_arready : out std_logic_vector(0 to 0); + s_axi_wvalid : in std_logic_vector(0 to 0); + s_axi_wlast : in std_logic_vector(0 to 0); + s_axi_wid : in std_logic_vector(7 downto 0); + s_axi_bready : in std_logic_vector(0 to 0); + s_axi_bresp : out std_logic_vector(1 downto 0); + s_axi_rready : in std_logic_vector(0 to 0); + s_axi_bid : out std_logic_vector(7 downto 0); + s_axi_rid : out std_logic_vector(7 downto 0); + s_axi_wdata : in std_logic_vector(31 downto 0); + s_axi_rdata : out std_logic_vector(31 downto 0); + s_axi_rresp : out std_logic_vector(1 downto 0); + s_axi_bvalid : out std_logic_vector(0 to 0); + s_axi_rvalid : out std_logic_vector(0 to 0); + s_axi_rlast : out std_logic_vector(0 to 0); + s_axi_wstrb : in std_logic_vector(3 downto 0); + m_axi_awvalid : out std_logic_vector(2 downto 0); + m_axi_awaddr : out std_logic_vector(95 downto 0); + m_axi_awlock : out std_logic_vector(5 downto 0); + m_axi_awready : in std_logic_vector(2 downto 0); + m_axi_arvalid : out std_logic_vector(2 downto 0); + m_axi_araddr : out std_logic_vector(95 downto 0); + m_axi_arlock : out std_logic_vector(5 downto 0); + m_axi_arready : in std_logic_vector(2 downto 0); + m_axi_wvalid : out std_logic_vector(2 downto 0); + m_axi_wlast : out std_logic_vector(2 downto 0); + m_axi_bready : out std_logic_vector(2 downto 0); + m_axi_bresp : in std_logic_vector(5 downto 0); + m_axi_rready : out std_logic_vector(2 downto 0); + m_axi_bid : in std_logic_vector(23 downto 0); + m_axi_rid : in std_logic_vector(23 downto 0); + m_axi_wdata : out std_logic_vector(95 downto 0); + m_axi_rdata : in std_logic_vector(95 downto 0); + m_axi_rresp : in std_logic_vector(5 downto 0); + m_axi_bvalid : in std_logic_vector(2 downto 0); + m_axi_rvalid : in std_logic_vector(2 downto 0); + m_axi_rlast : in std_logic_vector(2 downto 0); + m_axi_wstrb : out std_logic_vector(11 downto 0); + m_axi_wready : in std_logic_vector(2 downto 0); + s_axi_wready : out std_logic_vector(0 to 0); + s_axi_awprot : in std_logic_vector(2 downto 0); + s_axi_awcache : in std_logic_vector(3 downto 0); + s_axi_awqos : in std_logic_vector(3 downto 0); + s_axi_awuser : in std_logic_vector(2 downto 0); + s_axi_arqos : in std_logic_vector(3 downto 0); + s_axi_arcache : in std_logic_vector(3 downto 0); + m_axi_awprot : out std_logic_vector(8 downto 0); + s_axi_arid : in std_logic_vector(7 downto 0); + s_axi_arsize : in std_logic_vector(2 downto 0); + s_axi_arlen : in std_logic_vector(7 downto 0); + s_axi_arburst : in std_logic_vector(1 downto 0); + s_axi_arprot : in std_logic_vector(2 downto 0); + s_axi_awid : in std_logic_vector(7 downto 0); + s_axi_awburst : in std_logic_vector(1 downto 0); + s_axi_awlen : in std_logic_vector(7 downto 0); + s_axi_awsize : in std_logic_vector(2 downto 0); + m_axi_awid : out std_logic_vector(23 downto 0); + m_axi_awburst : out std_logic_vector(5 downto 0); + m_axi_awlen : out std_logic_vector(23 downto 0); + m_axi_awsize : out std_logic_vector(8 downto 0); + m_axi_awcache : out std_logic_vector(11 downto 0); + m_axi_awqos : out std_logic_vector(11 downto 0); + m_axi_awuser : out std_logic_vector(8 downto 0); + m_axi_arprot : out std_logic_vector(8 downto 0); + m_axi_arburst : out std_logic_vector(5 downto 0); + m_axi_arlen : out std_logic_vector(23 downto 0); + m_axi_arsize : out std_logic_vector(8 downto 0); + m_axi_arcache : out std_logic_vector(11 downto 0); + m_axi_arqos : out std_logic_vector(11 downto 0); + m_axi_aruser : out std_logic_vector(8 downto 0); + m_axi_awregion : out std_logic_vector(11 downto 0); + m_axi_arregion : out std_logic_vector(11 downto 0); + m_axi_arid : out std_logic_vector(23 downto 0); + m_axi_wuser : out std_logic_vector(8 downto 0); + m_axi_ruser : in std_logic_vector(8 downto 0); + m_axi_buser : in std_logic_vector(8 downto 0); + s_axi_aruser : in std_logic_vector(2 downto 0); + s_axi_wuser : in std_logic_vector(2 downto 0); + s_axi_buser : out std_logic_vector(2 downto 0); + s_axi_ruser : out std_logic_vector(2 downto 0) +); +end component gAXIS_1to3_switch; + +---------------------- End COMPONENT Declaration ------------ +------------- Begin Cut here for INSTANTIATION Template ----- +u_gAXIS_1to3_switch : gAXIS_1to3_switch +port map ( + rst_n => rst_n, + clk => clk, + s_axi_awvalid => s_axi_awvalid, + s_axi_awaddr => s_axi_awaddr, + s_axi_awlock => s_axi_awlock, + s_axi_awready => s_axi_awready, + s_axi_arvalid => s_axi_arvalid, + s_axi_araddr => s_axi_araddr, + s_axi_arlock => s_axi_arlock, + s_axi_arready => s_axi_arready, + s_axi_wvalid => s_axi_wvalid, + s_axi_wlast => s_axi_wlast, + s_axi_wid => s_axi_wid, + s_axi_bready => s_axi_bready, + s_axi_bresp => s_axi_bresp, + s_axi_rready => s_axi_rready, + s_axi_bid => s_axi_bid, + s_axi_rid => s_axi_rid, + s_axi_wdata => s_axi_wdata, + s_axi_rdata => s_axi_rdata, + s_axi_rresp => s_axi_rresp, + s_axi_bvalid => s_axi_bvalid, + s_axi_rvalid => s_axi_rvalid, + s_axi_rlast => s_axi_rlast, + s_axi_wstrb => s_axi_wstrb, + m_axi_awvalid => m_axi_awvalid, + m_axi_awaddr => m_axi_awaddr, + m_axi_awlock => m_axi_awlock, + m_axi_awready => m_axi_awready, + m_axi_arvalid => m_axi_arvalid, + m_axi_araddr => m_axi_araddr, + m_axi_arlock => m_axi_arlock, + m_axi_arready => m_axi_arready, + m_axi_wvalid => m_axi_wvalid, + m_axi_wlast => m_axi_wlast, + m_axi_bready => m_axi_bready, + m_axi_bresp => m_axi_bresp, + m_axi_rready => m_axi_rready, + m_axi_bid => m_axi_bid, + m_axi_rid => m_axi_rid, + m_axi_wdata => m_axi_wdata, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_rvalid => m_axi_rvalid, + m_axi_rlast => m_axi_rlast, + m_axi_wstrb => m_axi_wstrb, + m_axi_wready => m_axi_wready, + s_axi_wready => s_axi_wready, + s_axi_awprot => s_axi_awprot, + s_axi_awcache => s_axi_awcache, + s_axi_awqos => s_axi_awqos, + s_axi_awuser => s_axi_awuser, + s_axi_arqos => s_axi_arqos, + s_axi_arcache => s_axi_arcache, + m_axi_awprot => m_axi_awprot, + s_axi_arid => s_axi_arid, + s_axi_arsize => s_axi_arsize, + s_axi_arlen => s_axi_arlen, + s_axi_arburst => s_axi_arburst, + s_axi_arprot => s_axi_arprot, + s_axi_awid => s_axi_awid, + s_axi_awburst => s_axi_awburst, + s_axi_awlen => s_axi_awlen, + s_axi_awsize => s_axi_awsize, + m_axi_awid => m_axi_awid, + m_axi_awburst => m_axi_awburst, + m_axi_awlen => m_axi_awlen, + m_axi_awsize => m_axi_awsize, + m_axi_awcache => m_axi_awcache, + m_axi_awqos => m_axi_awqos, + m_axi_awuser => m_axi_awuser, + m_axi_arprot => m_axi_arprot, + m_axi_arburst => m_axi_arburst, + m_axi_arlen => m_axi_arlen, + m_axi_arsize => m_axi_arsize, + m_axi_arcache => m_axi_arcache, + m_axi_arqos => m_axi_arqos, + m_axi_aruser => m_axi_aruser, + m_axi_awregion => m_axi_awregion, + m_axi_arregion => m_axi_arregion, + m_axi_arid => m_axi_arid, + m_axi_wuser => m_axi_wuser, + m_axi_ruser => m_axi_ruser, + m_axi_buser => m_axi_buser, + s_axi_aruser => s_axi_aruser, + s_axi_wuser => s_axi_wuser, + s_axi_buser => s_axi_buser, + s_axi_ruser => s_axi_ruser +); + +------------------------ End INSTANTIATION Template --------- diff --git a/Ti375C529_devkit/ip/gAXIS_1to3_switch/ipm/component.pickle b/Ti375C529_devkit/ip/gAXIS_1to3_switch/ipm/component.pickle new file mode 100644 index 0000000..3730a24 Binary files /dev/null and b/Ti375C529_devkit/ip/gAXIS_1to3_switch/ipm/component.pickle differ diff --git a/Ti375C529_devkit/ip/gAXIS_1to3_switch/ipm/graph.pickle b/Ti375C529_devkit/ip/gAXIS_1to3_switch/ipm/graph.pickle new file mode 100644 index 0000000..264dde4 Binary files /dev/null and b/Ti375C529_devkit/ip/gAXIS_1to3_switch/ipm/graph.pickle differ diff --git a/Ti375C529_devkit/ip/gAXIS_1to3_switch/settings.json b/Ti375C529_devkit/ip/gAXIS_1to3_switch/settings.json new file mode 100644 index 0000000..9bd53cf --- /dev/null +++ b/Ti375C529_devkit/ip/gAXIS_1to3_switch/settings.json @@ -0,0 +1,54 @@ +{ + "args": [ + "-o", + "gAXIS_1to3_switch", + "--base_path", + "ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "axi_infra", + "name": "efx_axi_interconnect", + "version": "5.6" + } + ], + "conf": { + "ARB_MODE": "\"ROUND_ROBIN_1\"", + "S_PORTS": "1", + "TABLE0_AXI_S0__MIN": "32'd0", + "TABLE0_AXI_S1__MIN": "32'd512", + "TABLE0_AXI_S2__MIN": "32'd285212672", + "TABLE0_AXI_S3__MIN": "32'd286261248", + "TABLE0_AXI_S4__MIN": "32'd536870912", + "TABLE0_AXI_S5__MIN": "32'd805306368", + "TABLE0_AXI_S6__MIN": "32'd1073741824", + "TABLE0_AXI_S7__MIN": "32'd1090519040", + "TABLE0_AXI_S0__MAX": "32'd9", + "TABLE0_AXI_S1__MAX": "32'd8", + "TABLE0_AXI_S2__MAX": "32'd12", + "TABLE0_AXI_S3__MAX": "32'd20", + "TABLE0_AXI_S4__MAX": "32'd28", + "TABLE0_AXI_S5__MAX": "32'd28", + "TABLE0_AXI_S6__MAX": "32'd24", + "TABLE0_AXI_S7__MAX": "32'd20", + "DATA_WIDTH": "32", + "ADDR_WIDTH": "32", + "M_PORTS": "2", + "ID_WIDTH": "8", + "USER_WIDTH": "3", + "PROTOCOL": "\"AXI4_LITE\"" + }, + "output": { + "external_script_generator": [], + "external_source_source": [], + "external_example_example": [], + "external_testbench_synopsys": [], + "external_testbench_modelsim": [], + "external_testbench_ncsim": [], + "external_testbench_aldec": [], + "external_testbench_testbench": [] + }, + "ooc_synthesis": {}, + "sw_version": "2026.1.132", + "external_path_option": "RELATIVE_PATH" +} \ No newline at end of file diff --git a/Ti375C529_devkit/ip/gDMA/gDMA.v b/Ti375C529_devkit/ip/gDMA/gDMA.v new file mode 100644 index 0000000..97c9922 --- /dev/null +++ b/Ti375C529_devkit/ip/gDMA/gDMA.v @@ -0,0 +1,11641 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 6.4.2 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _a048ca8f51874147a1cd65d43e6523ef +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module gDMA +( + input clk, + input ctrl_reset, + input reset, + input ctrl_clk, + input [13:0] ctrl_PADDR, + output ctrl_PREADY, + input ctrl_PENABLE, + input ctrl_PSEL, + input ctrl_PWRITE, + input [31:0] ctrl_PWDATA, + output [31:0] ctrl_PRDATA, + output ctrl_PSLVERROR, + output [1:0] ctrl_interrupts, + output read_arvalid, + output [31:0] read_araddr, + input read_arready, + output [3:0] read_arregion, + output [7:0] read_arlen, + output [2:0] read_arsize, + output [1:0] read_arburst, + output read_arlock, + output [3:0] read_arcache, + output [3:0] read_arqos, + output [2:0] read_arprot, + output read_rready, + input read_rvalid, + input [127:0] read_rdata, + input read_rlast, + output write_awvalid, + input write_awready, + output [31:0] write_awaddr, + output [3:0] write_awregion, + output [7:0] write_awlen, + output [2:0] write_awsize, + output [1:0] write_awburst, + output write_awlock, + output [3:0] write_awcache, + output [3:0] write_awqos, + output [2:0] write_awprot, + output write_wvalid, + input write_wready, + output [127:0] write_wdata, + output [15:0] write_wstrb, + output write_wlast, + input write_bvalid, + output write_bready, + input [1:0] write_bresp, + output dat1_o_tvalid, + input dat1_o_tready, + output [7:0] dat1_o_tdata, + output [0:0] dat1_o_tkeep, + output [3:0] dat1_o_tdest, + output dat1_o_tlast, + output io_0_descriptorUpdate, + input dat1_o_clk, + input dat1_o_reset, + input dat0_i_clk, + input dat0_i_reset, + input dat0_i_tvalid, + output dat0_i_tready, + input [7:0] dat0_i_tdata, + input [0:0] dat0_i_tkeep, + input [3:0] dat0_i_tdest, + input dat0_i_tlast, + input [1:0] read_rresp, + output io_1_descriptorUpdate +); +`IP_MODULE_NAME(EfxDMA)u_EfxDMA +( + .clk ( clk ), + .ctrl_reset ( ctrl_reset ), + .reset ( reset ), + .ctrl_clk ( ctrl_clk ), + .ctrl_PADDR ( ctrl_PADDR ), + .ctrl_PREADY ( ctrl_PREADY ), + .ctrl_PENABLE ( ctrl_PENABLE ), + .ctrl_PSEL ( ctrl_PSEL ), + .ctrl_PWRITE ( ctrl_PWRITE ), + .ctrl_PWDATA ( ctrl_PWDATA ), + .ctrl_PRDATA ( ctrl_PRDATA ), + .ctrl_PSLVERROR ( ctrl_PSLVERROR ), + .ctrl_interrupts ( ctrl_interrupts ), + .read_arvalid ( read_arvalid ), + .read_araddr ( read_araddr ), + .read_arready ( read_arready ), + .read_arregion ( read_arregion ), + .read_arlen ( read_arlen ), + .read_arsize ( read_arsize ), + .read_arburst ( read_arburst ), + .read_arlock ( read_arlock ), + .read_arcache ( read_arcache ), + .read_arqos ( read_arqos ), + .read_arprot ( read_arprot ), + .read_rready ( read_rready ), + .read_rvalid ( read_rvalid ), + .read_rdata ( read_rdata ), + .read_rlast ( read_rlast ), + .write_awvalid ( write_awvalid ), + .write_awready ( write_awready ), + .write_awaddr ( write_awaddr ), + .write_awregion ( write_awregion ), + .write_awlen ( write_awlen ), + .write_awsize ( write_awsize ), + .write_awburst ( write_awburst ), + .write_awlock ( write_awlock ), + .write_awcache ( write_awcache ), + .write_awqos ( write_awqos ), + .write_awprot ( write_awprot ), + .write_wvalid ( write_wvalid ), + .write_wready ( write_wready ), + .write_wdata ( write_wdata ), + .write_wstrb ( write_wstrb ), + .write_wlast ( write_wlast ), + .write_bvalid ( write_bvalid ), + .write_bready ( write_bready ), + .write_bresp ( write_bresp ), + .dat1_o_tvalid ( dat1_o_tvalid ), + .dat1_o_tready ( dat1_o_tready ), + .dat1_o_tdata ( dat1_o_tdata ), + .dat1_o_tkeep ( dat1_o_tkeep ), + .dat1_o_tdest ( dat1_o_tdest ), + .dat1_o_tlast ( dat1_o_tlast ), + .io_0_descriptorUpdate ( io_0_descriptorUpdate ), + .dat1_o_clk ( dat1_o_clk ), + .dat1_o_reset ( dat1_o_reset ), + .dat0_i_clk ( dat0_i_clk ), + .dat0_i_reset ( dat0_i_reset ), + .dat0_i_tvalid ( dat0_i_tvalid ), + .dat0_i_tready ( dat0_i_tready ), + .dat0_i_tdata ( dat0_i_tdata ), + .dat0_i_tkeep ( dat0_i_tkeep ), + .dat0_i_tdest ( dat0_i_tdest ), + .dat0_i_tlast ( dat0_i_tlast ), + .read_rresp ( read_rresp ), + .io_1_descriptorUpdate ( io_1_descriptorUpdate ) +); +endmodule + +// Generator : SpinalHDL dev git head : a69f4b9a329be784802c37cd8038b7dc9aec3094 +// Component : EfxDMA_a048ca8f51874147a1cd65d43e6523ef + +`timescale 1ns/1ps + +module EfxDMA_a048ca8f51874147a1cd65d43e6523ef ( + input wire [13:0] ctrl_PADDR, + input wire [0:0] ctrl_PSEL, + input wire ctrl_PENABLE, + output wire ctrl_PREADY, + input wire ctrl_PWRITE, + input wire [31:0] ctrl_PWDATA, + output wire [31:0] ctrl_PRDATA, + output wire ctrl_PSLVERROR, + output wire [1:0] ctrl_interrupts, + output wire read_arvalid, + input wire read_arready, + output wire [31:0] read_araddr, + output wire [3:0] read_arregion, + output wire [7:0] read_arlen, + output wire [2:0] read_arsize, + output wire [1:0] read_arburst, + output wire [0:0] read_arlock, + output wire [3:0] read_arcache, + output wire [3:0] read_arqos, + output wire [2:0] read_arprot, + input wire read_rvalid, + output wire read_rready, + input wire [127:0] read_rdata, + input wire [1:0] read_rresp, + input wire read_rlast, + output wire write_awvalid, + input wire write_awready, + output wire [31:0] write_awaddr, + output wire [3:0] write_awregion, + output wire [7:0] write_awlen, + output wire [2:0] write_awsize, + output wire [1:0] write_awburst, + output wire [0:0] write_awlock, + output wire [3:0] write_awcache, + output wire [3:0] write_awqos, + output wire [2:0] write_awprot, + output wire write_wvalid, + input wire write_wready, + output wire [127:0] write_wdata, + output wire [15:0] write_wstrb, + output wire write_wlast, + input wire write_bvalid, + output wire write_bready, + input wire [1:0] write_bresp, + input wire dat0_i_tvalid, + output wire dat0_i_tready, + input wire [7:0] dat0_i_tdata, + input wire [0:0] dat0_i_tkeep, + input wire [3:0] dat0_i_tdest, + input wire dat0_i_tlast, + output wire dat1_o_tvalid, + input wire dat1_o_tready, + output wire [7:0] dat1_o_tdata, + output wire [0:0] dat1_o_tkeep, + output wire [3:0] dat1_o_tdest, + output wire dat1_o_tlast, + output wire io_0_descriptorUpdate, + output wire io_1_descriptorUpdate, + input wire clk, + input wire reset, + input wire ctrl_clk, + input wire ctrl_reset, + input wire dat0_i_clk, + input wire dat0_i_reset, + input wire dat1_o_clk, + input wire dat1_o_reset +); + + wire core_io_sgRead_cmd_valid; + wire core_io_sgRead_cmd_payload_last; + wire [0:0] core_io_sgRead_cmd_payload_fragment_opcode; + wire [31:0] core_io_sgRead_cmd_payload_fragment_address; + wire [4:0] core_io_sgRead_cmd_payload_fragment_length; + wire [0:0] core_io_sgRead_cmd_payload_fragment_context; + wire core_io_sgRead_rsp_ready; + wire core_io_sgWrite_cmd_valid; + wire core_io_sgWrite_cmd_payload_last; + wire [0:0] core_io_sgWrite_cmd_payload_fragment_opcode; + wire [31:0] core_io_sgWrite_cmd_payload_fragment_address; + wire [1:0] core_io_sgWrite_cmd_payload_fragment_length; + wire [127:0] core_io_sgWrite_cmd_payload_fragment_data; + wire [15:0] core_io_sgWrite_cmd_payload_fragment_mask; + wire [0:0] core_io_sgWrite_cmd_payload_fragment_context; + wire core_io_sgWrite_rsp_ready; + wire core_io_read_cmd_valid; + wire core_io_read_cmd_payload_last; + wire [0:0] core_io_read_cmd_payload_fragment_opcode; + wire [31:0] core_io_read_cmd_payload_fragment_address; + wire [11:0] core_io_read_cmd_payload_fragment_length; + wire [20:0] core_io_read_cmd_payload_fragment_context; + wire core_io_read_rsp_ready; + wire core_io_write_cmd_valid; + wire core_io_write_cmd_payload_last; + wire [0:0] core_io_write_cmd_payload_fragment_opcode; + wire [31:0] core_io_write_cmd_payload_fragment_address; + wire [11:0] core_io_write_cmd_payload_fragment_length; + wire [127:0] core_io_write_cmd_payload_fragment_data; + wire [15:0] core_io_write_cmd_payload_fragment_mask; + wire [12:0] core_io_write_cmd_payload_fragment_context; + wire core_io_write_rsp_ready; + wire core_io_outputs_0_valid; + wire [63:0] core_io_outputs_0_payload_data; + wire [7:0] core_io_outputs_0_payload_mask; + wire [3:0] core_io_outputs_0_payload_sink; + wire core_io_outputs_0_payload_last; + wire core_io_inputs_0_ready; + wire [1:0] core_io_interrupts; + wire core_io_ctrl_PREADY; + wire [31:0] core_io_ctrl_PRDATA; + wire core_io_ctrl_PSLVERROR; + wire core_ll_0_descriptorUpdate; + wire core_ll_1_descriptorUpdate; + wire withCtrlCc_apbCc_io_input_PREADY; + wire [31:0] withCtrlCc_apbCc_io_input_PRDATA; + wire withCtrlCc_apbCc_io_input_PSLVERROR; + wire [13:0] withCtrlCc_apbCc_io_output_PADDR; + wire [0:0] withCtrlCc_apbCc_io_output_PSEL; + wire withCtrlCc_apbCc_io_output_PENABLE; + wire withCtrlCc_apbCc_io_output_PWRITE; + wire [31:0] withCtrlCc_apbCc_io_output_PWDATA; + wire [1:0] io_interrupts_buffercc_io_dataOut; + wire readLogic_sourceRemover_io_input_cmd_ready; + wire readLogic_sourceRemover_io_input_rsp_valid; + wire readLogic_sourceRemover_io_input_rsp_payload_last; + wire [0:0] readLogic_sourceRemover_io_input_rsp_payload_fragment_source; + wire [0:0] readLogic_sourceRemover_io_input_rsp_payload_fragment_opcode; + wire [127:0] readLogic_sourceRemover_io_input_rsp_payload_fragment_data; + wire [20:0] readLogic_sourceRemover_io_input_rsp_payload_fragment_context; + wire readLogic_sourceRemover_io_output_cmd_valid; + wire readLogic_sourceRemover_io_output_cmd_payload_last; + wire [0:0] readLogic_sourceRemover_io_output_cmd_payload_fragment_opcode; + wire [31:0] readLogic_sourceRemover_io_output_cmd_payload_fragment_address; + wire [11:0] readLogic_sourceRemover_io_output_cmd_payload_fragment_length; + wire [21:0] readLogic_sourceRemover_io_output_cmd_payload_fragment_context; + wire readLogic_sourceRemover_io_output_rsp_ready; + wire readLogic_bridge_io_input_cmd_ready; + wire readLogic_bridge_io_input_rsp_valid; + wire readLogic_bridge_io_input_rsp_payload_last; + wire [0:0] readLogic_bridge_io_input_rsp_payload_fragment_opcode; + wire [127:0] readLogic_bridge_io_input_rsp_payload_fragment_data; + wire [21:0] readLogic_bridge_io_input_rsp_payload_fragment_context; + wire readLogic_bridge_io_output_ar_valid; + wire [31:0] readLogic_bridge_io_output_ar_payload_addr; + wire [7:0] readLogic_bridge_io_output_ar_payload_len; + wire [2:0] readLogic_bridge_io_output_ar_payload_size; + wire [3:0] readLogic_bridge_io_output_ar_payload_cache; + wire [2:0] readLogic_bridge_io_output_ar_payload_prot; + wire readLogic_bridge_io_output_r_ready; + wire writeLogic_sourceRemover_io_input_cmd_ready; + wire writeLogic_sourceRemover_io_input_rsp_valid; + wire writeLogic_sourceRemover_io_input_rsp_payload_last; + wire [0:0] writeLogic_sourceRemover_io_input_rsp_payload_fragment_source; + wire [0:0] writeLogic_sourceRemover_io_input_rsp_payload_fragment_opcode; + wire [12:0] writeLogic_sourceRemover_io_input_rsp_payload_fragment_context; + wire writeLogic_sourceRemover_io_output_cmd_valid; + wire writeLogic_sourceRemover_io_output_cmd_payload_last; + wire [0:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_opcode; + wire [31:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_address; + wire [11:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_length; + wire [127:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_data; + wire [15:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_mask; + wire [13:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_context; + wire writeLogic_sourceRemover_io_output_rsp_ready; + wire writeLogic_bridge_io_input_cmd_ready; + wire writeLogic_bridge_io_input_rsp_valid; + wire writeLogic_bridge_io_input_rsp_payload_last; + wire [0:0] writeLogic_bridge_io_input_rsp_payload_fragment_opcode; + wire [13:0] writeLogic_bridge_io_input_rsp_payload_fragment_context; + wire writeLogic_bridge_io_output_aw_valid; + wire [31:0] writeLogic_bridge_io_output_aw_payload_addr; + wire [7:0] writeLogic_bridge_io_output_aw_payload_len; + wire [2:0] writeLogic_bridge_io_output_aw_payload_size; + wire [3:0] writeLogic_bridge_io_output_aw_payload_cache; + wire [2:0] writeLogic_bridge_io_output_aw_payload_prot; + wire writeLogic_bridge_io_output_w_valid; + wire [127:0] writeLogic_bridge_io_output_w_payload_data; + wire [15:0] writeLogic_bridge_io_output_w_payload_strb; + wire writeLogic_bridge_io_output_w_payload_last; + wire writeLogic_bridge_io_output_b_ready; + wire inputsAdapter_0_upsizer_logic_io_input_ready; + wire inputsAdapter_0_upsizer_logic_io_output_valid; + wire [63:0] inputsAdapter_0_upsizer_logic_io_output_payload_data; + wire [7:0] inputsAdapter_0_upsizer_logic_io_output_payload_mask; + wire [3:0] inputsAdapter_0_upsizer_logic_io_output_payload_sink; + wire inputsAdapter_0_upsizer_logic_io_output_payload_last; + wire inputsAdapter_0_crossclock_fifo_io_push_ready; + wire inputsAdapter_0_crossclock_fifo_io_pop_valid; + wire [63:0] inputsAdapter_0_crossclock_fifo_io_pop_payload_data; + wire [7:0] inputsAdapter_0_crossclock_fifo_io_pop_payload_mask; + wire [3:0] inputsAdapter_0_crossclock_fifo_io_pop_payload_sink; + wire inputsAdapter_0_crossclock_fifo_io_pop_payload_last; + wire [4:0] inputsAdapter_0_crossclock_fifo_io_pushOccupancy; + wire [4:0] inputsAdapter_0_crossclock_fifo_io_popOccupancy; + wire outputsAdapter_0_crossclock_fifo_io_push_ready; + wire outputsAdapter_0_crossclock_fifo_io_pop_valid; + wire [63:0] outputsAdapter_0_crossclock_fifo_io_pop_payload_data; + wire [7:0] outputsAdapter_0_crossclock_fifo_io_pop_payload_mask; + wire [3:0] outputsAdapter_0_crossclock_fifo_io_pop_payload_sink; + wire outputsAdapter_0_crossclock_fifo_io_pop_payload_last; + wire [4:0] outputsAdapter_0_crossclock_fifo_io_pushOccupancy; + wire [4:0] outputsAdapter_0_crossclock_fifo_io_popOccupancy; + wire outputsAdapter_0_sparseDownsizer_logic_io_input_ready; + wire outputsAdapter_0_sparseDownsizer_logic_io_output_valid; + wire [7:0] outputsAdapter_0_sparseDownsizer_logic_io_output_payload_data; + wire [0:0] outputsAdapter_0_sparseDownsizer_logic_io_output_payload_mask; + wire [3:0] outputsAdapter_0_sparseDownsizer_logic_io_output_payload_sink; + wire outputsAdapter_0_sparseDownsizer_logic_io_output_payload_last; + wire interconnect_read_aggregated_arbiter_io_inputs_0_cmd_ready; + wire interconnect_read_aggregated_arbiter_io_inputs_0_rsp_valid; + wire interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_last; + wire [0:0] interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode; + wire [127:0] interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_data; + wire [0:0] interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context; + wire interconnect_read_aggregated_arbiter_io_inputs_1_cmd_ready; + wire interconnect_read_aggregated_arbiter_io_inputs_1_rsp_valid; + wire interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_last; + wire [0:0] interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode; + wire [127:0] interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_data; + wire [20:0] interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context; + wire interconnect_read_aggregated_arbiter_io_output_cmd_valid; + wire interconnect_read_aggregated_arbiter_io_output_cmd_payload_last; + wire [0:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_source; + wire [0:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_opcode; + wire [31:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_address; + wire [11:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_length; + wire [20:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_context; + wire interconnect_read_aggregated_arbiter_io_output_rsp_ready; + wire interconnect_write_aggregated_arbiter_io_inputs_0_cmd_ready; + wire interconnect_write_aggregated_arbiter_io_inputs_0_rsp_valid; + wire interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_last; + wire [0:0] interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode; + wire [0:0] interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context; + wire interconnect_write_aggregated_arbiter_io_inputs_1_cmd_ready; + wire interconnect_write_aggregated_arbiter_io_inputs_1_rsp_valid; + wire interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_last; + wire [0:0] interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode; + wire [12:0] interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context; + wire interconnect_write_aggregated_arbiter_io_output_cmd_valid; + wire interconnect_write_aggregated_arbiter_io_output_cmd_payload_last; + wire [0:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_source; + wire [0:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_opcode; + wire [31:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_address; + wire [11:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_length; + wire [127:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_data; + wire [15:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_mask; + wire [12:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_context; + wire interconnect_write_aggregated_arbiter_io_output_rsp_ready; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode; + wire [31:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address; + wire [11:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length; + wire [20:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode; + wire [127:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_data; + wire [20:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode; + wire [31:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address; + wire [4:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode; + wire [127:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode; + wire [31:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address; + wire [11:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length; + wire [127:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_data; + wire [15:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_mask; + wire [12:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode; + wire [12:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context; + wire io_write_cmd_s2mPipe_valid; + reg io_write_cmd_s2mPipe_ready; + wire io_write_cmd_s2mPipe_payload_last; + wire [0:0] io_write_cmd_s2mPipe_payload_fragment_opcode; + wire [31:0] io_write_cmd_s2mPipe_payload_fragment_address; + wire [11:0] io_write_cmd_s2mPipe_payload_fragment_length; + wire [127:0] io_write_cmd_s2mPipe_payload_fragment_data; + wire [15:0] io_write_cmd_s2mPipe_payload_fragment_mask; + wire [12:0] io_write_cmd_s2mPipe_payload_fragment_context; + reg io_write_cmd_rValidN; + reg io_write_cmd_rData_last; + reg [0:0] io_write_cmd_rData_fragment_opcode; + reg [31:0] io_write_cmd_rData_fragment_address; + reg [11:0] io_write_cmd_rData_fragment_length; + reg [127:0] io_write_cmd_rData_fragment_data; + reg [15:0] io_write_cmd_rData_fragment_mask; + reg [12:0] io_write_cmd_rData_fragment_context; + wire io_write_cmd_s2mPipe_m2sPipe_valid; + wire io_write_cmd_s2mPipe_m2sPipe_ready; + wire io_write_cmd_s2mPipe_m2sPipe_payload_last; + wire [0:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_opcode; + wire [31:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_address; + wire [11:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_length; + wire [127:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_data; + wire [15:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_mask; + wire [12:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_context; + reg io_write_cmd_s2mPipe_rValid; + reg io_write_cmd_s2mPipe_rData_last; + reg [0:0] io_write_cmd_s2mPipe_rData_fragment_opcode; + reg [31:0] io_write_cmd_s2mPipe_rData_fragment_address; + reg [11:0] io_write_cmd_s2mPipe_rData_fragment_length; + reg [127:0] io_write_cmd_s2mPipe_rData_fragment_data; + reg [15:0] io_write_cmd_s2mPipe_rData_fragment_mask; + reg [12:0] io_write_cmd_s2mPipe_rData_fragment_context; + wire when_Stream_l375; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode; + wire [31:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address; + wire [1:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length; + wire [127:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data; + wire [15:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context; + wire interconnect_read_aggregated_cmd_valid; + wire interconnect_read_aggregated_cmd_ready; + wire interconnect_read_aggregated_cmd_payload_last; + wire [0:0] interconnect_read_aggregated_cmd_payload_fragment_source; + wire [0:0] interconnect_read_aggregated_cmd_payload_fragment_opcode; + wire [31:0] interconnect_read_aggregated_cmd_payload_fragment_address; + wire [11:0] interconnect_read_aggregated_cmd_payload_fragment_length; + wire [20:0] interconnect_read_aggregated_cmd_payload_fragment_context; + wire interconnect_read_aggregated_rsp_valid; + wire interconnect_read_aggregated_rsp_ready; + wire interconnect_read_aggregated_rsp_payload_last; + wire [0:0] interconnect_read_aggregated_rsp_payload_fragment_source; + wire [0:0] interconnect_read_aggregated_rsp_payload_fragment_opcode; + wire [127:0] interconnect_read_aggregated_rsp_payload_fragment_data; + wire [20:0] interconnect_read_aggregated_rsp_payload_fragment_context; + wire interconnect_write_aggregated_cmd_valid; + reg interconnect_write_aggregated_cmd_ready; + wire interconnect_write_aggregated_cmd_payload_last; + wire [0:0] interconnect_write_aggregated_cmd_payload_fragment_source; + wire [0:0] interconnect_write_aggregated_cmd_payload_fragment_opcode; + wire [31:0] interconnect_write_aggregated_cmd_payload_fragment_address; + wire [11:0] interconnect_write_aggregated_cmd_payload_fragment_length; + wire [127:0] interconnect_write_aggregated_cmd_payload_fragment_data; + wire [15:0] interconnect_write_aggregated_cmd_payload_fragment_mask; + wire [12:0] interconnect_write_aggregated_cmd_payload_fragment_context; + wire interconnect_write_aggregated_rsp_valid; + wire interconnect_write_aggregated_rsp_ready; + wire interconnect_write_aggregated_rsp_payload_last; + wire [0:0] interconnect_write_aggregated_rsp_payload_fragment_source; + wire [0:0] interconnect_write_aggregated_rsp_payload_fragment_opcode; + wire [12:0] interconnect_write_aggregated_rsp_payload_fragment_context; + wire readLogic_resized_cmd_valid; + wire readLogic_resized_cmd_ready; + wire readLogic_resized_cmd_payload_last; + wire [0:0] readLogic_resized_cmd_payload_fragment_source; + wire [0:0] readLogic_resized_cmd_payload_fragment_opcode; + wire [31:0] readLogic_resized_cmd_payload_fragment_address; + wire [11:0] readLogic_resized_cmd_payload_fragment_length; + wire [20:0] readLogic_resized_cmd_payload_fragment_context; + wire readLogic_resized_rsp_valid; + wire readLogic_resized_rsp_ready; + wire readLogic_resized_rsp_payload_last; + wire [0:0] readLogic_resized_rsp_payload_fragment_source; + wire [0:0] readLogic_resized_rsp_payload_fragment_opcode; + wire [127:0] readLogic_resized_rsp_payload_fragment_data; + wire [20:0] readLogic_resized_rsp_payload_fragment_context; + wire interconnect_read_aggregated_cmd_halfPipe_valid; + wire interconnect_read_aggregated_cmd_halfPipe_ready; + wire interconnect_read_aggregated_cmd_halfPipe_payload_last; + wire [0:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_source; + wire [0:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_opcode; + wire [31:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_address; + wire [11:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_length; + wire [20:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_context; + reg interconnect_read_aggregated_cmd_rValid; + wire interconnect_read_aggregated_cmd_halfPipe_fire; + reg interconnect_read_aggregated_cmd_rData_last; + reg [0:0] interconnect_read_aggregated_cmd_rData_fragment_source; + reg [0:0] interconnect_read_aggregated_cmd_rData_fragment_opcode; + reg [31:0] interconnect_read_aggregated_cmd_rData_fragment_address; + reg [11:0] interconnect_read_aggregated_cmd_rData_fragment_length; + reg [20:0] interconnect_read_aggregated_cmd_rData_fragment_context; + wire readLogic_resized_rsp_combStage_valid; + wire readLogic_resized_rsp_combStage_ready; + wire readLogic_resized_rsp_combStage_payload_last; + wire [0:0] readLogic_resized_rsp_combStage_payload_fragment_source; + wire [0:0] readLogic_resized_rsp_combStage_payload_fragment_opcode; + wire [127:0] readLogic_resized_rsp_combStage_payload_fragment_data; + wire [20:0] readLogic_resized_rsp_combStage_payload_fragment_context; + wire readLogic_adapter_ar_valid; + wire readLogic_adapter_ar_ready; + wire [31:0] readLogic_adapter_ar_payload_addr; + wire [3:0] readLogic_adapter_ar_payload_region; + wire [7:0] readLogic_adapter_ar_payload_len; + wire [2:0] readLogic_adapter_ar_payload_size; + wire [1:0] readLogic_adapter_ar_payload_burst; + wire [0:0] readLogic_adapter_ar_payload_lock; + wire [3:0] readLogic_adapter_ar_payload_cache; + wire [3:0] readLogic_adapter_ar_payload_qos; + wire [2:0] readLogic_adapter_ar_payload_prot; + wire readLogic_adapter_r_valid; + wire readLogic_adapter_r_ready; + wire [127:0] readLogic_adapter_r_payload_data; + wire [1:0] readLogic_adapter_r_payload_resp; + wire readLogic_adapter_r_payload_last; + wire [3:0] _zz_readLogic_adapter_ar_payload_region; + wire readLogic_adapter_ar_halfPipe_valid; + wire readLogic_adapter_ar_halfPipe_ready; + wire [31:0] readLogic_adapter_ar_halfPipe_payload_addr; + wire [3:0] readLogic_adapter_ar_halfPipe_payload_region; + wire [7:0] readLogic_adapter_ar_halfPipe_payload_len; + wire [2:0] readLogic_adapter_ar_halfPipe_payload_size; + wire [1:0] readLogic_adapter_ar_halfPipe_payload_burst; + wire [0:0] readLogic_adapter_ar_halfPipe_payload_lock; + wire [3:0] readLogic_adapter_ar_halfPipe_payload_cache; + wire [3:0] readLogic_adapter_ar_halfPipe_payload_qos; + wire [2:0] readLogic_adapter_ar_halfPipe_payload_prot; + reg readLogic_adapter_ar_rValid; + wire readLogic_adapter_ar_halfPipe_fire; + reg [31:0] readLogic_adapter_ar_rData_addr; + reg [3:0] readLogic_adapter_ar_rData_region; + reg [7:0] readLogic_adapter_ar_rData_len; + reg [2:0] readLogic_adapter_ar_rData_size; + reg [1:0] readLogic_adapter_ar_rData_burst; + reg [0:0] readLogic_adapter_ar_rData_lock; + reg [3:0] readLogic_adapter_ar_rData_cache; + reg [3:0] readLogic_adapter_ar_rData_qos; + reg [2:0] readLogic_adapter_ar_rData_prot; + wire read_r_s2mPipe_valid; + reg read_r_s2mPipe_ready; + wire [127:0] read_r_s2mPipe_payload_data; + wire [1:0] read_r_s2mPipe_payload_resp; + wire read_r_s2mPipe_payload_last; + reg read_r_rValidN; + reg [127:0] read_r_rData_data; + reg [1:0] read_r_rData_resp; + reg read_r_rData_last; + wire readLogic_beforeQueue_valid; + wire readLogic_beforeQueue_ready; + wire [127:0] readLogic_beforeQueue_payload_data; + wire [1:0] readLogic_beforeQueue_payload_resp; + wire readLogic_beforeQueue_payload_last; + reg read_r_s2mPipe_rValid; + reg [127:0] read_r_s2mPipe_rData_data; + reg [1:0] read_r_s2mPipe_rData_resp; + reg read_r_s2mPipe_rData_last; + wire when_Stream_l375_1; + wire writeLogic_resized_cmd_valid; + wire writeLogic_resized_cmd_ready; + wire writeLogic_resized_cmd_payload_last; + wire [0:0] writeLogic_resized_cmd_payload_fragment_source; + wire [0:0] writeLogic_resized_cmd_payload_fragment_opcode; + wire [31:0] writeLogic_resized_cmd_payload_fragment_address; + wire [11:0] writeLogic_resized_cmd_payload_fragment_length; + wire [127:0] writeLogic_resized_cmd_payload_fragment_data; + wire [15:0] writeLogic_resized_cmd_payload_fragment_mask; + wire [12:0] writeLogic_resized_cmd_payload_fragment_context; + wire writeLogic_resized_rsp_valid; + wire writeLogic_resized_rsp_ready; + wire writeLogic_resized_rsp_payload_last; + wire [0:0] writeLogic_resized_rsp_payload_fragment_source; + wire [0:0] writeLogic_resized_rsp_payload_fragment_opcode; + wire [12:0] writeLogic_resized_rsp_payload_fragment_context; + wire interconnect_write_aggregated_cmd_m2sPipe_valid; + wire interconnect_write_aggregated_cmd_m2sPipe_ready; + wire interconnect_write_aggregated_cmd_m2sPipe_payload_last; + wire [0:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_source; + wire [0:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_opcode; + wire [31:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_address; + wire [11:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_length; + wire [127:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_data; + wire [15:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_mask; + wire [12:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_context; + reg interconnect_write_aggregated_cmd_rValid; + reg interconnect_write_aggregated_cmd_rData_last; + reg [0:0] interconnect_write_aggregated_cmd_rData_fragment_source; + reg [0:0] interconnect_write_aggregated_cmd_rData_fragment_opcode; + reg [31:0] interconnect_write_aggregated_cmd_rData_fragment_address; + reg [11:0] interconnect_write_aggregated_cmd_rData_fragment_length; + reg [127:0] interconnect_write_aggregated_cmd_rData_fragment_data; + reg [15:0] interconnect_write_aggregated_cmd_rData_fragment_mask; + reg [12:0] interconnect_write_aggregated_cmd_rData_fragment_context; + wire when_Stream_l375_2; + wire writeLogic_resized_rsp_combStage_valid; + wire writeLogic_resized_rsp_combStage_ready; + wire writeLogic_resized_rsp_combStage_payload_last; + wire [0:0] writeLogic_resized_rsp_combStage_payload_fragment_source; + wire [0:0] writeLogic_resized_rsp_combStage_payload_fragment_opcode; + wire [12:0] writeLogic_resized_rsp_combStage_payload_fragment_context; + wire writeLogic_adapter_aw_valid; + wire writeLogic_adapter_aw_ready; + wire [31:0] writeLogic_adapter_aw_payload_addr; + wire [3:0] writeLogic_adapter_aw_payload_region; + wire [7:0] writeLogic_adapter_aw_payload_len; + wire [2:0] writeLogic_adapter_aw_payload_size; + wire [1:0] writeLogic_adapter_aw_payload_burst; + wire [0:0] writeLogic_adapter_aw_payload_lock; + wire [3:0] writeLogic_adapter_aw_payload_cache; + wire [3:0] writeLogic_adapter_aw_payload_qos; + wire [2:0] writeLogic_adapter_aw_payload_prot; + wire writeLogic_adapter_w_valid; + wire writeLogic_adapter_w_ready; + wire [127:0] writeLogic_adapter_w_payload_data; + wire [15:0] writeLogic_adapter_w_payload_strb; + wire writeLogic_adapter_w_payload_last; + wire writeLogic_adapter_b_valid; + wire writeLogic_adapter_b_ready; + wire [1:0] writeLogic_adapter_b_payload_resp; + wire [3:0] _zz_writeLogic_adapter_aw_payload_region; + wire writeLogic_adapter_aw_halfPipe_valid; + wire writeLogic_adapter_aw_halfPipe_ready; + wire [31:0] writeLogic_adapter_aw_halfPipe_payload_addr; + wire [3:0] writeLogic_adapter_aw_halfPipe_payload_region; + wire [7:0] writeLogic_adapter_aw_halfPipe_payload_len; + wire [2:0] writeLogic_adapter_aw_halfPipe_payload_size; + wire [1:0] writeLogic_adapter_aw_halfPipe_payload_burst; + wire [0:0] writeLogic_adapter_aw_halfPipe_payload_lock; + wire [3:0] writeLogic_adapter_aw_halfPipe_payload_cache; + wire [3:0] writeLogic_adapter_aw_halfPipe_payload_qos; + wire [2:0] writeLogic_adapter_aw_halfPipe_payload_prot; + reg writeLogic_adapter_aw_rValid; + wire writeLogic_adapter_aw_halfPipe_fire; + reg [31:0] writeLogic_adapter_aw_rData_addr; + reg [3:0] writeLogic_adapter_aw_rData_region; + reg [7:0] writeLogic_adapter_aw_rData_len; + reg [2:0] writeLogic_adapter_aw_rData_size; + reg [1:0] writeLogic_adapter_aw_rData_burst; + reg [0:0] writeLogic_adapter_aw_rData_lock; + reg [3:0] writeLogic_adapter_aw_rData_cache; + reg [3:0] writeLogic_adapter_aw_rData_qos; + reg [2:0] writeLogic_adapter_aw_rData_prot; + wire writeLogic_adapter_w_s2mPipe_valid; + reg writeLogic_adapter_w_s2mPipe_ready; + wire [127:0] writeLogic_adapter_w_s2mPipe_payload_data; + wire [15:0] writeLogic_adapter_w_s2mPipe_payload_strb; + wire writeLogic_adapter_w_s2mPipe_payload_last; + reg writeLogic_adapter_w_rValidN; + reg [127:0] writeLogic_adapter_w_rData_data; + reg [15:0] writeLogic_adapter_w_rData_strb; + reg writeLogic_adapter_w_rData_last; + wire writeLogic_adapter_w_s2mPipe_m2sPipe_valid; + wire writeLogic_adapter_w_s2mPipe_m2sPipe_ready; + wire [127:0] writeLogic_adapter_w_s2mPipe_m2sPipe_payload_data; + wire [15:0] writeLogic_adapter_w_s2mPipe_m2sPipe_payload_strb; + wire writeLogic_adapter_w_s2mPipe_m2sPipe_payload_last; + reg writeLogic_adapter_w_s2mPipe_rValid; + reg [127:0] writeLogic_adapter_w_s2mPipe_rData_data; + reg [15:0] writeLogic_adapter_w_s2mPipe_rData_strb; + reg writeLogic_adapter_w_s2mPipe_rData_last; + wire when_Stream_l375_3; + wire write_b_halfPipe_valid; + wire write_b_halfPipe_ready; + wire [1:0] write_b_halfPipe_payload_resp; + reg write_b_rValid; + wire write_b_halfPipe_fire; + reg [1:0] write_b_rData_resp; + wire io_pop_s2mPipe_valid; + reg io_pop_s2mPipe_ready; + wire [63:0] io_pop_s2mPipe_payload_data; + wire [7:0] io_pop_s2mPipe_payload_mask; + wire [3:0] io_pop_s2mPipe_payload_sink; + wire io_pop_s2mPipe_payload_last; + reg io_pop_rValidN; + reg [63:0] io_pop_rData_data; + reg [7:0] io_pop_rData_mask; + reg [3:0] io_pop_rData_sink; + reg io_pop_rData_last; + wire io_pop_s2mPipe_m2sPipe_valid; + wire io_pop_s2mPipe_m2sPipe_ready; + wire [63:0] io_pop_s2mPipe_m2sPipe_payload_data; + wire [7:0] io_pop_s2mPipe_m2sPipe_payload_mask; + wire [3:0] io_pop_s2mPipe_m2sPipe_payload_sink; + wire io_pop_s2mPipe_m2sPipe_payload_last; + reg io_pop_s2mPipe_rValid; + reg [63:0] io_pop_s2mPipe_rData_data; + reg [7:0] io_pop_s2mPipe_rData_mask; + reg [3:0] io_pop_s2mPipe_rData_sink; + reg io_pop_s2mPipe_rData_last; + wire when_Stream_l375_4; + wire io_outputs_0_s2mPipe_valid; + reg io_outputs_0_s2mPipe_ready; + wire [63:0] io_outputs_0_s2mPipe_payload_data; + wire [7:0] io_outputs_0_s2mPipe_payload_mask; + wire [3:0] io_outputs_0_s2mPipe_payload_sink; + wire io_outputs_0_s2mPipe_payload_last; + reg io_outputs_0_rValidN; + reg [63:0] io_outputs_0_rData_data; + reg [7:0] io_outputs_0_rData_mask; + reg [3:0] io_outputs_0_rData_sink; + reg io_outputs_0_rData_last; + wire outputsAdapter_0_ptr_valid; + wire outputsAdapter_0_ptr_ready; + wire [63:0] outputsAdapter_0_ptr_payload_data; + wire [7:0] outputsAdapter_0_ptr_payload_mask; + wire [3:0] outputsAdapter_0_ptr_payload_sink; + wire outputsAdapter_0_ptr_payload_last; + reg io_outputs_0_s2mPipe_rValid; + reg [63:0] io_outputs_0_s2mPipe_rData_data; + reg [7:0] io_outputs_0_s2mPipe_rData_mask; + reg [3:0] io_outputs_0_s2mPipe_rData_sink; + reg io_outputs_0_s2mPipe_rData_last; + wire when_Stream_l375_5; + + EfxDMA_Core_a048ca8f51874147a1cd65d43e6523ef core ( + .io_sgRead_cmd_valid (core_io_sgRead_cmd_valid ), //o + .io_sgRead_cmd_ready (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready ), //i + .io_sgRead_cmd_payload_last (core_io_sgRead_cmd_payload_last ), //o + .io_sgRead_cmd_payload_fragment_opcode (core_io_sgRead_cmd_payload_fragment_opcode ), //o + .io_sgRead_cmd_payload_fragment_address (core_io_sgRead_cmd_payload_fragment_address[31:0] ), //o + .io_sgRead_cmd_payload_fragment_length (core_io_sgRead_cmd_payload_fragment_length[4:0] ), //o + .io_sgRead_cmd_payload_fragment_context (core_io_sgRead_cmd_payload_fragment_context ), //o + .io_sgRead_rsp_valid (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid ), //i + .io_sgRead_rsp_ready (core_io_sgRead_rsp_ready ), //o + .io_sgRead_rsp_payload_last (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last ), //i + .io_sgRead_rsp_payload_fragment_opcode (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode ), //i + .io_sgRead_rsp_payload_fragment_data (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data[127:0] ), //i + .io_sgRead_rsp_payload_fragment_context (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context ), //i + .io_sgWrite_cmd_valid (core_io_sgWrite_cmd_valid ), //o + .io_sgWrite_cmd_ready (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready ), //i + .io_sgWrite_cmd_payload_last (core_io_sgWrite_cmd_payload_last ), //o + .io_sgWrite_cmd_payload_fragment_opcode (core_io_sgWrite_cmd_payload_fragment_opcode ), //o + .io_sgWrite_cmd_payload_fragment_address (core_io_sgWrite_cmd_payload_fragment_address[31:0] ), //o + .io_sgWrite_cmd_payload_fragment_length (core_io_sgWrite_cmd_payload_fragment_length[1:0] ), //o + .io_sgWrite_cmd_payload_fragment_data (core_io_sgWrite_cmd_payload_fragment_data[127:0] ), //o + .io_sgWrite_cmd_payload_fragment_mask (core_io_sgWrite_cmd_payload_fragment_mask[15:0] ), //o + .io_sgWrite_cmd_payload_fragment_context (core_io_sgWrite_cmd_payload_fragment_context ), //o + .io_sgWrite_rsp_valid (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid ), //i + .io_sgWrite_rsp_ready (core_io_sgWrite_rsp_ready ), //o + .io_sgWrite_rsp_payload_last (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last ), //i + .io_sgWrite_rsp_payload_fragment_opcode (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode ), //i + .io_sgWrite_rsp_payload_fragment_context (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context ), //i + .io_read_cmd_valid (core_io_read_cmd_valid ), //o + .io_read_cmd_ready (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready ), //i + .io_read_cmd_payload_last (core_io_read_cmd_payload_last ), //o + .io_read_cmd_payload_fragment_opcode (core_io_read_cmd_payload_fragment_opcode ), //o + .io_read_cmd_payload_fragment_address (core_io_read_cmd_payload_fragment_address[31:0] ), //o + .io_read_cmd_payload_fragment_length (core_io_read_cmd_payload_fragment_length[11:0] ), //o + .io_read_cmd_payload_fragment_context (core_io_read_cmd_payload_fragment_context[20:0] ), //o + .io_read_rsp_valid (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid ), //i + .io_read_rsp_ready (core_io_read_rsp_ready ), //o + .io_read_rsp_payload_last (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last ), //i + .io_read_rsp_payload_fragment_opcode (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode ), //i + .io_read_rsp_payload_fragment_data (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_data[127:0] ), //i + .io_read_rsp_payload_fragment_context (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context[20:0] ), //i + .io_write_cmd_valid (core_io_write_cmd_valid ), //o + .io_write_cmd_ready (io_write_cmd_rValidN ), //i + .io_write_cmd_payload_last (core_io_write_cmd_payload_last ), //o + .io_write_cmd_payload_fragment_opcode (core_io_write_cmd_payload_fragment_opcode ), //o + .io_write_cmd_payload_fragment_address (core_io_write_cmd_payload_fragment_address[31:0] ), //o + .io_write_cmd_payload_fragment_length (core_io_write_cmd_payload_fragment_length[11:0] ), //o + .io_write_cmd_payload_fragment_data (core_io_write_cmd_payload_fragment_data[127:0] ), //o + .io_write_cmd_payload_fragment_mask (core_io_write_cmd_payload_fragment_mask[15:0] ), //o + .io_write_cmd_payload_fragment_context (core_io_write_cmd_payload_fragment_context[12:0] ), //o + .io_write_rsp_valid (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid ), //i + .io_write_rsp_ready (core_io_write_rsp_ready ), //o + .io_write_rsp_payload_last (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last ), //i + .io_write_rsp_payload_fragment_opcode (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode ), //i + .io_write_rsp_payload_fragment_context (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context[12:0]), //i + .io_outputs_0_valid (core_io_outputs_0_valid ), //o + .io_outputs_0_ready (io_outputs_0_rValidN ), //i + .io_outputs_0_payload_data (core_io_outputs_0_payload_data[63:0] ), //o + .io_outputs_0_payload_mask (core_io_outputs_0_payload_mask[7:0] ), //o + .io_outputs_0_payload_sink (core_io_outputs_0_payload_sink[3:0] ), //o + .io_outputs_0_payload_last (core_io_outputs_0_payload_last ), //o + .io_inputs_0_valid (io_pop_s2mPipe_m2sPipe_valid ), //i + .io_inputs_0_ready (core_io_inputs_0_ready ), //o + .io_inputs_0_payload_data (io_pop_s2mPipe_m2sPipe_payload_data[63:0] ), //i + .io_inputs_0_payload_mask (io_pop_s2mPipe_m2sPipe_payload_mask[7:0] ), //i + .io_inputs_0_payload_sink (io_pop_s2mPipe_m2sPipe_payload_sink[3:0] ), //i + .io_inputs_0_payload_last (io_pop_s2mPipe_m2sPipe_payload_last ), //i + .io_interrupts (core_io_interrupts[1:0] ), //o + .io_ctrl_PADDR (withCtrlCc_apbCc_io_output_PADDR[13:0] ), //i + .io_ctrl_PSEL (withCtrlCc_apbCc_io_output_PSEL ), //i + .io_ctrl_PENABLE (withCtrlCc_apbCc_io_output_PENABLE ), //i + .io_ctrl_PREADY (core_io_ctrl_PREADY ), //o + .io_ctrl_PWRITE (withCtrlCc_apbCc_io_output_PWRITE ), //i + .io_ctrl_PWDATA (withCtrlCc_apbCc_io_output_PWDATA[31:0] ), //i + .io_ctrl_PRDATA (core_io_ctrl_PRDATA[31:0] ), //o + .io_ctrl_PSLVERROR (core_io_ctrl_PSLVERROR ), //o + .ll_0_descriptorUpdate (core_ll_0_descriptorUpdate ), //o + .ll_1_descriptorUpdate (core_ll_1_descriptorUpdate ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_Apb3CC_a048ca8f51874147a1cd65d43e6523ef withCtrlCc_apbCc ( + .io_input_PADDR (ctrl_PADDR[13:0] ), //i + .io_input_PSEL (ctrl_PSEL ), //i + .io_input_PENABLE (ctrl_PENABLE ), //i + .io_input_PREADY (withCtrlCc_apbCc_io_input_PREADY ), //o + .io_input_PWRITE (ctrl_PWRITE ), //i + .io_input_PWDATA (ctrl_PWDATA[31:0] ), //i + .io_input_PRDATA (withCtrlCc_apbCc_io_input_PRDATA[31:0] ), //o + .io_input_PSLVERROR (withCtrlCc_apbCc_io_input_PSLVERROR ), //o + .io_output_PADDR (withCtrlCc_apbCc_io_output_PADDR[13:0] ), //o + .io_output_PSEL (withCtrlCc_apbCc_io_output_PSEL ), //o + .io_output_PENABLE (withCtrlCc_apbCc_io_output_PENABLE ), //o + .io_output_PREADY (core_io_ctrl_PREADY ), //i + .io_output_PWRITE (withCtrlCc_apbCc_io_output_PWRITE ), //o + .io_output_PWDATA (withCtrlCc_apbCc_io_output_PWDATA[31:0]), //o + .io_output_PRDATA (core_io_ctrl_PRDATA[31:0] ), //i + .io_output_PSLVERROR (core_io_ctrl_PSLVERROR ), //i + .ctrl_clk (ctrl_clk ), //i + .ctrl_reset (ctrl_reset ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_6_a048ca8f51874147a1cd65d43e6523ef io_interrupts_buffercc ( + .io_dataIn (core_io_interrupts[1:0] ), //i + .io_dataOut (io_interrupts_buffercc_io_dataOut[1:0]), //o + .ctrl_clk (ctrl_clk ), //i + .ctrl_reset (ctrl_reset ) //i + ); + EfxDMA_BmbSourceRemover_a048ca8f51874147a1cd65d43e6523ef readLogic_sourceRemover ( + .io_input_cmd_valid (readLogic_resized_cmd_valid ), //i + .io_input_cmd_ready (readLogic_sourceRemover_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (readLogic_resized_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (readLogic_resized_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (readLogic_resized_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (readLogic_resized_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (readLogic_resized_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_context (readLogic_resized_cmd_payload_fragment_context[20:0] ), //i + .io_input_rsp_valid (readLogic_sourceRemover_io_input_rsp_valid ), //o + .io_input_rsp_ready (readLogic_resized_rsp_ready ), //i + .io_input_rsp_payload_last (readLogic_sourceRemover_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (readLogic_sourceRemover_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (readLogic_sourceRemover_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (readLogic_sourceRemover_io_input_rsp_payload_fragment_data[127:0] ), //o + .io_input_rsp_payload_fragment_context (readLogic_sourceRemover_io_input_rsp_payload_fragment_context[20:0] ), //o + .io_output_cmd_valid (readLogic_sourceRemover_io_output_cmd_valid ), //o + .io_output_cmd_ready (readLogic_bridge_io_input_cmd_ready ), //i + .io_output_cmd_payload_last (readLogic_sourceRemover_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (readLogic_sourceRemover_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (readLogic_sourceRemover_io_output_cmd_payload_fragment_address[31:0]), //o + .io_output_cmd_payload_fragment_length (readLogic_sourceRemover_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_cmd_payload_fragment_context (readLogic_sourceRemover_io_output_cmd_payload_fragment_context[21:0]), //o + .io_output_rsp_valid (readLogic_bridge_io_input_rsp_valid ), //i + .io_output_rsp_ready (readLogic_sourceRemover_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (readLogic_bridge_io_input_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (readLogic_bridge_io_input_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (readLogic_bridge_io_input_rsp_payload_fragment_data[127:0] ), //i + .io_output_rsp_payload_fragment_context (readLogic_bridge_io_input_rsp_payload_fragment_context[21:0] ) //i + ); + EfxDMA_BmbToAxi4ReadOnlyBridge_a048ca8f51874147a1cd65d43e6523ef readLogic_bridge ( + .io_input_cmd_valid (readLogic_sourceRemover_io_output_cmd_valid ), //i + .io_input_cmd_ready (readLogic_bridge_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (readLogic_sourceRemover_io_output_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (readLogic_sourceRemover_io_output_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (readLogic_sourceRemover_io_output_cmd_payload_fragment_address[31:0]), //i + .io_input_cmd_payload_fragment_length (readLogic_sourceRemover_io_output_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_context (readLogic_sourceRemover_io_output_cmd_payload_fragment_context[21:0]), //i + .io_input_rsp_valid (readLogic_bridge_io_input_rsp_valid ), //o + .io_input_rsp_ready (readLogic_sourceRemover_io_output_rsp_ready ), //i + .io_input_rsp_payload_last (readLogic_bridge_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (readLogic_bridge_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (readLogic_bridge_io_input_rsp_payload_fragment_data[127:0] ), //o + .io_input_rsp_payload_fragment_context (readLogic_bridge_io_input_rsp_payload_fragment_context[21:0] ), //o + .io_output_ar_valid (readLogic_bridge_io_output_ar_valid ), //o + .io_output_ar_ready (readLogic_adapter_ar_ready ), //i + .io_output_ar_payload_addr (readLogic_bridge_io_output_ar_payload_addr[31:0] ), //o + .io_output_ar_payload_len (readLogic_bridge_io_output_ar_payload_len[7:0] ), //o + .io_output_ar_payload_size (readLogic_bridge_io_output_ar_payload_size[2:0] ), //o + .io_output_ar_payload_cache (readLogic_bridge_io_output_ar_payload_cache[3:0] ), //o + .io_output_ar_payload_prot (readLogic_bridge_io_output_ar_payload_prot[2:0] ), //o + .io_output_r_valid (readLogic_adapter_r_valid ), //i + .io_output_r_ready (readLogic_bridge_io_output_r_ready ), //o + .io_output_r_payload_data (readLogic_adapter_r_payload_data[127:0] ), //i + .io_output_r_payload_resp (readLogic_adapter_r_payload_resp[1:0] ), //i + .io_output_r_payload_last (readLogic_adapter_r_payload_last ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_BmbSourceRemover_1_a048ca8f51874147a1cd65d43e6523ef writeLogic_sourceRemover ( + .io_input_cmd_valid (writeLogic_resized_cmd_valid ), //i + .io_input_cmd_ready (writeLogic_sourceRemover_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (writeLogic_resized_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (writeLogic_resized_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (writeLogic_resized_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (writeLogic_resized_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (writeLogic_resized_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_data (writeLogic_resized_cmd_payload_fragment_data[127:0] ), //i + .io_input_cmd_payload_fragment_mask (writeLogic_resized_cmd_payload_fragment_mask[15:0] ), //i + .io_input_cmd_payload_fragment_context (writeLogic_resized_cmd_payload_fragment_context[12:0] ), //i + .io_input_rsp_valid (writeLogic_sourceRemover_io_input_rsp_valid ), //o + .io_input_rsp_ready (writeLogic_resized_rsp_ready ), //i + .io_input_rsp_payload_last (writeLogic_sourceRemover_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (writeLogic_sourceRemover_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (writeLogic_sourceRemover_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_context (writeLogic_sourceRemover_io_input_rsp_payload_fragment_context[12:0] ), //o + .io_output_cmd_valid (writeLogic_sourceRemover_io_output_cmd_valid ), //o + .io_output_cmd_ready (writeLogic_bridge_io_input_cmd_ready ), //i + .io_output_cmd_payload_last (writeLogic_sourceRemover_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (writeLogic_sourceRemover_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (writeLogic_sourceRemover_io_output_cmd_payload_fragment_address[31:0]), //o + .io_output_cmd_payload_fragment_length (writeLogic_sourceRemover_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_cmd_payload_fragment_data (writeLogic_sourceRemover_io_output_cmd_payload_fragment_data[127:0] ), //o + .io_output_cmd_payload_fragment_mask (writeLogic_sourceRemover_io_output_cmd_payload_fragment_mask[15:0] ), //o + .io_output_cmd_payload_fragment_context (writeLogic_sourceRemover_io_output_cmd_payload_fragment_context[13:0]), //o + .io_output_rsp_valid (writeLogic_bridge_io_input_rsp_valid ), //i + .io_output_rsp_ready (writeLogic_sourceRemover_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (writeLogic_bridge_io_input_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (writeLogic_bridge_io_input_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_context (writeLogic_bridge_io_input_rsp_payload_fragment_context[13:0] ) //i + ); + EfxDMA_BmbToAxi4WriteOnlyBridge_a048ca8f51874147a1cd65d43e6523ef writeLogic_bridge ( + .io_input_cmd_valid (writeLogic_sourceRemover_io_output_cmd_valid ), //i + .io_input_cmd_ready (writeLogic_bridge_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (writeLogic_sourceRemover_io_output_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (writeLogic_sourceRemover_io_output_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (writeLogic_sourceRemover_io_output_cmd_payload_fragment_address[31:0]), //i + .io_input_cmd_payload_fragment_length (writeLogic_sourceRemover_io_output_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_data (writeLogic_sourceRemover_io_output_cmd_payload_fragment_data[127:0] ), //i + .io_input_cmd_payload_fragment_mask (writeLogic_sourceRemover_io_output_cmd_payload_fragment_mask[15:0] ), //i + .io_input_cmd_payload_fragment_context (writeLogic_sourceRemover_io_output_cmd_payload_fragment_context[13:0]), //i + .io_input_rsp_valid (writeLogic_bridge_io_input_rsp_valid ), //o + .io_input_rsp_ready (writeLogic_sourceRemover_io_output_rsp_ready ), //i + .io_input_rsp_payload_last (writeLogic_bridge_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (writeLogic_bridge_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_context (writeLogic_bridge_io_input_rsp_payload_fragment_context[13:0] ), //o + .io_output_aw_valid (writeLogic_bridge_io_output_aw_valid ), //o + .io_output_aw_ready (writeLogic_adapter_aw_ready ), //i + .io_output_aw_payload_addr (writeLogic_bridge_io_output_aw_payload_addr[31:0] ), //o + .io_output_aw_payload_len (writeLogic_bridge_io_output_aw_payload_len[7:0] ), //o + .io_output_aw_payload_size (writeLogic_bridge_io_output_aw_payload_size[2:0] ), //o + .io_output_aw_payload_cache (writeLogic_bridge_io_output_aw_payload_cache[3:0] ), //o + .io_output_aw_payload_prot (writeLogic_bridge_io_output_aw_payload_prot[2:0] ), //o + .io_output_w_valid (writeLogic_bridge_io_output_w_valid ), //o + .io_output_w_ready (writeLogic_adapter_w_ready ), //i + .io_output_w_payload_data (writeLogic_bridge_io_output_w_payload_data[127:0] ), //o + .io_output_w_payload_strb (writeLogic_bridge_io_output_w_payload_strb[15:0] ), //o + .io_output_w_payload_last (writeLogic_bridge_io_output_w_payload_last ), //o + .io_output_b_valid (writeLogic_adapter_b_valid ), //i + .io_output_b_ready (writeLogic_bridge_io_output_b_ready ), //o + .io_output_b_payload_resp (writeLogic_adapter_b_payload_resp[1:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_BsbUpSizerDense_a048ca8f51874147a1cd65d43e6523ef inputsAdapter_0_upsizer_logic ( + .io_input_valid (dat0_i_tvalid ), //i + .io_input_ready (inputsAdapter_0_upsizer_logic_io_input_ready ), //o + .io_input_payload_data (dat0_i_tdata[7:0] ), //i + .io_input_payload_mask (dat0_i_tkeep ), //i + .io_input_payload_sink (dat0_i_tdest[3:0] ), //i + .io_input_payload_last (dat0_i_tlast ), //i + .io_output_valid (inputsAdapter_0_upsizer_logic_io_output_valid ), //o + .io_output_ready (inputsAdapter_0_crossclock_fifo_io_push_ready ), //i + .io_output_payload_data (inputsAdapter_0_upsizer_logic_io_output_payload_data[63:0]), //o + .io_output_payload_mask (inputsAdapter_0_upsizer_logic_io_output_payload_mask[7:0] ), //o + .io_output_payload_sink (inputsAdapter_0_upsizer_logic_io_output_payload_sink[3:0] ), //o + .io_output_payload_last (inputsAdapter_0_upsizer_logic_io_output_payload_last ), //o + .dat0_i_clk (dat0_i_clk ), //i + .dat0_i_reset (dat0_i_reset ) //i + ); + EfxDMA_StreamFifoCC_a048ca8f51874147a1cd65d43e6523ef inputsAdapter_0_crossclock_fifo ( + .io_push_valid (inputsAdapter_0_upsizer_logic_io_output_valid ), //i + .io_push_ready (inputsAdapter_0_crossclock_fifo_io_push_ready ), //o + .io_push_payload_data (inputsAdapter_0_upsizer_logic_io_output_payload_data[63:0]), //i + .io_push_payload_mask (inputsAdapter_0_upsizer_logic_io_output_payload_mask[7:0] ), //i + .io_push_payload_sink (inputsAdapter_0_upsizer_logic_io_output_payload_sink[3:0] ), //i + .io_push_payload_last (inputsAdapter_0_upsizer_logic_io_output_payload_last ), //i + .io_pop_valid (inputsAdapter_0_crossclock_fifo_io_pop_valid ), //o + .io_pop_ready (io_pop_rValidN ), //i + .io_pop_payload_data (inputsAdapter_0_crossclock_fifo_io_pop_payload_data[63:0] ), //o + .io_pop_payload_mask (inputsAdapter_0_crossclock_fifo_io_pop_payload_mask[7:0] ), //o + .io_pop_payload_sink (inputsAdapter_0_crossclock_fifo_io_pop_payload_sink[3:0] ), //o + .io_pop_payload_last (inputsAdapter_0_crossclock_fifo_io_pop_payload_last ), //o + .io_pushOccupancy (inputsAdapter_0_crossclock_fifo_io_pushOccupancy[4:0] ), //o + .io_popOccupancy (inputsAdapter_0_crossclock_fifo_io_popOccupancy[4:0] ), //o + .dat0_i_clk (dat0_i_clk ), //i + .dat0_i_reset (dat0_i_reset ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_StreamFifoCC_1_a048ca8f51874147a1cd65d43e6523ef outputsAdapter_0_crossclock_fifo ( + .io_push_valid (outputsAdapter_0_ptr_valid ), //i + .io_push_ready (outputsAdapter_0_crossclock_fifo_io_push_ready ), //o + .io_push_payload_data (outputsAdapter_0_ptr_payload_data[63:0] ), //i + .io_push_payload_mask (outputsAdapter_0_ptr_payload_mask[7:0] ), //i + .io_push_payload_sink (outputsAdapter_0_ptr_payload_sink[3:0] ), //i + .io_push_payload_last (outputsAdapter_0_ptr_payload_last ), //i + .io_pop_valid (outputsAdapter_0_crossclock_fifo_io_pop_valid ), //o + .io_pop_ready (outputsAdapter_0_sparseDownsizer_logic_io_input_ready ), //i + .io_pop_payload_data (outputsAdapter_0_crossclock_fifo_io_pop_payload_data[63:0]), //o + .io_pop_payload_mask (outputsAdapter_0_crossclock_fifo_io_pop_payload_mask[7:0] ), //o + .io_pop_payload_sink (outputsAdapter_0_crossclock_fifo_io_pop_payload_sink[3:0] ), //o + .io_pop_payload_last (outputsAdapter_0_crossclock_fifo_io_pop_payload_last ), //o + .io_pushOccupancy (outputsAdapter_0_crossclock_fifo_io_pushOccupancy[4:0] ), //o + .io_popOccupancy (outputsAdapter_0_crossclock_fifo_io_popOccupancy[4:0] ), //o + .clk (clk ), //i + .reset (reset ), //i + .dat1_o_clk (dat1_o_clk ), //i + .dat1_o_reset (dat1_o_reset ) //i + ); + EfxDMA_BsbDownSizerSparse_a048ca8f51874147a1cd65d43e6523ef outputsAdapter_0_sparseDownsizer_logic ( + .io_input_valid (outputsAdapter_0_crossclock_fifo_io_pop_valid ), //i + .io_input_ready (outputsAdapter_0_sparseDownsizer_logic_io_input_ready ), //o + .io_input_payload_data (outputsAdapter_0_crossclock_fifo_io_pop_payload_data[63:0] ), //i + .io_input_payload_mask (outputsAdapter_0_crossclock_fifo_io_pop_payload_mask[7:0] ), //i + .io_input_payload_sink (outputsAdapter_0_crossclock_fifo_io_pop_payload_sink[3:0] ), //i + .io_input_payload_last (outputsAdapter_0_crossclock_fifo_io_pop_payload_last ), //i + .io_output_valid (outputsAdapter_0_sparseDownsizer_logic_io_output_valid ), //o + .io_output_ready (dat1_o_tready ), //i + .io_output_payload_data (outputsAdapter_0_sparseDownsizer_logic_io_output_payload_data[7:0]), //o + .io_output_payload_mask (outputsAdapter_0_sparseDownsizer_logic_io_output_payload_mask ), //o + .io_output_payload_sink (outputsAdapter_0_sparseDownsizer_logic_io_output_payload_sink[3:0]), //o + .io_output_payload_last (outputsAdapter_0_sparseDownsizer_logic_io_output_payload_last ), //o + .dat1_o_clk (dat1_o_clk ), //i + .dat1_o_reset (dat1_o_reset ) //i + ); + EfxDMA_BmbArbiter_a048ca8f51874147a1cd65d43e6523ef interconnect_read_aggregated_arbiter ( + .io_inputs_0_cmd_valid (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid ), //i + .io_inputs_0_cmd_ready (interconnect_read_aggregated_arbiter_io_inputs_0_cmd_ready ), //o + .io_inputs_0_cmd_payload_last (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last ), //i + .io_inputs_0_cmd_payload_fragment_opcode (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode ), //i + .io_inputs_0_cmd_payload_fragment_address (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address[31:0]), //i + .io_inputs_0_cmd_payload_fragment_length (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length[4:0] ), //i + .io_inputs_0_cmd_payload_fragment_context (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context ), //i + .io_inputs_0_rsp_valid (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_valid ), //o + .io_inputs_0_rsp_ready (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready ), //i + .io_inputs_0_rsp_payload_last (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_last ), //o + .io_inputs_0_rsp_payload_fragment_opcode (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode ), //o + .io_inputs_0_rsp_payload_fragment_data (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_data[127:0] ), //o + .io_inputs_0_rsp_payload_fragment_context (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context ), //o + .io_inputs_1_cmd_valid (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid ), //i + .io_inputs_1_cmd_ready (interconnect_read_aggregated_arbiter_io_inputs_1_cmd_ready ), //o + .io_inputs_1_cmd_payload_last (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last ), //i + .io_inputs_1_cmd_payload_fragment_opcode (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode ), //i + .io_inputs_1_cmd_payload_fragment_address (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address[31:0]), //i + .io_inputs_1_cmd_payload_fragment_length (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length[11:0] ), //i + .io_inputs_1_cmd_payload_fragment_context (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context[20:0]), //i + .io_inputs_1_rsp_valid (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_valid ), //o + .io_inputs_1_rsp_ready (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready ), //i + .io_inputs_1_rsp_payload_last (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_last ), //o + .io_inputs_1_rsp_payload_fragment_opcode (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //o + .io_inputs_1_rsp_payload_fragment_data (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_data[127:0] ), //o + .io_inputs_1_rsp_payload_fragment_context (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context[20:0] ), //o + .io_output_cmd_valid (interconnect_read_aggregated_arbiter_io_output_cmd_valid ), //o + .io_output_cmd_ready (interconnect_read_aggregated_cmd_ready ), //i + .io_output_cmd_payload_last (interconnect_read_aggregated_arbiter_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_source (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_source ), //o + .io_output_cmd_payload_fragment_opcode (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_cmd_payload_fragment_context (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_context[20:0] ), //o + .io_output_rsp_valid (interconnect_read_aggregated_rsp_valid ), //i + .io_output_rsp_ready (interconnect_read_aggregated_arbiter_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (interconnect_read_aggregated_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_source (interconnect_read_aggregated_rsp_payload_fragment_source ), //i + .io_output_rsp_payload_fragment_opcode (interconnect_read_aggregated_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (interconnect_read_aggregated_rsp_payload_fragment_data[127:0] ), //i + .io_output_rsp_payload_fragment_context (interconnect_read_aggregated_rsp_payload_fragment_context[20:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_BmbArbiter_1_a048ca8f51874147a1cd65d43e6523ef interconnect_write_aggregated_arbiter ( + .io_inputs_0_cmd_valid (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid ), //i + .io_inputs_0_cmd_ready (interconnect_write_aggregated_arbiter_io_inputs_0_cmd_ready ), //o + .io_inputs_0_cmd_payload_last (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last ), //i + .io_inputs_0_cmd_payload_fragment_opcode (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode ), //i + .io_inputs_0_cmd_payload_fragment_address (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address[31:0]), //i + .io_inputs_0_cmd_payload_fragment_length (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length[1:0] ), //i + .io_inputs_0_cmd_payload_fragment_data (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data[127:0] ), //i + .io_inputs_0_cmd_payload_fragment_mask (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask[15:0] ), //i + .io_inputs_0_cmd_payload_fragment_context (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context ), //i + .io_inputs_0_rsp_valid (interconnect_write_aggregated_arbiter_io_inputs_0_rsp_valid ), //o + .io_inputs_0_rsp_ready (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready ), //i + .io_inputs_0_rsp_payload_last (interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_last ), //o + .io_inputs_0_rsp_payload_fragment_opcode (interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode ), //o + .io_inputs_0_rsp_payload_fragment_context (interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context ), //o + .io_inputs_1_cmd_valid (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid ), //i + .io_inputs_1_cmd_ready (interconnect_write_aggregated_arbiter_io_inputs_1_cmd_ready ), //o + .io_inputs_1_cmd_payload_last (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last ), //i + .io_inputs_1_cmd_payload_fragment_opcode (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode ), //i + .io_inputs_1_cmd_payload_fragment_address (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address[31:0]), //i + .io_inputs_1_cmd_payload_fragment_length (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length[11:0] ), //i + .io_inputs_1_cmd_payload_fragment_data (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_data[127:0] ), //i + .io_inputs_1_cmd_payload_fragment_mask (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_mask[15:0] ), //i + .io_inputs_1_cmd_payload_fragment_context (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context[12:0]), //i + .io_inputs_1_rsp_valid (interconnect_write_aggregated_arbiter_io_inputs_1_rsp_valid ), //o + .io_inputs_1_rsp_ready (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready ), //i + .io_inputs_1_rsp_payload_last (interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_last ), //o + .io_inputs_1_rsp_payload_fragment_opcode (interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //o + .io_inputs_1_rsp_payload_fragment_context (interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context[12:0] ), //o + .io_output_cmd_valid (interconnect_write_aggregated_arbiter_io_output_cmd_valid ), //o + .io_output_cmd_ready (interconnect_write_aggregated_cmd_ready ), //i + .io_output_cmd_payload_last (interconnect_write_aggregated_arbiter_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_source (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_source ), //o + .io_output_cmd_payload_fragment_opcode (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_cmd_payload_fragment_data (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_data[127:0] ), //o + .io_output_cmd_payload_fragment_mask (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_mask[15:0] ), //o + .io_output_cmd_payload_fragment_context (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_context[12:0] ), //o + .io_output_rsp_valid (interconnect_write_aggregated_rsp_valid ), //i + .io_output_rsp_ready (interconnect_write_aggregated_arbiter_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (interconnect_write_aggregated_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_source (interconnect_write_aggregated_rsp_payload_fragment_source ), //i + .io_output_rsp_payload_fragment_opcode (interconnect_write_aggregated_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_context (interconnect_write_aggregated_rsp_payload_fragment_context[12:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign io_0_descriptorUpdate = core_ll_0_descriptorUpdate; + assign io_1_descriptorUpdate = core_ll_1_descriptorUpdate; + assign ctrl_PREADY = withCtrlCc_apbCc_io_input_PREADY; + assign ctrl_PRDATA = withCtrlCc_apbCc_io_input_PRDATA; + assign ctrl_PSLVERROR = withCtrlCc_apbCc_io_input_PSLVERROR; + assign ctrl_interrupts = io_interrupts_buffercc_io_dataOut; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid = core_io_read_cmd_valid; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready = core_io_read_rsp_ready; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last = core_io_read_cmd_payload_last; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode = core_io_read_cmd_payload_fragment_opcode; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address = core_io_read_cmd_payload_fragment_address; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length = core_io_read_cmd_payload_fragment_length; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context = core_io_read_cmd_payload_fragment_context; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid = core_io_sgRead_cmd_valid; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready = core_io_sgRead_rsp_ready; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last = core_io_sgRead_cmd_payload_last; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode = core_io_sgRead_cmd_payload_fragment_opcode; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address = core_io_sgRead_cmd_payload_fragment_address; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length = core_io_sgRead_cmd_payload_fragment_length; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context = core_io_sgRead_cmd_payload_fragment_context; + assign io_write_cmd_s2mPipe_valid = (core_io_write_cmd_valid || (! io_write_cmd_rValidN)); + assign io_write_cmd_s2mPipe_payload_last = (io_write_cmd_rValidN ? core_io_write_cmd_payload_last : io_write_cmd_rData_last); + assign io_write_cmd_s2mPipe_payload_fragment_opcode = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_opcode : io_write_cmd_rData_fragment_opcode); + assign io_write_cmd_s2mPipe_payload_fragment_address = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_address : io_write_cmd_rData_fragment_address); + assign io_write_cmd_s2mPipe_payload_fragment_length = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_length : io_write_cmd_rData_fragment_length); + assign io_write_cmd_s2mPipe_payload_fragment_data = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_data : io_write_cmd_rData_fragment_data); + assign io_write_cmd_s2mPipe_payload_fragment_mask = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_mask : io_write_cmd_rData_fragment_mask); + assign io_write_cmd_s2mPipe_payload_fragment_context = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_context : io_write_cmd_rData_fragment_context); + always @(*) begin + io_write_cmd_s2mPipe_ready = io_write_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l375) begin + io_write_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! io_write_cmd_s2mPipe_m2sPipe_valid); + assign io_write_cmd_s2mPipe_m2sPipe_valid = io_write_cmd_s2mPipe_rValid; + assign io_write_cmd_s2mPipe_m2sPipe_payload_last = io_write_cmd_s2mPipe_rData_last; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_opcode = io_write_cmd_s2mPipe_rData_fragment_opcode; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_address = io_write_cmd_s2mPipe_rData_fragment_address; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_length = io_write_cmd_s2mPipe_rData_fragment_length; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_data = io_write_cmd_s2mPipe_rData_fragment_data; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_mask = io_write_cmd_s2mPipe_rData_fragment_mask; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_context = io_write_cmd_s2mPipe_rData_fragment_context; + assign io_write_cmd_s2mPipe_m2sPipe_ready = interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid = io_write_cmd_s2mPipe_m2sPipe_valid; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready = core_io_write_rsp_ready; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last = io_write_cmd_s2mPipe_m2sPipe_payload_last; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_opcode; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_address; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_length; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_data = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_data; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_mask = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_mask; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_context; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid = core_io_sgWrite_cmd_valid; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready = core_io_sgWrite_rsp_ready; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last = core_io_sgWrite_cmd_payload_last; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode = core_io_sgWrite_cmd_payload_fragment_opcode; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address = core_io_sgWrite_cmd_payload_fragment_address; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length = core_io_sgWrite_cmd_payload_fragment_length; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data = core_io_sgWrite_cmd_payload_fragment_data; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask = core_io_sgWrite_cmd_payload_fragment_mask; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context = core_io_sgWrite_cmd_payload_fragment_context; + assign interconnect_read_aggregated_cmd_halfPipe_fire = (interconnect_read_aggregated_cmd_halfPipe_valid && interconnect_read_aggregated_cmd_halfPipe_ready); + assign interconnect_read_aggregated_cmd_ready = (! interconnect_read_aggregated_cmd_rValid); + assign interconnect_read_aggregated_cmd_halfPipe_valid = interconnect_read_aggregated_cmd_rValid; + assign interconnect_read_aggregated_cmd_halfPipe_payload_last = interconnect_read_aggregated_cmd_rData_last; + assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_source = interconnect_read_aggregated_cmd_rData_fragment_source; + assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_opcode = interconnect_read_aggregated_cmd_rData_fragment_opcode; + assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_address = interconnect_read_aggregated_cmd_rData_fragment_address; + assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_length = interconnect_read_aggregated_cmd_rData_fragment_length; + assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_context = interconnect_read_aggregated_cmd_rData_fragment_context; + assign readLogic_resized_cmd_valid = interconnect_read_aggregated_cmd_halfPipe_valid; + assign interconnect_read_aggregated_cmd_halfPipe_ready = readLogic_resized_cmd_ready; + assign readLogic_resized_cmd_payload_last = interconnect_read_aggregated_cmd_halfPipe_payload_last; + assign readLogic_resized_cmd_payload_fragment_source = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_source; + assign readLogic_resized_cmd_payload_fragment_opcode = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_opcode; + assign readLogic_resized_cmd_payload_fragment_address = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_address; + assign readLogic_resized_cmd_payload_fragment_length = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_length; + assign readLogic_resized_cmd_payload_fragment_context = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_context; + assign readLogic_resized_rsp_combStage_valid = readLogic_resized_rsp_valid; + assign readLogic_resized_rsp_ready = readLogic_resized_rsp_combStage_ready; + assign readLogic_resized_rsp_combStage_payload_last = readLogic_resized_rsp_payload_last; + assign readLogic_resized_rsp_combStage_payload_fragment_source = readLogic_resized_rsp_payload_fragment_source; + assign readLogic_resized_rsp_combStage_payload_fragment_opcode = readLogic_resized_rsp_payload_fragment_opcode; + assign readLogic_resized_rsp_combStage_payload_fragment_data = readLogic_resized_rsp_payload_fragment_data; + assign readLogic_resized_rsp_combStage_payload_fragment_context = readLogic_resized_rsp_payload_fragment_context; + assign interconnect_read_aggregated_rsp_valid = readLogic_resized_rsp_combStage_valid; + assign readLogic_resized_rsp_combStage_ready = interconnect_read_aggregated_rsp_ready; + assign interconnect_read_aggregated_rsp_payload_last = readLogic_resized_rsp_combStage_payload_last; + assign interconnect_read_aggregated_rsp_payload_fragment_source = readLogic_resized_rsp_combStage_payload_fragment_source; + assign interconnect_read_aggregated_rsp_payload_fragment_opcode = readLogic_resized_rsp_combStage_payload_fragment_opcode; + assign interconnect_read_aggregated_rsp_payload_fragment_data = readLogic_resized_rsp_combStage_payload_fragment_data; + assign interconnect_read_aggregated_rsp_payload_fragment_context = readLogic_resized_rsp_combStage_payload_fragment_context; + assign readLogic_resized_cmd_ready = readLogic_sourceRemover_io_input_cmd_ready; + assign readLogic_resized_rsp_valid = readLogic_sourceRemover_io_input_rsp_valid; + assign readLogic_resized_rsp_payload_last = readLogic_sourceRemover_io_input_rsp_payload_last; + assign readLogic_resized_rsp_payload_fragment_source = readLogic_sourceRemover_io_input_rsp_payload_fragment_source; + assign readLogic_resized_rsp_payload_fragment_opcode = readLogic_sourceRemover_io_input_rsp_payload_fragment_opcode; + assign readLogic_resized_rsp_payload_fragment_data = readLogic_sourceRemover_io_input_rsp_payload_fragment_data; + assign readLogic_resized_rsp_payload_fragment_context = readLogic_sourceRemover_io_input_rsp_payload_fragment_context; + assign readLogic_adapter_ar_valid = readLogic_bridge_io_output_ar_valid; + assign readLogic_adapter_ar_payload_addr = readLogic_bridge_io_output_ar_payload_addr; + assign _zz_readLogic_adapter_ar_payload_region[3 : 0] = 4'b0000; + assign readLogic_adapter_ar_payload_region = _zz_readLogic_adapter_ar_payload_region; + assign readLogic_adapter_ar_payload_len = readLogic_bridge_io_output_ar_payload_len; + assign readLogic_adapter_ar_payload_size = readLogic_bridge_io_output_ar_payload_size; + assign readLogic_adapter_ar_payload_burst = 2'b01; + assign readLogic_adapter_ar_payload_lock = 1'b0; + assign readLogic_adapter_ar_payload_cache = readLogic_bridge_io_output_ar_payload_cache; + assign readLogic_adapter_ar_payload_qos = 4'b0000; + assign readLogic_adapter_ar_payload_prot = readLogic_bridge_io_output_ar_payload_prot; + assign readLogic_adapter_r_ready = readLogic_bridge_io_output_r_ready; + assign readLogic_adapter_ar_halfPipe_fire = (readLogic_adapter_ar_halfPipe_valid && readLogic_adapter_ar_halfPipe_ready); + assign readLogic_adapter_ar_ready = (! readLogic_adapter_ar_rValid); + assign readLogic_adapter_ar_halfPipe_valid = readLogic_adapter_ar_rValid; + assign readLogic_adapter_ar_halfPipe_payload_addr = readLogic_adapter_ar_rData_addr; + assign readLogic_adapter_ar_halfPipe_payload_region = readLogic_adapter_ar_rData_region; + assign readLogic_adapter_ar_halfPipe_payload_len = readLogic_adapter_ar_rData_len; + assign readLogic_adapter_ar_halfPipe_payload_size = readLogic_adapter_ar_rData_size; + assign readLogic_adapter_ar_halfPipe_payload_burst = readLogic_adapter_ar_rData_burst; + assign readLogic_adapter_ar_halfPipe_payload_lock = readLogic_adapter_ar_rData_lock; + assign readLogic_adapter_ar_halfPipe_payload_cache = readLogic_adapter_ar_rData_cache; + assign readLogic_adapter_ar_halfPipe_payload_qos = readLogic_adapter_ar_rData_qos; + assign readLogic_adapter_ar_halfPipe_payload_prot = readLogic_adapter_ar_rData_prot; + assign read_arvalid = readLogic_adapter_ar_halfPipe_valid; + assign readLogic_adapter_ar_halfPipe_ready = read_arready; + assign read_araddr = readLogic_adapter_ar_halfPipe_payload_addr; + assign read_arregion = readLogic_adapter_ar_halfPipe_payload_region; + assign read_arlen = readLogic_adapter_ar_halfPipe_payload_len; + assign read_arsize = readLogic_adapter_ar_halfPipe_payload_size; + assign read_arburst = readLogic_adapter_ar_halfPipe_payload_burst; + assign read_arlock = readLogic_adapter_ar_halfPipe_payload_lock; + assign read_arcache = readLogic_adapter_ar_halfPipe_payload_cache; + assign read_arqos = readLogic_adapter_ar_halfPipe_payload_qos; + assign read_arprot = readLogic_adapter_ar_halfPipe_payload_prot; + assign read_rready = read_r_rValidN; + assign read_r_s2mPipe_valid = (read_rvalid || (! read_r_rValidN)); + assign read_r_s2mPipe_payload_data = (read_r_rValidN ? read_rdata : read_r_rData_data); + assign read_r_s2mPipe_payload_resp = (read_r_rValidN ? read_rresp : read_r_rData_resp); + assign read_r_s2mPipe_payload_last = (read_r_rValidN ? read_rlast : read_r_rData_last); + always @(*) begin + read_r_s2mPipe_ready = readLogic_beforeQueue_ready; + if(when_Stream_l375_1) begin + read_r_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375_1 = (! readLogic_beforeQueue_valid); + assign readLogic_beforeQueue_valid = read_r_s2mPipe_rValid; + assign readLogic_beforeQueue_payload_data = read_r_s2mPipe_rData_data; + assign readLogic_beforeQueue_payload_resp = read_r_s2mPipe_rData_resp; + assign readLogic_beforeQueue_payload_last = read_r_s2mPipe_rData_last; + assign readLogic_adapter_r_valid = readLogic_beforeQueue_valid; + assign readLogic_beforeQueue_ready = readLogic_adapter_r_ready; + assign readLogic_adapter_r_payload_data = readLogic_beforeQueue_payload_data; + assign readLogic_adapter_r_payload_resp = readLogic_beforeQueue_payload_resp; + assign readLogic_adapter_r_payload_last = readLogic_beforeQueue_payload_last; + always @(*) begin + interconnect_write_aggregated_cmd_ready = interconnect_write_aggregated_cmd_m2sPipe_ready; + if(when_Stream_l375_2) begin + interconnect_write_aggregated_cmd_ready = 1'b1; + end + end + + assign when_Stream_l375_2 = (! interconnect_write_aggregated_cmd_m2sPipe_valid); + assign interconnect_write_aggregated_cmd_m2sPipe_valid = interconnect_write_aggregated_cmd_rValid; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_last = interconnect_write_aggregated_cmd_rData_last; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_source = interconnect_write_aggregated_cmd_rData_fragment_source; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_opcode = interconnect_write_aggregated_cmd_rData_fragment_opcode; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_address = interconnect_write_aggregated_cmd_rData_fragment_address; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_length = interconnect_write_aggregated_cmd_rData_fragment_length; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_data = interconnect_write_aggregated_cmd_rData_fragment_data; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_mask = interconnect_write_aggregated_cmd_rData_fragment_mask; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_context = interconnect_write_aggregated_cmd_rData_fragment_context; + assign writeLogic_resized_cmd_valid = interconnect_write_aggregated_cmd_m2sPipe_valid; + assign interconnect_write_aggregated_cmd_m2sPipe_ready = writeLogic_resized_cmd_ready; + assign writeLogic_resized_cmd_payload_last = interconnect_write_aggregated_cmd_m2sPipe_payload_last; + assign writeLogic_resized_cmd_payload_fragment_source = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_source; + assign writeLogic_resized_cmd_payload_fragment_opcode = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_opcode; + assign writeLogic_resized_cmd_payload_fragment_address = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_address; + assign writeLogic_resized_cmd_payload_fragment_length = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_length; + assign writeLogic_resized_cmd_payload_fragment_data = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_data; + assign writeLogic_resized_cmd_payload_fragment_mask = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_mask; + assign writeLogic_resized_cmd_payload_fragment_context = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_context; + assign writeLogic_resized_rsp_combStage_valid = writeLogic_resized_rsp_valid; + assign writeLogic_resized_rsp_ready = writeLogic_resized_rsp_combStage_ready; + assign writeLogic_resized_rsp_combStage_payload_last = writeLogic_resized_rsp_payload_last; + assign writeLogic_resized_rsp_combStage_payload_fragment_source = writeLogic_resized_rsp_payload_fragment_source; + assign writeLogic_resized_rsp_combStage_payload_fragment_opcode = writeLogic_resized_rsp_payload_fragment_opcode; + assign writeLogic_resized_rsp_combStage_payload_fragment_context = writeLogic_resized_rsp_payload_fragment_context; + assign interconnect_write_aggregated_rsp_valid = writeLogic_resized_rsp_combStage_valid; + assign writeLogic_resized_rsp_combStage_ready = interconnect_write_aggregated_rsp_ready; + assign interconnect_write_aggregated_rsp_payload_last = writeLogic_resized_rsp_combStage_payload_last; + assign interconnect_write_aggregated_rsp_payload_fragment_source = writeLogic_resized_rsp_combStage_payload_fragment_source; + assign interconnect_write_aggregated_rsp_payload_fragment_opcode = writeLogic_resized_rsp_combStage_payload_fragment_opcode; + assign interconnect_write_aggregated_rsp_payload_fragment_context = writeLogic_resized_rsp_combStage_payload_fragment_context; + assign writeLogic_resized_cmd_ready = writeLogic_sourceRemover_io_input_cmd_ready; + assign writeLogic_resized_rsp_valid = writeLogic_sourceRemover_io_input_rsp_valid; + assign writeLogic_resized_rsp_payload_last = writeLogic_sourceRemover_io_input_rsp_payload_last; + assign writeLogic_resized_rsp_payload_fragment_source = writeLogic_sourceRemover_io_input_rsp_payload_fragment_source; + assign writeLogic_resized_rsp_payload_fragment_opcode = writeLogic_sourceRemover_io_input_rsp_payload_fragment_opcode; + assign writeLogic_resized_rsp_payload_fragment_context = writeLogic_sourceRemover_io_input_rsp_payload_fragment_context; + assign writeLogic_adapter_aw_valid = writeLogic_bridge_io_output_aw_valid; + assign writeLogic_adapter_aw_payload_addr = writeLogic_bridge_io_output_aw_payload_addr; + assign _zz_writeLogic_adapter_aw_payload_region[3 : 0] = 4'b0000; + assign writeLogic_adapter_aw_payload_region = _zz_writeLogic_adapter_aw_payload_region; + assign writeLogic_adapter_aw_payload_len = writeLogic_bridge_io_output_aw_payload_len; + assign writeLogic_adapter_aw_payload_size = writeLogic_bridge_io_output_aw_payload_size; + assign writeLogic_adapter_aw_payload_burst = 2'b01; + assign writeLogic_adapter_aw_payload_lock = 1'b0; + assign writeLogic_adapter_aw_payload_cache = writeLogic_bridge_io_output_aw_payload_cache; + assign writeLogic_adapter_aw_payload_qos = 4'b0000; + assign writeLogic_adapter_aw_payload_prot = writeLogic_bridge_io_output_aw_payload_prot; + assign writeLogic_adapter_w_valid = writeLogic_bridge_io_output_w_valid; + assign writeLogic_adapter_w_payload_data = writeLogic_bridge_io_output_w_payload_data; + assign writeLogic_adapter_w_payload_strb = writeLogic_bridge_io_output_w_payload_strb; + assign writeLogic_adapter_w_payload_last = writeLogic_bridge_io_output_w_payload_last; + assign writeLogic_adapter_b_ready = writeLogic_bridge_io_output_b_ready; + assign writeLogic_adapter_aw_halfPipe_fire = (writeLogic_adapter_aw_halfPipe_valid && writeLogic_adapter_aw_halfPipe_ready); + assign writeLogic_adapter_aw_ready = (! writeLogic_adapter_aw_rValid); + assign writeLogic_adapter_aw_halfPipe_valid = writeLogic_adapter_aw_rValid; + assign writeLogic_adapter_aw_halfPipe_payload_addr = writeLogic_adapter_aw_rData_addr; + assign writeLogic_adapter_aw_halfPipe_payload_region = writeLogic_adapter_aw_rData_region; + assign writeLogic_adapter_aw_halfPipe_payload_len = writeLogic_adapter_aw_rData_len; + assign writeLogic_adapter_aw_halfPipe_payload_size = writeLogic_adapter_aw_rData_size; + assign writeLogic_adapter_aw_halfPipe_payload_burst = writeLogic_adapter_aw_rData_burst; + assign writeLogic_adapter_aw_halfPipe_payload_lock = writeLogic_adapter_aw_rData_lock; + assign writeLogic_adapter_aw_halfPipe_payload_cache = writeLogic_adapter_aw_rData_cache; + assign writeLogic_adapter_aw_halfPipe_payload_qos = writeLogic_adapter_aw_rData_qos; + assign writeLogic_adapter_aw_halfPipe_payload_prot = writeLogic_adapter_aw_rData_prot; + assign write_awvalid = writeLogic_adapter_aw_halfPipe_valid; + assign writeLogic_adapter_aw_halfPipe_ready = write_awready; + assign write_awaddr = writeLogic_adapter_aw_halfPipe_payload_addr; + assign write_awregion = writeLogic_adapter_aw_halfPipe_payload_region; + assign write_awlen = writeLogic_adapter_aw_halfPipe_payload_len; + assign write_awsize = writeLogic_adapter_aw_halfPipe_payload_size; + assign write_awburst = writeLogic_adapter_aw_halfPipe_payload_burst; + assign write_awlock = writeLogic_adapter_aw_halfPipe_payload_lock; + assign write_awcache = writeLogic_adapter_aw_halfPipe_payload_cache; + assign write_awqos = writeLogic_adapter_aw_halfPipe_payload_qos; + assign write_awprot = writeLogic_adapter_aw_halfPipe_payload_prot; + assign writeLogic_adapter_w_ready = writeLogic_adapter_w_rValidN; + assign writeLogic_adapter_w_s2mPipe_valid = (writeLogic_adapter_w_valid || (! writeLogic_adapter_w_rValidN)); + assign writeLogic_adapter_w_s2mPipe_payload_data = (writeLogic_adapter_w_rValidN ? writeLogic_adapter_w_payload_data : writeLogic_adapter_w_rData_data); + assign writeLogic_adapter_w_s2mPipe_payload_strb = (writeLogic_adapter_w_rValidN ? writeLogic_adapter_w_payload_strb : writeLogic_adapter_w_rData_strb); + assign writeLogic_adapter_w_s2mPipe_payload_last = (writeLogic_adapter_w_rValidN ? writeLogic_adapter_w_payload_last : writeLogic_adapter_w_rData_last); + always @(*) begin + writeLogic_adapter_w_s2mPipe_ready = writeLogic_adapter_w_s2mPipe_m2sPipe_ready; + if(when_Stream_l375_3) begin + writeLogic_adapter_w_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375_3 = (! writeLogic_adapter_w_s2mPipe_m2sPipe_valid); + assign writeLogic_adapter_w_s2mPipe_m2sPipe_valid = writeLogic_adapter_w_s2mPipe_rValid; + assign writeLogic_adapter_w_s2mPipe_m2sPipe_payload_data = writeLogic_adapter_w_s2mPipe_rData_data; + assign writeLogic_adapter_w_s2mPipe_m2sPipe_payload_strb = writeLogic_adapter_w_s2mPipe_rData_strb; + assign writeLogic_adapter_w_s2mPipe_m2sPipe_payload_last = writeLogic_adapter_w_s2mPipe_rData_last; + assign write_wvalid = writeLogic_adapter_w_s2mPipe_m2sPipe_valid; + assign writeLogic_adapter_w_s2mPipe_m2sPipe_ready = write_wready; + assign write_wdata = writeLogic_adapter_w_s2mPipe_m2sPipe_payload_data; + assign write_wstrb = writeLogic_adapter_w_s2mPipe_m2sPipe_payload_strb; + assign write_wlast = writeLogic_adapter_w_s2mPipe_m2sPipe_payload_last; + assign write_b_halfPipe_fire = (write_b_halfPipe_valid && write_b_halfPipe_ready); + assign write_bready = (! write_b_rValid); + assign write_b_halfPipe_valid = write_b_rValid; + assign write_b_halfPipe_payload_resp = write_b_rData_resp; + assign writeLogic_adapter_b_valid = write_b_halfPipe_valid; + assign write_b_halfPipe_ready = writeLogic_adapter_b_ready; + assign writeLogic_adapter_b_payload_resp = write_b_halfPipe_payload_resp; + assign dat0_i_tready = inputsAdapter_0_upsizer_logic_io_input_ready; + assign io_pop_s2mPipe_valid = (inputsAdapter_0_crossclock_fifo_io_pop_valid || (! io_pop_rValidN)); + assign io_pop_s2mPipe_payload_data = (io_pop_rValidN ? inputsAdapter_0_crossclock_fifo_io_pop_payload_data : io_pop_rData_data); + assign io_pop_s2mPipe_payload_mask = (io_pop_rValidN ? inputsAdapter_0_crossclock_fifo_io_pop_payload_mask : io_pop_rData_mask); + assign io_pop_s2mPipe_payload_sink = (io_pop_rValidN ? inputsAdapter_0_crossclock_fifo_io_pop_payload_sink : io_pop_rData_sink); + assign io_pop_s2mPipe_payload_last = (io_pop_rValidN ? inputsAdapter_0_crossclock_fifo_io_pop_payload_last : io_pop_rData_last); + always @(*) begin + io_pop_s2mPipe_ready = io_pop_s2mPipe_m2sPipe_ready; + if(when_Stream_l375_4) begin + io_pop_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375_4 = (! io_pop_s2mPipe_m2sPipe_valid); + assign io_pop_s2mPipe_m2sPipe_valid = io_pop_s2mPipe_rValid; + assign io_pop_s2mPipe_m2sPipe_payload_data = io_pop_s2mPipe_rData_data; + assign io_pop_s2mPipe_m2sPipe_payload_mask = io_pop_s2mPipe_rData_mask; + assign io_pop_s2mPipe_m2sPipe_payload_sink = io_pop_s2mPipe_rData_sink; + assign io_pop_s2mPipe_m2sPipe_payload_last = io_pop_s2mPipe_rData_last; + assign io_pop_s2mPipe_m2sPipe_ready = core_io_inputs_0_ready; + assign io_outputs_0_s2mPipe_valid = (core_io_outputs_0_valid || (! io_outputs_0_rValidN)); + assign io_outputs_0_s2mPipe_payload_data = (io_outputs_0_rValidN ? core_io_outputs_0_payload_data : io_outputs_0_rData_data); + assign io_outputs_0_s2mPipe_payload_mask = (io_outputs_0_rValidN ? core_io_outputs_0_payload_mask : io_outputs_0_rData_mask); + assign io_outputs_0_s2mPipe_payload_sink = (io_outputs_0_rValidN ? core_io_outputs_0_payload_sink : io_outputs_0_rData_sink); + assign io_outputs_0_s2mPipe_payload_last = (io_outputs_0_rValidN ? core_io_outputs_0_payload_last : io_outputs_0_rData_last); + always @(*) begin + io_outputs_0_s2mPipe_ready = outputsAdapter_0_ptr_ready; + if(when_Stream_l375_5) begin + io_outputs_0_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375_5 = (! outputsAdapter_0_ptr_valid); + assign outputsAdapter_0_ptr_valid = io_outputs_0_s2mPipe_rValid; + assign outputsAdapter_0_ptr_payload_data = io_outputs_0_s2mPipe_rData_data; + assign outputsAdapter_0_ptr_payload_mask = io_outputs_0_s2mPipe_rData_mask; + assign outputsAdapter_0_ptr_payload_sink = io_outputs_0_s2mPipe_rData_sink; + assign outputsAdapter_0_ptr_payload_last = io_outputs_0_s2mPipe_rData_last; + assign outputsAdapter_0_ptr_ready = outputsAdapter_0_crossclock_fifo_io_push_ready; + assign dat1_o_tvalid = outputsAdapter_0_sparseDownsizer_logic_io_output_valid; + assign dat1_o_tdata = outputsAdapter_0_sparseDownsizer_logic_io_output_payload_data; + assign dat1_o_tkeep = outputsAdapter_0_sparseDownsizer_logic_io_output_payload_mask; + assign dat1_o_tdest = outputsAdapter_0_sparseDownsizer_logic_io_output_payload_sink; + assign dat1_o_tlast = outputsAdapter_0_sparseDownsizer_logic_io_output_payload_last; + assign interconnect_read_aggregated_cmd_valid = interconnect_read_aggregated_arbiter_io_output_cmd_valid; + assign interconnect_read_aggregated_rsp_ready = interconnect_read_aggregated_arbiter_io_output_rsp_ready; + assign interconnect_read_aggregated_cmd_payload_last = interconnect_read_aggregated_arbiter_io_output_cmd_payload_last; + assign interconnect_read_aggregated_cmd_payload_fragment_source = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_source; + assign interconnect_read_aggregated_cmd_payload_fragment_opcode = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_opcode; + assign interconnect_read_aggregated_cmd_payload_fragment_address = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_address; + assign interconnect_read_aggregated_cmd_payload_fragment_length = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_length; + assign interconnect_read_aggregated_cmd_payload_fragment_context = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_context; + assign interconnect_write_aggregated_cmd_valid = interconnect_write_aggregated_arbiter_io_output_cmd_valid; + assign interconnect_write_aggregated_rsp_ready = interconnect_write_aggregated_arbiter_io_output_rsp_ready; + assign interconnect_write_aggregated_cmd_payload_last = interconnect_write_aggregated_arbiter_io_output_cmd_payload_last; + assign interconnect_write_aggregated_cmd_payload_fragment_source = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_source; + assign interconnect_write_aggregated_cmd_payload_fragment_opcode = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_opcode; + assign interconnect_write_aggregated_cmd_payload_fragment_address = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_address; + assign interconnect_write_aggregated_cmd_payload_fragment_length = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_length; + assign interconnect_write_aggregated_cmd_payload_fragment_data = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_data; + assign interconnect_write_aggregated_cmd_payload_fragment_mask = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_mask; + assign interconnect_write_aggregated_cmd_payload_fragment_context = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_context; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready = interconnect_read_aggregated_arbiter_io_inputs_0_cmd_ready; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_valid; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_last; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_data; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready = interconnect_read_aggregated_arbiter_io_inputs_1_cmd_ready; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_valid; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_last; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_data = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_data; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready = interconnect_write_aggregated_arbiter_io_inputs_0_cmd_ready; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid = interconnect_write_aggregated_arbiter_io_inputs_0_rsp_valid; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last = interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_last; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode = interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context = interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready = interconnect_write_aggregated_arbiter_io_inputs_1_cmd_ready; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid = interconnect_write_aggregated_arbiter_io_inputs_1_rsp_valid; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last = interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_last; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode = interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context = interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context; + always @(posedge clk) begin + if(reset) begin + io_write_cmd_rValidN <= 1'b1; + io_write_cmd_s2mPipe_rValid <= 1'b0; + interconnect_read_aggregated_cmd_rValid <= 1'b0; + readLogic_adapter_ar_rValid <= 1'b0; + read_r_rValidN <= 1'b1; + read_r_s2mPipe_rValid <= 1'b0; + interconnect_write_aggregated_cmd_rValid <= 1'b0; + writeLogic_adapter_aw_rValid <= 1'b0; + writeLogic_adapter_w_rValidN <= 1'b1; + writeLogic_adapter_w_s2mPipe_rValid <= 1'b0; + write_b_rValid <= 1'b0; + io_pop_rValidN <= 1'b1; + io_pop_s2mPipe_rValid <= 1'b0; + io_outputs_0_rValidN <= 1'b1; + io_outputs_0_s2mPipe_rValid <= 1'b0; + end else begin + if(core_io_write_cmd_valid) begin + io_write_cmd_rValidN <= 1'b0; + end + if(io_write_cmd_s2mPipe_ready) begin + io_write_cmd_rValidN <= 1'b1; + end + if(io_write_cmd_s2mPipe_ready) begin + io_write_cmd_s2mPipe_rValid <= io_write_cmd_s2mPipe_valid; + end + if(interconnect_read_aggregated_cmd_valid) begin + interconnect_read_aggregated_cmd_rValid <= 1'b1; + end + if(interconnect_read_aggregated_cmd_halfPipe_fire) begin + interconnect_read_aggregated_cmd_rValid <= 1'b0; + end + if(readLogic_adapter_ar_valid) begin + readLogic_adapter_ar_rValid <= 1'b1; + end + if(readLogic_adapter_ar_halfPipe_fire) begin + readLogic_adapter_ar_rValid <= 1'b0; + end + if(read_rvalid) begin + read_r_rValidN <= 1'b0; + end + if(read_r_s2mPipe_ready) begin + read_r_rValidN <= 1'b1; + end + if(read_r_s2mPipe_ready) begin + read_r_s2mPipe_rValid <= read_r_s2mPipe_valid; + end + if(interconnect_write_aggregated_cmd_ready) begin + interconnect_write_aggregated_cmd_rValid <= interconnect_write_aggregated_cmd_valid; + end + if(writeLogic_adapter_aw_valid) begin + writeLogic_adapter_aw_rValid <= 1'b1; + end + if(writeLogic_adapter_aw_halfPipe_fire) begin + writeLogic_adapter_aw_rValid <= 1'b0; + end + if(writeLogic_adapter_w_valid) begin + writeLogic_adapter_w_rValidN <= 1'b0; + end + if(writeLogic_adapter_w_s2mPipe_ready) begin + writeLogic_adapter_w_rValidN <= 1'b1; + end + if(writeLogic_adapter_w_s2mPipe_ready) begin + writeLogic_adapter_w_s2mPipe_rValid <= writeLogic_adapter_w_s2mPipe_valid; + end + if(write_bvalid) begin + write_b_rValid <= 1'b1; + end + if(write_b_halfPipe_fire) begin + write_b_rValid <= 1'b0; + end + if(inputsAdapter_0_crossclock_fifo_io_pop_valid) begin + io_pop_rValidN <= 1'b0; + end + if(io_pop_s2mPipe_ready) begin + io_pop_rValidN <= 1'b1; + end + if(io_pop_s2mPipe_ready) begin + io_pop_s2mPipe_rValid <= io_pop_s2mPipe_valid; + end + if(core_io_outputs_0_valid) begin + io_outputs_0_rValidN <= 1'b0; + end + if(io_outputs_0_s2mPipe_ready) begin + io_outputs_0_rValidN <= 1'b1; + end + if(io_outputs_0_s2mPipe_ready) begin + io_outputs_0_s2mPipe_rValid <= io_outputs_0_s2mPipe_valid; + end + end + end + + always @(posedge clk) begin + if(io_write_cmd_rValidN) begin + io_write_cmd_rData_last <= core_io_write_cmd_payload_last; + io_write_cmd_rData_fragment_opcode <= core_io_write_cmd_payload_fragment_opcode; + io_write_cmd_rData_fragment_address <= core_io_write_cmd_payload_fragment_address; + io_write_cmd_rData_fragment_length <= core_io_write_cmd_payload_fragment_length; + io_write_cmd_rData_fragment_data <= core_io_write_cmd_payload_fragment_data; + io_write_cmd_rData_fragment_mask <= core_io_write_cmd_payload_fragment_mask; + io_write_cmd_rData_fragment_context <= core_io_write_cmd_payload_fragment_context; + end + if(io_write_cmd_s2mPipe_ready) begin + io_write_cmd_s2mPipe_rData_last <= io_write_cmd_s2mPipe_payload_last; + io_write_cmd_s2mPipe_rData_fragment_opcode <= io_write_cmd_s2mPipe_payload_fragment_opcode; + io_write_cmd_s2mPipe_rData_fragment_address <= io_write_cmd_s2mPipe_payload_fragment_address; + io_write_cmd_s2mPipe_rData_fragment_length <= io_write_cmd_s2mPipe_payload_fragment_length; + io_write_cmd_s2mPipe_rData_fragment_data <= io_write_cmd_s2mPipe_payload_fragment_data; + io_write_cmd_s2mPipe_rData_fragment_mask <= io_write_cmd_s2mPipe_payload_fragment_mask; + io_write_cmd_s2mPipe_rData_fragment_context <= io_write_cmd_s2mPipe_payload_fragment_context; + end + if(interconnect_read_aggregated_cmd_ready) begin + interconnect_read_aggregated_cmd_rData_last <= interconnect_read_aggregated_cmd_payload_last; + interconnect_read_aggregated_cmd_rData_fragment_source <= interconnect_read_aggregated_cmd_payload_fragment_source; + interconnect_read_aggregated_cmd_rData_fragment_opcode <= interconnect_read_aggregated_cmd_payload_fragment_opcode; + interconnect_read_aggregated_cmd_rData_fragment_address <= interconnect_read_aggregated_cmd_payload_fragment_address; + interconnect_read_aggregated_cmd_rData_fragment_length <= interconnect_read_aggregated_cmd_payload_fragment_length; + interconnect_read_aggregated_cmd_rData_fragment_context <= interconnect_read_aggregated_cmd_payload_fragment_context; + end + if(readLogic_adapter_ar_ready) begin + readLogic_adapter_ar_rData_addr <= readLogic_adapter_ar_payload_addr; + readLogic_adapter_ar_rData_region <= readLogic_adapter_ar_payload_region; + readLogic_adapter_ar_rData_len <= readLogic_adapter_ar_payload_len; + readLogic_adapter_ar_rData_size <= readLogic_adapter_ar_payload_size; + readLogic_adapter_ar_rData_burst <= readLogic_adapter_ar_payload_burst; + readLogic_adapter_ar_rData_lock <= readLogic_adapter_ar_payload_lock; + readLogic_adapter_ar_rData_cache <= readLogic_adapter_ar_payload_cache; + readLogic_adapter_ar_rData_qos <= readLogic_adapter_ar_payload_qos; + readLogic_adapter_ar_rData_prot <= readLogic_adapter_ar_payload_prot; + end + if(read_rready) begin + read_r_rData_data <= read_rdata; + read_r_rData_resp <= read_rresp; + read_r_rData_last <= read_rlast; + end + if(read_r_s2mPipe_ready) begin + read_r_s2mPipe_rData_data <= read_r_s2mPipe_payload_data; + read_r_s2mPipe_rData_resp <= read_r_s2mPipe_payload_resp; + read_r_s2mPipe_rData_last <= read_r_s2mPipe_payload_last; + end + if(interconnect_write_aggregated_cmd_ready) begin + interconnect_write_aggregated_cmd_rData_last <= interconnect_write_aggregated_cmd_payload_last; + interconnect_write_aggregated_cmd_rData_fragment_source <= interconnect_write_aggregated_cmd_payload_fragment_source; + interconnect_write_aggregated_cmd_rData_fragment_opcode <= interconnect_write_aggregated_cmd_payload_fragment_opcode; + interconnect_write_aggregated_cmd_rData_fragment_address <= interconnect_write_aggregated_cmd_payload_fragment_address; + interconnect_write_aggregated_cmd_rData_fragment_length <= interconnect_write_aggregated_cmd_payload_fragment_length; + interconnect_write_aggregated_cmd_rData_fragment_data <= interconnect_write_aggregated_cmd_payload_fragment_data; + interconnect_write_aggregated_cmd_rData_fragment_mask <= interconnect_write_aggregated_cmd_payload_fragment_mask; + interconnect_write_aggregated_cmd_rData_fragment_context <= interconnect_write_aggregated_cmd_payload_fragment_context; + end + if(writeLogic_adapter_aw_ready) begin + writeLogic_adapter_aw_rData_addr <= writeLogic_adapter_aw_payload_addr; + writeLogic_adapter_aw_rData_region <= writeLogic_adapter_aw_payload_region; + writeLogic_adapter_aw_rData_len <= writeLogic_adapter_aw_payload_len; + writeLogic_adapter_aw_rData_size <= writeLogic_adapter_aw_payload_size; + writeLogic_adapter_aw_rData_burst <= writeLogic_adapter_aw_payload_burst; + writeLogic_adapter_aw_rData_lock <= writeLogic_adapter_aw_payload_lock; + writeLogic_adapter_aw_rData_cache <= writeLogic_adapter_aw_payload_cache; + writeLogic_adapter_aw_rData_qos <= writeLogic_adapter_aw_payload_qos; + writeLogic_adapter_aw_rData_prot <= writeLogic_adapter_aw_payload_prot; + end + if(writeLogic_adapter_w_ready) begin + writeLogic_adapter_w_rData_data <= writeLogic_adapter_w_payload_data; + writeLogic_adapter_w_rData_strb <= writeLogic_adapter_w_payload_strb; + writeLogic_adapter_w_rData_last <= writeLogic_adapter_w_payload_last; + end + if(writeLogic_adapter_w_s2mPipe_ready) begin + writeLogic_adapter_w_s2mPipe_rData_data <= writeLogic_adapter_w_s2mPipe_payload_data; + writeLogic_adapter_w_s2mPipe_rData_strb <= writeLogic_adapter_w_s2mPipe_payload_strb; + writeLogic_adapter_w_s2mPipe_rData_last <= writeLogic_adapter_w_s2mPipe_payload_last; + end + if(write_bready) begin + write_b_rData_resp <= write_bresp; + end + if(io_pop_rValidN) begin + io_pop_rData_data <= inputsAdapter_0_crossclock_fifo_io_pop_payload_data; + io_pop_rData_mask <= inputsAdapter_0_crossclock_fifo_io_pop_payload_mask; + io_pop_rData_sink <= inputsAdapter_0_crossclock_fifo_io_pop_payload_sink; + io_pop_rData_last <= inputsAdapter_0_crossclock_fifo_io_pop_payload_last; + end + if(io_pop_s2mPipe_ready) begin + io_pop_s2mPipe_rData_data <= io_pop_s2mPipe_payload_data; + io_pop_s2mPipe_rData_mask <= io_pop_s2mPipe_payload_mask; + io_pop_s2mPipe_rData_sink <= io_pop_s2mPipe_payload_sink; + io_pop_s2mPipe_rData_last <= io_pop_s2mPipe_payload_last; + end + if(io_outputs_0_rValidN) begin + io_outputs_0_rData_data <= core_io_outputs_0_payload_data; + io_outputs_0_rData_mask <= core_io_outputs_0_payload_mask; + io_outputs_0_rData_sink <= core_io_outputs_0_payload_sink; + io_outputs_0_rData_last <= core_io_outputs_0_payload_last; + end + if(io_outputs_0_s2mPipe_ready) begin + io_outputs_0_s2mPipe_rData_data <= io_outputs_0_s2mPipe_payload_data; + io_outputs_0_s2mPipe_rData_mask <= io_outputs_0_s2mPipe_payload_mask; + io_outputs_0_s2mPipe_rData_sink <= io_outputs_0_s2mPipe_payload_sink; + io_outputs_0_s2mPipe_rData_last <= io_outputs_0_s2mPipe_payload_last; + end + end + + +endmodule + +module EfxDMA_BmbArbiter_1_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_inputs_0_cmd_valid, + output wire io_inputs_0_cmd_ready, + input wire io_inputs_0_cmd_payload_last, + input wire [0:0] io_inputs_0_cmd_payload_fragment_opcode, + input wire [31:0] io_inputs_0_cmd_payload_fragment_address, + input wire [1:0] io_inputs_0_cmd_payload_fragment_length, + input wire [127:0] io_inputs_0_cmd_payload_fragment_data, + input wire [15:0] io_inputs_0_cmd_payload_fragment_mask, + input wire [0:0] io_inputs_0_cmd_payload_fragment_context, + output wire io_inputs_0_rsp_valid, + input wire io_inputs_0_rsp_ready, + output wire io_inputs_0_rsp_payload_last, + output wire [0:0] io_inputs_0_rsp_payload_fragment_opcode, + output wire [0:0] io_inputs_0_rsp_payload_fragment_context, + input wire io_inputs_1_cmd_valid, + output wire io_inputs_1_cmd_ready, + input wire io_inputs_1_cmd_payload_last, + input wire [0:0] io_inputs_1_cmd_payload_fragment_opcode, + input wire [31:0] io_inputs_1_cmd_payload_fragment_address, + input wire [11:0] io_inputs_1_cmd_payload_fragment_length, + input wire [127:0] io_inputs_1_cmd_payload_fragment_data, + input wire [15:0] io_inputs_1_cmd_payload_fragment_mask, + input wire [12:0] io_inputs_1_cmd_payload_fragment_context, + output wire io_inputs_1_rsp_valid, + input wire io_inputs_1_rsp_ready, + output wire io_inputs_1_rsp_payload_last, + output wire [0:0] io_inputs_1_rsp_payload_fragment_opcode, + output wire [12:0] io_inputs_1_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_source, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + output wire [127:0] io_output_cmd_payload_fragment_data, + output wire [15:0] io_output_cmd_payload_fragment_mask, + output wire [12:0] io_output_cmd_payload_fragment_context, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_source, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [12:0] io_output_rsp_payload_fragment_context, + input wire clk, + input wire reset +); + + wire [11:0] memory_arbiter_io_inputs_0_payload_fragment_length; + wire [12:0] memory_arbiter_io_inputs_0_payload_fragment_context; + wire memory_arbiter_io_inputs_0_ready; + wire memory_arbiter_io_inputs_1_ready; + wire memory_arbiter_io_output_valid; + wire memory_arbiter_io_output_payload_last; + wire [0:0] memory_arbiter_io_output_payload_fragment_source; + wire [0:0] memory_arbiter_io_output_payload_fragment_opcode; + wire [31:0] memory_arbiter_io_output_payload_fragment_address; + wire [11:0] memory_arbiter_io_output_payload_fragment_length; + wire [127:0] memory_arbiter_io_output_payload_fragment_data; + wire [15:0] memory_arbiter_io_output_payload_fragment_mask; + wire [12:0] memory_arbiter_io_output_payload_fragment_context; + wire [0:0] memory_arbiter_io_chosen; + wire [1:0] memory_arbiter_io_chosenOH; + wire [1:0] _zz_io_output_cmd_payload_fragment_source; + reg _zz_io_output_rsp_ready; + wire [0:0] memory_rspSel; + + assign _zz_io_output_cmd_payload_fragment_source = {memory_arbiter_io_output_payload_fragment_source,memory_arbiter_io_chosen}; + EfxDMA_StreamArbiter_1_a048ca8f51874147a1cd65d43e6523ef memory_arbiter ( + .io_inputs_0_valid (io_inputs_0_cmd_valid ), //i + .io_inputs_0_ready (memory_arbiter_io_inputs_0_ready ), //o + .io_inputs_0_payload_last (io_inputs_0_cmd_payload_last ), //i + .io_inputs_0_payload_fragment_source (1'b0 ), //i + .io_inputs_0_payload_fragment_opcode (io_inputs_0_cmd_payload_fragment_opcode ), //i + .io_inputs_0_payload_fragment_address (io_inputs_0_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_0_payload_fragment_length (memory_arbiter_io_inputs_0_payload_fragment_length[11:0] ), //i + .io_inputs_0_payload_fragment_data (io_inputs_0_cmd_payload_fragment_data[127:0] ), //i + .io_inputs_0_payload_fragment_mask (io_inputs_0_cmd_payload_fragment_mask[15:0] ), //i + .io_inputs_0_payload_fragment_context (memory_arbiter_io_inputs_0_payload_fragment_context[12:0]), //i + .io_inputs_1_valid (io_inputs_1_cmd_valid ), //i + .io_inputs_1_ready (memory_arbiter_io_inputs_1_ready ), //o + .io_inputs_1_payload_last (io_inputs_1_cmd_payload_last ), //i + .io_inputs_1_payload_fragment_source (1'b0 ), //i + .io_inputs_1_payload_fragment_opcode (io_inputs_1_cmd_payload_fragment_opcode ), //i + .io_inputs_1_payload_fragment_address (io_inputs_1_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_1_payload_fragment_length (io_inputs_1_cmd_payload_fragment_length[11:0] ), //i + .io_inputs_1_payload_fragment_data (io_inputs_1_cmd_payload_fragment_data[127:0] ), //i + .io_inputs_1_payload_fragment_mask (io_inputs_1_cmd_payload_fragment_mask[15:0] ), //i + .io_inputs_1_payload_fragment_context (io_inputs_1_cmd_payload_fragment_context[12:0] ), //i + .io_output_valid (memory_arbiter_io_output_valid ), //o + .io_output_ready (io_output_cmd_ready ), //i + .io_output_payload_last (memory_arbiter_io_output_payload_last ), //o + .io_output_payload_fragment_source (memory_arbiter_io_output_payload_fragment_source ), //o + .io_output_payload_fragment_opcode (memory_arbiter_io_output_payload_fragment_opcode ), //o + .io_output_payload_fragment_address (memory_arbiter_io_output_payload_fragment_address[31:0] ), //o + .io_output_payload_fragment_length (memory_arbiter_io_output_payload_fragment_length[11:0] ), //o + .io_output_payload_fragment_data (memory_arbiter_io_output_payload_fragment_data[127:0] ), //o + .io_output_payload_fragment_mask (memory_arbiter_io_output_payload_fragment_mask[15:0] ), //o + .io_output_payload_fragment_context (memory_arbiter_io_output_payload_fragment_context[12:0] ), //o + .io_chosen (memory_arbiter_io_chosen ), //o + .io_chosenOH (memory_arbiter_io_chosenOH[1:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(memory_rspSel) + 1'b0 : _zz_io_output_rsp_ready = io_inputs_0_rsp_ready; + default : _zz_io_output_rsp_ready = io_inputs_1_rsp_ready; + endcase + end + + assign io_inputs_0_cmd_ready = memory_arbiter_io_inputs_0_ready; + assign memory_arbiter_io_inputs_0_payload_fragment_length = {10'd0, io_inputs_0_cmd_payload_fragment_length}; + assign memory_arbiter_io_inputs_0_payload_fragment_context = {12'd0, io_inputs_0_cmd_payload_fragment_context}; + assign io_inputs_1_cmd_ready = memory_arbiter_io_inputs_1_ready; + assign io_output_cmd_valid = memory_arbiter_io_output_valid; + assign io_output_cmd_payload_last = memory_arbiter_io_output_payload_last; + assign io_output_cmd_payload_fragment_opcode = memory_arbiter_io_output_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = memory_arbiter_io_output_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = memory_arbiter_io_output_payload_fragment_length; + assign io_output_cmd_payload_fragment_data = memory_arbiter_io_output_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = memory_arbiter_io_output_payload_fragment_mask; + assign io_output_cmd_payload_fragment_context = memory_arbiter_io_output_payload_fragment_context; + assign io_output_cmd_payload_fragment_source = _zz_io_output_cmd_payload_fragment_source[0:0]; + assign memory_rspSel = io_output_rsp_payload_fragment_source[0 : 0]; + assign io_inputs_0_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b0)); + assign io_inputs_0_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_0_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_0_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context[0:0]; + assign io_inputs_1_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b1)); + assign io_inputs_1_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_1_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_1_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; + assign io_output_rsp_ready = _zz_io_output_rsp_ready; + +endmodule + +module EfxDMA_BmbArbiter_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_inputs_0_cmd_valid, + output wire io_inputs_0_cmd_ready, + input wire io_inputs_0_cmd_payload_last, + input wire [0:0] io_inputs_0_cmd_payload_fragment_opcode, + input wire [31:0] io_inputs_0_cmd_payload_fragment_address, + input wire [4:0] io_inputs_0_cmd_payload_fragment_length, + input wire [0:0] io_inputs_0_cmd_payload_fragment_context, + output wire io_inputs_0_rsp_valid, + input wire io_inputs_0_rsp_ready, + output wire io_inputs_0_rsp_payload_last, + output wire [0:0] io_inputs_0_rsp_payload_fragment_opcode, + output wire [127:0] io_inputs_0_rsp_payload_fragment_data, + output wire [0:0] io_inputs_0_rsp_payload_fragment_context, + input wire io_inputs_1_cmd_valid, + output wire io_inputs_1_cmd_ready, + input wire io_inputs_1_cmd_payload_last, + input wire [0:0] io_inputs_1_cmd_payload_fragment_opcode, + input wire [31:0] io_inputs_1_cmd_payload_fragment_address, + input wire [11:0] io_inputs_1_cmd_payload_fragment_length, + input wire [20:0] io_inputs_1_cmd_payload_fragment_context, + output wire io_inputs_1_rsp_valid, + input wire io_inputs_1_rsp_ready, + output wire io_inputs_1_rsp_payload_last, + output wire [0:0] io_inputs_1_rsp_payload_fragment_opcode, + output wire [127:0] io_inputs_1_rsp_payload_fragment_data, + output wire [20:0] io_inputs_1_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_source, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + output wire [20:0] io_output_cmd_payload_fragment_context, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_source, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [127:0] io_output_rsp_payload_fragment_data, + input wire [20:0] io_output_rsp_payload_fragment_context, + input wire clk, + input wire reset +); + + wire [11:0] memory_arbiter_io_inputs_0_payload_fragment_length; + wire [20:0] memory_arbiter_io_inputs_0_payload_fragment_context; + wire memory_arbiter_io_inputs_0_ready; + wire memory_arbiter_io_inputs_1_ready; + wire memory_arbiter_io_output_valid; + wire memory_arbiter_io_output_payload_last; + wire [0:0] memory_arbiter_io_output_payload_fragment_source; + wire [0:0] memory_arbiter_io_output_payload_fragment_opcode; + wire [31:0] memory_arbiter_io_output_payload_fragment_address; + wire [11:0] memory_arbiter_io_output_payload_fragment_length; + wire [20:0] memory_arbiter_io_output_payload_fragment_context; + wire [0:0] memory_arbiter_io_chosen; + wire [1:0] memory_arbiter_io_chosenOH; + wire [1:0] _zz_io_output_cmd_payload_fragment_source; + reg _zz_io_output_rsp_ready; + wire [0:0] memory_rspSel; + + assign _zz_io_output_cmd_payload_fragment_source = {memory_arbiter_io_output_payload_fragment_source,memory_arbiter_io_chosen}; + EfxDMA_StreamArbiter_a048ca8f51874147a1cd65d43e6523ef memory_arbiter ( + .io_inputs_0_valid (io_inputs_0_cmd_valid ), //i + .io_inputs_0_ready (memory_arbiter_io_inputs_0_ready ), //o + .io_inputs_0_payload_last (io_inputs_0_cmd_payload_last ), //i + .io_inputs_0_payload_fragment_source (1'b0 ), //i + .io_inputs_0_payload_fragment_opcode (io_inputs_0_cmd_payload_fragment_opcode ), //i + .io_inputs_0_payload_fragment_address (io_inputs_0_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_0_payload_fragment_length (memory_arbiter_io_inputs_0_payload_fragment_length[11:0] ), //i + .io_inputs_0_payload_fragment_context (memory_arbiter_io_inputs_0_payload_fragment_context[20:0]), //i + .io_inputs_1_valid (io_inputs_1_cmd_valid ), //i + .io_inputs_1_ready (memory_arbiter_io_inputs_1_ready ), //o + .io_inputs_1_payload_last (io_inputs_1_cmd_payload_last ), //i + .io_inputs_1_payload_fragment_source (1'b0 ), //i + .io_inputs_1_payload_fragment_opcode (io_inputs_1_cmd_payload_fragment_opcode ), //i + .io_inputs_1_payload_fragment_address (io_inputs_1_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_1_payload_fragment_length (io_inputs_1_cmd_payload_fragment_length[11:0] ), //i + .io_inputs_1_payload_fragment_context (io_inputs_1_cmd_payload_fragment_context[20:0] ), //i + .io_output_valid (memory_arbiter_io_output_valid ), //o + .io_output_ready (io_output_cmd_ready ), //i + .io_output_payload_last (memory_arbiter_io_output_payload_last ), //o + .io_output_payload_fragment_source (memory_arbiter_io_output_payload_fragment_source ), //o + .io_output_payload_fragment_opcode (memory_arbiter_io_output_payload_fragment_opcode ), //o + .io_output_payload_fragment_address (memory_arbiter_io_output_payload_fragment_address[31:0] ), //o + .io_output_payload_fragment_length (memory_arbiter_io_output_payload_fragment_length[11:0] ), //o + .io_output_payload_fragment_context (memory_arbiter_io_output_payload_fragment_context[20:0] ), //o + .io_chosen (memory_arbiter_io_chosen ), //o + .io_chosenOH (memory_arbiter_io_chosenOH[1:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(memory_rspSel) + 1'b0 : _zz_io_output_rsp_ready = io_inputs_0_rsp_ready; + default : _zz_io_output_rsp_ready = io_inputs_1_rsp_ready; + endcase + end + + assign io_inputs_0_cmd_ready = memory_arbiter_io_inputs_0_ready; + assign memory_arbiter_io_inputs_0_payload_fragment_length = {7'd0, io_inputs_0_cmd_payload_fragment_length}; + assign memory_arbiter_io_inputs_0_payload_fragment_context = {20'd0, io_inputs_0_cmd_payload_fragment_context}; + assign io_inputs_1_cmd_ready = memory_arbiter_io_inputs_1_ready; + assign io_output_cmd_valid = memory_arbiter_io_output_valid; + assign io_output_cmd_payload_last = memory_arbiter_io_output_payload_last; + assign io_output_cmd_payload_fragment_opcode = memory_arbiter_io_output_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = memory_arbiter_io_output_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = memory_arbiter_io_output_payload_fragment_length; + assign io_output_cmd_payload_fragment_context = memory_arbiter_io_output_payload_fragment_context; + assign io_output_cmd_payload_fragment_source = _zz_io_output_cmd_payload_fragment_source[0:0]; + assign memory_rspSel = io_output_rsp_payload_fragment_source[0 : 0]; + assign io_inputs_0_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b0)); + assign io_inputs_0_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_0_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_0_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_inputs_0_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context[0:0]; + assign io_inputs_1_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b1)); + assign io_inputs_1_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_1_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_1_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_inputs_1_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; + assign io_output_rsp_ready = _zz_io_output_rsp_ready; + +endmodule + +module EfxDMA_BsbDownSizerSparse_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_input_valid, + output wire io_input_ready, + input wire [63:0] io_input_payload_data, + input wire [7:0] io_input_payload_mask, + input wire [3:0] io_input_payload_sink, + input wire io_input_payload_last, + output wire io_output_valid, + input wire io_output_ready, + output wire [7:0] io_output_payload_data, + output wire [0:0] io_output_payload_mask, + output wire [3:0] io_output_payload_sink, + output wire io_output_payload_last, + input wire dat1_o_clk, + input wire dat1_o_reset +); + + reg [7:0] _zz_io_output_payload_data; + reg [0:0] _zz_io_output_payload_mask; + reg [2:0] counter; + wire end_1; + wire io_output_fire; + + always @(*) begin + case(counter) + 3'b000 : begin + _zz_io_output_payload_data = io_input_payload_data[7 : 0]; + _zz_io_output_payload_mask = io_input_payload_mask[0 : 0]; + end + 3'b001 : begin + _zz_io_output_payload_data = io_input_payload_data[15 : 8]; + _zz_io_output_payload_mask = io_input_payload_mask[1 : 1]; + end + 3'b010 : begin + _zz_io_output_payload_data = io_input_payload_data[23 : 16]; + _zz_io_output_payload_mask = io_input_payload_mask[2 : 2]; + end + 3'b011 : begin + _zz_io_output_payload_data = io_input_payload_data[31 : 24]; + _zz_io_output_payload_mask = io_input_payload_mask[3 : 3]; + end + 3'b100 : begin + _zz_io_output_payload_data = io_input_payload_data[39 : 32]; + _zz_io_output_payload_mask = io_input_payload_mask[4 : 4]; + end + 3'b101 : begin + _zz_io_output_payload_data = io_input_payload_data[47 : 40]; + _zz_io_output_payload_mask = io_input_payload_mask[5 : 5]; + end + 3'b110 : begin + _zz_io_output_payload_data = io_input_payload_data[55 : 48]; + _zz_io_output_payload_mask = io_input_payload_mask[6 : 6]; + end + default : begin + _zz_io_output_payload_data = io_input_payload_data[63 : 56]; + _zz_io_output_payload_mask = io_input_payload_mask[7 : 7]; + end + endcase + end + + assign end_1 = (counter == 3'b111); + assign io_output_fire = (io_output_valid && io_output_ready); + assign io_input_ready = (io_output_ready && end_1); + assign io_output_valid = io_input_valid; + assign io_output_payload_data = _zz_io_output_payload_data; + assign io_output_payload_mask = _zz_io_output_payload_mask; + assign io_output_payload_sink = io_input_payload_sink; + assign io_output_payload_last = (io_input_payload_last && end_1); + always @(posedge dat1_o_clk) begin + if(dat1_o_reset) begin + counter <= 3'b000; + end else begin + if(io_output_fire) begin + counter <= (counter + 3'b001); + end + end + end + + +endmodule + +module EfxDMA_StreamFifoCC_1_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_push_valid, + output wire io_push_ready, + input wire [63:0] io_push_payload_data, + input wire [7:0] io_push_payload_mask, + input wire [3:0] io_push_payload_sink, + input wire io_push_payload_last, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [63:0] io_pop_payload_data, + output wire [7:0] io_pop_payload_mask, + output wire [3:0] io_pop_payload_sink, + output wire io_pop_payload_last, + output wire [4:0] io_pushOccupancy, + output wire [4:0] io_popOccupancy, + input wire clk, + input wire reset, + input wire dat1_o_clk, + input wire dat1_o_reset +); + + reg [76:0] ram_spinal_port1; + wire [4:0] popToPushGray_buffercc_io_dataOut; + wire [4:0] pushToPopGray_buffercc_io_dataOut; + wire [4:0] _zz_pushCC_pushPtrGray; + wire [3:0] _zz_ram_port; + wire [76:0] _zz_ram_port_1; + wire [4:0] _zz_popCC_popPtrGray; + reg _zz_1; + wire [4:0] popToPushGray; + wire [4:0] pushToPopGray; + reg [4:0] pushCC_pushPtr; + wire [4:0] pushCC_pushPtrPlus; + wire io_push_fire; + reg [4:0] pushCC_pushPtrGray; + wire [4:0] pushCC_popPtrGray; + wire pushCC_full; + wire _zz_io_pushOccupancy; + wire _zz_io_pushOccupancy_1; + wire _zz_io_pushOccupancy_2; + wire _zz_io_pushOccupancy_3; + reg [4:0] popCC_popPtr; + (* keep , syn_keep *) wire [4:0] popCC_popPtrPlus /* synthesis syn_keep = 1 */ ; + wire [4:0] popCC_popPtrGray; + wire [4:0] popCC_pushPtrGray; + wire popCC_addressGen_valid; + reg popCC_addressGen_ready; + wire [3:0] popCC_addressGen_payload; + wire popCC_empty; + wire popCC_addressGen_fire; + wire popCC_readArbitation_valid; + wire popCC_readArbitation_ready; + wire [3:0] popCC_readArbitation_payload; + reg popCC_addressGen_rValid; + reg [3:0] popCC_addressGen_rData; + wire when_Stream_l375; + wire popCC_readPort_cmd_valid; + wire [3:0] popCC_readPort_cmd_payload; + wire [63:0] popCC_readPort_rsp_data; + wire [7:0] popCC_readPort_rsp_mask; + wire [3:0] popCC_readPort_rsp_sink; + wire popCC_readPort_rsp_last; + wire [76:0] _zz_popCC_readPort_rsp_data; + wire popCC_readArbitation_translated_valid; + wire popCC_readArbitation_translated_ready; + wire [63:0] popCC_readArbitation_translated_payload_data; + wire [7:0] popCC_readArbitation_translated_payload_mask; + wire [3:0] popCC_readArbitation_translated_payload_sink; + wire popCC_readArbitation_translated_payload_last; + wire popCC_readArbitation_fire; + reg [4:0] popCC_ptrToPush; + reg [4:0] popCC_ptrToOccupancy; + wire _zz_io_popOccupancy; + wire _zz_io_popOccupancy_1; + wire _zz_io_popOccupancy_2; + wire _zz_io_popOccupancy_3; + reg [76:0] ram [0:15]; + + assign _zz_pushCC_pushPtrGray = (pushCC_pushPtrPlus >>> 1'b1); + assign _zz_ram_port = pushCC_pushPtr[3:0]; + assign _zz_popCC_popPtrGray = (popCC_popPtr >>> 1'b1); + assign _zz_ram_port_1 = {io_push_payload_last,{io_push_payload_sink,{io_push_payload_mask,io_push_payload_data}}}; + always @(posedge clk) begin + if(_zz_1) begin + ram[_zz_ram_port] <= _zz_ram_port_1; + end + end + + always @(posedge dat1_o_clk) begin + if(popCC_readPort_cmd_valid) begin + ram_spinal_port1 <= ram[popCC_readPort_cmd_payload]; + end + end + + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_3_a048ca8f51874147a1cd65d43e6523ef popToPushGray_buffercc ( + .io_dataIn (popToPushGray[4:0] ), //i + .io_dataOut (popToPushGray_buffercc_io_dataOut[4:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_5_a048ca8f51874147a1cd65d43e6523ef pushToPopGray_buffercc ( + .io_dataIn (pushToPopGray[4:0] ), //i + .io_dataOut (pushToPopGray_buffercc_io_dataOut[4:0]), //o + .dat1_o_clk (dat1_o_clk ), //i + .dat1_o_reset (dat1_o_reset ) //i + ); + always @(*) begin + _zz_1 = 1'b0; + if(io_push_fire) begin + _zz_1 = 1'b1; + end + end + + assign pushCC_pushPtrPlus = (pushCC_pushPtr + 5'h01); + assign io_push_fire = (io_push_valid && io_push_ready); + assign pushCC_popPtrGray = popToPushGray_buffercc_io_dataOut; + assign pushCC_full = ((pushCC_pushPtrGray[4 : 3] == (~ pushCC_popPtrGray[4 : 3])) && (pushCC_pushPtrGray[2 : 0] == pushCC_popPtrGray[2 : 0])); + assign io_push_ready = (! pushCC_full); + assign _zz_io_pushOccupancy = (pushCC_popPtrGray[1] ^ _zz_io_pushOccupancy_1); + assign _zz_io_pushOccupancy_1 = (pushCC_popPtrGray[2] ^ _zz_io_pushOccupancy_2); + assign _zz_io_pushOccupancy_2 = (pushCC_popPtrGray[3] ^ _zz_io_pushOccupancy_3); + assign _zz_io_pushOccupancy_3 = pushCC_popPtrGray[4]; + assign io_pushOccupancy = (pushCC_pushPtr - {_zz_io_pushOccupancy_3,{_zz_io_pushOccupancy_2,{_zz_io_pushOccupancy_1,{_zz_io_pushOccupancy,(pushCC_popPtrGray[0] ^ _zz_io_pushOccupancy)}}}}); + assign popCC_popPtrPlus = (popCC_popPtr + 5'h01); + assign popCC_popPtrGray = (_zz_popCC_popPtrGray ^ popCC_popPtr); + assign popCC_pushPtrGray = pushToPopGray_buffercc_io_dataOut; + assign popCC_empty = (popCC_popPtrGray == popCC_pushPtrGray); + assign popCC_addressGen_valid = (! popCC_empty); + assign popCC_addressGen_payload = popCC_popPtr[3:0]; + assign popCC_addressGen_fire = (popCC_addressGen_valid && popCC_addressGen_ready); + always @(*) begin + popCC_addressGen_ready = popCC_readArbitation_ready; + if(when_Stream_l375) begin + popCC_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! popCC_readArbitation_valid); + assign popCC_readArbitation_valid = popCC_addressGen_rValid; + assign popCC_readArbitation_payload = popCC_addressGen_rData; + assign _zz_popCC_readPort_rsp_data = ram_spinal_port1; + assign popCC_readPort_rsp_data = _zz_popCC_readPort_rsp_data[63 : 0]; + assign popCC_readPort_rsp_mask = _zz_popCC_readPort_rsp_data[71 : 64]; + assign popCC_readPort_rsp_sink = _zz_popCC_readPort_rsp_data[75 : 72]; + assign popCC_readPort_rsp_last = _zz_popCC_readPort_rsp_data[76]; + assign popCC_readPort_cmd_valid = popCC_addressGen_fire; + assign popCC_readPort_cmd_payload = popCC_addressGen_payload; + assign popCC_readArbitation_translated_valid = popCC_readArbitation_valid; + assign popCC_readArbitation_ready = popCC_readArbitation_translated_ready; + assign popCC_readArbitation_translated_payload_data = popCC_readPort_rsp_data; + assign popCC_readArbitation_translated_payload_mask = popCC_readPort_rsp_mask; + assign popCC_readArbitation_translated_payload_sink = popCC_readPort_rsp_sink; + assign popCC_readArbitation_translated_payload_last = popCC_readPort_rsp_last; + assign io_pop_valid = popCC_readArbitation_translated_valid; + assign popCC_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_data = popCC_readArbitation_translated_payload_data; + assign io_pop_payload_mask = popCC_readArbitation_translated_payload_mask; + assign io_pop_payload_sink = popCC_readArbitation_translated_payload_sink; + assign io_pop_payload_last = popCC_readArbitation_translated_payload_last; + assign popCC_readArbitation_fire = (popCC_readArbitation_valid && popCC_readArbitation_ready); + assign _zz_io_popOccupancy = (popCC_pushPtrGray[1] ^ _zz_io_popOccupancy_1); + assign _zz_io_popOccupancy_1 = (popCC_pushPtrGray[2] ^ _zz_io_popOccupancy_2); + assign _zz_io_popOccupancy_2 = (popCC_pushPtrGray[3] ^ _zz_io_popOccupancy_3); + assign _zz_io_popOccupancy_3 = popCC_pushPtrGray[4]; + assign io_popOccupancy = ({_zz_io_popOccupancy_3,{_zz_io_popOccupancy_2,{_zz_io_popOccupancy_1,{_zz_io_popOccupancy,(popCC_pushPtrGray[0] ^ _zz_io_popOccupancy)}}}} - popCC_ptrToOccupancy); + assign pushToPopGray = pushCC_pushPtrGray; + assign popToPushGray = popCC_ptrToPush; + always @(posedge clk) begin + if(reset) begin + pushCC_pushPtr <= 5'h0; + pushCC_pushPtrGray <= 5'h0; + end else begin + if(io_push_fire) begin + pushCC_pushPtrGray <= (_zz_pushCC_pushPtrGray ^ pushCC_pushPtrPlus); + end + if(io_push_fire) begin + pushCC_pushPtr <= pushCC_pushPtrPlus; + end + end + end + + always @(posedge dat1_o_clk) begin + if(dat1_o_reset) begin + popCC_popPtr <= 5'h0; + popCC_addressGen_rValid <= 1'b0; + popCC_ptrToPush <= 5'h0; + popCC_ptrToOccupancy <= 5'h0; + end else begin + if(popCC_addressGen_fire) begin + popCC_popPtr <= popCC_popPtrPlus; + end + if(popCC_addressGen_ready) begin + popCC_addressGen_rValid <= popCC_addressGen_valid; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToPush <= popCC_popPtrGray; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToOccupancy <= popCC_popPtr; + end + end + end + + always @(posedge dat1_o_clk) begin + if(popCC_addressGen_ready) begin + popCC_addressGen_rData <= popCC_addressGen_payload; + end + end + + +endmodule + +module EfxDMA_StreamFifoCC_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_push_valid, + output wire io_push_ready, + input wire [63:0] io_push_payload_data, + input wire [7:0] io_push_payload_mask, + input wire [3:0] io_push_payload_sink, + input wire io_push_payload_last, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [63:0] io_pop_payload_data, + output wire [7:0] io_pop_payload_mask, + output wire [3:0] io_pop_payload_sink, + output wire io_pop_payload_last, + output wire [4:0] io_pushOccupancy, + output wire [4:0] io_popOccupancy, + input wire dat0_i_clk, + input wire dat0_i_reset, + input wire clk, + input wire reset +); + + reg [76:0] ram_spinal_port1; + wire [4:0] popToPushGray_buffercc_io_dataOut; + wire [4:0] pushToPopGray_buffercc_io_dataOut; + wire [4:0] _zz_pushCC_pushPtrGray; + wire [3:0] _zz_ram_port; + wire [76:0] _zz_ram_port_1; + wire [4:0] _zz_popCC_popPtrGray; + reg _zz_1; + wire [4:0] popToPushGray; + wire [4:0] pushToPopGray; + reg [4:0] pushCC_pushPtr; + wire [4:0] pushCC_pushPtrPlus; + wire io_push_fire; + reg [4:0] pushCC_pushPtrGray; + wire [4:0] pushCC_popPtrGray; + wire pushCC_full; + wire _zz_io_pushOccupancy; + wire _zz_io_pushOccupancy_1; + wire _zz_io_pushOccupancy_2; + wire _zz_io_pushOccupancy_3; + reg [4:0] popCC_popPtr; + (* keep , syn_keep *) wire [4:0] popCC_popPtrPlus /* synthesis syn_keep = 1 */ ; + wire [4:0] popCC_popPtrGray; + wire [4:0] popCC_pushPtrGray; + wire popCC_addressGen_valid; + reg popCC_addressGen_ready; + wire [3:0] popCC_addressGen_payload; + wire popCC_empty; + wire popCC_addressGen_fire; + wire popCC_readArbitation_valid; + wire popCC_readArbitation_ready; + wire [3:0] popCC_readArbitation_payload; + reg popCC_addressGen_rValid; + reg [3:0] popCC_addressGen_rData; + wire when_Stream_l375; + wire popCC_readPort_cmd_valid; + wire [3:0] popCC_readPort_cmd_payload; + wire [63:0] popCC_readPort_rsp_data; + wire [7:0] popCC_readPort_rsp_mask; + wire [3:0] popCC_readPort_rsp_sink; + wire popCC_readPort_rsp_last; + wire [76:0] _zz_popCC_readPort_rsp_data; + wire popCC_readArbitation_translated_valid; + wire popCC_readArbitation_translated_ready; + wire [63:0] popCC_readArbitation_translated_payload_data; + wire [7:0] popCC_readArbitation_translated_payload_mask; + wire [3:0] popCC_readArbitation_translated_payload_sink; + wire popCC_readArbitation_translated_payload_last; + wire popCC_readArbitation_fire; + reg [4:0] popCC_ptrToPush; + reg [4:0] popCC_ptrToOccupancy; + wire _zz_io_popOccupancy; + wire _zz_io_popOccupancy_1; + wire _zz_io_popOccupancy_2; + wire _zz_io_popOccupancy_3; + reg [76:0] ram [0:15]; + + assign _zz_pushCC_pushPtrGray = (pushCC_pushPtrPlus >>> 1'b1); + assign _zz_ram_port = pushCC_pushPtr[3:0]; + assign _zz_popCC_popPtrGray = (popCC_popPtr >>> 1'b1); + assign _zz_ram_port_1 = {io_push_payload_last,{io_push_payload_sink,{io_push_payload_mask,io_push_payload_data}}}; + always @(posedge dat0_i_clk) begin + if(_zz_1) begin + ram[_zz_ram_port] <= _zz_ram_port_1; + end + end + + always @(posedge clk) begin + if(popCC_readPort_cmd_valid) begin + ram_spinal_port1 <= ram[popCC_readPort_cmd_payload]; + end + end + + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_2_a048ca8f51874147a1cd65d43e6523ef popToPushGray_buffercc ( + .io_dataIn (popToPushGray[4:0] ), //i + .io_dataOut (popToPushGray_buffercc_io_dataOut[4:0]), //o + .dat0_i_clk (dat0_i_clk ), //i + .dat0_i_reset (dat0_i_reset ) //i + ); + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_3_a048ca8f51874147a1cd65d43e6523ef pushToPopGray_buffercc ( + .io_dataIn (pushToPopGray[4:0] ), //i + .io_dataOut (pushToPopGray_buffercc_io_dataOut[4:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + _zz_1 = 1'b0; + if(io_push_fire) begin + _zz_1 = 1'b1; + end + end + + assign pushCC_pushPtrPlus = (pushCC_pushPtr + 5'h01); + assign io_push_fire = (io_push_valid && io_push_ready); + assign pushCC_popPtrGray = popToPushGray_buffercc_io_dataOut; + assign pushCC_full = ((pushCC_pushPtrGray[4 : 3] == (~ pushCC_popPtrGray[4 : 3])) && (pushCC_pushPtrGray[2 : 0] == pushCC_popPtrGray[2 : 0])); + assign io_push_ready = (! pushCC_full); + assign _zz_io_pushOccupancy = (pushCC_popPtrGray[1] ^ _zz_io_pushOccupancy_1); + assign _zz_io_pushOccupancy_1 = (pushCC_popPtrGray[2] ^ _zz_io_pushOccupancy_2); + assign _zz_io_pushOccupancy_2 = (pushCC_popPtrGray[3] ^ _zz_io_pushOccupancy_3); + assign _zz_io_pushOccupancy_3 = pushCC_popPtrGray[4]; + assign io_pushOccupancy = (pushCC_pushPtr - {_zz_io_pushOccupancy_3,{_zz_io_pushOccupancy_2,{_zz_io_pushOccupancy_1,{_zz_io_pushOccupancy,(pushCC_popPtrGray[0] ^ _zz_io_pushOccupancy)}}}}); + assign popCC_popPtrPlus = (popCC_popPtr + 5'h01); + assign popCC_popPtrGray = (_zz_popCC_popPtrGray ^ popCC_popPtr); + assign popCC_pushPtrGray = pushToPopGray_buffercc_io_dataOut; + assign popCC_empty = (popCC_popPtrGray == popCC_pushPtrGray); + assign popCC_addressGen_valid = (! popCC_empty); + assign popCC_addressGen_payload = popCC_popPtr[3:0]; + assign popCC_addressGen_fire = (popCC_addressGen_valid && popCC_addressGen_ready); + always @(*) begin + popCC_addressGen_ready = popCC_readArbitation_ready; + if(when_Stream_l375) begin + popCC_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! popCC_readArbitation_valid); + assign popCC_readArbitation_valid = popCC_addressGen_rValid; + assign popCC_readArbitation_payload = popCC_addressGen_rData; + assign _zz_popCC_readPort_rsp_data = ram_spinal_port1; + assign popCC_readPort_rsp_data = _zz_popCC_readPort_rsp_data[63 : 0]; + assign popCC_readPort_rsp_mask = _zz_popCC_readPort_rsp_data[71 : 64]; + assign popCC_readPort_rsp_sink = _zz_popCC_readPort_rsp_data[75 : 72]; + assign popCC_readPort_rsp_last = _zz_popCC_readPort_rsp_data[76]; + assign popCC_readPort_cmd_valid = popCC_addressGen_fire; + assign popCC_readPort_cmd_payload = popCC_addressGen_payload; + assign popCC_readArbitation_translated_valid = popCC_readArbitation_valid; + assign popCC_readArbitation_ready = popCC_readArbitation_translated_ready; + assign popCC_readArbitation_translated_payload_data = popCC_readPort_rsp_data; + assign popCC_readArbitation_translated_payload_mask = popCC_readPort_rsp_mask; + assign popCC_readArbitation_translated_payload_sink = popCC_readPort_rsp_sink; + assign popCC_readArbitation_translated_payload_last = popCC_readPort_rsp_last; + assign io_pop_valid = popCC_readArbitation_translated_valid; + assign popCC_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_data = popCC_readArbitation_translated_payload_data; + assign io_pop_payload_mask = popCC_readArbitation_translated_payload_mask; + assign io_pop_payload_sink = popCC_readArbitation_translated_payload_sink; + assign io_pop_payload_last = popCC_readArbitation_translated_payload_last; + assign popCC_readArbitation_fire = (popCC_readArbitation_valid && popCC_readArbitation_ready); + assign _zz_io_popOccupancy = (popCC_pushPtrGray[1] ^ _zz_io_popOccupancy_1); + assign _zz_io_popOccupancy_1 = (popCC_pushPtrGray[2] ^ _zz_io_popOccupancy_2); + assign _zz_io_popOccupancy_2 = (popCC_pushPtrGray[3] ^ _zz_io_popOccupancy_3); + assign _zz_io_popOccupancy_3 = popCC_pushPtrGray[4]; + assign io_popOccupancy = ({_zz_io_popOccupancy_3,{_zz_io_popOccupancy_2,{_zz_io_popOccupancy_1,{_zz_io_popOccupancy,(popCC_pushPtrGray[0] ^ _zz_io_popOccupancy)}}}} - popCC_ptrToOccupancy); + assign pushToPopGray = pushCC_pushPtrGray; + assign popToPushGray = popCC_ptrToPush; + always @(posedge dat0_i_clk) begin + if(dat0_i_reset) begin + pushCC_pushPtr <= 5'h0; + pushCC_pushPtrGray <= 5'h0; + end else begin + if(io_push_fire) begin + pushCC_pushPtrGray <= (_zz_pushCC_pushPtrGray ^ pushCC_pushPtrPlus); + end + if(io_push_fire) begin + pushCC_pushPtr <= pushCC_pushPtrPlus; + end + end + end + + always @(posedge clk) begin + if(reset) begin + popCC_popPtr <= 5'h0; + popCC_addressGen_rValid <= 1'b0; + popCC_ptrToPush <= 5'h0; + popCC_ptrToOccupancy <= 5'h0; + end else begin + if(popCC_addressGen_fire) begin + popCC_popPtr <= popCC_popPtrPlus; + end + if(popCC_addressGen_ready) begin + popCC_addressGen_rValid <= popCC_addressGen_valid; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToPush <= popCC_popPtrGray; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToOccupancy <= popCC_popPtr; + end + end + end + + always @(posedge clk) begin + if(popCC_addressGen_ready) begin + popCC_addressGen_rData <= popCC_addressGen_payload; + end + end + + +endmodule + +module EfxDMA_BsbUpSizerDense_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_input_valid, + output wire io_input_ready, + input wire [7:0] io_input_payload_data, + input wire [0:0] io_input_payload_mask, + input wire [3:0] io_input_payload_sink, + input wire io_input_payload_last, + output wire io_output_valid, + input wire io_output_ready, + output wire [63:0] io_output_payload_data, + output wire [7:0] io_output_payload_mask, + output wire [3:0] io_output_payload_sink, + output wire io_output_payload_last, + input wire dat0_i_clk, + input wire dat0_i_reset +); + + reg valid; + reg [2:0] counter; + reg [63:0] buffer_data; + reg [7:0] buffer_mask; + reg [3:0] buffer_sink; + reg buffer_last; + wire full; + wire canAggregate; + wire onOutput; + wire [2:0] counterSample; + wire io_output_fire; + wire io_input_fire; + wire [7:0] _zz_1; + wire [7:0] _zz_2; + + assign full = ((counter == 3'b000) || buffer_last); + assign canAggregate = ((((valid && (! buffer_last)) && (! full)) && 1'b1) && (buffer_sink == io_input_payload_sink)); + assign counterSample = (canAggregate ? counter : 3'b000); + assign io_output_fire = (io_output_valid && io_output_ready); + assign io_input_fire = (io_input_valid && io_input_ready); + assign _zz_1 = ({7'd0,1'b1} <<< counterSample); + assign _zz_2 = ({7'd0,1'b1} <<< counterSample); + assign io_output_valid = (valid && ((valid && full) || (io_input_valid && (! canAggregate)))); + assign io_output_payload_data = buffer_data; + assign io_output_payload_mask = buffer_mask; + assign io_output_payload_sink = buffer_sink; + assign io_output_payload_last = buffer_last; + assign io_input_ready = (((! valid) || canAggregate) || io_output_ready); + always @(posedge dat0_i_clk) begin + if(dat0_i_reset) begin + valid <= 1'b0; + counter <= 3'b000; + buffer_last <= 1'b0; + buffer_mask <= 8'h0; + end else begin + if(io_output_fire) begin + valid <= 1'b0; + buffer_mask <= 8'h0; + end + if(io_input_fire) begin + valid <= 1'b1; + if(_zz_2[0]) begin + buffer_mask[0 : 0] <= io_input_payload_mask; + end + if(_zz_2[1]) begin + buffer_mask[1 : 1] <= io_input_payload_mask; + end + if(_zz_2[2]) begin + buffer_mask[2 : 2] <= io_input_payload_mask; + end + if(_zz_2[3]) begin + buffer_mask[3 : 3] <= io_input_payload_mask; + end + if(_zz_2[4]) begin + buffer_mask[4 : 4] <= io_input_payload_mask; + end + if(_zz_2[5]) begin + buffer_mask[5 : 5] <= io_input_payload_mask; + end + if(_zz_2[6]) begin + buffer_mask[6 : 6] <= io_input_payload_mask; + end + if(_zz_2[7]) begin + buffer_mask[7 : 7] <= io_input_payload_mask; + end + buffer_last <= io_input_payload_last; + counter <= (counterSample + 3'b001); + end + end + end + + always @(posedge dat0_i_clk) begin + if(io_input_fire) begin + buffer_sink <= io_input_payload_sink; + if(_zz_1[0]) begin + buffer_data[7 : 0] <= io_input_payload_data; + end + if(_zz_1[1]) begin + buffer_data[15 : 8] <= io_input_payload_data; + end + if(_zz_1[2]) begin + buffer_data[23 : 16] <= io_input_payload_data; + end + if(_zz_1[3]) begin + buffer_data[31 : 24] <= io_input_payload_data; + end + if(_zz_1[4]) begin + buffer_data[39 : 32] <= io_input_payload_data; + end + if(_zz_1[5]) begin + buffer_data[47 : 40] <= io_input_payload_data; + end + if(_zz_1[6]) begin + buffer_data[55 : 48] <= io_input_payload_data; + end + if(_zz_1[7]) begin + buffer_data[63 : 56] <= io_input_payload_data; + end + end + end + + +endmodule + +module EfxDMA_BmbToAxi4WriteOnlyBridge_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [127:0] io_input_cmd_payload_fragment_data, + input wire [15:0] io_input_cmd_payload_fragment_mask, + input wire [13:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [13:0] io_input_rsp_payload_fragment_context, + output wire io_output_aw_valid, + input wire io_output_aw_ready, + output wire [31:0] io_output_aw_payload_addr, + output wire [7:0] io_output_aw_payload_len, + output wire [2:0] io_output_aw_payload_size, + output wire [3:0] io_output_aw_payload_cache, + output wire [2:0] io_output_aw_payload_prot, + output wire io_output_w_valid, + input wire io_output_w_ready, + output wire [127:0] io_output_w_payload_data, + output wire [15:0] io_output_w_payload_strb, + output wire io_output_w_payload_last, + input wire io_output_b_valid, + output wire io_output_b_ready, + input wire [1:0] io_output_b_payload_resp, + input wire clk, + input wire reset +); + + reg contextRemover_io_output_cmd_ready; + reg [0:0] contextRemover_io_output_rsp_payload_fragment_opcode; + wire contextRemover_io_input_cmd_ready; + wire contextRemover_io_input_rsp_valid; + wire contextRemover_io_input_rsp_payload_last; + wire [0:0] contextRemover_io_input_rsp_payload_fragment_opcode; + wire [13:0] contextRemover_io_input_rsp_payload_fragment_context; + wire contextRemover_io_output_cmd_valid; + wire contextRemover_io_output_cmd_payload_last; + wire [0:0] contextRemover_io_output_cmd_payload_fragment_opcode; + wire [31:0] contextRemover_io_output_cmd_payload_fragment_address; + wire [11:0] contextRemover_io_output_cmd_payload_fragment_length; + wire [127:0] contextRemover_io_output_cmd_payload_fragment_data; + wire [15:0] contextRemover_io_output_cmd_payload_fragment_mask; + wire contextRemover_io_output_rsp_ready; + wire [8:0] _zz_io_output_aw_payload_len; + wire [12:0] _zz_io_output_aw_payload_len_1; + wire [12:0] _zz_io_output_aw_payload_len_2; + wire [3:0] _zz_io_output_aw_payload_len_3; + wire cmdFork_valid; + reg cmdFork_ready; + wire cmdFork_payload_last; + wire [0:0] cmdFork_payload_fragment_opcode; + wire [31:0] cmdFork_payload_fragment_address; + wire [11:0] cmdFork_payload_fragment_length; + wire [127:0] cmdFork_payload_fragment_data; + wire [15:0] cmdFork_payload_fragment_mask; + wire dataFork_valid; + wire dataFork_ready; + wire dataFork_payload_last; + wire [0:0] dataFork_payload_fragment_opcode; + wire [31:0] dataFork_payload_fragment_address; + wire [11:0] dataFork_payload_fragment_length; + wire [127:0] dataFork_payload_fragment_data; + wire [15:0] dataFork_payload_fragment_mask; + reg contextRemover_io_output_cmd_fork2_logic_linkEnable_0; + reg contextRemover_io_output_cmd_fork2_logic_linkEnable_1; + wire when_Stream_l1063; + wire when_Stream_l1063_1; + wire cmdFork_fire; + wire dataFork_fire; + wire contextRemover_io_output_cmd_fire; + reg contextRemover_io_output_cmd_payload_first; + wire when_Stream_l445; + reg cmdStage_valid; + wire cmdStage_ready; + wire cmdStage_payload_last; + wire [0:0] cmdStage_payload_fragment_opcode; + wire [31:0] cmdStage_payload_fragment_address; + wire [11:0] cmdStage_payload_fragment_length; + wire [127:0] cmdStage_payload_fragment_data; + wire [15:0] cmdStage_payload_fragment_mask; + wire when_BmbToAxi4Bridge_l297; + + assign _zz_io_output_aw_payload_len = _zz_io_output_aw_payload_len_1[12 : 4]; + assign _zz_io_output_aw_payload_len_1 = ({1'b0,cmdStage_payload_fragment_length} + _zz_io_output_aw_payload_len_2); + assign _zz_io_output_aw_payload_len_3 = cmdStage_payload_fragment_address[3 : 0]; + assign _zz_io_output_aw_payload_len_2 = {9'd0, _zz_io_output_aw_payload_len_3}; + EfxDMA_BmbContextRemover_1_a048ca8f51874147a1cd65d43e6523ef contextRemover ( + .io_input_cmd_valid (io_input_cmd_valid ), //i + .io_input_cmd_ready (contextRemover_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (io_input_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (io_input_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (io_input_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (io_input_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_data (io_input_cmd_payload_fragment_data[127:0] ), //i + .io_input_cmd_payload_fragment_mask (io_input_cmd_payload_fragment_mask[15:0] ), //i + .io_input_cmd_payload_fragment_context (io_input_cmd_payload_fragment_context[13:0] ), //i + .io_input_rsp_valid (contextRemover_io_input_rsp_valid ), //o + .io_input_rsp_ready (io_input_rsp_ready ), //i + .io_input_rsp_payload_last (contextRemover_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (contextRemover_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_context (contextRemover_io_input_rsp_payload_fragment_context[13:0] ), //o + .io_output_cmd_valid (contextRemover_io_output_cmd_valid ), //o + .io_output_cmd_ready (contextRemover_io_output_cmd_ready ), //i + .io_output_cmd_payload_last (contextRemover_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (contextRemover_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (contextRemover_io_output_cmd_payload_fragment_address[31:0]), //o + .io_output_cmd_payload_fragment_length (contextRemover_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_cmd_payload_fragment_data (contextRemover_io_output_cmd_payload_fragment_data[127:0] ), //o + .io_output_cmd_payload_fragment_mask (contextRemover_io_output_cmd_payload_fragment_mask[15:0] ), //o + .io_output_rsp_valid (io_output_b_valid ), //i + .io_output_rsp_ready (contextRemover_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (1'b1 ), //i + .io_output_rsp_payload_fragment_opcode (contextRemover_io_output_rsp_payload_fragment_opcode ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign io_input_cmd_ready = contextRemover_io_input_cmd_ready; + assign io_input_rsp_valid = contextRemover_io_input_rsp_valid; + assign io_input_rsp_payload_last = contextRemover_io_input_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = contextRemover_io_input_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_context = contextRemover_io_input_rsp_payload_fragment_context; + always @(*) begin + contextRemover_io_output_cmd_ready = 1'b1; + if(when_Stream_l1063) begin + contextRemover_io_output_cmd_ready = 1'b0; + end + if(when_Stream_l1063_1) begin + contextRemover_io_output_cmd_ready = 1'b0; + end + end + + assign when_Stream_l1063 = ((! cmdFork_ready) && contextRemover_io_output_cmd_fork2_logic_linkEnable_0); + assign when_Stream_l1063_1 = ((! dataFork_ready) && contextRemover_io_output_cmd_fork2_logic_linkEnable_1); + assign cmdFork_valid = (contextRemover_io_output_cmd_valid && contextRemover_io_output_cmd_fork2_logic_linkEnable_0); + assign cmdFork_payload_last = contextRemover_io_output_cmd_payload_last; + assign cmdFork_payload_fragment_opcode = contextRemover_io_output_cmd_payload_fragment_opcode; + assign cmdFork_payload_fragment_address = contextRemover_io_output_cmd_payload_fragment_address; + assign cmdFork_payload_fragment_length = contextRemover_io_output_cmd_payload_fragment_length; + assign cmdFork_payload_fragment_data = contextRemover_io_output_cmd_payload_fragment_data; + assign cmdFork_payload_fragment_mask = contextRemover_io_output_cmd_payload_fragment_mask; + assign cmdFork_fire = (cmdFork_valid && cmdFork_ready); + assign dataFork_valid = (contextRemover_io_output_cmd_valid && contextRemover_io_output_cmd_fork2_logic_linkEnable_1); + assign dataFork_payload_last = contextRemover_io_output_cmd_payload_last; + assign dataFork_payload_fragment_opcode = contextRemover_io_output_cmd_payload_fragment_opcode; + assign dataFork_payload_fragment_address = contextRemover_io_output_cmd_payload_fragment_address; + assign dataFork_payload_fragment_length = contextRemover_io_output_cmd_payload_fragment_length; + assign dataFork_payload_fragment_data = contextRemover_io_output_cmd_payload_fragment_data; + assign dataFork_payload_fragment_mask = contextRemover_io_output_cmd_payload_fragment_mask; + assign dataFork_fire = (dataFork_valid && dataFork_ready); + assign contextRemover_io_output_cmd_fire = (contextRemover_io_output_cmd_valid && contextRemover_io_output_cmd_ready); + assign when_Stream_l445 = (! contextRemover_io_output_cmd_payload_first); + always @(*) begin + cmdStage_valid = cmdFork_valid; + if(when_Stream_l445) begin + cmdStage_valid = 1'b0; + end + end + + always @(*) begin + cmdFork_ready = cmdStage_ready; + if(when_Stream_l445) begin + cmdFork_ready = 1'b1; + end + end + + assign cmdStage_payload_last = cmdFork_payload_last; + assign cmdStage_payload_fragment_opcode = cmdFork_payload_fragment_opcode; + assign cmdStage_payload_fragment_address = cmdFork_payload_fragment_address; + assign cmdStage_payload_fragment_length = cmdFork_payload_fragment_length; + assign cmdStage_payload_fragment_data = cmdFork_payload_fragment_data; + assign cmdStage_payload_fragment_mask = cmdFork_payload_fragment_mask; + assign io_output_aw_valid = cmdStage_valid; + assign cmdStage_ready = io_output_aw_ready; + assign io_output_aw_payload_addr = cmdStage_payload_fragment_address; + assign io_output_aw_payload_len = _zz_io_output_aw_payload_len[7:0]; + assign io_output_aw_payload_size = 3'b100; + assign io_output_aw_payload_prot = 3'b010; + assign io_output_aw_payload_cache = 4'b1111; + assign io_output_w_valid = dataFork_valid; + assign dataFork_ready = io_output_w_ready; + assign io_output_w_payload_data = dataFork_payload_fragment_data; + assign io_output_w_payload_strb = dataFork_payload_fragment_mask; + assign io_output_w_payload_last = dataFork_payload_last; + assign io_output_b_ready = contextRemover_io_output_rsp_ready; + assign when_BmbToAxi4Bridge_l297 = (io_output_b_payload_resp == 2'b00); + always @(*) begin + if(when_BmbToAxi4Bridge_l297) begin + contextRemover_io_output_rsp_payload_fragment_opcode = 1'b0; + end else begin + contextRemover_io_output_rsp_payload_fragment_opcode = 1'b1; + end + end + + always @(posedge clk) begin + if(reset) begin + contextRemover_io_output_cmd_fork2_logic_linkEnable_0 <= 1'b1; + contextRemover_io_output_cmd_fork2_logic_linkEnable_1 <= 1'b1; + contextRemover_io_output_cmd_payload_first <= 1'b1; + end else begin + if(cmdFork_fire) begin + contextRemover_io_output_cmd_fork2_logic_linkEnable_0 <= 1'b0; + end + if(dataFork_fire) begin + contextRemover_io_output_cmd_fork2_logic_linkEnable_1 <= 1'b0; + end + if(contextRemover_io_output_cmd_ready) begin + contextRemover_io_output_cmd_fork2_logic_linkEnable_0 <= 1'b1; + contextRemover_io_output_cmd_fork2_logic_linkEnable_1 <= 1'b1; + end + if(contextRemover_io_output_cmd_fire) begin + contextRemover_io_output_cmd_payload_first <= contextRemover_io_output_cmd_payload_last; + end + end + end + + +endmodule + +module EfxDMA_BmbSourceRemover_1_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_source, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [127:0] io_input_cmd_payload_fragment_data, + input wire [15:0] io_input_cmd_payload_fragment_mask, + input wire [12:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_source, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [12:0] io_input_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + output wire [127:0] io_output_cmd_payload_fragment_data, + output wire [15:0] io_output_cmd_payload_fragment_mask, + output wire [13:0] io_output_cmd_payload_fragment_context, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [13:0] io_output_rsp_payload_fragment_context +); + + wire [0:0] cmdContext_source; + wire [12:0] cmdContext_context; + wire [0:0] rspContext_source; + wire [12:0] rspContext_context; + wire [13:0] _zz_rspContext_source; + + assign cmdContext_source = io_input_cmd_payload_fragment_source; + assign cmdContext_context = io_input_cmd_payload_fragment_context; + assign io_output_cmd_valid = io_input_cmd_valid; + assign io_input_cmd_ready = io_output_cmd_ready; + assign io_output_cmd_payload_last = io_input_cmd_payload_last; + assign io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign io_output_cmd_payload_fragment_context = {cmdContext_context,cmdContext_source}; + assign _zz_rspContext_source = io_output_rsp_payload_fragment_context; + assign rspContext_source = _zz_rspContext_source[0 : 0]; + assign rspContext_context = _zz_rspContext_source[13 : 1]; + assign io_input_rsp_valid = io_output_rsp_valid; + assign io_output_rsp_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = io_output_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_source = rspContext_source; + assign io_input_rsp_payload_fragment_context = rspContext_context; + +endmodule + +module EfxDMA_BmbToAxi4ReadOnlyBridge_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [21:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [127:0] io_input_rsp_payload_fragment_data, + output wire [21:0] io_input_rsp_payload_fragment_context, + output wire io_output_ar_valid, + input wire io_output_ar_ready, + output wire [31:0] io_output_ar_payload_addr, + output wire [7:0] io_output_ar_payload_len, + output wire [2:0] io_output_ar_payload_size, + output wire [3:0] io_output_ar_payload_cache, + output wire [2:0] io_output_ar_payload_prot, + input wire io_output_r_valid, + output wire io_output_r_ready, + input wire [127:0] io_output_r_payload_data, + input wire [1:0] io_output_r_payload_resp, + input wire io_output_r_payload_last, + input wire clk, + input wire reset +); + + reg [0:0] contextRemover_io_output_rsp_payload_fragment_opcode; + wire contextRemover_io_input_cmd_ready; + wire contextRemover_io_input_rsp_valid; + wire contextRemover_io_input_rsp_payload_last; + wire [0:0] contextRemover_io_input_rsp_payload_fragment_opcode; + wire [127:0] contextRemover_io_input_rsp_payload_fragment_data; + wire [21:0] contextRemover_io_input_rsp_payload_fragment_context; + wire contextRemover_io_output_cmd_valid; + wire contextRemover_io_output_cmd_payload_last; + wire [0:0] contextRemover_io_output_cmd_payload_fragment_opcode; + wire [31:0] contextRemover_io_output_cmd_payload_fragment_address; + wire [11:0] contextRemover_io_output_cmd_payload_fragment_length; + wire contextRemover_io_output_rsp_ready; + wire [8:0] _zz_io_output_ar_payload_len; + wire [12:0] _zz_io_output_ar_payload_len_1; + wire [12:0] _zz_io_output_ar_payload_len_2; + wire [3:0] _zz_io_output_ar_payload_len_3; + wire when_BmbToAxi4Bridge_l243; + + assign _zz_io_output_ar_payload_len = _zz_io_output_ar_payload_len_1[12 : 4]; + assign _zz_io_output_ar_payload_len_1 = ({1'b0,contextRemover_io_output_cmd_payload_fragment_length} + _zz_io_output_ar_payload_len_2); + assign _zz_io_output_ar_payload_len_3 = contextRemover_io_output_cmd_payload_fragment_address[3 : 0]; + assign _zz_io_output_ar_payload_len_2 = {9'd0, _zz_io_output_ar_payload_len_3}; + EfxDMA_BmbContextRemover_a048ca8f51874147a1cd65d43e6523ef contextRemover ( + .io_input_cmd_valid (io_input_cmd_valid ), //i + .io_input_cmd_ready (contextRemover_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (io_input_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (io_input_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (io_input_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (io_input_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_context (io_input_cmd_payload_fragment_context[21:0] ), //i + .io_input_rsp_valid (contextRemover_io_input_rsp_valid ), //o + .io_input_rsp_ready (io_input_rsp_ready ), //i + .io_input_rsp_payload_last (contextRemover_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (contextRemover_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (contextRemover_io_input_rsp_payload_fragment_data[127:0] ), //o + .io_input_rsp_payload_fragment_context (contextRemover_io_input_rsp_payload_fragment_context[21:0] ), //o + .io_output_cmd_valid (contextRemover_io_output_cmd_valid ), //o + .io_output_cmd_ready (io_output_ar_ready ), //i + .io_output_cmd_payload_last (contextRemover_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (contextRemover_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (contextRemover_io_output_cmd_payload_fragment_address[31:0]), //o + .io_output_cmd_payload_fragment_length (contextRemover_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_rsp_valid (io_output_r_valid ), //i + .io_output_rsp_ready (contextRemover_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (io_output_r_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (contextRemover_io_output_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (io_output_r_payload_data[127:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign io_input_cmd_ready = contextRemover_io_input_cmd_ready; + assign io_input_rsp_valid = contextRemover_io_input_rsp_valid; + assign io_input_rsp_payload_last = contextRemover_io_input_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = contextRemover_io_input_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = contextRemover_io_input_rsp_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = contextRemover_io_input_rsp_payload_fragment_context; + assign io_output_ar_valid = contextRemover_io_output_cmd_valid; + assign io_output_ar_payload_addr = contextRemover_io_output_cmd_payload_fragment_address; + assign io_output_ar_payload_len = _zz_io_output_ar_payload_len[7:0]; + assign io_output_ar_payload_size = 3'b100; + assign io_output_ar_payload_prot = 3'b010; + assign io_output_ar_payload_cache = 4'b1111; + assign io_output_r_ready = contextRemover_io_output_rsp_ready; + assign when_BmbToAxi4Bridge_l243 = (io_output_r_payload_resp == 2'b00); + always @(*) begin + if(when_BmbToAxi4Bridge_l243) begin + contextRemover_io_output_rsp_payload_fragment_opcode = 1'b0; + end else begin + contextRemover_io_output_rsp_payload_fragment_opcode = 1'b1; + end + end + + +endmodule + +module EfxDMA_BmbSourceRemover_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_source, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [20:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_source, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [127:0] io_input_rsp_payload_fragment_data, + output wire [20:0] io_input_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + output wire [21:0] io_output_cmd_payload_fragment_context, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [127:0] io_output_rsp_payload_fragment_data, + input wire [21:0] io_output_rsp_payload_fragment_context +); + + wire [0:0] cmdContext_source; + wire [20:0] cmdContext_context; + wire [0:0] rspContext_source; + wire [20:0] rspContext_context; + wire [21:0] _zz_rspContext_source; + + assign cmdContext_source = io_input_cmd_payload_fragment_source; + assign cmdContext_context = io_input_cmd_payload_fragment_context; + assign io_output_cmd_valid = io_input_cmd_valid; + assign io_input_cmd_ready = io_output_cmd_ready; + assign io_output_cmd_payload_last = io_input_cmd_payload_last; + assign io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign io_output_cmd_payload_fragment_context = {cmdContext_context,cmdContext_source}; + assign _zz_rspContext_source = io_output_rsp_payload_fragment_context; + assign rspContext_source = _zz_rspContext_source[0 : 0]; + assign rspContext_context = _zz_rspContext_source[21 : 1]; + assign io_input_rsp_valid = io_output_rsp_valid; + assign io_output_rsp_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = io_output_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_input_rsp_payload_fragment_source = rspContext_source; + assign io_input_rsp_payload_fragment_context = rspContext_context; + +endmodule + +module EfxDMA_BufferCC_6_a048ca8f51874147a1cd65d43e6523ef ( + input wire [1:0] io_dataIn, + output wire [1:0] io_dataOut, + input wire ctrl_clk, + input wire ctrl_reset +); + + (* async_reg = "true" *) reg [1:0] buffers_0; + (* async_reg = "true" *) reg [1:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge ctrl_clk) begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + + +endmodule + +module EfxDMA_Apb3CC_a048ca8f51874147a1cd65d43e6523ef ( + input wire [13:0] io_input_PADDR, + input wire [0:0] io_input_PSEL, + input wire io_input_PENABLE, + output wire io_input_PREADY, + input wire io_input_PWRITE, + input wire [31:0] io_input_PWDATA, + output wire [31:0] io_input_PRDATA, + output wire io_input_PSLVERROR, + output wire [13:0] io_output_PADDR, + output reg [0:0] io_output_PSEL, + output reg io_output_PENABLE, + input wire io_output_PREADY, + output wire io_output_PWRITE, + output wire [31:0] io_output_PWDATA, + input wire [31:0] io_output_PRDATA, + input wire io_output_PSLVERROR, + input wire ctrl_clk, + input wire ctrl_reset, + input wire clk, + input wire reset +); + + wire flowCCUnsafeByToggle_io_output_valid; + wire [13:0] flowCCUnsafeByToggle_io_output_payload_PADDR; + wire flowCCUnsafeByToggle_io_output_payload_PWRITE; + wire [31:0] flowCCUnsafeByToggle_io_output_payload_PWDATA; + wire flowCCUnsafeByToggle_1_io_output_valid; + wire [31:0] flowCCUnsafeByToggle_1_io_output_payload_PRDATA; + wire flowCCUnsafeByToggle_1_io_output_payload_PSLVERROR; + wire inputLogic_inputCmd_valid; + wire [13:0] inputLogic_inputCmd_payload_PADDR; + wire inputLogic_inputCmd_payload_PWRITE; + wire [31:0] inputLogic_inputCmd_payload_PWDATA; + wire inputLogic_inputRsp_valid; + wire [31:0] inputLogic_inputRsp_payload_PRDATA; + wire inputLogic_inputRsp_payload_PSLVERROR; + reg inputLogic_state; + wire flowCCUnsafeByToggle_io_output_toStream_valid; + reg flowCCUnsafeByToggle_io_output_toStream_ready; + wire [13:0] flowCCUnsafeByToggle_io_output_toStream_payload_PADDR; + wire flowCCUnsafeByToggle_io_output_toStream_payload_PWRITE; + wire [31:0] flowCCUnsafeByToggle_io_output_toStream_payload_PWDATA; + wire outputLogic_outputCmd_valid; + reg outputLogic_outputCmd_ready; + wire [13:0] outputLogic_outputCmd_payload_PADDR; + wire outputLogic_outputCmd_payload_PWRITE; + wire [31:0] outputLogic_outputCmd_payload_PWDATA; + reg flowCCUnsafeByToggle_io_output_toStream_rValid; + wire flowCCUnsafeByToggle_io_output_toStream_fire; + (* async_reg = "true" *) reg [13:0] flowCCUnsafeByToggle_io_output_toStream_rData_PADDR; + (* async_reg = "true" *) reg flowCCUnsafeByToggle_io_output_toStream_rData_PWRITE; + (* async_reg = "true" *) reg [31:0] flowCCUnsafeByToggle_io_output_toStream_rData_PWDATA; + wire when_Stream_l375; + reg outputLogic_state; + wire when_Apb3CCToggle_l81; + wire outputLogic_outputRsp_valid; + wire [31:0] outputLogic_outputRsp_payload_PRDATA; + wire outputLogic_outputRsp_payload_PSLVERROR; + wire outputLogic_outputCmd_fire; + + EfxDMA_FlowCCUnsafeByToggle_a048ca8f51874147a1cd65d43e6523ef flowCCUnsafeByToggle ( + .io_input_valid (inputLogic_inputCmd_valid ), //i + .io_input_payload_PADDR (inputLogic_inputCmd_payload_PADDR[13:0] ), //i + .io_input_payload_PWRITE (inputLogic_inputCmd_payload_PWRITE ), //i + .io_input_payload_PWDATA (inputLogic_inputCmd_payload_PWDATA[31:0] ), //i + .io_output_valid (flowCCUnsafeByToggle_io_output_valid ), //o + .io_output_payload_PADDR (flowCCUnsafeByToggle_io_output_payload_PADDR[13:0] ), //o + .io_output_payload_PWRITE (flowCCUnsafeByToggle_io_output_payload_PWRITE ), //o + .io_output_payload_PWDATA (flowCCUnsafeByToggle_io_output_payload_PWDATA[31:0]), //o + .ctrl_clk (ctrl_clk ), //i + .ctrl_reset (ctrl_reset ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_FlowCCUnsafeByToggle_1_a048ca8f51874147a1cd65d43e6523ef flowCCUnsafeByToggle_1 ( + .io_input_valid (outputLogic_outputRsp_valid ), //i + .io_input_payload_PRDATA (outputLogic_outputRsp_payload_PRDATA[31:0] ), //i + .io_input_payload_PSLVERROR (outputLogic_outputRsp_payload_PSLVERROR ), //i + .io_output_valid (flowCCUnsafeByToggle_1_io_output_valid ), //o + .io_output_payload_PRDATA (flowCCUnsafeByToggle_1_io_output_payload_PRDATA[31:0]), //o + .io_output_payload_PSLVERROR (flowCCUnsafeByToggle_1_io_output_payload_PSLVERROR ), //o + .clk (clk ), //i + .reset (reset ), //i + .ctrl_clk (ctrl_clk ), //i + .ctrl_reset (ctrl_reset ) //i + ); + assign inputLogic_inputCmd_valid = ((io_input_PSEL[0] && io_input_PENABLE) && (! inputLogic_state)); + assign inputLogic_inputCmd_payload_PADDR = io_input_PADDR; + assign inputLogic_inputCmd_payload_PWRITE = io_input_PWRITE; + assign inputLogic_inputCmd_payload_PWDATA = io_input_PWDATA; + assign io_input_PREADY = inputLogic_inputRsp_valid; + assign io_input_PRDATA = inputLogic_inputRsp_payload_PRDATA; + assign io_input_PSLVERROR = inputLogic_inputRsp_payload_PSLVERROR; + assign flowCCUnsafeByToggle_io_output_toStream_valid = flowCCUnsafeByToggle_io_output_valid; + assign flowCCUnsafeByToggle_io_output_toStream_payload_PADDR = flowCCUnsafeByToggle_io_output_payload_PADDR; + assign flowCCUnsafeByToggle_io_output_toStream_payload_PWRITE = flowCCUnsafeByToggle_io_output_payload_PWRITE; + assign flowCCUnsafeByToggle_io_output_toStream_payload_PWDATA = flowCCUnsafeByToggle_io_output_payload_PWDATA; + assign flowCCUnsafeByToggle_io_output_toStream_fire = (flowCCUnsafeByToggle_io_output_toStream_valid && flowCCUnsafeByToggle_io_output_toStream_ready); + always @(*) begin + flowCCUnsafeByToggle_io_output_toStream_ready = outputLogic_outputCmd_ready; + if(when_Stream_l375) begin + flowCCUnsafeByToggle_io_output_toStream_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! outputLogic_outputCmd_valid); + assign outputLogic_outputCmd_valid = flowCCUnsafeByToggle_io_output_toStream_rValid; + assign outputLogic_outputCmd_payload_PADDR = flowCCUnsafeByToggle_io_output_toStream_rData_PADDR; + assign outputLogic_outputCmd_payload_PWRITE = flowCCUnsafeByToggle_io_output_toStream_rData_PWRITE; + assign outputLogic_outputCmd_payload_PWDATA = flowCCUnsafeByToggle_io_output_toStream_rData_PWDATA; + always @(*) begin + io_output_PENABLE = 1'b0; + if(outputLogic_outputCmd_valid) begin + if(when_Apb3CCToggle_l81) begin + io_output_PENABLE = 1'b0; + end else begin + io_output_PENABLE = 1'b1; + end + end + end + + always @(*) begin + io_output_PSEL = 1'b0; + if(outputLogic_outputCmd_valid) begin + io_output_PSEL = 1'b1; + end + end + + assign io_output_PADDR = outputLogic_outputCmd_payload_PADDR; + assign io_output_PWDATA = outputLogic_outputCmd_payload_PWDATA; + assign io_output_PWRITE = outputLogic_outputCmd_payload_PWRITE; + always @(*) begin + outputLogic_outputCmd_ready = 1'b0; + if(outputLogic_outputCmd_valid) begin + if(!when_Apb3CCToggle_l81) begin + if(io_output_PREADY) begin + outputLogic_outputCmd_ready = 1'b1; + end + end + end + end + + assign when_Apb3CCToggle_l81 = (! outputLogic_state); + assign outputLogic_outputCmd_fire = (outputLogic_outputCmd_valid && outputLogic_outputCmd_ready); + assign outputLogic_outputRsp_valid = outputLogic_outputCmd_fire; + assign outputLogic_outputRsp_payload_PRDATA = io_output_PRDATA; + assign outputLogic_outputRsp_payload_PSLVERROR = io_output_PSLVERROR; + assign inputLogic_inputRsp_valid = flowCCUnsafeByToggle_1_io_output_valid; + assign inputLogic_inputRsp_payload_PRDATA = flowCCUnsafeByToggle_1_io_output_payload_PRDATA; + assign inputLogic_inputRsp_payload_PSLVERROR = flowCCUnsafeByToggle_1_io_output_payload_PSLVERROR; + always @(posedge ctrl_clk) begin + if(ctrl_reset) begin + inputLogic_state <= 1'b0; + end else begin + if(inputLogic_inputCmd_valid) begin + inputLogic_state <= 1'b1; + end + if(inputLogic_inputRsp_valid) begin + inputLogic_state <= 1'b0; + end + end + end + + always @(posedge clk) begin + if(reset) begin + flowCCUnsafeByToggle_io_output_toStream_rValid <= 1'b0; + outputLogic_state <= 1'b0; + end else begin + if(flowCCUnsafeByToggle_io_output_toStream_ready) begin + flowCCUnsafeByToggle_io_output_toStream_rValid <= flowCCUnsafeByToggle_io_output_toStream_valid; + end + if(outputLogic_outputCmd_valid) begin + if(when_Apb3CCToggle_l81) begin + outputLogic_state <= 1'b1; + end else begin + if(io_output_PREADY) begin + outputLogic_state <= 1'b0; + end + end + end + end + end + + always @(posedge clk) begin + if(flowCCUnsafeByToggle_io_output_toStream_fire) begin + flowCCUnsafeByToggle_io_output_toStream_rData_PADDR <= flowCCUnsafeByToggle_io_output_toStream_payload_PADDR; + flowCCUnsafeByToggle_io_output_toStream_rData_PWRITE <= flowCCUnsafeByToggle_io_output_toStream_payload_PWRITE; + flowCCUnsafeByToggle_io_output_toStream_rData_PWDATA <= flowCCUnsafeByToggle_io_output_toStream_payload_PWDATA; + end + end + + +endmodule + +module EfxDMA_Core_a048ca8f51874147a1cd65d43e6523ef ( + output wire io_sgRead_cmd_valid, + input wire io_sgRead_cmd_ready, + output wire io_sgRead_cmd_payload_last, + output wire [0:0] io_sgRead_cmd_payload_fragment_opcode, + output wire [31:0] io_sgRead_cmd_payload_fragment_address, + output wire [4:0] io_sgRead_cmd_payload_fragment_length, + output wire [0:0] io_sgRead_cmd_payload_fragment_context, + input wire io_sgRead_rsp_valid, + output wire io_sgRead_rsp_ready, + input wire io_sgRead_rsp_payload_last, + input wire [0:0] io_sgRead_rsp_payload_fragment_opcode, + input wire [127:0] io_sgRead_rsp_payload_fragment_data, + input wire [0:0] io_sgRead_rsp_payload_fragment_context, + output wire io_sgWrite_cmd_valid, + input wire io_sgWrite_cmd_ready, + output wire io_sgWrite_cmd_payload_last, + output wire [0:0] io_sgWrite_cmd_payload_fragment_opcode, + output wire [31:0] io_sgWrite_cmd_payload_fragment_address, + output wire [1:0] io_sgWrite_cmd_payload_fragment_length, + output reg [127:0] io_sgWrite_cmd_payload_fragment_data, + output reg [15:0] io_sgWrite_cmd_payload_fragment_mask, + output wire [0:0] io_sgWrite_cmd_payload_fragment_context, + input wire io_sgWrite_rsp_valid, + output wire io_sgWrite_rsp_ready, + input wire io_sgWrite_rsp_payload_last, + input wire [0:0] io_sgWrite_rsp_payload_fragment_opcode, + input wire [0:0] io_sgWrite_rsp_payload_fragment_context, + output reg io_read_cmd_valid, + input wire io_read_cmd_ready, + output wire io_read_cmd_payload_last, + output wire [0:0] io_read_cmd_payload_fragment_opcode, + output wire [31:0] io_read_cmd_payload_fragment_address, + output wire [11:0] io_read_cmd_payload_fragment_length, + output wire [20:0] io_read_cmd_payload_fragment_context, + input wire io_read_rsp_valid, + output wire io_read_rsp_ready, + input wire io_read_rsp_payload_last, + input wire [0:0] io_read_rsp_payload_fragment_opcode, + input wire [127:0] io_read_rsp_payload_fragment_data, + input wire [20:0] io_read_rsp_payload_fragment_context, + output wire io_write_cmd_valid, + input wire io_write_cmd_ready, + output wire io_write_cmd_payload_last, + output wire [0:0] io_write_cmd_payload_fragment_opcode, + output wire [31:0] io_write_cmd_payload_fragment_address, + output wire [11:0] io_write_cmd_payload_fragment_length, + output wire [127:0] io_write_cmd_payload_fragment_data, + output wire [15:0] io_write_cmd_payload_fragment_mask, + output wire [12:0] io_write_cmd_payload_fragment_context, + input wire io_write_rsp_valid, + output wire io_write_rsp_ready, + input wire io_write_rsp_payload_last, + input wire [0:0] io_write_rsp_payload_fragment_opcode, + input wire [12:0] io_write_rsp_payload_fragment_context, + output wire io_outputs_0_valid, + input wire io_outputs_0_ready, + output wire [63:0] io_outputs_0_payload_data, + output wire [7:0] io_outputs_0_payload_mask, + output wire [3:0] io_outputs_0_payload_sink, + output wire io_outputs_0_payload_last, + input wire io_inputs_0_valid, + output reg io_inputs_0_ready, + input wire [63:0] io_inputs_0_payload_data, + input wire [7:0] io_inputs_0_payload_mask, + input wire [3:0] io_inputs_0_payload_sink, + input wire io_inputs_0_payload_last, + output reg [1:0] io_interrupts, + input wire [13:0] io_ctrl_PADDR, + input wire [0:0] io_ctrl_PSEL, + input wire io_ctrl_PENABLE, + output wire io_ctrl_PREADY, + input wire io_ctrl_PWRITE, + input wire [31:0] io_ctrl_PWDATA, + output reg [31:0] io_ctrl_PRDATA, + output wire io_ctrl_PSLVERROR, + output wire ll_0_descriptorUpdate, + output wire ll_1_descriptorUpdate, + input wire clk, + input wire reset +); + + wire [9:0] memory_core_io_writes_0_cmd_payload_address; + wire [6:0] memory_core_io_writes_0_cmd_payload_context; + wire [9:0] memory_core_io_writes_1_cmd_payload_address; + reg [15:0] memory_core_io_writes_1_cmd_payload_mask; + wire [6:0] memory_core_io_writes_1_cmd_payload_context; + wire memory_core_io_reads_0_cmd_valid; + wire [9:0] memory_core_io_reads_0_cmd_payload_address; + wire [2:0] memory_core_io_reads_0_cmd_payload_context; + wire [9:0] memory_core_io_reads_1_cmd_payload_address; + wire [11:0] memory_core_io_reads_1_cmd_payload_context; + wire [15:0] b2m_fsm_aggregate_engine_io_input_payload_mask; + wire b2m_fsm_aggregate_engine_io_flush; + wire [3:0] b2m_fsm_aggregate_engine_io_offset; + wire memory_core_io_writes_0_cmd_ready; + wire memory_core_io_writes_0_rsp_valid; + wire [6:0] memory_core_io_writes_0_rsp_payload_context; + wire memory_core_io_writes_1_cmd_ready; + wire memory_core_io_writes_1_rsp_valid; + wire [6:0] memory_core_io_writes_1_rsp_payload_context; + wire memory_core_io_reads_0_cmd_ready; + wire memory_core_io_reads_0_rsp_valid; + wire [63:0] memory_core_io_reads_0_rsp_payload_data; + wire [7:0] memory_core_io_reads_0_rsp_payload_mask; + wire [2:0] memory_core_io_reads_0_rsp_payload_context; + wire memory_core_io_reads_1_cmd_ready; + wire memory_core_io_reads_1_rsp_valid; + wire [127:0] memory_core_io_reads_1_rsp_payload_data; + wire [15:0] memory_core_io_reads_1_rsp_payload_mask; + wire [11:0] memory_core_io_reads_1_rsp_payload_context; + wire b2m_fsm_aggregate_engine_io_input_ready; + wire [127:0] b2m_fsm_aggregate_engine_io_output_data; + wire [15:0] b2m_fsm_aggregate_engine_io_output_mask; + wire b2m_fsm_aggregate_engine_io_output_consumed; + wire [3:0] b2m_fsm_aggregate_engine_io_output_usedUntil; + wire [26:0] _zz_channels_0_bytesProbe_value; + wire [26:0] _zz_channels_0_bytesProbe_value_1; + wire [13:0] _zz_channels_0_fifo_pop_withOverride_backupNext; + wire [13:0] _zz_channels_0_fifo_pop_withOverride_exposed; + wire [26:0] _zz_channels_0_pop_b2m_selfFlush; + wire [13:0] _zz_channels_0_pop_b2m_request; + wire [10:0] _zz_channels_0_pop_b2m_request_1; + wire [9:0] _zz_channels_0_pop_b2m_request_2; + wire [3:0] _zz_channels_0_pop_b2m_memPending; + wire [3:0] _zz_channels_0_pop_b2m_memPending_1; + wire [0:0] _zz_channels_0_pop_b2m_memPending_2; + wire [3:0] _zz_channels_0_pop_b2m_memPending_3; + wire [0:0] _zz_channels_0_pop_b2m_memPending_4; + wire [10:0] _zz_channels_0_fifo_push_available; + wire [26:0] _zz_channels_1_bytesProbe_value; + wire [26:0] _zz_channels_1_bytesProbe_value_1; + wire [13:0] _zz_channels_1_fifo_pop_withoutOverride_exposed; + wire [3:0] _zz_channels_1_push_m2b_memPending; + wire [3:0] _zz_channels_1_push_m2b_memPending_1; + wire [0:0] _zz_channels_1_push_m2b_memPending_2; + wire [3:0] _zz_channels_1_push_m2b_memPending_3; + wire [0:0] _zz_channels_1_push_m2b_memPending_4; + wire [10:0] _zz_channels_1_push_m2b_loadRequest; + wire [8:0] _zz_channels_1_push_m2b_loadRequest_1; + wire [25:0] _zz_when_DmaSg_l486; + wire [10:0] _zz_channels_1_fifo_push_available; + wire [0:0] _zz_s2b_0_cmd_firsts; + wire [4:0] _zz_s2b_0_cmd_firsts_1; + wire [3:0] _zz_s2b_0_cmd_byteCount_8; + reg [3:0] _zz_s2b_0_cmd_byteCount_9; + wire [2:0] _zz_s2b_0_cmd_byteCount_10; + reg [3:0] _zz_s2b_0_cmd_byteCount_11; + wire [2:0] _zz_s2b_0_cmd_byteCount_12; + reg [3:0] _zz_s2b_0_cmd_byteCount_13; + wire [2:0] _zz_s2b_0_cmd_byteCount_14; + wire [1:0] _zz_s2b_0_cmd_byteCount_15; + wire [1:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2; + wire [1:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2_1; + wire [0:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2_2; + reg [0:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3; + wire [25:0] _zz_m2b_cmd_s0_length; + wire [25:0] _zz_m2b_cmd_s0_length_1; + wire [25:0] _zz_m2b_cmd_s0_length_2; + wire [25:0] _zz_m2b_cmd_s0_lastBurst; + wire [31:0] _zz_m2b_cmd_s1_context_stop; + wire [31:0] _zz_m2b_cmd_s1_context_stop_1; + wire [31:0] _zz_m2b_cmd_s1_addressNext; + wire [31:0] _zz_m2b_cmd_s1_addressNext_1; + wire [25:0] _zz_m2b_cmd_s1_byteLeftNext; + wire [25:0] _zz_m2b_cmd_s1_byteLeftNext_1; + wire [12:0] _zz_m2b_cmd_s1_fifoPushDecr; + wire [11:0] _zz_m2b_cmd_s1_fifoPushDecr_1; + wire [11:0] _zz_m2b_cmd_s1_fifoPushDecr_2; + wire [3:0] _zz_m2b_cmd_s1_fifoPushDecr_3; + wire [12:0] _zz_m2b_cmd_s1_fifoPushDecr_4; + wire [1:0] _zz_m2b_cmd_s1_fifoPushDecr_5; + wire [1:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2; + wire [1:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_1; + wire [0:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_2; + reg [0:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3; + wire [0:0] _zz_when; + wire [12:0] _zz_b2m_fsm_bytesInBurstP1; + wire [1:0] _zz_b2m_fsm_bytesInBurstP1_1; + wire [31:0] _zz_b2m_fsm_addressNext; + wire [26:0] _zz_b2m_fsm_bytesLeftNext; + wire [13:0] _zz_b2m_fsm_bytesLeftNext_1; + wire [25:0] _zz__zz_b2m_fsm_sel_bytesInBurst_1; + wire [25:0] _zz__zz_b2m_fsm_sel_bytesInBurst_1_1; + wire [11:0] _zz__zz_b2m_fsm_sel_bytesInBurst_2; + wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_3; + wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_4; + wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_5; + wire [13:0] _zz_b2m_fsm_fifoCompletion; + wire [13:0] _zz_b2m_fsm_fifoCompletion_1; + wire [11:0] _zz_b2m_fsm_beatCounter; + wire [11:0] _zz_b2m_fsm_beatCounter_1; + wire [3:0] _zz_b2m_fsm_beatCounter_2; + wire [10:0] _zz_b2m_fsm_sel_ptr; + wire [3:0] _zz_b2m_fsm_aggregate_bytesToSkipMask; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_1; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_2; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_3; + wire [0:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_4; + wire [9:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_5; + wire [3:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_6; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_7; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_8; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_9; + wire [0:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_10; + wire [3:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_11; + wire [3:0] _zz_b2m_fsm_cmd_maskLastTriggerComb; + wire [3:0] _zz_b2m_fsm_cmd_maskLast; + wire _zz_b2m_fsm_cmd_maskLast_1; + wire [0:0] _zz_b2m_fsm_cmd_maskLast_2; + wire [7:0] _zz_b2m_fsm_cmd_maskLast_3; + wire [3:0] _zz_b2m_fsm_cmd_maskLast_4; + wire [3:0] _zz_b2m_fsm_cmd_maskLast_5; + wire [3:0] _zz_b2m_fsm_cmd_maskFirst; + wire _zz_b2m_fsm_cmd_maskFirst_1; + wire [0:0] _zz_b2m_fsm_cmd_maskFirst_2; + wire [7:0] _zz_b2m_fsm_cmd_maskFirst_3; + wire [3:0] _zz_b2m_fsm_cmd_maskFirst_4; + wire [3:0] _zz_b2m_fsm_cmd_maskFirst_5; + wire [0:0] _zz_when_1; + wire [0:0] _zz_when_2; + wire [1:0] _zz__zz_ll_arbiter_head_1; + wire [1:0] _zz__zz_ll_arbiter_head_1_1; + wire [1:0] _zz_ll_arbiter_head_2; + wire [1:0] _zz_ll_arbiter_isJustASink; + wire [1:0] _zz_ll_arbiter_doDescriptorStall; + wire [1:0] _zz_ll_arbiter_onSgStream; + wire [1:0] _zz_ll_cmd_ptr; + wire [1:0] _zz_ll_cmd_ptrNext; + wire [1:0] _zz_ll_cmd_endOfPacket; + wire [0:0] _zz_channels_0_channelStart; + wire [0:0] _zz_channels_0_ctrl_kick; + wire [0:0] _zz_channels_0_channelStart_1; + wire [0:0] _zz_channels_0_ll_sgStart; + wire [0:0] _zz_channels_0_interrupts_completion_valid; + wire [0:0] _zz_channels_0_interrupts_onChannelCompletion_valid; + wire [0:0] _zz_channels_0_interrupts_onLinkedListUpdate_valid; + wire [0:0] _zz_channels_0_interrupts_s2mPacket_valid; + wire [0:0] _zz_channels_1_channelStart; + wire [0:0] _zz_channels_1_ctrl_kick; + wire [0:0] _zz_channels_1_channelStart_1; + wire [0:0] _zz_channels_1_ll_sgStart; + wire [0:0] _zz_channels_1_interrupts_completion_valid; + wire [0:0] _zz_channels_1_interrupts_onChannelCompletion_valid; + wire [0:0] _zz_channels_1_interrupts_onLinkedListUpdate_valid; + wire [31:0] _zz_io_ctrl_PRDATA; + wire [31:0] _zz_io_ctrl_PRDATA_1; + wire [10:0] _zz_channels_0_fifo_push_ptrIncr_value; + wire [0:0] _zz_channels_0_fifo_push_ptrIncr_value_1; + wire [13:0] _zz_channels_0_fifo_pop_bytesIncr_value_1; + wire [3:0] _zz_channels_0_fifo_pop_bytesIncr_value_2; + wire [10:0] _zz_channels_0_fifo_pop_ptrIncr_value; + wire [1:0] _zz_channels_0_fifo_pop_ptrIncr_value_1; + wire [10:0] _zz_channels_1_fifo_push_ptrIncr_value_1; + wire [1:0] _zz_channels_1_fifo_push_ptrIncr_value_2; + wire [13:0] _zz_channels_1_fifo_pop_bytesIncr_value_1; + wire [4:0] _zz_channels_1_fifo_pop_bytesIncr_value_2; + wire [4:0] _zz_channels_1_fifo_pop_bytesIncr_value_3; + wire [10:0] _zz_channels_1_fifo_pop_ptrIncr_value; + wire [0:0] _zz_channels_1_fifo_pop_ptrIncr_value_1; + wire ctrl_readErrorFlag; + wire ctrl_writeErrorFlag; + wire ctrl_askWrite; + wire ctrl_askRead; + wire ctrl_doWrite; + wire ctrl_doRead; + reg channels_0_channelStart; + reg channels_0_channelStop; + reg channels_0_channelCompletion; + reg channels_0_channelValid; + reg channels_0_descriptorStart; + reg channels_0_descriptorCompletion; + reg channels_0_descriptorValid; + reg [25:0] channels_0_bytes; + reg [1:0] channels_0_priority; + reg [1:0] channels_0_weight; + reg channels_0_readyToStop; + reg [26:0] channels_0_bytesProbe_value; + reg channels_0_bytesProbe_incr_valid; + reg [11:0] channels_0_bytesProbe_incr_payload; + reg channels_0_ctrl_kick; + reg channels_0_ll_sgStart; + reg channels_0_ll_valid; + reg channels_0_ll_onSgStream; + reg channels_0_ll_head; + reg channels_0_ll_justASync; + reg channels_0_ll_waitDone; + reg channels_0_ll_readDone; + reg channels_0_ll_writeDone; + reg channels_0_ll_gotDescriptorStall; + reg channels_0_ll_controlNoCompletion; + reg channels_0_ll_packet; + reg channels_0_ll_requireSync; + reg [31:0] channels_0_ll_ptr; + reg [31:0] channels_0_ll_ptrNext; + wire channels_0_ll_requestLl; + reg channels_0_ll_descriptorUpdated; + wire when_DmaSg_l318; + wire when_DmaSg_l320; + wire when_DmaSg_l322; + wire when_DmaSg_l328; + wire [10:0] channels_0_fifo_base; + wire [10:0] channels_0_fifo_words; + reg [10:0] channels_0_fifo_push_available; + wire [10:0] channels_0_fifo_push_availableDecr; + reg [10:0] channels_0_fifo_push_ptr; + wire [10:0] channels_0_fifo_push_ptrWithBase; + wire [10:0] channels_0_fifo_push_ptrIncr_value; + reg [10:0] channels_0_fifo_pop_ptr; + wire [13:0] channels_0_fifo_pop_bytes; + wire [10:0] channels_0_fifo_pop_ptrWithBase; + wire [13:0] channels_0_fifo_pop_bytesIncr_value; + wire [13:0] channels_0_fifo_pop_bytesDecr_value; + wire channels_0_fifo_pop_empty; + wire [10:0] channels_0_fifo_pop_ptrIncr_value; + reg [13:0] channels_0_fifo_pop_withOverride_backup; + wire [13:0] channels_0_fifo_pop_withOverride_backupNext; + reg channels_0_fifo_pop_withOverride_load; + reg channels_0_fifo_pop_withOverride_unload; + reg [13:0] channels_0_fifo_pop_withOverride_exposed; + reg channels_0_fifo_pop_withOverride_valid; + wire when_DmaSg_l409; + wire channels_0_fifo_empty; + reg channels_0_push_memory; + reg channels_0_push_s2b_completionOnLast; + reg channels_0_push_s2b_packetEvent; + reg channels_0_push_s2b_packetLock; + reg channels_0_push_s2b_waitFirst; + wire when_DmaSg_l457; + reg channels_0_pop_memory; + wire [11:0] channels_0_pop_b2m_bytePerBurst; + reg channels_0_pop_b2m_fire; + reg channels_0_pop_b2m_waitFinalRsp; + reg channels_0_pop_b2m_flush; + reg channels_0_pop_b2m_packetSync; + reg channels_0_pop_b2m_packet; + wire when_DmaSg_l505; + reg channels_0_pop_b2m_memRsp; + reg [3:0] channels_0_pop_b2m_memPending; + reg [31:0] channels_0_pop_b2m_address; + reg [26:0] channels_0_pop_b2m_bytesLeft; + wire channels_0_pop_b2m_selfFlush; + wire channels_0_pop_b2m_request; + reg [3:0] channels_0_pop_b2m_bytesToSkip; + reg [13:0] channels_0_pop_b2m_decrBytes; + reg channels_0_pop_b2m_memPendingInc; + wire when_DmaSg_l523; + wire when_DmaSg_l532; + wire when_DmaSg_l536; + wire when_DmaSg_l547; + wire when_DmaSg_l563; + wire channels_0_readyForChannelCompletion; + wire when_DmaSg_l575; + reg _zz_when_DmaSg_l593; + wire when_DmaSg_l593; + wire channels_0_s2b_full; + reg [10:0] channels_0_fifo_pop_ptrIncr_value_regNext; + wire when_DmaSg_l255; + reg channels_0_interrupts_completion_enable; + reg channels_0_interrupts_completion_valid; + wire when_DmaSg_l255_1; + wire when_DmaSg_l255_2; + reg channels_0_interrupts_onChannelCompletion_enable; + reg channels_0_interrupts_onChannelCompletion_valid; + wire when_DmaSg_l255_3; + reg channels_0_interrupts_onLinkedListUpdate_enable; + reg channels_0_interrupts_onLinkedListUpdate_valid; + wire when_DmaSg_l255_4; + reg channels_0_interrupts_s2mPacket_enable; + reg channels_0_interrupts_s2mPacket_valid; + wire when_DmaSg_l255_5; + wire when_DmaSg_l625; + reg channels_1_channelStart; + reg channels_1_channelStop; + reg channels_1_channelCompletion; + reg channels_1_channelValid; + reg channels_1_descriptorStart; + reg channels_1_descriptorCompletion; + reg channels_1_descriptorValid; + reg [25:0] channels_1_bytes; + reg [1:0] channels_1_priority; + reg [1:0] channels_1_weight; + reg channels_1_readyToStop; + reg [26:0] channels_1_bytesProbe_value; + reg channels_1_bytesProbe_incr_valid; + reg [11:0] channels_1_bytesProbe_incr_payload; + reg channels_1_ctrl_kick; + reg channels_1_ll_sgStart; + reg channels_1_ll_valid; + reg channels_1_ll_onSgStream; + reg channels_1_ll_head; + reg channels_1_ll_justASync; + reg channels_1_ll_waitDone; + reg channels_1_ll_readDone; + reg channels_1_ll_writeDone; + reg channels_1_ll_gotDescriptorStall; + reg channels_1_ll_controlNoCompletion; + reg channels_1_ll_packet; + reg channels_1_ll_requireSync; + reg [31:0] channels_1_ll_ptr; + reg [31:0] channels_1_ll_ptrNext; + wire channels_1_ll_requestLl; + reg channels_1_ll_descriptorUpdated; + wire when_DmaSg_l318_1; + wire when_DmaSg_l320_1; + wire when_DmaSg_l322_1; + wire when_DmaSg_l328_1; + wire [10:0] channels_1_fifo_base; + wire [10:0] channels_1_fifo_words; + reg [10:0] channels_1_fifo_push_available; + reg [10:0] channels_1_fifo_push_availableDecr; + reg [10:0] channels_1_fifo_push_ptr; + wire [10:0] channels_1_fifo_push_ptrWithBase; + wire [10:0] channels_1_fifo_push_ptrIncr_value; + reg [10:0] channels_1_fifo_pop_ptr; + wire [13:0] channels_1_fifo_pop_bytes; + wire [10:0] channels_1_fifo_pop_ptrWithBase; + wire [13:0] channels_1_fifo_pop_bytesIncr_value; + wire [13:0] channels_1_fifo_pop_bytesDecr_value; + wire channels_1_fifo_pop_empty; + wire [10:0] channels_1_fifo_pop_ptrIncr_value; + reg [13:0] channels_1_fifo_pop_withoutOverride_exposed; + wire channels_1_fifo_empty; + reg channels_1_push_memory; + reg [31:0] channels_1_push_m2b_address; + wire [11:0] channels_1_push_m2b_bytePerBurst; + reg channels_1_push_m2b_loadDone; + reg [25:0] channels_1_push_m2b_bytesLeft; + reg [3:0] channels_1_push_m2b_memPending; + reg channels_1_push_m2b_memPendingIncr; + reg channels_1_push_m2b_memPendingDecr; + reg channels_1_push_m2b_loadRequest; + reg channels_1_pop_memory; + reg channels_1_pop_b2s_last; + reg [3:0] channels_1_pop_b2s_sinkId; + reg channels_1_pop_b2s_veryLastTrigger; + reg channels_1_pop_b2s_veryLastValid; + wire when_DmaSg_l474; + reg [10:0] channels_1_pop_b2s_veryLastPtr; + reg channels_1_pop_b2s_veryLastEndPacket; + wire when_DmaSg_l483; + wire when_DmaSg_l486; + wire when_DmaSg_l562; + reg channels_1_readyForChannelCompletion; + wire when_DmaSg_l566; + wire when_DmaSg_l575_1; + reg _zz_when_DmaSg_l593_1; + wire when_DmaSg_l593_1; + wire channels_1_s2b_full; + reg [10:0] channels_1_fifo_pop_ptrIncr_value_regNext; + wire when_DmaSg_l255_6; + reg channels_1_interrupts_completion_enable; + reg channels_1_interrupts_completion_valid; + wire when_DmaSg_l255_7; + wire when_DmaSg_l255_8; + reg channels_1_interrupts_onChannelCompletion_enable; + reg channels_1_interrupts_onChannelCompletion_valid; + wire when_DmaSg_l255_9; + reg channels_1_interrupts_onLinkedListUpdate_enable; + reg channels_1_interrupts_onLinkedListUpdate_valid; + wire when_DmaSg_l255_10; + wire when_DmaSg_l625_1; + wire io_inputs_0_fire; + wire when_package_l12; + reg io_inputs_0_payload_last_regNextWhen; + wire when_package_l12_1; + reg io_inputs_0_payload_last_regNextWhen_1; + wire when_package_l12_2; + reg io_inputs_0_payload_last_regNextWhen_2; + wire when_package_l12_3; + reg io_inputs_0_payload_last_regNextWhen_3; + wire when_package_l12_4; + reg io_inputs_0_payload_last_regNextWhen_4; + wire when_package_l12_5; + reg io_inputs_0_payload_last_regNextWhen_5; + wire when_package_l12_6; + reg io_inputs_0_payload_last_regNextWhen_6; + wire when_package_l12_7; + reg io_inputs_0_payload_last_regNextWhen_7; + wire when_package_l12_8; + reg io_inputs_0_payload_last_regNextWhen_8; + wire when_package_l12_9; + reg io_inputs_0_payload_last_regNextWhen_9; + wire when_package_l12_10; + reg io_inputs_0_payload_last_regNextWhen_10; + wire when_package_l12_11; + reg io_inputs_0_payload_last_regNextWhen_11; + wire when_package_l12_12; + reg io_inputs_0_payload_last_regNextWhen_12; + wire when_package_l12_13; + reg io_inputs_0_payload_last_regNextWhen_13; + wire when_package_l12_14; + reg io_inputs_0_payload_last_regNextWhen_14; + wire when_package_l12_15; + reg io_inputs_0_payload_last_regNextWhen_15; + wire [15:0] s2b_0_cmd_firsts; + wire s2b_0_cmd_first; + wire [0:0] s2b_0_cmd_channelsOh; + wire s2b_0_cmd_noHit; + wire [0:0] s2b_0_cmd_channelsFull; + reg io_inputs_0_thrown_valid; + wire io_inputs_0_thrown_ready; + wire [63:0] io_inputs_0_thrown_payload_data; + wire [7:0] io_inputs_0_thrown_payload_mask; + wire [3:0] io_inputs_0_thrown_payload_sink; + wire io_inputs_0_thrown_payload_last; + wire _zz_io_inputs_0_thrown_ready; + wire s2b_0_cmd_sinkHalted_valid; + wire s2b_0_cmd_sinkHalted_ready; + wire [63:0] s2b_0_cmd_sinkHalted_payload_data; + wire [7:0] s2b_0_cmd_sinkHalted_payload_mask; + wire [3:0] s2b_0_cmd_sinkHalted_payload_sink; + wire s2b_0_cmd_sinkHalted_payload_last; + wire [3:0] _zz_s2b_0_cmd_byteCount; + wire [3:0] _zz_s2b_0_cmd_byteCount_1; + wire [3:0] _zz_s2b_0_cmd_byteCount_2; + wire [3:0] _zz_s2b_0_cmd_byteCount_3; + wire [3:0] _zz_s2b_0_cmd_byteCount_4; + wire [3:0] _zz_s2b_0_cmd_byteCount_5; + wire [3:0] _zz_s2b_0_cmd_byteCount_6; + wire [3:0] _zz_s2b_0_cmd_byteCount_7; + wire [3:0] s2b_0_cmd_byteCount; + wire [0:0] s2b_0_cmd_context_channel; + wire [3:0] s2b_0_cmd_context_bytes; + wire s2b_0_cmd_context_flush; + wire s2b_0_cmd_context_packet; + wire memory_core_io_writes_0_cmd_fire; + wire when_DmaSg_l665; + wire [0:0] s2b_0_rsp_context_channel; + wire [3:0] s2b_0_rsp_context_bytes; + wire s2b_0_rsp_context_flush; + wire s2b_0_rsp_context_packet; + wire [6:0] _zz_s2b_0_rsp_context_channel; + wire _zz_channels_0_fifo_pop_bytesIncr_value; + wire when_DmaSg_l679; + wire when_DmaSg_l681; + wire when_DmaSg_l682; + wire [0:0] b2s_0_cmd_channelsOh; + wire [0:0] b2s_0_cmd_context_channel; + wire b2s_0_cmd_context_veryLast; + wire b2s_0_cmd_context_endPacket; + wire [10:0] b2s_0_cmd_veryLastPtr; + wire [10:0] b2s_0_cmd_address; + wire [0:0] b2s_0_rsp_context_channel; + wire b2s_0_rsp_context_veryLast; + wire b2s_0_rsp_context_endPacket; + wire [2:0] _zz_b2s_0_rsp_context_channel; + wire io_outputs_0_fire; + wire when_DmaSg_l725; + wire when_DmaSg_l726; + reg m2b_cmd_s0_valid; + wire [1:0] _zz_m2b_cmd_s0_priority_masked; + wire [0:0] m2b_cmd_s0_priority_masked; + reg [0:0] m2b_cmd_s0_priority_roundRobins_0; + reg [0:0] m2b_cmd_s0_priority_roundRobins_1; + reg [0:0] m2b_cmd_s0_priority_roundRobins_2; + reg [0:0] m2b_cmd_s0_priority_roundRobins_3; + reg [1:0] m2b_cmd_s0_priority_counter; + wire [0:0] _zz_m2b_cmd_s0_priority_chosenOh; + wire [1:0] _zz_m2b_cmd_s0_priority_chosenOh_1; + wire [1:0] _zz_m2b_cmd_s0_priority_chosenOh_2; + wire [0:0] m2b_cmd_s0_priority_chosenOh; + wire m2b_cmd_s0_priority_weightLast; + wire [0:0] m2b_cmd_s0_priority_contextNext; + wire when_DmaSg_l758; + wire when_DmaSg_l760; + wire when_DmaSg_l763; + wire when_DmaSg_l763_1; + wire when_DmaSg_l763_2; + wire when_DmaSg_l763_3; + wire when_DmaSg_l773; + wire [31:0] m2b_cmd_s0_address; + wire [25:0] m2b_cmd_s0_bytesLeft; + wire [11:0] m2b_cmd_s0_readAddressBurstRange; + wire [11:0] m2b_cmd_s0_lengthHead; + wire [11:0] m2b_cmd_s0_length; + wire m2b_cmd_s0_lastBurst; + reg m2b_cmd_s1_valid; + reg [31:0] m2b_cmd_s1_address; + reg [11:0] m2b_cmd_s1_length; + reg m2b_cmd_s1_lastBurst; + reg [25:0] m2b_cmd_s1_bytesLeft; + wire [3:0] m2b_cmd_s1_context_start; + wire [3:0] m2b_cmd_s1_context_stop; + wire [11:0] m2b_cmd_s1_context_length; + wire m2b_cmd_s1_context_last; + wire [31:0] m2b_cmd_s1_addressNext; + wire [25:0] m2b_cmd_s1_byteLeftNext; + wire [9:0] m2b_cmd_s1_fifoPushDecr; + wire when_DmaSg_l828; + wire [3:0] m2b_rsp_context_start; + wire [3:0] m2b_rsp_context_stop; + wire [11:0] m2b_rsp_context_length; + wire m2b_rsp_context_last; + wire [20:0] _zz_m2b_rsp_context_start; + wire m2b_rsp_veryLast; + wire io_read_rsp_fire; + wire when_DmaSg_l847; + wire when_DmaSg_l848; + reg m2b_rsp_first; + wire m2b_rsp_writeContext_last; + wire m2b_rsp_writeContext_lastOfBurst; + wire [4:0] m2b_rsp_writeContext_loadByteInNextBeat; + wire memory_core_io_writes_1_cmd_fire; + wire _zz_channels_1_fifo_push_ptrIncr_value; + wire when_DmaSg_l874; + wire m2b_writeRsp_context_last; + wire m2b_writeRsp_context_lastOfBurst; + wire [4:0] m2b_writeRsp_context_loadByteInNextBeat; + wire [6:0] _zz_m2b_writeRsp_context_last; + wire _zz_channels_1_fifo_pop_bytesIncr_value; + wire when_DmaSg_l893; + reg b2m_fsm_sel_valid; + reg b2m_fsm_sel_ready; + reg [11:0] b2m_fsm_sel_bytePerBurst; + reg [11:0] b2m_fsm_sel_bytesInBurst; + reg [13:0] b2m_fsm_sel_bytesInFifo; + reg [31:0] b2m_fsm_sel_address; + reg [10:0] b2m_fsm_sel_ptr; + reg [10:0] b2m_fsm_sel_ptrMask; + reg b2m_fsm_sel_flush; + reg b2m_fsm_sel_packet; + reg [25:0] b2m_fsm_sel_bytesLeft; + reg b2m_fsm_arbiter_logic_valid; + wire [1:0] _zz_b2m_fsm_arbiter_logic_priority_masked; + wire [0:0] b2m_fsm_arbiter_logic_priority_masked; + reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_0; + reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_1; + reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_2; + reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_3; + reg [1:0] b2m_fsm_arbiter_logic_priority_counter; + wire [0:0] _zz_b2m_fsm_arbiter_logic_priority_chosenOh; + wire [1:0] _zz_b2m_fsm_arbiter_logic_priority_chosenOh_1; + wire [1:0] _zz_b2m_fsm_arbiter_logic_priority_chosenOh_2; + wire [0:0] b2m_fsm_arbiter_logic_priority_chosenOh; + wire b2m_fsm_arbiter_logic_priority_weightLast; + wire [0:0] b2m_fsm_arbiter_logic_priority_contextNext; + wire when_DmaSg_l758_1; + wire when_DmaSg_l760_1; + wire when_DmaSg_l763_4; + wire when_DmaSg_l763_5; + wire when_DmaSg_l763_6; + wire when_DmaSg_l763_7; + wire when_DmaSg_l773_1; + wire when_DmaSg_l935; + wire [12:0] b2m_fsm_bytesInBurstP1; + wire [31:0] b2m_fsm_addressNext; + wire [26:0] b2m_fsm_bytesLeftNext; + wire b2m_fsm_isFinalCmd; + reg [7:0] b2m_fsm_beatCounter; + reg b2m_fsm_sel_valid_regNext; + wire b2m_fsm_s0; + reg b2m_fsm_s1; + reg b2m_fsm_s2; + wire when_DmaSg_l986; + wire [13:0] _zz_b2m_fsm_sel_bytesInBurst; + wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_1; + wire [11:0] _zz_b2m_fsm_sel_bytesInBurst_2; + wire b2m_fsm_fifoCompletion; + wire when_DmaSg_l996; + wire when_DmaSg_l1001; + reg b2m_fsm_toggle; + wire when_DmaSg_l1013; + wire [10:0] b2m_fsm_fetch_context_ptr; + wire b2m_fsm_fetch_context_toggle; + wire when_DmaSg_l1033; + wire [10:0] b2m_fsm_aggregate_context_ptr; + wire b2m_fsm_aggregate_context_toggle; + wire [11:0] _zz_b2m_fsm_aggregate_context_ptr; + wire memory_core_io_reads_1_rsp_s2mPipe_valid; + reg memory_core_io_reads_1_rsp_s2mPipe_ready; + wire [127:0] memory_core_io_reads_1_rsp_s2mPipe_payload_data; + wire [15:0] memory_core_io_reads_1_rsp_s2mPipe_payload_mask; + wire [11:0] memory_core_io_reads_1_rsp_s2mPipe_payload_context; + reg memory_core_io_reads_1_rsp_rValidN; + reg [127:0] memory_core_io_reads_1_rsp_rData_data; + reg [15:0] memory_core_io_reads_1_rsp_rData_mask; + reg [11:0] memory_core_io_reads_1_rsp_rData_context; + wire when_Stream_l445; + reg b2m_fsm_aggregate_memoryPort_valid; + wire b2m_fsm_aggregate_memoryPort_ready; + wire [127:0] b2m_fsm_aggregate_memoryPort_payload_data; + wire [15:0] b2m_fsm_aggregate_memoryPort_payload_mask; + wire [11:0] b2m_fsm_aggregate_memoryPort_payload_context; + reg b2m_fsm_aggregate_first; + wire b2m_fsm_aggregate_memoryPort_fire; + wire when_DmaSg_l1050; + wire [3:0] b2m_fsm_aggregate_bytesToSkip; + wire [15:0] b2m_fsm_aggregate_bytesToSkipMask; + reg _zz_io_flush; + wire [3:0] b2m_fsm_cmd_maskFirstTrigger; + wire [3:0] b2m_fsm_cmd_maskLastTriggerComb; + reg [3:0] b2m_fsm_cmd_maskLastTriggerReg; + reg [15:0] b2m_fsm_cmd_maskLast; + wire [15:0] b2m_fsm_cmd_maskFirst; + wire b2m_fsm_cmd_enoughAggregation; + wire io_write_cmd_fire; + reg io_write_cmd_payload_first; + wire b2m_fsm_cmd_doPtrIncr; + wire [11:0] b2m_fsm_cmd_context_length; + wire b2m_fsm_cmd_context_doPacketSync; + wire when_DmaSg_l1102; + wire [11:0] b2m_rsp_context_length; + wire b2m_rsp_context_doPacketSync; + wire [12:0] _zz_b2m_rsp_context_length; + wire io_write_rsp_fire; + wire when_DmaSg_l1116; + wire [1:0] _zz_ll_arbiter_head; + wire _zz_ll_arbiter_head_1; + wire ll_arbiter_head; + wire ll_arbiter_isJustASink; + wire ll_arbiter_doDescriptorStall; + wire ll_arbiter_onSgStream; + reg ll_cmd_valid; + wire when_DmaSg_l1149; + reg ll_cmd_oh_0; + reg ll_cmd_oh_1; + wire when_DmaSg_l1148; + reg [31:0] ll_cmd_ptr; + wire when_DmaSg_l1148_1; + reg [31:0] ll_cmd_ptrNext; + wire when_DmaSg_l1148_2; + reg [26:0] ll_cmd_bytesDone; + wire when_DmaSg_l1148_3; + reg ll_cmd_endOfPacket; + wire when_DmaSg_l1154; + reg ll_cmd_isJustASink; + wire when_DmaSg_l1155; + reg ll_cmd_doDescriptorStall; + wire when_DmaSg_l1156; + reg ll_cmd_onSgStream; + reg ll_cmd_readFired; + reg ll_cmd_writeFired; + wire when_DmaSg_l1160; + wire when_DmaSg_l1161; + wire when_DmaSg_l1169; + wire when_DmaSg_l1169_1; + wire when_DmaSg_l1177; + wire [0:0] ll_cmd_context_channel; + wire [3:0] ll_cmd_writeMaskSplit_0; + wire [3:0] ll_cmd_writeMaskSplit_1; + wire [3:0] ll_cmd_writeMaskSplit_2; + wire [3:0] ll_cmd_writeMaskSplit_3; + wire [31:0] ll_cmd_writeDataSplit_0; + wire [31:0] ll_cmd_writeDataSplit_1; + wire [31:0] ll_cmd_writeDataSplit_2; + wire [31:0] ll_cmd_writeDataSplit_3; + wire io_sgRead_cmd_fire; + wire io_sgWrite_cmd_fire; + wire [0:0] ll_readRsp_context_channel; + wire [1:0] _zz_ll_readRsp_oh_0; + wire ll_readRsp_oh_0; + wire ll_readRsp_oh_1; + reg [0:0] ll_readRsp_beatCounter; + reg ll_readRsp_completed; + wire io_sgRead_rsp_fire; + wire when_DmaSg_l1248; + wire when_DmaSg_l1248_1; + wire when_DmaSg_l1248_2; + wire when_DmaSg_l1248_3; + wire when_DmaSg_l1248_4; + wire when_DmaSg_l1248_5; + wire when_DmaSg_l1248_6; + wire when_DmaSg_l1271; + wire [0:0] ll_writeRsp_context_channel; + wire [1:0] _zz_ll_writeRsp_oh_0; + wire ll_writeRsp_oh_0; + wire ll_writeRsp_oh_1; + wire io_sgWrite_rsp_fire; + reg when_BusSlaveFactory_l377; + wire when_BusSlaveFactory_l379; + reg when_BusSlaveFactory_l377_1; + wire when_BusSlaveFactory_l379_1; + reg when_BusSlaveFactory_l377_2; + wire when_BusSlaveFactory_l379_2; + reg when_BusSlaveFactory_l377_3; + wire when_BusSlaveFactory_l379_3; + reg when_BusSlaveFactory_l341; + wire when_BusSlaveFactory_l347; + reg when_BusSlaveFactory_l341_1; + wire when_BusSlaveFactory_l347_1; + reg when_BusSlaveFactory_l341_2; + wire when_BusSlaveFactory_l347_2; + reg when_BusSlaveFactory_l341_3; + wire when_BusSlaveFactory_l347_3; + reg when_BusSlaveFactory_l377_4; + wire when_BusSlaveFactory_l379_4; + reg when_BusSlaveFactory_l377_5; + wire when_BusSlaveFactory_l379_5; + reg when_BusSlaveFactory_l377_6; + wire when_BusSlaveFactory_l379_6; + reg when_BusSlaveFactory_l377_7; + wire when_BusSlaveFactory_l379_7; + reg when_BusSlaveFactory_l341_4; + wire when_BusSlaveFactory_l347_4; + reg when_BusSlaveFactory_l341_5; + wire when_BusSlaveFactory_l347_5; + reg when_BusSlaveFactory_l341_6; + wire when_BusSlaveFactory_l347_6; + wire when_Apb3SlaveFactory_l81; + wire when_Apb3SlaveFactory_l81_1; + wire when_Apb3SlaveFactory_l81_2; + wire when_Apb3SlaveFactory_l81_3; + function [15:0] zz_io_sgWrite_cmd_payload_fragment_mask(input dummy); + begin + zz_io_sgWrite_cmd_payload_fragment_mask[7 : 4] = 4'b0000; + zz_io_sgWrite_cmd_payload_fragment_mask[11 : 8] = 4'b0000; + zz_io_sgWrite_cmd_payload_fragment_mask[15 : 12] = 4'b0000; + zz_io_sgWrite_cmd_payload_fragment_mask[3 : 0] = 4'b1111; + end + endfunction + wire [15:0] _zz_1; + + assign _zz_channels_0_bytesProbe_value = (channels_0_bytesProbe_value + _zz_channels_0_bytesProbe_value_1); + assign _zz_channels_0_bytesProbe_value_1 = {15'd0, channels_0_bytesProbe_incr_payload}; + assign _zz_channels_0_fifo_pop_withOverride_backupNext = (channels_0_fifo_pop_withOverride_backup + channels_0_fifo_pop_bytesIncr_value); + assign _zz_channels_0_fifo_pop_withOverride_exposed = (channels_0_fifo_pop_withOverride_exposed - channels_0_fifo_pop_bytesDecr_value); + assign _zz_channels_0_pop_b2m_selfFlush = {13'd0, channels_0_fifo_pop_bytes}; + assign _zz_channels_0_pop_b2m_request = {2'd0, channels_0_pop_b2m_bytePerBurst}; + assign _zz_channels_0_pop_b2m_request_2 = (channels_0_fifo_words >>> 1'd1); + assign _zz_channels_0_pop_b2m_request_1 = {1'd0, _zz_channels_0_pop_b2m_request_2}; + assign _zz_channels_0_pop_b2m_memPending = (channels_0_pop_b2m_memPending + _zz_channels_0_pop_b2m_memPending_1); + assign _zz_channels_0_pop_b2m_memPending_2 = channels_0_pop_b2m_memPendingInc; + assign _zz_channels_0_pop_b2m_memPending_1 = {3'd0, _zz_channels_0_pop_b2m_memPending_2}; + assign _zz_channels_0_pop_b2m_memPending_4 = channels_0_pop_b2m_memRsp; + assign _zz_channels_0_pop_b2m_memPending_3 = {3'd0, _zz_channels_0_pop_b2m_memPending_4}; + assign _zz_channels_0_fifo_push_available = (channels_0_fifo_push_available + channels_0_fifo_pop_ptrIncr_value_regNext); + assign _zz_channels_1_bytesProbe_value = (channels_1_bytesProbe_value + _zz_channels_1_bytesProbe_value_1); + assign _zz_channels_1_bytesProbe_value_1 = {15'd0, channels_1_bytesProbe_incr_payload}; + assign _zz_channels_1_fifo_pop_withoutOverride_exposed = (channels_1_fifo_pop_withoutOverride_exposed + channels_1_fifo_pop_bytesIncr_value); + assign _zz_channels_1_push_m2b_memPending = (channels_1_push_m2b_memPending + _zz_channels_1_push_m2b_memPending_1); + assign _zz_channels_1_push_m2b_memPending_2 = channels_1_push_m2b_memPendingIncr; + assign _zz_channels_1_push_m2b_memPending_1 = {3'd0, _zz_channels_1_push_m2b_memPending_2}; + assign _zz_channels_1_push_m2b_memPending_4 = channels_1_push_m2b_memPendingDecr; + assign _zz_channels_1_push_m2b_memPending_3 = {3'd0, _zz_channels_1_push_m2b_memPending_4}; + assign _zz_channels_1_push_m2b_loadRequest_1 = (channels_1_push_m2b_bytePerBurst >>> 2'd3); + assign _zz_channels_1_push_m2b_loadRequest = {2'd0, _zz_channels_1_push_m2b_loadRequest_1}; + assign _zz_when_DmaSg_l486 = {14'd0, channels_1_push_m2b_bytePerBurst}; + assign _zz_channels_1_fifo_push_available = (channels_1_fifo_push_available + channels_1_fifo_pop_ptrIncr_value_regNext); + assign _zz_s2b_0_cmd_byteCount_8 = (_zz_s2b_0_cmd_byteCount_9 + _zz_s2b_0_cmd_byteCount_11); + assign _zz_s2b_0_cmd_byteCount_15 = {s2b_0_cmd_sinkHalted_payload_mask[7],s2b_0_cmd_sinkHalted_payload_mask[6]}; + assign _zz_s2b_0_cmd_byteCount_14 = {1'd0, _zz_s2b_0_cmd_byteCount_15}; + assign _zz__zz_m2b_cmd_s0_priority_chosenOh_2 = (_zz_m2b_cmd_s0_priority_chosenOh_1 - _zz__zz_m2b_cmd_s0_priority_chosenOh_2_1); + assign _zz__zz_m2b_cmd_s0_priority_chosenOh_2_2 = _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3; + assign _zz__zz_m2b_cmd_s0_priority_chosenOh_2_1 = {1'd0, _zz__zz_m2b_cmd_s0_priority_chosenOh_2_2}; + assign _zz_m2b_cmd_s0_length = ((_zz_m2b_cmd_s0_length_1 < m2b_cmd_s0_bytesLeft) ? _zz_m2b_cmd_s0_length_2 : m2b_cmd_s0_bytesLeft); + assign _zz_m2b_cmd_s0_length_1 = {14'd0, m2b_cmd_s0_lengthHead}; + assign _zz_m2b_cmd_s0_length_2 = {14'd0, m2b_cmd_s0_lengthHead}; + assign _zz_m2b_cmd_s0_lastBurst = {14'd0, m2b_cmd_s0_length}; + assign _zz_m2b_cmd_s1_context_stop = (m2b_cmd_s1_address + _zz_m2b_cmd_s1_context_stop_1); + assign _zz_m2b_cmd_s1_context_stop_1 = {20'd0, m2b_cmd_s1_length}; + assign _zz_m2b_cmd_s1_addressNext = (m2b_cmd_s1_address + _zz_m2b_cmd_s1_addressNext_1); + assign _zz_m2b_cmd_s1_addressNext_1 = {20'd0, m2b_cmd_s1_length}; + assign _zz_m2b_cmd_s1_byteLeftNext = (m2b_cmd_s1_bytesLeft - _zz_m2b_cmd_s1_byteLeftNext_1); + assign _zz_m2b_cmd_s1_byteLeftNext_1 = {14'd0, m2b_cmd_s1_length}; + assign _zz_m2b_cmd_s1_fifoPushDecr = ({1'b0,(_zz_m2b_cmd_s1_fifoPushDecr_1 | 12'h00f)} + _zz_m2b_cmd_s1_fifoPushDecr_4); + assign _zz_m2b_cmd_s1_fifoPushDecr_1 = (_zz_m2b_cmd_s1_fifoPushDecr_2 + io_read_cmd_payload_fragment_length); + assign _zz_m2b_cmd_s1_fifoPushDecr_3 = m2b_cmd_s1_address[3 : 0]; + assign _zz_m2b_cmd_s1_fifoPushDecr_2 = {8'd0, _zz_m2b_cmd_s1_fifoPushDecr_3}; + assign _zz_m2b_cmd_s1_fifoPushDecr_5 = {1'b0,1'b1}; + assign _zz_m2b_cmd_s1_fifoPushDecr_4 = {11'd0, _zz_m2b_cmd_s1_fifoPushDecr_5}; + assign _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2 = (_zz_b2m_fsm_arbiter_logic_priority_chosenOh_1 - _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_1); + assign _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_2 = _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3; + assign _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_1 = {1'd0, _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_2}; + assign _zz_when = 1'b1; + assign _zz_b2m_fsm_bytesInBurstP1_1 = {1'b0,1'b1}; + assign _zz_b2m_fsm_bytesInBurstP1 = {11'd0, _zz_b2m_fsm_bytesInBurstP1_1}; + assign _zz_b2m_fsm_addressNext = {19'd0, b2m_fsm_bytesInBurstP1}; + assign _zz_b2m_fsm_bytesLeftNext_1 = {1'b0,b2m_fsm_bytesInBurstP1}; + assign _zz_b2m_fsm_bytesLeftNext = {13'd0, _zz_b2m_fsm_bytesLeftNext_1}; + assign _zz__zz_b2m_fsm_sel_bytesInBurst_1 = {12'd0, _zz_b2m_fsm_sel_bytesInBurst}; + assign _zz__zz_b2m_fsm_sel_bytesInBurst_1_1 = {12'd0, _zz_b2m_fsm_sel_bytesInBurst}; + assign _zz__zz_b2m_fsm_sel_bytesInBurst_2 = b2m_fsm_sel_address[11:0]; + assign _zz_b2m_fsm_sel_bytesInBurst_3 = ((_zz_b2m_fsm_sel_bytesInBurst_1 < _zz_b2m_fsm_sel_bytesInBurst_4) ? _zz_b2m_fsm_sel_bytesInBurst_1 : _zz_b2m_fsm_sel_bytesInBurst_5); + assign _zz_b2m_fsm_sel_bytesInBurst_4 = {14'd0, _zz_b2m_fsm_sel_bytesInBurst_2}; + assign _zz_b2m_fsm_sel_bytesInBurst_5 = {14'd0, _zz_b2m_fsm_sel_bytesInBurst_2}; + assign _zz_b2m_fsm_fifoCompletion = {2'd0, b2m_fsm_sel_bytesInBurst}; + assign _zz_b2m_fsm_fifoCompletion_1 = (b2m_fsm_sel_bytesInFifo - 14'h0001); + assign _zz_b2m_fsm_beatCounter = (_zz_b2m_fsm_beatCounter_1 + b2m_fsm_sel_bytesInBurst); + assign _zz_b2m_fsm_beatCounter_2 = b2m_fsm_sel_address[3 : 0]; + assign _zz_b2m_fsm_beatCounter_1 = {8'd0, _zz_b2m_fsm_beatCounter_2}; + assign _zz_b2m_fsm_sel_ptr = (b2m_fsm_sel_ptr + 11'h002); + assign _zz_b2m_fsm_cmd_maskLastTriggerComb = b2m_fsm_sel_bytesInBurst[3:0]; + assign _zz_when_1 = 1'b1; + assign _zz_when_2 = 1'b1; + assign _zz__zz_ll_arbiter_head_1 = (_zz_ll_arbiter_head & (~ _zz__zz_ll_arbiter_head_1_1)); + assign _zz__zz_ll_arbiter_head_1_1 = (_zz_ll_arbiter_head - 2'b01); + assign _zz_ll_arbiter_head_2 = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_arbiter_isJustASink = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_arbiter_doDescriptorStall = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_arbiter_onSgStream = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_cmd_ptr = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_cmd_ptrNext = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_cmd_endOfPacket = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_channels_0_channelStart = 1'b1; + assign _zz_channels_0_ctrl_kick = 1'b1; + assign _zz_channels_0_channelStart_1 = 1'b1; + assign _zz_channels_0_ll_sgStart = 1'b1; + assign _zz_channels_0_interrupts_completion_valid = 1'b0; + assign _zz_channels_0_interrupts_onChannelCompletion_valid = 1'b0; + assign _zz_channels_0_interrupts_onLinkedListUpdate_valid = 1'b0; + assign _zz_channels_0_interrupts_s2mPacket_valid = 1'b0; + assign _zz_channels_1_channelStart = 1'b1; + assign _zz_channels_1_ctrl_kick = 1'b1; + assign _zz_channels_1_channelStart_1 = 1'b1; + assign _zz_channels_1_ll_sgStart = 1'b1; + assign _zz_channels_1_interrupts_completion_valid = 1'b0; + assign _zz_channels_1_interrupts_onChannelCompletion_valid = 1'b0; + assign _zz_channels_1_interrupts_onLinkedListUpdate_valid = 1'b0; + assign _zz_io_ctrl_PRDATA = channels_0_ll_ptr; + assign _zz_io_ctrl_PRDATA_1 = channels_1_ll_ptr; + assign _zz_channels_0_fifo_push_ptrIncr_value_1 = ((when_DmaSg_l665 && (|s2b_0_cmd_sinkHalted_payload_mask)) ? 1'b1 : 1'b0); + assign _zz_channels_0_fifo_push_ptrIncr_value = {10'd0, _zz_channels_0_fifo_push_ptrIncr_value_1}; + assign _zz_channels_0_fifo_pop_bytesIncr_value_2 = (_zz_channels_0_fifo_pop_bytesIncr_value ? s2b_0_rsp_context_bytes : 4'b0000); + assign _zz_channels_0_fifo_pop_bytesIncr_value_1 = {10'd0, _zz_channels_0_fifo_pop_bytesIncr_value_2}; + assign _zz_channels_0_fifo_pop_ptrIncr_value_1 = ((b2m_fsm_cmd_doPtrIncr && 1'b1) ? 2'b10 : 2'b00); + assign _zz_channels_0_fifo_pop_ptrIncr_value = {9'd0, _zz_channels_0_fifo_pop_ptrIncr_value_1}; + assign _zz_channels_1_fifo_push_ptrIncr_value_2 = (_zz_channels_1_fifo_push_ptrIncr_value ? 2'b10 : 2'b00); + assign _zz_channels_1_fifo_push_ptrIncr_value_1 = {9'd0, _zz_channels_1_fifo_push_ptrIncr_value_2}; + assign _zz_channels_1_fifo_pop_bytesIncr_value_2 = (_zz_channels_1_fifo_pop_bytesIncr_value ? _zz_channels_1_fifo_pop_bytesIncr_value_3 : 5'h0); + assign _zz_channels_1_fifo_pop_bytesIncr_value_1 = {9'd0, _zz_channels_1_fifo_pop_bytesIncr_value_2}; + assign _zz_channels_1_fifo_pop_bytesIncr_value_3 = (m2b_writeRsp_context_loadByteInNextBeat + 5'h01); + assign _zz_channels_1_fifo_pop_ptrIncr_value_1 = ((b2s_0_cmd_channelsOh[0] && memory_core_io_reads_0_cmd_ready) ? 1'b1 : 1'b0); + assign _zz_channels_1_fifo_pop_ptrIncr_value = {10'd0, _zz_channels_1_fifo_pop_ptrIncr_value_1}; + assign _zz_s2b_0_cmd_byteCount_10 = {s2b_0_cmd_sinkHalted_payload_mask[2],{s2b_0_cmd_sinkHalted_payload_mask[1],s2b_0_cmd_sinkHalted_payload_mask[0]}}; + assign _zz_s2b_0_cmd_byteCount_12 = {s2b_0_cmd_sinkHalted_payload_mask[5],{s2b_0_cmd_sinkHalted_payload_mask[4],s2b_0_cmd_sinkHalted_payload_mask[3]}}; + assign _zz_s2b_0_cmd_firsts = io_inputs_0_payload_last_regNextWhen_5; + assign _zz_s2b_0_cmd_firsts_1 = {io_inputs_0_payload_last_regNextWhen_4,{io_inputs_0_payload_last_regNextWhen_3,{io_inputs_0_payload_last_regNextWhen_2,{io_inputs_0_payload_last_regNextWhen_1,io_inputs_0_payload_last_regNextWhen}}}}; + assign _zz_b2m_fsm_aggregate_bytesToSkipMask = 4'b1101; + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_1 = (! b2m_fsm_aggregate_first); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_2 = (b2m_fsm_aggregate_bytesToSkip <= 4'b1100); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_3 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1011)); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_4 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1010)); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_5 = {((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1001)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1000)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= _zz_b2m_fsm_aggregate_bytesToSkipMask_6)),{(_zz_b2m_fsm_aggregate_bytesToSkipMask_7 || _zz_b2m_fsm_aggregate_bytesToSkipMask_8),{_zz_b2m_fsm_aggregate_bytesToSkipMask_9,{_zz_b2m_fsm_aggregate_bytesToSkipMask_10,_zz_b2m_fsm_aggregate_bytesToSkipMask_11}}}}}}; + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_6 = 4'b0111; + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_7 = (! b2m_fsm_aggregate_first); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_8 = (b2m_fsm_aggregate_bytesToSkip <= 4'b0110); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_9 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0101)); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_10 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0100)); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_11 = {((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0011)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0010)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0001)),((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0000))}}}; + assign _zz_b2m_fsm_cmd_maskLast = 4'b1010; + assign _zz_b2m_fsm_cmd_maskLast_1 = (4'b1001 <= b2m_fsm_cmd_maskLastTriggerComb); + assign _zz_b2m_fsm_cmd_maskLast_2 = (4'b1000 <= b2m_fsm_cmd_maskLastTriggerComb); + assign _zz_b2m_fsm_cmd_maskLast_3 = {(4'b0111 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0110 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0101 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0100 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0011 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0010 <= b2m_fsm_cmd_maskLastTriggerComb),{(_zz_b2m_fsm_cmd_maskLast_4 <= b2m_fsm_cmd_maskLastTriggerComb),(_zz_b2m_fsm_cmd_maskLast_5 <= b2m_fsm_cmd_maskLastTriggerComb)}}}}}}}; + assign _zz_b2m_fsm_cmd_maskLast_4 = 4'b0001; + assign _zz_b2m_fsm_cmd_maskLast_5 = 4'b0000; + assign _zz_b2m_fsm_cmd_maskFirst = 4'b1010; + assign _zz_b2m_fsm_cmd_maskFirst_1 = (b2m_fsm_cmd_maskFirstTrigger <= 4'b1001); + assign _zz_b2m_fsm_cmd_maskFirst_2 = (b2m_fsm_cmd_maskFirstTrigger <= 4'b1000); + assign _zz_b2m_fsm_cmd_maskFirst_3 = {(b2m_fsm_cmd_maskFirstTrigger <= 4'b0111),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0110),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0101),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0100),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0011),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0010),{(b2m_fsm_cmd_maskFirstTrigger <= _zz_b2m_fsm_cmd_maskFirst_4),(b2m_fsm_cmd_maskFirstTrigger <= _zz_b2m_fsm_cmd_maskFirst_5)}}}}}}}; + assign _zz_b2m_fsm_cmd_maskFirst_4 = 4'b0001; + assign _zz_b2m_fsm_cmd_maskFirst_5 = 4'b0000; + EfxDMA_DmaMemoryCore_a048ca8f51874147a1cd65d43e6523ef memory_core ( + .io_writes_0_cmd_valid (s2b_0_cmd_sinkHalted_valid ), //i + .io_writes_0_cmd_ready (memory_core_io_writes_0_cmd_ready ), //o + .io_writes_0_cmd_payload_address (memory_core_io_writes_0_cmd_payload_address[9:0]), //i + .io_writes_0_cmd_payload_data (s2b_0_cmd_sinkHalted_payload_data[63:0] ), //i + .io_writes_0_cmd_payload_mask (s2b_0_cmd_sinkHalted_payload_mask[7:0] ), //i + .io_writes_0_cmd_payload_priority (channels_0_priority[1:0] ), //i + .io_writes_0_cmd_payload_context (memory_core_io_writes_0_cmd_payload_context[6:0]), //i + .io_writes_0_rsp_valid (memory_core_io_writes_0_rsp_valid ), //o + .io_writes_0_rsp_payload_context (memory_core_io_writes_0_rsp_payload_context[6:0]), //o + .io_writes_1_cmd_valid (io_read_rsp_valid ), //i + .io_writes_1_cmd_ready (memory_core_io_writes_1_cmd_ready ), //o + .io_writes_1_cmd_payload_address (memory_core_io_writes_1_cmd_payload_address[9:0]), //i + .io_writes_1_cmd_payload_data (io_read_rsp_payload_fragment_data[127:0] ), //i + .io_writes_1_cmd_payload_mask (memory_core_io_writes_1_cmd_payload_mask[15:0] ), //i + .io_writes_1_cmd_payload_context (memory_core_io_writes_1_cmd_payload_context[6:0]), //i + .io_writes_1_rsp_valid (memory_core_io_writes_1_rsp_valid ), //o + .io_writes_1_rsp_payload_context (memory_core_io_writes_1_rsp_payload_context[6:0]), //o + .io_reads_0_cmd_valid (memory_core_io_reads_0_cmd_valid ), //i + .io_reads_0_cmd_ready (memory_core_io_reads_0_cmd_ready ), //o + .io_reads_0_cmd_payload_address (memory_core_io_reads_0_cmd_payload_address[9:0] ), //i + .io_reads_0_cmd_payload_priority (channels_1_priority[1:0] ), //i + .io_reads_0_cmd_payload_context (memory_core_io_reads_0_cmd_payload_context[2:0] ), //i + .io_reads_0_rsp_valid (memory_core_io_reads_0_rsp_valid ), //o + .io_reads_0_rsp_ready (io_outputs_0_ready ), //i + .io_reads_0_rsp_payload_data (memory_core_io_reads_0_rsp_payload_data[63:0] ), //o + .io_reads_0_rsp_payload_mask (memory_core_io_reads_0_rsp_payload_mask[7:0] ), //o + .io_reads_0_rsp_payload_context (memory_core_io_reads_0_rsp_payload_context[2:0] ), //o + .io_reads_1_cmd_valid (b2m_fsm_sel_valid ), //i + .io_reads_1_cmd_ready (memory_core_io_reads_1_cmd_ready ), //o + .io_reads_1_cmd_payload_address (memory_core_io_reads_1_cmd_payload_address[9:0] ), //i + .io_reads_1_cmd_payload_context (memory_core_io_reads_1_cmd_payload_context[11:0]), //i + .io_reads_1_rsp_valid (memory_core_io_reads_1_rsp_valid ), //o + .io_reads_1_rsp_ready (memory_core_io_reads_1_rsp_rValidN ), //i + .io_reads_1_rsp_payload_data (memory_core_io_reads_1_rsp_payload_data[127:0] ), //o + .io_reads_1_rsp_payload_mask (memory_core_io_reads_1_rsp_payload_mask[15:0] ), //o + .io_reads_1_rsp_payload_context (memory_core_io_reads_1_rsp_payload_context[11:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_Aggregator_a048ca8f51874147a1cd65d43e6523ef b2m_fsm_aggregate_engine ( + .io_input_valid (b2m_fsm_aggregate_memoryPort_valid ), //i + .io_input_ready (b2m_fsm_aggregate_engine_io_input_ready ), //o + .io_input_payload_data (b2m_fsm_aggregate_memoryPort_payload_data[127:0] ), //i + .io_input_payload_mask (b2m_fsm_aggregate_engine_io_input_payload_mask[15:0]), //i + .io_output_data (b2m_fsm_aggregate_engine_io_output_data[127:0] ), //o + .io_output_mask (b2m_fsm_aggregate_engine_io_output_mask[15:0] ), //o + .io_output_enough (b2m_fsm_cmd_enoughAggregation ), //i + .io_output_consume (io_write_cmd_fire ), //i + .io_output_consumed (b2m_fsm_aggregate_engine_io_output_consumed ), //o + .io_output_lastByteUsed (b2m_fsm_cmd_maskLastTriggerReg[3:0] ), //i + .io_output_usedUntil (b2m_fsm_aggregate_engine_io_output_usedUntil[3:0] ), //o + .io_flush (b2m_fsm_aggregate_engine_io_flush ), //i + .io_offset (b2m_fsm_aggregate_engine_io_offset[3:0] ), //i + .io_burstLength (b2m_fsm_sel_bytesInBurst[11:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_s2b_0_cmd_byteCount_10) + 3'b000 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount; + 3'b001 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_1; + 3'b010 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_2; + 3'b011 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_3; + 3'b100 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_4; + 3'b101 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_5; + 3'b110 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_6; + default : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_7; + endcase + end + + always @(*) begin + case(_zz_s2b_0_cmd_byteCount_12) + 3'b000 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount; + 3'b001 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_1; + 3'b010 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_2; + 3'b011 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_3; + 3'b100 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_4; + 3'b101 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_5; + 3'b110 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_6; + default : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_7; + endcase + end + + always @(*) begin + case(_zz_s2b_0_cmd_byteCount_14) + 3'b000 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount; + 3'b001 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_1; + 3'b010 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_2; + 3'b011 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_3; + 3'b100 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_4; + 3'b101 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_5; + 3'b110 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_6; + default : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_7; + endcase + end + + always @(*) begin + case(_zz_m2b_cmd_s0_priority_masked) + 2'b00 : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_0; + 2'b01 : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_1; + 2'b10 : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_2; + default : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_3; + endcase + end + + always @(*) begin + case(_zz_b2m_fsm_arbiter_logic_priority_masked) + 2'b00 : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_0; + 2'b01 : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_1; + 2'b10 : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_2; + default : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_3; + endcase + end + + assign ctrl_readErrorFlag = 1'b0; + assign ctrl_writeErrorFlag = 1'b0; + assign io_ctrl_PREADY = 1'b1; + always @(*) begin + io_ctrl_PRDATA = 32'h0; + case(io_ctrl_PADDR) + 14'h002c : begin + io_ctrl_PRDATA[0 : 0] = channels_0_channelValid; + end + 14'h0054 : begin + io_ctrl_PRDATA[0 : 0] = channels_0_interrupts_completion_valid; + io_ctrl_PRDATA[2 : 2] = channels_0_interrupts_onChannelCompletion_valid; + io_ctrl_PRDATA[3 : 3] = channels_0_interrupts_onLinkedListUpdate_valid; + io_ctrl_PRDATA[4 : 4] = channels_0_interrupts_s2mPacket_valid; + end + 14'h0060 : begin + io_ctrl_PRDATA[26 : 0] = channels_0_bytesProbe_value; + end + 14'h00ac : begin + io_ctrl_PRDATA[0 : 0] = channels_1_channelValid; + end + 14'h00d4 : begin + io_ctrl_PRDATA[0 : 0] = channels_1_interrupts_completion_valid; + io_ctrl_PRDATA[2 : 2] = channels_1_interrupts_onChannelCompletion_valid; + io_ctrl_PRDATA[3 : 3] = channels_1_interrupts_onLinkedListUpdate_valid; + end + 14'h00e0 : begin + io_ctrl_PRDATA[26 : 0] = channels_1_bytesProbe_value; + end + default : begin + end + endcase + if(when_Apb3SlaveFactory_l81_1) begin + io_ctrl_PRDATA[31 : 0] = _zz_io_ctrl_PRDATA[31 : 0]; + end + if(when_Apb3SlaveFactory_l81_3) begin + io_ctrl_PRDATA[31 : 0] = _zz_io_ctrl_PRDATA_1[31 : 0]; + end + end + + assign ctrl_askWrite = ((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && io_ctrl_PWRITE); + assign ctrl_askRead = ((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && (! io_ctrl_PWRITE)); + assign ctrl_doWrite = (((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && io_ctrl_PREADY) && io_ctrl_PWRITE); + assign ctrl_doRead = (((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && io_ctrl_PREADY) && (! io_ctrl_PWRITE)); + assign io_ctrl_PSLVERROR = ((ctrl_doWrite && ctrl_writeErrorFlag) || (ctrl_doRead && ctrl_readErrorFlag)); + always @(*) begin + channels_0_channelStart = 1'b0; + if(when_BusSlaveFactory_l377) begin + if(when_BusSlaveFactory_l379) begin + channels_0_channelStart = _zz_channels_0_channelStart[0]; + end + end + if(when_BusSlaveFactory_l377_2) begin + if(when_BusSlaveFactory_l379_2) begin + channels_0_channelStart = _zz_channels_0_channelStart_1[0]; + end + end + end + + always @(*) begin + channels_0_channelCompletion = 1'b0; + if(channels_0_channelValid) begin + if(channels_0_channelStop) begin + if(channels_0_readyToStop) begin + channels_0_channelCompletion = 1'b1; + end + end + end + end + + always @(*) begin + channels_0_descriptorStart = 1'b0; + if(channels_0_ctrl_kick) begin + channels_0_descriptorStart = 1'b1; + end + if(when_DmaSg_l318) begin + if(when_DmaSg_l320) begin + if(when_DmaSg_l322) begin + channels_0_descriptorStart = 1'b1; + end + end + end + end + + always @(*) begin + channels_0_descriptorCompletion = 1'b0; + if(channels_0_pop_b2m_packetSync) begin + if(when_DmaSg_l532) begin + if(channels_0_push_s2b_completionOnLast) begin + channels_0_descriptorCompletion = 1'b1; + end + end + end + if(when_DmaSg_l547) begin + channels_0_descriptorCompletion = 1'b1; + end + if(channels_0_channelValid) begin + if(channels_0_channelStop) begin + if(channels_0_readyToStop) begin + channels_0_descriptorCompletion = 1'b1; + end + end + end + end + + always @(*) begin + channels_0_readyToStop = 1'b1; + if(channels_0_ll_waitDone) begin + channels_0_readyToStop = 1'b0; + end + if(when_DmaSg_l563) begin + channels_0_readyToStop = 1'b0; + end + end + + always @(*) begin + channels_0_bytesProbe_incr_valid = 1'b0; + if(io_write_rsp_fire) begin + if(when_DmaSg_l1116) begin + channels_0_bytesProbe_incr_valid = 1'b1; + end + end + end + + always @(*) begin + channels_0_bytesProbe_incr_payload = 12'bxxxxxxxxxxxx; + if(io_write_rsp_fire) begin + if(when_DmaSg_l1116) begin + channels_0_bytesProbe_incr_payload = b2m_rsp_context_length; + end + end + end + + always @(*) begin + channels_0_ll_sgStart = 1'b0; + if(when_BusSlaveFactory_l377_3) begin + if(when_BusSlaveFactory_l379_3) begin + channels_0_ll_sgStart = _zz_channels_0_ll_sgStart[0]; + end + end + end + + assign channels_0_ll_requestLl = ((((channels_0_channelValid && channels_0_ll_valid) && (! channels_0_channelStop)) && (! channels_0_ll_waitDone)) && ((! channels_0_descriptorValid) || channels_0_ll_requireSync)); + always @(*) begin + channels_0_ll_descriptorUpdated = 1'b0; + if(when_DmaSg_l318) begin + if(when_DmaSg_l328) begin + channels_0_ll_descriptorUpdated = 1'b1; + end + end + end + + assign when_DmaSg_l318 = (((channels_0_ll_valid && channels_0_ll_waitDone) && channels_0_ll_writeDone) && channels_0_ll_readDone); + assign when_DmaSg_l320 = (! channels_0_ll_justASync); + assign when_DmaSg_l322 = (! channels_0_ll_gotDescriptorStall); + assign when_DmaSg_l328 = (! channels_0_ll_head); + assign channels_0_fifo_base = 11'h0; + assign channels_0_fifo_words = 11'h1ff; + assign channels_0_fifo_push_availableDecr = 11'h0; + assign channels_0_fifo_push_ptrWithBase = ((channels_0_fifo_base & (~ channels_0_fifo_words)) | (channels_0_fifo_push_ptr & channels_0_fifo_words)); + assign channels_0_fifo_pop_ptrWithBase = ((channels_0_fifo_base & (~ channels_0_fifo_words)) | (channels_0_fifo_pop_ptr & channels_0_fifo_words)); + assign channels_0_fifo_pop_empty = (channels_0_fifo_pop_ptr == channels_0_fifo_push_ptr); + assign channels_0_fifo_pop_withOverride_backupNext = (_zz_channels_0_fifo_pop_withOverride_backupNext - channels_0_fifo_pop_bytesDecr_value); + always @(*) begin + channels_0_fifo_pop_withOverride_load = 1'b0; + if(when_DmaSg_l457) begin + channels_0_fifo_pop_withOverride_load = 1'b1; + end + end + + always @(*) begin + channels_0_fifo_pop_withOverride_unload = 1'b0; + if(channels_0_pop_b2m_packetSync) begin + channels_0_fifo_pop_withOverride_unload = 1'b1; + end + end + + assign when_DmaSg_l409 = (channels_0_channelStart || channels_0_fifo_pop_withOverride_unload); + assign channels_0_fifo_pop_bytes = channels_0_fifo_pop_withOverride_exposed; + assign channels_0_fifo_empty = (channels_0_fifo_push_ptr == channels_0_fifo_pop_ptr); + always @(*) begin + channels_0_push_s2b_packetEvent = 1'b0; + if(when_DmaSg_l679) begin + channels_0_push_s2b_packetEvent = 1'b1; + end + end + + assign when_DmaSg_l457 = (channels_0_push_s2b_packetEvent && channels_0_push_s2b_completionOnLast); + assign channels_0_pop_b2m_bytePerBurst = 12'h3ff; + always @(*) begin + channels_0_pop_b2m_fire = 1'b0; + if(when_DmaSg_l935) begin + if(_zz_when[0]) begin + channels_0_pop_b2m_fire = 1'b1; + end + end + end + + always @(*) begin + channels_0_pop_b2m_packetSync = 1'b0; + if(when_DmaSg_l523) begin + if(channels_0_pop_b2m_packet) begin + channels_0_pop_b2m_packetSync = 1'b1; + end + end + if(io_write_rsp_fire) begin + if(when_DmaSg_l1116) begin + if(b2m_rsp_context_doPacketSync) begin + channels_0_pop_b2m_packetSync = 1'b1; + end + end + end + end + + assign when_DmaSg_l505 = (channels_0_channelStart || channels_0_pop_b2m_fire); + always @(*) begin + channels_0_pop_b2m_memRsp = 1'b0; + if(io_write_rsp_fire) begin + if(_zz_when_2[0]) begin + channels_0_pop_b2m_memRsp = 1'b1; + end + end + end + + assign channels_0_pop_b2m_selfFlush = (channels_0_pop_b2m_bytesLeft < _zz_channels_0_pop_b2m_selfFlush); + assign channels_0_pop_b2m_request = ((((((channels_0_descriptorValid && (! channels_0_channelStop)) && (! channels_0_pop_b2m_waitFinalRsp)) && channels_0_pop_memory) && ((_zz_channels_0_pop_b2m_request < channels_0_fifo_pop_bytes) || (((channels_0_fifo_push_available < _zz_channels_0_pop_b2m_request_1) || channels_0_pop_b2m_flush) || channels_0_pop_b2m_selfFlush))) && (channels_0_fifo_pop_bytes != 14'h0)) && (channels_0_pop_b2m_memPending != 4'b1111)); + always @(*) begin + channels_0_pop_b2m_memPendingInc = 1'b0; + if(when_DmaSg_l758_1) begin + if(when_DmaSg_l773_1) begin + channels_0_pop_b2m_memPendingInc = 1'b1; + end + end + end + + always @(*) begin + channels_0_pop_b2m_decrBytes = 14'h0; + if(b2m_fsm_s1) begin + if(when_DmaSg_l996) begin + channels_0_pop_b2m_decrBytes = {1'd0, b2m_fsm_bytesInBurstP1}; + end + end + end + + assign when_DmaSg_l523 = ((channels_0_pop_b2m_memPending == 4'b0000) && (channels_0_fifo_pop_bytes == 14'h0)); + assign when_DmaSg_l532 = (channels_0_descriptorValid && (! channels_0_push_memory)); + assign when_DmaSg_l536 = (! channels_0_pop_b2m_waitFinalRsp); + assign when_DmaSg_l547 = ((channels_0_descriptorValid && (channels_0_pop_b2m_memPending == 4'b0000)) && channels_0_pop_b2m_waitFinalRsp); + assign when_DmaSg_l563 = (channels_0_pop_b2m_memPending != 4'b0000); + assign channels_0_readyForChannelCompletion = 1'b1; + assign when_DmaSg_l575 = (! channels_0_descriptorValid); + always @(*) begin + _zz_when_DmaSg_l593 = 1'b1; + if(channels_0_ctrl_kick) begin + _zz_when_DmaSg_l593 = 1'b0; + end + if(channels_0_ll_valid) begin + _zz_when_DmaSg_l593 = 1'b0; + end + end + + assign when_DmaSg_l593 = (_zz_when_DmaSg_l593 && channels_0_readyForChannelCompletion); + assign channels_0_s2b_full = (channels_0_fifo_push_available < 11'h002); + assign when_DmaSg_l255 = (channels_0_descriptorValid && channels_0_descriptorCompletion); + assign when_DmaSg_l255_1 = (! channels_0_interrupts_completion_enable); + assign when_DmaSg_l255_2 = (channels_0_channelValid && channels_0_channelCompletion); + assign when_DmaSg_l255_3 = (! channels_0_interrupts_onChannelCompletion_enable); + assign when_DmaSg_l255_4 = (! channels_0_interrupts_onLinkedListUpdate_enable); + assign when_DmaSg_l255_5 = (! channels_0_interrupts_s2mPacket_enable); + assign when_DmaSg_l625 = (channels_0_channelStart || channels_0_descriptorStart); + always @(*) begin + channels_1_channelStart = 1'b0; + if(when_BusSlaveFactory_l377_4) begin + if(when_BusSlaveFactory_l379_4) begin + channels_1_channelStart = _zz_channels_1_channelStart[0]; + end + end + if(when_BusSlaveFactory_l377_6) begin + if(when_BusSlaveFactory_l379_6) begin + channels_1_channelStart = _zz_channels_1_channelStart_1[0]; + end + end + end + + always @(*) begin + channels_1_channelCompletion = 1'b0; + if(channels_1_channelValid) begin + if(channels_1_channelStop) begin + if(channels_1_readyToStop) begin + channels_1_channelCompletion = 1'b1; + end + end + end + end + + always @(*) begin + channels_1_descriptorStart = 1'b0; + if(channels_1_ctrl_kick) begin + channels_1_descriptorStart = 1'b1; + end + if(when_DmaSg_l318_1) begin + if(when_DmaSg_l320_1) begin + if(when_DmaSg_l322_1) begin + channels_1_descriptorStart = 1'b1; + end + end + end + end + + always @(*) begin + channels_1_descriptorCompletion = 1'b0; + if(when_DmaSg_l483) begin + channels_1_descriptorCompletion = 1'b1; + end + if(channels_1_channelValid) begin + if(channels_1_channelStop) begin + if(channels_1_readyToStop) begin + channels_1_descriptorCompletion = 1'b1; + end + end + end + end + + always @(*) begin + channels_1_readyToStop = 1'b1; + if(channels_1_ll_waitDone) begin + channels_1_readyToStop = 1'b0; + end + if(when_DmaSg_l562) begin + channels_1_readyToStop = 1'b0; + end + end + + always @(*) begin + channels_1_bytesProbe_incr_valid = 1'b0; + if(when_DmaSg_l874) begin + channels_1_bytesProbe_incr_valid = 1'b1; + end + end + + always @(*) begin + channels_1_bytesProbe_incr_payload = 12'bxxxxxxxxxxxx; + if(when_DmaSg_l874) begin + channels_1_bytesProbe_incr_payload = m2b_rsp_context_length; + end + end + + always @(*) begin + channels_1_ll_sgStart = 1'b0; + if(when_BusSlaveFactory_l377_7) begin + if(when_BusSlaveFactory_l379_7) begin + channels_1_ll_sgStart = _zz_channels_1_ll_sgStart[0]; + end + end + end + + assign channels_1_ll_requestLl = ((((channels_1_channelValid && channels_1_ll_valid) && (! channels_1_channelStop)) && (! channels_1_ll_waitDone)) && ((! channels_1_descriptorValid) || channels_1_ll_requireSync)); + always @(*) begin + channels_1_ll_descriptorUpdated = 1'b0; + if(when_DmaSg_l318_1) begin + if(when_DmaSg_l328_1) begin + channels_1_ll_descriptorUpdated = 1'b1; + end + end + end + + assign when_DmaSg_l318_1 = (((channels_1_ll_valid && channels_1_ll_waitDone) && channels_1_ll_writeDone) && channels_1_ll_readDone); + assign when_DmaSg_l320_1 = (! channels_1_ll_justASync); + assign when_DmaSg_l322_1 = (! channels_1_ll_gotDescriptorStall); + assign when_DmaSg_l328_1 = (! channels_1_ll_head); + assign channels_1_fifo_base = 11'h200; + assign channels_1_fifo_words = 11'h1ff; + always @(*) begin + channels_1_fifo_push_availableDecr = 11'h0; + if(m2b_cmd_s1_valid) begin + if(io_read_cmd_ready) begin + if(when_DmaSg_l828) begin + channels_1_fifo_push_availableDecr = {1'd0, m2b_cmd_s1_fifoPushDecr}; + end + end + end + end + + assign channels_1_fifo_push_ptrWithBase = ((channels_1_fifo_base & (~ channels_1_fifo_words)) | (channels_1_fifo_push_ptr & channels_1_fifo_words)); + assign channels_1_fifo_pop_ptrWithBase = ((channels_1_fifo_base & (~ channels_1_fifo_words)) | (channels_1_fifo_pop_ptr & channels_1_fifo_words)); + assign channels_1_fifo_pop_empty = (channels_1_fifo_pop_ptr == channels_1_fifo_push_ptr); + assign channels_1_fifo_pop_bytes = channels_1_fifo_pop_withoutOverride_exposed; + assign channels_1_fifo_empty = (channels_1_fifo_push_ptr == channels_1_fifo_pop_ptr); + assign channels_1_push_m2b_bytePerBurst = 12'h3ff; + always @(*) begin + channels_1_push_m2b_memPendingIncr = 1'b0; + if(when_DmaSg_l758) begin + if(when_DmaSg_l773) begin + channels_1_push_m2b_memPendingIncr = 1'b1; + end + end + end + + always @(*) begin + channels_1_push_m2b_memPendingDecr = 1'b0; + if(when_DmaSg_l893) begin + channels_1_push_m2b_memPendingDecr = 1'b1; + end + end + + always @(*) begin + channels_1_push_m2b_loadRequest = (((((channels_1_descriptorValid && (! channels_1_channelStop)) && (! channels_1_push_m2b_loadDone)) && channels_1_push_memory) && (_zz_channels_1_push_m2b_loadRequest < channels_1_fifo_push_available)) && (channels_1_push_m2b_memPending != 4'b1111)); + if(when_DmaSg_l486) begin + channels_1_push_m2b_loadRequest = 1'b0; + end + end + + always @(*) begin + channels_1_pop_b2s_veryLastTrigger = 1'b0; + if(when_DmaSg_l847) begin + if(when_DmaSg_l848) begin + channels_1_pop_b2s_veryLastTrigger = 1'b1; + end + end + end + + assign when_DmaSg_l474 = (channels_1_pop_b2s_veryLastTrigger && channels_1_pop_b2s_last); + assign when_DmaSg_l483 = ((((channels_1_descriptorValid && (! channels_1_pop_memory)) && channels_1_push_memory) && channels_1_push_m2b_loadDone) && (channels_1_push_m2b_memPending == 4'b0000)); + assign when_DmaSg_l486 = (((! channels_1_pop_memory) && channels_1_pop_b2s_veryLastValid) && (channels_1_push_m2b_bytesLeft <= _zz_when_DmaSg_l486)); + assign when_DmaSg_l562 = (channels_1_push_m2b_memPending != 4'b0000); + always @(*) begin + channels_1_readyForChannelCompletion = 1'b1; + if(when_DmaSg_l566) begin + channels_1_readyForChannelCompletion = 1'b0; + end + end + + assign when_DmaSg_l566 = ((! channels_1_pop_memory) && (! channels_1_fifo_pop_empty)); + assign when_DmaSg_l575_1 = (! channels_1_descriptorValid); + always @(*) begin + _zz_when_DmaSg_l593_1 = 1'b1; + if(channels_1_ctrl_kick) begin + _zz_when_DmaSg_l593_1 = 1'b0; + end + if(channels_1_ll_valid) begin + _zz_when_DmaSg_l593_1 = 1'b0; + end + end + + assign when_DmaSg_l593_1 = (_zz_when_DmaSg_l593_1 && channels_1_readyForChannelCompletion); + assign channels_1_s2b_full = (channels_1_fifo_push_available < 11'h002); + assign when_DmaSg_l255_6 = (channels_1_descriptorValid && channels_1_descriptorCompletion); + assign when_DmaSg_l255_7 = (! channels_1_interrupts_completion_enable); + assign when_DmaSg_l255_8 = (channels_1_channelValid && channels_1_channelCompletion); + assign when_DmaSg_l255_9 = (! channels_1_interrupts_onChannelCompletion_enable); + assign when_DmaSg_l255_10 = (! channels_1_interrupts_onLinkedListUpdate_enable); + assign when_DmaSg_l625_1 = (channels_1_channelStart || channels_1_descriptorStart); + assign io_inputs_0_fire = (io_inputs_0_valid && io_inputs_0_ready); + assign when_package_l12 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0000)); + assign when_package_l12_1 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0001)); + assign when_package_l12_2 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0010)); + assign when_package_l12_3 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0011)); + assign when_package_l12_4 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0100)); + assign when_package_l12_5 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0101)); + assign when_package_l12_6 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0110)); + assign when_package_l12_7 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0111)); + assign when_package_l12_8 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1000)); + assign when_package_l12_9 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1001)); + assign when_package_l12_10 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1010)); + assign when_package_l12_11 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1011)); + assign when_package_l12_12 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1100)); + assign when_package_l12_13 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1101)); + assign when_package_l12_14 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1110)); + assign when_package_l12_15 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1111)); + assign s2b_0_cmd_firsts = {io_inputs_0_payload_last_regNextWhen_15,{io_inputs_0_payload_last_regNextWhen_14,{io_inputs_0_payload_last_regNextWhen_13,{io_inputs_0_payload_last_regNextWhen_12,{io_inputs_0_payload_last_regNextWhen_11,{io_inputs_0_payload_last_regNextWhen_10,{io_inputs_0_payload_last_regNextWhen_9,{io_inputs_0_payload_last_regNextWhen_8,{io_inputs_0_payload_last_regNextWhen_7,{io_inputs_0_payload_last_regNextWhen_6,{_zz_s2b_0_cmd_firsts,_zz_s2b_0_cmd_firsts_1}}}}}}}}}}}; + assign s2b_0_cmd_first = s2b_0_cmd_firsts[io_inputs_0_payload_sink]; + assign s2b_0_cmd_channelsOh = ((((channels_0_channelValid && (s2b_0_cmd_first || (! channels_0_push_s2b_waitFirst))) && (! channels_0_push_memory)) && 1'b1) && (io_inputs_0_payload_sink == 4'b0000)); + assign s2b_0_cmd_noHit = (! (|s2b_0_cmd_channelsOh)); + assign s2b_0_cmd_channelsFull = (channels_0_s2b_full || (channels_0_push_s2b_packetLock && io_inputs_0_payload_last)); + always @(*) begin + io_inputs_0_thrown_valid = io_inputs_0_valid; + if(s2b_0_cmd_noHit) begin + io_inputs_0_thrown_valid = 1'b0; + end + end + + always @(*) begin + io_inputs_0_ready = io_inputs_0_thrown_ready; + if(s2b_0_cmd_noHit) begin + io_inputs_0_ready = 1'b1; + end + end + + assign io_inputs_0_thrown_payload_data = io_inputs_0_payload_data; + assign io_inputs_0_thrown_payload_mask = io_inputs_0_payload_mask; + assign io_inputs_0_thrown_payload_sink = io_inputs_0_payload_sink; + assign io_inputs_0_thrown_payload_last = io_inputs_0_payload_last; + assign _zz_io_inputs_0_thrown_ready = (! (|(s2b_0_cmd_channelsOh & s2b_0_cmd_channelsFull))); + assign s2b_0_cmd_sinkHalted_valid = (io_inputs_0_thrown_valid && _zz_io_inputs_0_thrown_ready); + assign io_inputs_0_thrown_ready = (s2b_0_cmd_sinkHalted_ready && _zz_io_inputs_0_thrown_ready); + assign s2b_0_cmd_sinkHalted_payload_data = io_inputs_0_thrown_payload_data; + assign s2b_0_cmd_sinkHalted_payload_mask = io_inputs_0_thrown_payload_mask; + assign s2b_0_cmd_sinkHalted_payload_sink = io_inputs_0_thrown_payload_sink; + assign s2b_0_cmd_sinkHalted_payload_last = io_inputs_0_thrown_payload_last; + assign _zz_s2b_0_cmd_byteCount = 4'b0000; + assign _zz_s2b_0_cmd_byteCount_1 = 4'b0001; + assign _zz_s2b_0_cmd_byteCount_2 = 4'b0001; + assign _zz_s2b_0_cmd_byteCount_3 = 4'b0010; + assign _zz_s2b_0_cmd_byteCount_4 = 4'b0001; + assign _zz_s2b_0_cmd_byteCount_5 = 4'b0010; + assign _zz_s2b_0_cmd_byteCount_6 = 4'b0010; + assign _zz_s2b_0_cmd_byteCount_7 = 4'b0011; + assign s2b_0_cmd_byteCount = (_zz_s2b_0_cmd_byteCount_8 + _zz_s2b_0_cmd_byteCount_13); + assign s2b_0_cmd_context_channel = s2b_0_cmd_channelsOh; + assign s2b_0_cmd_context_bytes = s2b_0_cmd_byteCount; + assign s2b_0_cmd_context_flush = io_inputs_0_payload_last; + assign s2b_0_cmd_context_packet = io_inputs_0_payload_last; + assign s2b_0_cmd_sinkHalted_ready = memory_core_io_writes_0_cmd_ready; + assign memory_core_io_writes_0_cmd_payload_address = channels_0_fifo_push_ptrWithBase[9:0]; + assign memory_core_io_writes_0_cmd_payload_context = {s2b_0_cmd_context_packet,{s2b_0_cmd_context_flush,{s2b_0_cmd_context_bytes,s2b_0_cmd_context_channel}}}; + assign memory_core_io_writes_0_cmd_fire = (s2b_0_cmd_sinkHalted_valid && memory_core_io_writes_0_cmd_ready); + assign when_DmaSg_l665 = (s2b_0_cmd_channelsOh[0] && memory_core_io_writes_0_cmd_fire); + assign _zz_s2b_0_rsp_context_channel = memory_core_io_writes_0_rsp_payload_context; + assign s2b_0_rsp_context_channel = _zz_s2b_0_rsp_context_channel[0 : 0]; + assign s2b_0_rsp_context_bytes = _zz_s2b_0_rsp_context_channel[4 : 1]; + assign s2b_0_rsp_context_flush = _zz_s2b_0_rsp_context_channel[5]; + assign s2b_0_rsp_context_packet = _zz_s2b_0_rsp_context_channel[6]; + assign _zz_channels_0_fifo_pop_bytesIncr_value = (memory_core_io_writes_0_rsp_valid && s2b_0_rsp_context_channel[0]); + assign when_DmaSg_l679 = (_zz_channels_0_fifo_pop_bytesIncr_value && s2b_0_rsp_context_packet); + assign when_DmaSg_l681 = (_zz_channels_0_fifo_pop_bytesIncr_value && s2b_0_rsp_context_flush); + assign when_DmaSg_l682 = (_zz_channels_0_fifo_pop_bytesIncr_value && s2b_0_rsp_context_packet); + assign b2s_0_cmd_channelsOh = (((channels_1_channelValid && (! channels_1_pop_memory)) && 1'b1) && (! channels_1_fifo_pop_empty)); + assign b2s_0_cmd_veryLastPtr = channels_1_pop_b2s_veryLastPtr; + assign b2s_0_cmd_address = channels_1_fifo_pop_ptrWithBase; + assign b2s_0_cmd_context_channel = b2s_0_cmd_channelsOh; + assign b2s_0_cmd_context_veryLast = ((channels_1_pop_b2s_veryLastValid && (b2s_0_cmd_address[10 : 1] == b2s_0_cmd_veryLastPtr[10 : 1])) && (b2s_0_cmd_address[0 : 0] == 1'b1)); + assign b2s_0_cmd_context_endPacket = channels_1_pop_b2s_veryLastEndPacket; + assign memory_core_io_reads_0_cmd_valid = (|b2s_0_cmd_channelsOh); + assign memory_core_io_reads_0_cmd_payload_address = b2s_0_cmd_address[9:0]; + assign memory_core_io_reads_0_cmd_payload_context = {b2s_0_cmd_context_endPacket,{b2s_0_cmd_context_veryLast,b2s_0_cmd_context_channel}}; + assign _zz_b2s_0_rsp_context_channel = memory_core_io_reads_0_rsp_payload_context; + assign b2s_0_rsp_context_channel = _zz_b2s_0_rsp_context_channel[0 : 0]; + assign b2s_0_rsp_context_veryLast = _zz_b2s_0_rsp_context_channel[1]; + assign b2s_0_rsp_context_endPacket = _zz_b2s_0_rsp_context_channel[2]; + assign io_outputs_0_valid = memory_core_io_reads_0_rsp_valid; + assign io_outputs_0_payload_data = memory_core_io_reads_0_rsp_payload_data; + assign io_outputs_0_payload_mask = memory_core_io_reads_0_rsp_payload_mask; + assign io_outputs_0_payload_sink = channels_1_pop_b2s_sinkId; + assign io_outputs_0_payload_last = (b2s_0_rsp_context_veryLast && b2s_0_rsp_context_endPacket); + assign io_outputs_0_fire = (io_outputs_0_valid && io_outputs_0_ready); + assign when_DmaSg_l725 = (io_outputs_0_fire && b2s_0_rsp_context_veryLast); + assign when_DmaSg_l726 = b2s_0_rsp_context_channel[0]; + assign _zz_m2b_cmd_s0_priority_masked = channels_1_priority; + assign m2b_cmd_s0_priority_masked = (channels_1_push_m2b_loadRequest && (channels_1_priority == _zz_m2b_cmd_s0_priority_masked)); + assign _zz_m2b_cmd_s0_priority_chosenOh = m2b_cmd_s0_priority_masked; + assign _zz_m2b_cmd_s0_priority_chosenOh_1 = {_zz_m2b_cmd_s0_priority_chosenOh,_zz_m2b_cmd_s0_priority_chosenOh}; + assign _zz_m2b_cmd_s0_priority_chosenOh_2 = (_zz_m2b_cmd_s0_priority_chosenOh_1 & (~ _zz__zz_m2b_cmd_s0_priority_chosenOh_2)); + assign m2b_cmd_s0_priority_chosenOh = (_zz_m2b_cmd_s0_priority_chosenOh_2[1 : 1] | _zz_m2b_cmd_s0_priority_chosenOh_2[0 : 0]); + assign m2b_cmd_s0_priority_weightLast = (channels_1_weight == m2b_cmd_s0_priority_counter); + assign m2b_cmd_s0_priority_contextNext = (m2b_cmd_s0_priority_weightLast ? m2b_cmd_s0_priority_chosenOh[0 : 0] : m2b_cmd_s0_priority_chosenOh); + assign when_DmaSg_l758 = (! m2b_cmd_s0_valid); + assign when_DmaSg_l760 = (|channels_1_push_m2b_loadRequest); + assign when_DmaSg_l763 = (2'b00 == _zz_m2b_cmd_s0_priority_masked); + assign when_DmaSg_l763_1 = (2'b01 == _zz_m2b_cmd_s0_priority_masked); + assign when_DmaSg_l763_2 = (2'b10 == _zz_m2b_cmd_s0_priority_masked); + assign when_DmaSg_l763_3 = (2'b11 == _zz_m2b_cmd_s0_priority_masked); + assign when_DmaSg_l773 = (channels_1_push_m2b_loadRequest && m2b_cmd_s0_priority_chosenOh[0]); + assign m2b_cmd_s0_address = channels_1_push_m2b_address; + assign m2b_cmd_s0_bytesLeft = channels_1_push_m2b_bytesLeft; + assign m2b_cmd_s0_readAddressBurstRange = m2b_cmd_s0_address[11 : 0]; + assign m2b_cmd_s0_lengthHead = ((~ m2b_cmd_s0_readAddressBurstRange) & channels_1_push_m2b_bytePerBurst); + assign m2b_cmd_s0_length = _zz_m2b_cmd_s0_length[11:0]; + assign m2b_cmd_s0_lastBurst = (m2b_cmd_s0_bytesLeft == _zz_m2b_cmd_s0_lastBurst); + assign m2b_cmd_s1_context_start = m2b_cmd_s1_address[3:0]; + assign m2b_cmd_s1_context_stop = _zz_m2b_cmd_s1_context_stop[3:0]; + assign m2b_cmd_s1_context_last = m2b_cmd_s1_lastBurst; + assign m2b_cmd_s1_context_length = m2b_cmd_s1_length; + always @(*) begin + io_read_cmd_valid = 1'b0; + if(m2b_cmd_s1_valid) begin + io_read_cmd_valid = 1'b1; + end + end + + assign io_read_cmd_payload_last = 1'b1; + assign io_read_cmd_payload_fragment_opcode = 1'b0; + assign io_read_cmd_payload_fragment_address = m2b_cmd_s1_address; + assign io_read_cmd_payload_fragment_length = m2b_cmd_s1_length; + assign io_read_cmd_payload_fragment_context = {m2b_cmd_s1_context_last,{m2b_cmd_s1_context_length,{m2b_cmd_s1_context_stop,m2b_cmd_s1_context_start}}}; + assign m2b_cmd_s1_addressNext = (_zz_m2b_cmd_s1_addressNext + 32'h00000001); + assign m2b_cmd_s1_byteLeftNext = (_zz_m2b_cmd_s1_byteLeftNext - 26'h0000001); + assign m2b_cmd_s1_fifoPushDecr = (_zz_m2b_cmd_s1_fifoPushDecr >>> 2'd3); + assign when_DmaSg_l828 = 1'b1; + assign _zz_m2b_rsp_context_start = io_read_rsp_payload_fragment_context; + assign m2b_rsp_context_start = _zz_m2b_rsp_context_start[3 : 0]; + assign m2b_rsp_context_stop = _zz_m2b_rsp_context_start[7 : 4]; + assign m2b_rsp_context_length = _zz_m2b_rsp_context_start[19 : 8]; + assign m2b_rsp_context_last = _zz_m2b_rsp_context_start[20]; + assign m2b_rsp_veryLast = (m2b_rsp_context_last && io_read_rsp_payload_last); + assign io_read_rsp_fire = (io_read_rsp_valid && io_read_rsp_ready); + assign when_DmaSg_l847 = (io_read_rsp_fire && m2b_rsp_veryLast); + assign when_DmaSg_l848 = 1'b1; + always @(*) begin + memory_core_io_writes_1_cmd_payload_mask[0] = ((! (m2b_rsp_first && (4'b0000 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0000)))); + memory_core_io_writes_1_cmd_payload_mask[1] = ((! (m2b_rsp_first && (4'b0001 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0001)))); + memory_core_io_writes_1_cmd_payload_mask[2] = ((! (m2b_rsp_first && (4'b0010 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0010)))); + memory_core_io_writes_1_cmd_payload_mask[3] = ((! (m2b_rsp_first && (4'b0011 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0011)))); + memory_core_io_writes_1_cmd_payload_mask[4] = ((! (m2b_rsp_first && (4'b0100 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0100)))); + memory_core_io_writes_1_cmd_payload_mask[5] = ((! (m2b_rsp_first && (4'b0101 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0101)))); + memory_core_io_writes_1_cmd_payload_mask[6] = ((! (m2b_rsp_first && (4'b0110 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0110)))); + memory_core_io_writes_1_cmd_payload_mask[7] = ((! (m2b_rsp_first && (4'b0111 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0111)))); + memory_core_io_writes_1_cmd_payload_mask[8] = ((! (m2b_rsp_first && (4'b1000 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1000)))); + memory_core_io_writes_1_cmd_payload_mask[9] = ((! (m2b_rsp_first && (4'b1001 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1001)))); + memory_core_io_writes_1_cmd_payload_mask[10] = ((! (m2b_rsp_first && (4'b1010 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1010)))); + memory_core_io_writes_1_cmd_payload_mask[11] = ((! (m2b_rsp_first && (4'b1011 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1011)))); + memory_core_io_writes_1_cmd_payload_mask[12] = ((! (m2b_rsp_first && (4'b1100 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1100)))); + memory_core_io_writes_1_cmd_payload_mask[13] = ((! (m2b_rsp_first && (4'b1101 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1101)))); + memory_core_io_writes_1_cmd_payload_mask[14] = ((! (m2b_rsp_first && (4'b1110 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1110)))); + memory_core_io_writes_1_cmd_payload_mask[15] = ((! (m2b_rsp_first && (4'b1111 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1111)))); + end + + assign m2b_rsp_writeContext_last = m2b_rsp_veryLast; + assign m2b_rsp_writeContext_lastOfBurst = io_read_rsp_payload_last; + assign m2b_rsp_writeContext_loadByteInNextBeat = ({1'b0,(io_read_rsp_payload_last ? m2b_rsp_context_stop : 4'b1111)} - {1'b0,(m2b_rsp_first ? m2b_rsp_context_start : 4'b0000)}); + assign memory_core_io_writes_1_cmd_payload_address = channels_1_fifo_push_ptrWithBase[9:0]; + assign io_read_rsp_ready = memory_core_io_writes_1_cmd_ready; + assign memory_core_io_writes_1_cmd_payload_context = {m2b_rsp_writeContext_loadByteInNextBeat,{m2b_rsp_writeContext_lastOfBurst,m2b_rsp_writeContext_last}}; + assign memory_core_io_writes_1_cmd_fire = (io_read_rsp_valid && memory_core_io_writes_1_cmd_ready); + assign _zz_channels_1_fifo_push_ptrIncr_value = (memory_core_io_writes_1_cmd_fire && 1'b1); + assign when_DmaSg_l874 = (_zz_channels_1_fifo_push_ptrIncr_value && io_read_rsp_payload_last); + assign _zz_m2b_writeRsp_context_last = memory_core_io_writes_1_rsp_payload_context; + assign m2b_writeRsp_context_last = _zz_m2b_writeRsp_context_last[0]; + assign m2b_writeRsp_context_lastOfBurst = _zz_m2b_writeRsp_context_last[1]; + assign m2b_writeRsp_context_loadByteInNextBeat = _zz_m2b_writeRsp_context_last[6 : 2]; + assign _zz_channels_1_fifo_pop_bytesIncr_value = (memory_core_io_writes_1_rsp_valid && 1'b1); + assign when_DmaSg_l893 = (_zz_channels_1_fifo_pop_bytesIncr_value && m2b_writeRsp_context_lastOfBurst); + assign _zz_b2m_fsm_arbiter_logic_priority_masked = channels_0_priority; + assign b2m_fsm_arbiter_logic_priority_masked = (channels_0_pop_b2m_request && (channels_0_priority == _zz_b2m_fsm_arbiter_logic_priority_masked)); + assign _zz_b2m_fsm_arbiter_logic_priority_chosenOh = b2m_fsm_arbiter_logic_priority_masked; + assign _zz_b2m_fsm_arbiter_logic_priority_chosenOh_1 = {_zz_b2m_fsm_arbiter_logic_priority_chosenOh,_zz_b2m_fsm_arbiter_logic_priority_chosenOh}; + assign _zz_b2m_fsm_arbiter_logic_priority_chosenOh_2 = (_zz_b2m_fsm_arbiter_logic_priority_chosenOh_1 & (~ _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2)); + assign b2m_fsm_arbiter_logic_priority_chosenOh = (_zz_b2m_fsm_arbiter_logic_priority_chosenOh_2[1 : 1] | _zz_b2m_fsm_arbiter_logic_priority_chosenOh_2[0 : 0]); + assign b2m_fsm_arbiter_logic_priority_weightLast = (channels_0_weight == b2m_fsm_arbiter_logic_priority_counter); + assign b2m_fsm_arbiter_logic_priority_contextNext = (b2m_fsm_arbiter_logic_priority_weightLast ? b2m_fsm_arbiter_logic_priority_chosenOh[0 : 0] : b2m_fsm_arbiter_logic_priority_chosenOh); + assign when_DmaSg_l758_1 = (! b2m_fsm_arbiter_logic_valid); + assign when_DmaSg_l760_1 = (|channels_0_pop_b2m_request); + assign when_DmaSg_l763_4 = (2'b00 == _zz_b2m_fsm_arbiter_logic_priority_masked); + assign when_DmaSg_l763_5 = (2'b01 == _zz_b2m_fsm_arbiter_logic_priority_masked); + assign when_DmaSg_l763_6 = (2'b10 == _zz_b2m_fsm_arbiter_logic_priority_masked); + assign when_DmaSg_l763_7 = (2'b11 == _zz_b2m_fsm_arbiter_logic_priority_masked); + assign when_DmaSg_l773_1 = (channels_0_pop_b2m_request && b2m_fsm_arbiter_logic_priority_chosenOh[0]); + assign when_DmaSg_l935 = ((! b2m_fsm_sel_valid) && b2m_fsm_arbiter_logic_valid); + assign b2m_fsm_bytesInBurstP1 = ({1'b0,b2m_fsm_sel_bytesInBurst} + _zz_b2m_fsm_bytesInBurstP1); + assign b2m_fsm_addressNext = (b2m_fsm_sel_address + _zz_b2m_fsm_addressNext); + assign b2m_fsm_bytesLeftNext = ({1'b0,b2m_fsm_sel_bytesLeft} - _zz_b2m_fsm_bytesLeftNext); + assign b2m_fsm_isFinalCmd = b2m_fsm_bytesLeftNext[26]; + assign b2m_fsm_s0 = (b2m_fsm_sel_valid && (! b2m_fsm_sel_valid_regNext)); + assign when_DmaSg_l986 = (! b2m_fsm_sel_valid); + assign _zz_b2m_fsm_sel_bytesInBurst = (b2m_fsm_sel_bytesInFifo - 14'h0001); + assign _zz_b2m_fsm_sel_bytesInBurst_1 = ((_zz__zz_b2m_fsm_sel_bytesInBurst_1 < b2m_fsm_sel_bytesLeft) ? _zz__zz_b2m_fsm_sel_bytesInBurst_1_1 : b2m_fsm_sel_bytesLeft); + assign _zz_b2m_fsm_sel_bytesInBurst_2 = (b2m_fsm_sel_bytePerBurst - (_zz__zz_b2m_fsm_sel_bytesInBurst_2 & b2m_fsm_sel_bytePerBurst)); + assign b2m_fsm_fifoCompletion = (_zz_b2m_fsm_fifoCompletion == _zz_b2m_fsm_fifoCompletion_1); + assign when_DmaSg_l996 = 1'b1; + assign when_DmaSg_l1001 = (! b2m_fsm_fifoCompletion); + assign when_DmaSg_l1013 = (b2m_fsm_sel_valid && b2m_fsm_sel_ready); + always @(*) begin + b2m_fsm_sel_ready = 1'b0; + if(when_DmaSg_l1102) begin + b2m_fsm_sel_ready = 1'b1; + end + end + + assign b2m_fsm_fetch_context_ptr = channels_0_fifo_pop_ptr; + assign b2m_fsm_fetch_context_toggle = b2m_fsm_toggle; + assign memory_core_io_reads_1_cmd_payload_address = b2m_fsm_sel_ptr[9:0]; + assign memory_core_io_reads_1_cmd_payload_context = {b2m_fsm_fetch_context_toggle,b2m_fsm_fetch_context_ptr}; + assign when_DmaSg_l1033 = (b2m_fsm_sel_valid && memory_core_io_reads_1_cmd_ready); + assign _zz_b2m_fsm_aggregate_context_ptr = memory_core_io_reads_1_rsp_payload_context; + assign b2m_fsm_aggregate_context_ptr = _zz_b2m_fsm_aggregate_context_ptr[10 : 0]; + assign b2m_fsm_aggregate_context_toggle = _zz_b2m_fsm_aggregate_context_ptr[11]; + assign memory_core_io_reads_1_rsp_s2mPipe_valid = (memory_core_io_reads_1_rsp_valid || (! memory_core_io_reads_1_rsp_rValidN)); + assign memory_core_io_reads_1_rsp_s2mPipe_payload_data = (memory_core_io_reads_1_rsp_rValidN ? memory_core_io_reads_1_rsp_payload_data : memory_core_io_reads_1_rsp_rData_data); + assign memory_core_io_reads_1_rsp_s2mPipe_payload_mask = (memory_core_io_reads_1_rsp_rValidN ? memory_core_io_reads_1_rsp_payload_mask : memory_core_io_reads_1_rsp_rData_mask); + assign memory_core_io_reads_1_rsp_s2mPipe_payload_context = (memory_core_io_reads_1_rsp_rValidN ? memory_core_io_reads_1_rsp_payload_context : memory_core_io_reads_1_rsp_rData_context); + assign when_Stream_l445 = (b2m_fsm_aggregate_context_toggle != b2m_fsm_toggle); + always @(*) begin + b2m_fsm_aggregate_memoryPort_valid = memory_core_io_reads_1_rsp_s2mPipe_valid; + if(when_Stream_l445) begin + b2m_fsm_aggregate_memoryPort_valid = 1'b0; + end + end + + always @(*) begin + memory_core_io_reads_1_rsp_s2mPipe_ready = b2m_fsm_aggregate_memoryPort_ready; + if(when_Stream_l445) begin + memory_core_io_reads_1_rsp_s2mPipe_ready = 1'b1; + end + end + + assign b2m_fsm_aggregate_memoryPort_payload_data = memory_core_io_reads_1_rsp_s2mPipe_payload_data; + assign b2m_fsm_aggregate_memoryPort_payload_mask = memory_core_io_reads_1_rsp_s2mPipe_payload_mask; + assign b2m_fsm_aggregate_memoryPort_payload_context = memory_core_io_reads_1_rsp_s2mPipe_payload_context; + assign b2m_fsm_aggregate_memoryPort_fire = (b2m_fsm_aggregate_memoryPort_valid && b2m_fsm_aggregate_memoryPort_ready); + assign when_DmaSg_l1050 = (! (b2m_fsm_sel_valid && (! b2m_fsm_sel_ready))); + assign b2m_fsm_aggregate_bytesToSkip = channels_0_pop_b2m_bytesToSkip; + assign b2m_fsm_aggregate_bytesToSkipMask = {((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1111)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1110)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= _zz_b2m_fsm_aggregate_bytesToSkipMask)),{(_zz_b2m_fsm_aggregate_bytesToSkipMask_1 || _zz_b2m_fsm_aggregate_bytesToSkipMask_2),{_zz_b2m_fsm_aggregate_bytesToSkipMask_3,{_zz_b2m_fsm_aggregate_bytesToSkipMask_4,_zz_b2m_fsm_aggregate_bytesToSkipMask_5}}}}}}; + assign b2m_fsm_aggregate_memoryPort_ready = b2m_fsm_aggregate_engine_io_input_ready; + assign b2m_fsm_aggregate_engine_io_input_payload_mask = (b2m_fsm_aggregate_memoryPort_payload_mask & b2m_fsm_aggregate_bytesToSkipMask); + assign b2m_fsm_aggregate_engine_io_offset = b2m_fsm_sel_address[3:0]; + assign b2m_fsm_aggregate_engine_io_flush = (! _zz_io_flush); + assign b2m_fsm_cmd_maskFirstTrigger = b2m_fsm_sel_address[3:0]; + assign b2m_fsm_cmd_maskLastTriggerComb = (b2m_fsm_cmd_maskFirstTrigger + _zz_b2m_fsm_cmd_maskLastTriggerComb); + assign b2m_fsm_cmd_maskFirst = {(b2m_fsm_cmd_maskFirstTrigger <= 4'b1111),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1110),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1101),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1100),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1011),{(b2m_fsm_cmd_maskFirstTrigger <= _zz_b2m_fsm_cmd_maskFirst),{_zz_b2m_fsm_cmd_maskFirst_1,{_zz_b2m_fsm_cmd_maskFirst_2,_zz_b2m_fsm_cmd_maskFirst_3}}}}}}}}; + assign b2m_fsm_cmd_enoughAggregation = (((b2m_fsm_s2 && b2m_fsm_sel_valid) && (! b2m_fsm_aggregate_engine_io_flush)) && (io_write_cmd_payload_last ? ((b2m_fsm_aggregate_engine_io_output_mask & b2m_fsm_cmd_maskLast) == b2m_fsm_cmd_maskLast) : (&b2m_fsm_aggregate_engine_io_output_mask))); + assign io_write_cmd_fire = (io_write_cmd_valid && io_write_cmd_ready); + assign io_write_cmd_valid = b2m_fsm_cmd_enoughAggregation; + assign io_write_cmd_payload_last = (b2m_fsm_beatCounter == 8'h0); + assign io_write_cmd_payload_fragment_address = b2m_fsm_sel_address; + assign io_write_cmd_payload_fragment_opcode = 1'b1; + assign io_write_cmd_payload_fragment_data = b2m_fsm_aggregate_engine_io_output_data; + assign io_write_cmd_payload_fragment_mask = (~ ((io_write_cmd_payload_first ? (~ b2m_fsm_cmd_maskFirst) : 16'h0) | (io_write_cmd_payload_last ? (~ b2m_fsm_cmd_maskLast) : 16'h0))); + assign io_write_cmd_payload_fragment_length = b2m_fsm_sel_bytesInBurst; + assign b2m_fsm_cmd_doPtrIncr = (b2m_fsm_sel_valid && (b2m_fsm_aggregate_engine_io_output_consumed || ((io_write_cmd_fire && io_write_cmd_payload_last) && (b2m_fsm_aggregate_engine_io_output_usedUntil == 4'b1111)))); + assign b2m_fsm_cmd_context_length = b2m_fsm_sel_bytesInBurst; + assign b2m_fsm_cmd_context_doPacketSync = (b2m_fsm_sel_packet && b2m_fsm_fifoCompletion); + assign io_write_cmd_payload_fragment_context = {b2m_fsm_cmd_context_doPacketSync,b2m_fsm_cmd_context_length}; + assign when_DmaSg_l1102 = (io_write_cmd_fire && io_write_cmd_payload_last); + assign io_write_rsp_ready = 1'b1; + assign _zz_b2m_rsp_context_length = io_write_rsp_payload_fragment_context; + assign b2m_rsp_context_length = _zz_b2m_rsp_context_length[11 : 0]; + assign b2m_rsp_context_doPacketSync = _zz_b2m_rsp_context_length[12]; + assign io_write_rsp_fire = (io_write_rsp_valid && io_write_rsp_ready); + assign when_DmaSg_l1116 = 1'b1; + assign _zz_ll_arbiter_head = {channels_1_ll_requestLl,channels_0_ll_requestLl}; + assign _zz_ll_arbiter_head_1 = _zz__zz_ll_arbiter_head_1[1]; + assign ll_arbiter_head = (_zz_ll_arbiter_head_2[0] ? channels_0_ll_head : channels_1_ll_head); + assign ll_arbiter_isJustASink = (_zz_ll_arbiter_isJustASink[0] ? channels_0_descriptorValid : channels_1_descriptorValid); + assign ll_arbiter_doDescriptorStall = (_zz_ll_arbiter_doDescriptorStall[0] ? ((! channels_0_ll_controlNoCompletion) || channels_0_ll_gotDescriptorStall) : ((! channels_1_ll_controlNoCompletion) || channels_1_ll_gotDescriptorStall)); + assign ll_arbiter_onSgStream = (_zz_ll_arbiter_onSgStream[0] ? channels_0_ll_onSgStream : channels_1_ll_onSgStream); + assign when_DmaSg_l1149 = (! ll_cmd_valid); + assign when_DmaSg_l1148 = (! ll_cmd_valid); + assign when_DmaSg_l1148_1 = (! ll_cmd_valid); + assign when_DmaSg_l1148_2 = (! ll_cmd_valid); + assign when_DmaSg_l1148_3 = (! ll_cmd_valid); + assign when_DmaSg_l1154 = (! ll_cmd_valid); + assign when_DmaSg_l1155 = (! ll_cmd_valid); + assign when_DmaSg_l1156 = (! ll_cmd_valid); + assign when_DmaSg_l1160 = (! ll_cmd_valid); + assign when_DmaSg_l1161 = (|{_zz_ll_arbiter_head_1,channels_0_ll_requestLl}); + assign when_DmaSg_l1169 = (! ll_arbiter_isJustASink); + assign when_DmaSg_l1169_1 = (! ll_arbiter_isJustASink); + assign when_DmaSg_l1177 = (ll_cmd_writeFired && ll_cmd_readFired); + assign ll_cmd_context_channel = ll_cmd_oh_1; + assign io_sgRead_cmd_valid = ((ll_cmd_valid && (! ll_cmd_readFired)) && (! ll_cmd_onSgStream)); + assign io_sgRead_cmd_payload_last = 1'b1; + assign io_sgRead_cmd_payload_fragment_address = {ll_cmd_ptrNext[31 : 5],5'h0}; + assign io_sgRead_cmd_payload_fragment_length = 5'h1f; + assign io_sgRead_cmd_payload_fragment_opcode = 1'b0; + assign io_sgRead_cmd_payload_fragment_context = ll_cmd_context_channel; + assign io_sgWrite_cmd_valid = ((ll_cmd_valid && (! ll_cmd_writeFired)) && (! ll_cmd_onSgStream)); + assign io_sgWrite_cmd_payload_last = 1'b1; + assign io_sgWrite_cmd_payload_fragment_address = {ll_cmd_ptr[31 : 5],5'h0}; + assign io_sgWrite_cmd_payload_fragment_length = 2'b11; + assign io_sgWrite_cmd_payload_fragment_opcode = 1'b1; + assign io_sgWrite_cmd_payload_fragment_context = ll_cmd_context_channel; + assign ll_cmd_writeMaskSplit_0 = io_sgWrite_cmd_payload_fragment_mask[3 : 0]; + assign ll_cmd_writeMaskSplit_1 = io_sgWrite_cmd_payload_fragment_mask[7 : 4]; + assign ll_cmd_writeMaskSplit_2 = io_sgWrite_cmd_payload_fragment_mask[11 : 8]; + assign ll_cmd_writeMaskSplit_3 = io_sgWrite_cmd_payload_fragment_mask[15 : 12]; + assign ll_cmd_writeDataSplit_0 = io_sgWrite_cmd_payload_fragment_data[31 : 0]; + assign ll_cmd_writeDataSplit_1 = io_sgWrite_cmd_payload_fragment_data[63 : 32]; + assign ll_cmd_writeDataSplit_2 = io_sgWrite_cmd_payload_fragment_data[95 : 64]; + assign ll_cmd_writeDataSplit_3 = io_sgWrite_cmd_payload_fragment_data[127 : 96]; + assign _zz_1 = zz_io_sgWrite_cmd_payload_fragment_mask(1'b0); + always @(*) io_sgWrite_cmd_payload_fragment_mask = _zz_1; + always @(*) begin + io_sgWrite_cmd_payload_fragment_data[63 : 32] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + io_sgWrite_cmd_payload_fragment_data[95 : 64] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + io_sgWrite_cmd_payload_fragment_data[127 : 96] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + io_sgWrite_cmd_payload_fragment_data[31 : 0] = 32'h0; + io_sgWrite_cmd_payload_fragment_data[26 : 0] = ll_cmd_bytesDone; + io_sgWrite_cmd_payload_fragment_data[30] = ll_cmd_endOfPacket; + io_sgWrite_cmd_payload_fragment_data[31] = ((! ll_cmd_isJustASink) && ll_cmd_doDescriptorStall); + end + + assign io_sgRead_cmd_fire = (io_sgRead_cmd_valid && io_sgRead_cmd_ready); + assign io_sgWrite_cmd_fire = (io_sgWrite_cmd_valid && io_sgWrite_cmd_ready); + assign ll_readRsp_context_channel = io_sgRead_rsp_payload_fragment_context[0 : 0]; + assign _zz_ll_readRsp_oh_0 = (2'b01 <<< ll_readRsp_context_channel); + assign ll_readRsp_oh_0 = _zz_ll_readRsp_oh_0[0]; + assign ll_readRsp_oh_1 = _zz_ll_readRsp_oh_0[1]; + assign io_sgRead_rsp_ready = 1'b1; + assign io_sgRead_rsp_fire = (io_sgRead_rsp_valid && io_sgRead_rsp_ready); + assign when_DmaSg_l1248 = (1'b0 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_1 = (1'b1 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_2 = (1'b1 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_3 = (1'b0 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_4 = (1'b0 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_5 = (1'b0 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_6 = (1'b0 == ll_readRsp_beatCounter); + assign when_DmaSg_l1271 = (io_sgRead_rsp_fire && io_sgRead_rsp_payload_last); + assign ll_writeRsp_context_channel = io_sgWrite_rsp_payload_fragment_context[0 : 0]; + assign _zz_ll_writeRsp_oh_0 = (2'b01 <<< ll_writeRsp_context_channel); + assign ll_writeRsp_oh_0 = _zz_ll_writeRsp_oh_0[0]; + assign ll_writeRsp_oh_1 = _zz_ll_writeRsp_oh_0[1]; + assign io_sgWrite_rsp_ready = 1'b1; + assign io_sgWrite_rsp_fire = (io_sgWrite_rsp_valid && io_sgWrite_rsp_ready); + always @(*) begin + io_interrupts = 2'b00; + if(channels_0_interrupts_completion_valid) begin + io_interrupts[0] = 1'b1; + end + if(channels_0_interrupts_onChannelCompletion_valid) begin + io_interrupts[0] = 1'b1; + end + if(channels_0_interrupts_onLinkedListUpdate_valid) begin + io_interrupts[0] = 1'b1; + end + if(channels_0_interrupts_s2mPacket_valid) begin + io_interrupts[0] = 1'b1; + end + if(channels_1_interrupts_completion_valid) begin + io_interrupts[1] = 1'b1; + end + if(channels_1_interrupts_onChannelCompletion_valid) begin + io_interrupts[1] = 1'b1; + end + if(channels_1_interrupts_onLinkedListUpdate_valid) begin + io_interrupts[1] = 1'b1; + end + end + + always @(*) begin + when_BusSlaveFactory_l377 = 1'b0; + case(io_ctrl_PADDR) + 14'h002c : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l377_1 = 1'b0; + case(io_ctrl_PADDR) + 14'h002c : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_1 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l377_2 = 1'b0; + case(io_ctrl_PADDR) + 14'h002c : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_2 = io_ctrl_PWDATA[4]; + always @(*) begin + when_BusSlaveFactory_l377_3 = 1'b0; + case(io_ctrl_PADDR) + 14'h002c : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_3 = io_ctrl_PWDATA[4]; + always @(*) begin + when_BusSlaveFactory_l341 = 1'b0; + case(io_ctrl_PADDR) + 14'h0054 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l341_1 = 1'b0; + case(io_ctrl_PADDR) + 14'h0054 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_1 = io_ctrl_PWDATA[2]; + always @(*) begin + when_BusSlaveFactory_l341_2 = 1'b0; + case(io_ctrl_PADDR) + 14'h0054 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_2 = io_ctrl_PWDATA[3]; + always @(*) begin + when_BusSlaveFactory_l341_3 = 1'b0; + case(io_ctrl_PADDR) + 14'h0054 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_3 = io_ctrl_PWDATA[4]; + always @(*) begin + when_BusSlaveFactory_l377_4 = 1'b0; + case(io_ctrl_PADDR) + 14'h00ac : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_4 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_4 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l377_5 = 1'b0; + case(io_ctrl_PADDR) + 14'h00ac : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_5 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_5 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l377_6 = 1'b0; + case(io_ctrl_PADDR) + 14'h00ac : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_6 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_6 = io_ctrl_PWDATA[4]; + always @(*) begin + when_BusSlaveFactory_l377_7 = 1'b0; + case(io_ctrl_PADDR) + 14'h00ac : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_7 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_7 = io_ctrl_PWDATA[4]; + always @(*) begin + when_BusSlaveFactory_l341_4 = 1'b0; + case(io_ctrl_PADDR) + 14'h00d4 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_4 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_4 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l341_5 = 1'b0; + case(io_ctrl_PADDR) + 14'h00d4 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_5 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_5 = io_ctrl_PWDATA[2]; + always @(*) begin + when_BusSlaveFactory_l341_6 = 1'b0; + case(io_ctrl_PADDR) + 14'h00d4 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_6 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_6 = io_ctrl_PWDATA[3]; + assign when_Apb3SlaveFactory_l81 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h0010); + assign when_Apb3SlaveFactory_l81_1 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h0070); + assign when_Apb3SlaveFactory_l81_2 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h0080); + assign when_Apb3SlaveFactory_l81_3 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h00f0); + assign channels_0_fifo_push_ptrIncr_value = _zz_channels_0_fifo_push_ptrIncr_value; + assign channels_0_fifo_pop_bytesIncr_value = _zz_channels_0_fifo_pop_bytesIncr_value_1; + assign channels_0_fifo_pop_bytesDecr_value = channels_0_pop_b2m_decrBytes; + assign channels_0_fifo_pop_ptrIncr_value = _zz_channels_0_fifo_pop_ptrIncr_value; + assign channels_1_fifo_push_ptrIncr_value = _zz_channels_1_fifo_push_ptrIncr_value_1; + assign channels_1_fifo_pop_bytesIncr_value = _zz_channels_1_fifo_pop_bytesIncr_value_1; + assign channels_1_fifo_pop_bytesDecr_value = 14'h0; + assign channels_1_fifo_pop_ptrIncr_value = _zz_channels_1_fifo_pop_ptrIncr_value; + assign ll_0_descriptorUpdate = (channels_0_ll_descriptorUpdated && (! channels_0_ll_gotDescriptorStall)); + assign ll_1_descriptorUpdate = (channels_1_ll_descriptorUpdated && (! channels_1_ll_gotDescriptorStall)); + always @(posedge clk) begin + if(reset) begin + channels_0_channelValid <= 1'b0; + channels_0_descriptorValid <= 1'b0; + channels_0_priority <= 2'b00; + channels_0_weight <= 2'b00; + channels_0_ctrl_kick <= 1'b0; + channels_0_ll_valid <= 1'b0; + channels_0_ll_onSgStream <= 1'b0; + channels_0_pop_b2m_memPending <= 4'b0000; + channels_0_interrupts_completion_enable <= 1'b0; + channels_0_interrupts_completion_valid <= 1'b0; + channels_0_interrupts_onChannelCompletion_enable <= 1'b0; + channels_0_interrupts_onChannelCompletion_valid <= 1'b0; + channels_0_interrupts_onLinkedListUpdate_enable <= 1'b0; + channels_0_interrupts_onLinkedListUpdate_valid <= 1'b0; + channels_0_interrupts_s2mPacket_enable <= 1'b0; + channels_0_interrupts_s2mPacket_valid <= 1'b0; + channels_1_channelValid <= 1'b0; + channels_1_descriptorValid <= 1'b0; + channels_1_priority <= 2'b00; + channels_1_weight <= 2'b00; + channels_1_ctrl_kick <= 1'b0; + channels_1_ll_valid <= 1'b0; + channels_1_ll_onSgStream <= 1'b0; + channels_1_push_m2b_loadDone <= 1'b1; + channels_1_push_m2b_memPending <= 4'b0000; + channels_1_interrupts_completion_enable <= 1'b0; + channels_1_interrupts_completion_valid <= 1'b0; + channels_1_interrupts_onChannelCompletion_enable <= 1'b0; + channels_1_interrupts_onChannelCompletion_valid <= 1'b0; + channels_1_interrupts_onLinkedListUpdate_enable <= 1'b0; + channels_1_interrupts_onLinkedListUpdate_valid <= 1'b0; + io_inputs_0_payload_last_regNextWhen <= 1'b1; + io_inputs_0_payload_last_regNextWhen_1 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_2 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_3 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_4 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_5 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_6 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_7 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_8 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_9 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_10 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_11 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_12 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_13 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_14 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_15 <= 1'b1; + m2b_cmd_s0_valid <= 1'b0; + m2b_cmd_s0_priority_roundRobins_0 <= 1'b1; + m2b_cmd_s0_priority_roundRobins_1 <= 1'b1; + m2b_cmd_s0_priority_roundRobins_2 <= 1'b1; + m2b_cmd_s0_priority_roundRobins_3 <= 1'b1; + m2b_cmd_s0_priority_counter <= 2'b00; + m2b_cmd_s1_valid <= 1'b0; + m2b_rsp_first <= 1'b1; + b2m_fsm_sel_valid <= 1'b0; + b2m_fsm_arbiter_logic_valid <= 1'b0; + b2m_fsm_arbiter_logic_priority_roundRobins_0 <= 1'b1; + b2m_fsm_arbiter_logic_priority_roundRobins_1 <= 1'b1; + b2m_fsm_arbiter_logic_priority_roundRobins_2 <= 1'b1; + b2m_fsm_arbiter_logic_priority_roundRobins_3 <= 1'b1; + b2m_fsm_arbiter_logic_priority_counter <= 2'b00; + b2m_fsm_sel_valid_regNext <= 1'b0; + b2m_fsm_s1 <= 1'b0; + b2m_fsm_s2 <= 1'b0; + b2m_fsm_toggle <= 1'b0; + memory_core_io_reads_1_rsp_rValidN <= 1'b1; + _zz_io_flush <= 1'b0; + io_write_cmd_payload_first <= 1'b1; + ll_cmd_valid <= 1'b0; + ll_readRsp_beatCounter <= 1'b0; + end else begin + if(channels_0_channelStart) begin + channels_0_channelValid <= 1'b1; + end + if(channels_0_channelCompletion) begin + channels_0_channelValid <= 1'b0; + end + if(channels_0_descriptorStart) begin + channels_0_descriptorValid <= 1'b1; + end + if(channels_0_descriptorCompletion) begin + channels_0_descriptorValid <= 1'b0; + end + channels_0_ctrl_kick <= 1'b0; + if(channels_0_channelCompletion) begin + channels_0_ctrl_kick <= 1'b0; + end + if(when_DmaSg_l318) begin + if(when_DmaSg_l320) begin + if(!when_DmaSg_l322) begin + channels_0_ll_valid <= 1'b0; + end + end + end + if(channels_0_ll_sgStart) begin + channels_0_ll_valid <= 1'b1; + end + if(channels_0_channelCompletion) begin + channels_0_ll_valid <= 1'b0; + end + channels_0_pop_b2m_memPending <= (_zz_channels_0_pop_b2m_memPending - _zz_channels_0_pop_b2m_memPending_3); + if(when_DmaSg_l255) begin + channels_0_interrupts_completion_valid <= 1'b1; + end + if(when_DmaSg_l255_1) begin + channels_0_interrupts_completion_valid <= 1'b0; + end + if(when_DmaSg_l255_2) begin + channels_0_interrupts_onChannelCompletion_valid <= 1'b1; + end + if(when_DmaSg_l255_3) begin + channels_0_interrupts_onChannelCompletion_valid <= 1'b0; + end + if(channels_0_ll_descriptorUpdated) begin + channels_0_interrupts_onLinkedListUpdate_valid <= 1'b1; + end + if(when_DmaSg_l255_4) begin + channels_0_interrupts_onLinkedListUpdate_valid <= 1'b0; + end + if(channels_0_pop_b2m_packetSync) begin + channels_0_interrupts_s2mPacket_valid <= 1'b1; + end + if(when_DmaSg_l255_5) begin + channels_0_interrupts_s2mPacket_valid <= 1'b0; + end + if(channels_1_channelStart) begin + channels_1_channelValid <= 1'b1; + end + if(channels_1_channelCompletion) begin + channels_1_channelValid <= 1'b0; + end + if(channels_1_descriptorStart) begin + channels_1_descriptorValid <= 1'b1; + end + if(channels_1_descriptorCompletion) begin + channels_1_descriptorValid <= 1'b0; + end + channels_1_ctrl_kick <= 1'b0; + if(channels_1_channelCompletion) begin + channels_1_ctrl_kick <= 1'b0; + end + if(when_DmaSg_l318_1) begin + if(when_DmaSg_l320_1) begin + if(!when_DmaSg_l322_1) begin + channels_1_ll_valid <= 1'b0; + end + end + end + if(channels_1_ll_sgStart) begin + channels_1_ll_valid <= 1'b1; + end + if(channels_1_channelCompletion) begin + channels_1_ll_valid <= 1'b0; + end + channels_1_push_m2b_memPending <= (_zz_channels_1_push_m2b_memPending - _zz_channels_1_push_m2b_memPending_3); + if(channels_1_descriptorStart) begin + channels_1_push_m2b_loadDone <= 1'b0; + end + if(when_DmaSg_l255_6) begin + channels_1_interrupts_completion_valid <= 1'b1; + end + if(when_DmaSg_l255_7) begin + channels_1_interrupts_completion_valid <= 1'b0; + end + if(when_DmaSg_l255_8) begin + channels_1_interrupts_onChannelCompletion_valid <= 1'b1; + end + if(when_DmaSg_l255_9) begin + channels_1_interrupts_onChannelCompletion_valid <= 1'b0; + end + if(channels_1_ll_descriptorUpdated) begin + channels_1_interrupts_onLinkedListUpdate_valid <= 1'b1; + end + if(when_DmaSg_l255_10) begin + channels_1_interrupts_onLinkedListUpdate_valid <= 1'b0; + end + if(when_package_l12) begin + io_inputs_0_payload_last_regNextWhen <= io_inputs_0_payload_last; + end + if(when_package_l12_1) begin + io_inputs_0_payload_last_regNextWhen_1 <= io_inputs_0_payload_last; + end + if(when_package_l12_2) begin + io_inputs_0_payload_last_regNextWhen_2 <= io_inputs_0_payload_last; + end + if(when_package_l12_3) begin + io_inputs_0_payload_last_regNextWhen_3 <= io_inputs_0_payload_last; + end + if(when_package_l12_4) begin + io_inputs_0_payload_last_regNextWhen_4 <= io_inputs_0_payload_last; + end + if(when_package_l12_5) begin + io_inputs_0_payload_last_regNextWhen_5 <= io_inputs_0_payload_last; + end + if(when_package_l12_6) begin + io_inputs_0_payload_last_regNextWhen_6 <= io_inputs_0_payload_last; + end + if(when_package_l12_7) begin + io_inputs_0_payload_last_regNextWhen_7 <= io_inputs_0_payload_last; + end + if(when_package_l12_8) begin + io_inputs_0_payload_last_regNextWhen_8 <= io_inputs_0_payload_last; + end + if(when_package_l12_9) begin + io_inputs_0_payload_last_regNextWhen_9 <= io_inputs_0_payload_last; + end + if(when_package_l12_10) begin + io_inputs_0_payload_last_regNextWhen_10 <= io_inputs_0_payload_last; + end + if(when_package_l12_11) begin + io_inputs_0_payload_last_regNextWhen_11 <= io_inputs_0_payload_last; + end + if(when_package_l12_12) begin + io_inputs_0_payload_last_regNextWhen_12 <= io_inputs_0_payload_last; + end + if(when_package_l12_13) begin + io_inputs_0_payload_last_regNextWhen_13 <= io_inputs_0_payload_last; + end + if(when_package_l12_14) begin + io_inputs_0_payload_last_regNextWhen_14 <= io_inputs_0_payload_last; + end + if(when_package_l12_15) begin + io_inputs_0_payload_last_regNextWhen_15 <= io_inputs_0_payload_last; + end + if(when_DmaSg_l758) begin + if(when_DmaSg_l760) begin + m2b_cmd_s0_valid <= 1'b1; + if(when_DmaSg_l763) begin + m2b_cmd_s0_priority_roundRobins_0 <= m2b_cmd_s0_priority_contextNext; + end + if(when_DmaSg_l763_1) begin + m2b_cmd_s0_priority_roundRobins_1 <= m2b_cmd_s0_priority_contextNext; + end + if(when_DmaSg_l763_2) begin + m2b_cmd_s0_priority_roundRobins_2 <= m2b_cmd_s0_priority_contextNext; + end + if(when_DmaSg_l763_3) begin + m2b_cmd_s0_priority_roundRobins_3 <= m2b_cmd_s0_priority_contextNext; + end + m2b_cmd_s0_priority_counter <= (m2b_cmd_s0_priority_counter + 2'b01); + if(m2b_cmd_s0_priority_weightLast) begin + m2b_cmd_s0_priority_counter <= 2'b00; + end + end + end + if(m2b_cmd_s0_valid) begin + m2b_cmd_s1_valid <= 1'b1; + end + if(m2b_cmd_s1_valid) begin + if(io_read_cmd_ready) begin + m2b_cmd_s0_valid <= 1'b0; + m2b_cmd_s1_valid <= 1'b0; + if(when_DmaSg_l828) begin + if(m2b_cmd_s1_lastBurst) begin + channels_1_push_m2b_loadDone <= 1'b1; + end + end + end + end + if(io_read_rsp_fire) begin + m2b_rsp_first <= io_read_rsp_payload_last; + end + if(when_DmaSg_l758_1) begin + if(when_DmaSg_l760_1) begin + b2m_fsm_arbiter_logic_valid <= 1'b1; + if(when_DmaSg_l763_4) begin + b2m_fsm_arbiter_logic_priority_roundRobins_0 <= b2m_fsm_arbiter_logic_priority_contextNext; + end + if(when_DmaSg_l763_5) begin + b2m_fsm_arbiter_logic_priority_roundRobins_1 <= b2m_fsm_arbiter_logic_priority_contextNext; + end + if(when_DmaSg_l763_6) begin + b2m_fsm_arbiter_logic_priority_roundRobins_2 <= b2m_fsm_arbiter_logic_priority_contextNext; + end + if(when_DmaSg_l763_7) begin + b2m_fsm_arbiter_logic_priority_roundRobins_3 <= b2m_fsm_arbiter_logic_priority_contextNext; + end + b2m_fsm_arbiter_logic_priority_counter <= (b2m_fsm_arbiter_logic_priority_counter + 2'b01); + if(b2m_fsm_arbiter_logic_priority_weightLast) begin + b2m_fsm_arbiter_logic_priority_counter <= 2'b00; + end + end + end + if(b2m_fsm_sel_ready) begin + b2m_fsm_sel_valid <= 1'b0; + if(b2m_fsm_sel_valid) begin + b2m_fsm_arbiter_logic_valid <= 1'b0; + end + end + if(when_DmaSg_l935) begin + b2m_fsm_sel_valid <= 1'b1; + end + b2m_fsm_sel_valid_regNext <= b2m_fsm_sel_valid; + b2m_fsm_s1 <= b2m_fsm_s0; + if(b2m_fsm_s1) begin + b2m_fsm_s2 <= 1'b1; + end + if(when_DmaSg_l986) begin + b2m_fsm_s2 <= 1'b0; + end + if(when_DmaSg_l1013) begin + b2m_fsm_toggle <= (! b2m_fsm_toggle); + end + if(memory_core_io_reads_1_rsp_valid) begin + memory_core_io_reads_1_rsp_rValidN <= 1'b0; + end + if(memory_core_io_reads_1_rsp_s2mPipe_ready) begin + memory_core_io_reads_1_rsp_rValidN <= 1'b1; + end + _zz_io_flush <= (b2m_fsm_sel_valid && (! b2m_fsm_sel_ready)); + if(io_write_cmd_fire) begin + io_write_cmd_payload_first <= io_write_cmd_payload_last; + end + if(when_DmaSg_l1160) begin + if(when_DmaSg_l1161) begin + ll_cmd_valid <= 1'b1; + end + end else begin + if(when_DmaSg_l1177) begin + ll_cmd_valid <= 1'b0; + end + end + if(io_sgRead_rsp_fire) begin + ll_readRsp_beatCounter <= (ll_readRsp_beatCounter + 1'b1); + end + if(when_BusSlaveFactory_l377_1) begin + if(when_BusSlaveFactory_l379_1) begin + channels_0_ctrl_kick <= _zz_channels_0_ctrl_kick[0]; + end + end + if(when_BusSlaveFactory_l341) begin + if(when_BusSlaveFactory_l347) begin + channels_0_interrupts_completion_valid <= _zz_channels_0_interrupts_completion_valid[0]; + end + end + if(when_BusSlaveFactory_l341_1) begin + if(when_BusSlaveFactory_l347_1) begin + channels_0_interrupts_onChannelCompletion_valid <= _zz_channels_0_interrupts_onChannelCompletion_valid[0]; + end + end + if(when_BusSlaveFactory_l341_2) begin + if(when_BusSlaveFactory_l347_2) begin + channels_0_interrupts_onLinkedListUpdate_valid <= _zz_channels_0_interrupts_onLinkedListUpdate_valid[0]; + end + end + if(when_BusSlaveFactory_l341_3) begin + if(when_BusSlaveFactory_l347_3) begin + channels_0_interrupts_s2mPacket_valid <= _zz_channels_0_interrupts_s2mPacket_valid[0]; + end + end + if(when_BusSlaveFactory_l377_5) begin + if(when_BusSlaveFactory_l379_5) begin + channels_1_ctrl_kick <= _zz_channels_1_ctrl_kick[0]; + end + end + if(when_BusSlaveFactory_l341_4) begin + if(when_BusSlaveFactory_l347_4) begin + channels_1_interrupts_completion_valid <= _zz_channels_1_interrupts_completion_valid[0]; + end + end + if(when_BusSlaveFactory_l341_5) begin + if(when_BusSlaveFactory_l347_5) begin + channels_1_interrupts_onChannelCompletion_valid <= _zz_channels_1_interrupts_onChannelCompletion_valid[0]; + end + end + if(when_BusSlaveFactory_l341_6) begin + if(when_BusSlaveFactory_l347_6) begin + channels_1_interrupts_onLinkedListUpdate_valid <= _zz_channels_1_interrupts_onLinkedListUpdate_valid[0]; + end + end + case(io_ctrl_PADDR) + 14'h0078 : begin + if(ctrl_doWrite) begin + channels_0_ll_onSgStream <= io_ctrl_PWDATA[0]; + end + end + 14'h0044 : begin + if(ctrl_doWrite) begin + channels_0_priority <= io_ctrl_PWDATA[1 : 0]; + channels_0_weight <= io_ctrl_PWDATA[9 : 8]; + end + end + 14'h0050 : begin + if(ctrl_doWrite) begin + channels_0_interrupts_completion_enable <= io_ctrl_PWDATA[0]; + channels_0_interrupts_onChannelCompletion_enable <= io_ctrl_PWDATA[2]; + channels_0_interrupts_onLinkedListUpdate_enable <= io_ctrl_PWDATA[3]; + channels_0_interrupts_s2mPacket_enable <= io_ctrl_PWDATA[4]; + end + end + 14'h00f8 : begin + if(ctrl_doWrite) begin + channels_1_ll_onSgStream <= io_ctrl_PWDATA[0]; + end + end + 14'h00c4 : begin + if(ctrl_doWrite) begin + channels_1_priority <= io_ctrl_PWDATA[1 : 0]; + channels_1_weight <= io_ctrl_PWDATA[9 : 8]; + end + end + 14'h00d0 : begin + if(ctrl_doWrite) begin + channels_1_interrupts_completion_enable <= io_ctrl_PWDATA[0]; + channels_1_interrupts_onChannelCompletion_enable <= io_ctrl_PWDATA[2]; + channels_1_interrupts_onLinkedListUpdate_enable <= io_ctrl_PWDATA[3]; + end + end + default : begin + end + endcase + end + end + + always @(posedge clk) begin + if(channels_0_bytesProbe_incr_valid) begin + channels_0_bytesProbe_value <= (_zz_channels_0_bytesProbe_value + 27'h0000001); + end + if(channels_0_descriptorStart) begin + channels_0_ll_packet <= 1'b0; + end + if(channels_0_descriptorStart) begin + channels_0_ll_requireSync <= 1'b0; + end + if(when_DmaSg_l318) begin + channels_0_ll_waitDone <= 1'b0; + if(when_DmaSg_l320) begin + channels_0_ll_head <= 1'b0; + end + end + if(channels_0_channelStart) begin + channels_0_ll_waitDone <= 1'b0; + channels_0_ll_head <= 1'b1; + end + channels_0_fifo_push_ptr <= (channels_0_fifo_push_ptr + channels_0_fifo_push_ptrIncr_value); + if(channels_0_channelStart) begin + channels_0_fifo_push_ptr <= 11'h0; + end + channels_0_fifo_pop_ptr <= (channels_0_fifo_pop_ptr + channels_0_fifo_pop_ptrIncr_value); + channels_0_fifo_pop_withOverride_backup <= channels_0_fifo_pop_withOverride_backupNext; + if(when_DmaSg_l409) begin + channels_0_fifo_pop_withOverride_valid <= 1'b0; + end + if(channels_0_fifo_pop_withOverride_load) begin + channels_0_fifo_pop_withOverride_valid <= 1'b1; + end + channels_0_fifo_pop_withOverride_exposed <= ((! channels_0_fifo_pop_withOverride_valid) ? channels_0_fifo_pop_withOverride_backupNext : _zz_channels_0_fifo_pop_withOverride_exposed); + if(channels_0_channelStart) begin + channels_0_fifo_pop_withOverride_backup <= 14'h0; + channels_0_fifo_pop_withOverride_valid <= 1'b0; + end + if(channels_0_channelStart) begin + channels_0_push_s2b_packetLock <= 1'b0; + end + if(channels_0_pop_b2m_fire) begin + channels_0_pop_b2m_flush <= 1'b0; + end + if(when_DmaSg_l505) begin + channels_0_pop_b2m_packet <= 1'b0; + end + if(when_DmaSg_l523) begin + channels_0_pop_b2m_flush <= 1'b0; + channels_0_pop_b2m_packet <= 1'b0; + end + if(channels_0_pop_b2m_packetSync) begin + channels_0_push_s2b_packetLock <= 1'b0; + if(when_DmaSg_l532) begin + if(!channels_0_push_s2b_completionOnLast) begin + if(when_DmaSg_l536) begin + channels_0_ll_requireSync <= 1'b1; + end + end + channels_0_ll_packet <= 1'b1; + end + end + if(channels_0_channelStart) begin + channels_0_pop_b2m_bytesToSkip <= 4'b0000; + channels_0_pop_b2m_flush <= 1'b0; + end + if(channels_0_descriptorStart) begin + channels_0_pop_b2m_bytesLeft <= {1'd0, channels_0_bytes}; + channels_0_pop_b2m_waitFinalRsp <= 1'b0; + end + if(channels_0_channelValid) begin + if(!channels_0_channelStop) begin + if(when_DmaSg_l575) begin + if(when_DmaSg_l593) begin + channels_0_channelStop <= 1'b1; + end + end + end + end + channels_0_fifo_pop_ptrIncr_value_regNext <= channels_0_fifo_pop_ptrIncr_value; + channels_0_fifo_push_available <= (_zz_channels_0_fifo_push_available - (channels_0_push_memory ? channels_0_fifo_push_availableDecr : channels_0_fifo_push_ptrIncr_value)); + if(channels_0_channelStart) begin + channels_0_fifo_push_ptr <= 11'h0; + channels_0_fifo_push_available <= (channels_0_fifo_words + 11'h001); + channels_0_fifo_pop_ptr <= 11'h0; + end + if(when_DmaSg_l625) begin + channels_0_bytesProbe_value <= 27'h0; + end + if(channels_1_bytesProbe_incr_valid) begin + channels_1_bytesProbe_value <= (_zz_channels_1_bytesProbe_value + 27'h0000001); + end + if(channels_1_descriptorStart) begin + channels_1_ll_packet <= 1'b0; + end + if(channels_1_descriptorStart) begin + channels_1_ll_requireSync <= 1'b0; + end + if(when_DmaSg_l318_1) begin + channels_1_ll_waitDone <= 1'b0; + if(when_DmaSg_l320_1) begin + channels_1_ll_head <= 1'b0; + end + end + if(channels_1_channelStart) begin + channels_1_ll_waitDone <= 1'b0; + channels_1_ll_head <= 1'b1; + end + channels_1_fifo_push_ptr <= (channels_1_fifo_push_ptr + channels_1_fifo_push_ptrIncr_value); + if(channels_1_channelStart) begin + channels_1_fifo_push_ptr <= 11'h0; + end + channels_1_fifo_pop_ptr <= (channels_1_fifo_pop_ptr + channels_1_fifo_pop_ptrIncr_value); + channels_1_fifo_pop_withoutOverride_exposed <= (_zz_channels_1_fifo_pop_withoutOverride_exposed - channels_1_fifo_pop_bytesDecr_value); + if(channels_1_channelStart) begin + channels_1_fifo_pop_withoutOverride_exposed <= 14'h0; + end + if(channels_1_descriptorStart) begin + channels_1_push_m2b_bytesLeft <= channels_1_bytes; + end + if(when_DmaSg_l474) begin + channels_1_pop_b2s_veryLastValid <= 1'b1; + end + if(channels_1_pop_b2s_veryLastTrigger) begin + channels_1_pop_b2s_veryLastPtr <= channels_1_fifo_push_ptrWithBase; + channels_1_pop_b2s_veryLastEndPacket <= channels_1_pop_b2s_last; + end + if(channels_1_channelStart) begin + channels_1_pop_b2s_veryLastValid <= 1'b0; + end + if(channels_1_channelValid) begin + if(!channels_1_channelStop) begin + if(when_DmaSg_l575_1) begin + if(when_DmaSg_l593_1) begin + channels_1_channelStop <= 1'b1; + end + end + end + end + channels_1_fifo_pop_ptrIncr_value_regNext <= channels_1_fifo_pop_ptrIncr_value; + channels_1_fifo_push_available <= (_zz_channels_1_fifo_push_available - (channels_1_push_memory ? channels_1_fifo_push_availableDecr : channels_1_fifo_push_ptrIncr_value)); + if(channels_1_channelStart) begin + channels_1_fifo_push_ptr <= 11'h0; + channels_1_fifo_push_available <= (channels_1_fifo_words + 11'h001); + channels_1_fifo_pop_ptr <= 11'h0; + end + if(when_DmaSg_l625_1) begin + channels_1_bytesProbe_value <= 27'h0; + end + if(when_DmaSg_l665) begin + channels_0_push_s2b_waitFirst <= 1'b0; + if(io_inputs_0_payload_last) begin + channels_0_push_s2b_packetLock <= 1'b1; + end + end + if(when_DmaSg_l681) begin + channels_0_pop_b2m_flush <= 1'b1; + end + if(when_DmaSg_l682) begin + channels_0_pop_b2m_packet <= 1'b1; + end + if(when_DmaSg_l725) begin + if(when_DmaSg_l726) begin + channels_1_pop_b2s_veryLastValid <= 1'b0; + end + end + m2b_cmd_s1_address <= m2b_cmd_s0_address; + m2b_cmd_s1_length <= m2b_cmd_s0_length; + m2b_cmd_s1_lastBurst <= m2b_cmd_s0_lastBurst; + m2b_cmd_s1_bytesLeft <= m2b_cmd_s0_bytesLeft; + if(m2b_cmd_s1_valid) begin + if(io_read_cmd_ready) begin + if(when_DmaSg_l828) begin + channels_1_push_m2b_address <= m2b_cmd_s1_addressNext; + channels_1_push_m2b_bytesLeft <= m2b_cmd_s1_byteLeftNext; + end + end + end + if(when_DmaSg_l935) begin + b2m_fsm_sel_address <= channels_0_pop_b2m_address; + b2m_fsm_sel_ptr <= channels_0_fifo_pop_ptrWithBase; + b2m_fsm_sel_ptrMask <= channels_0_fifo_words; + b2m_fsm_sel_bytePerBurst <= channels_0_pop_b2m_bytePerBurst; + b2m_fsm_sel_bytesInFifo <= channels_0_fifo_pop_bytes; + b2m_fsm_sel_flush <= channels_0_pop_b2m_flush; + b2m_fsm_sel_packet <= channels_0_pop_b2m_packet; + b2m_fsm_sel_bytesLeft <= channels_0_pop_b2m_bytesLeft[25:0]; + end + if(b2m_fsm_s0) begin + b2m_fsm_sel_bytesInBurst <= _zz_b2m_fsm_sel_bytesInBurst_3[11:0]; + end + if(b2m_fsm_s1) begin + b2m_fsm_beatCounter <= (_zz_b2m_fsm_beatCounter >>> 3'd4); + if(when_DmaSg_l996) begin + channels_0_pop_b2m_address <= b2m_fsm_addressNext; + channels_0_pop_b2m_bytesLeft <= b2m_fsm_bytesLeftNext; + if(b2m_fsm_isFinalCmd) begin + channels_0_pop_b2m_waitFinalRsp <= 1'b1; + end + if(when_DmaSg_l1001) begin + if(b2m_fsm_sel_flush) begin + channels_0_pop_b2m_flush <= 1'b1; + end + if(b2m_fsm_sel_packet) begin + channels_0_pop_b2m_packet <= 1'b1; + end + end + end + end + if(when_DmaSg_l1033) begin + b2m_fsm_sel_ptr <= ((b2m_fsm_sel_ptr & (~ b2m_fsm_sel_ptrMask)) | (_zz_b2m_fsm_sel_ptr & b2m_fsm_sel_ptrMask)); + end + if(memory_core_io_reads_1_rsp_rValidN) begin + memory_core_io_reads_1_rsp_rData_data <= memory_core_io_reads_1_rsp_payload_data; + memory_core_io_reads_1_rsp_rData_mask <= memory_core_io_reads_1_rsp_payload_mask; + memory_core_io_reads_1_rsp_rData_context <= memory_core_io_reads_1_rsp_payload_context; + end + if(b2m_fsm_aggregate_memoryPort_fire) begin + b2m_fsm_aggregate_first <= 1'b0; + end + if(when_DmaSg_l1050) begin + b2m_fsm_aggregate_first <= 1'b1; + end + b2m_fsm_cmd_maskLastTriggerReg <= b2m_fsm_cmd_maskLastTriggerComb; + b2m_fsm_cmd_maskLast <= {(4'b1111 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1110 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1101 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1100 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1011 <= b2m_fsm_cmd_maskLastTriggerComb),{(_zz_b2m_fsm_cmd_maskLast <= b2m_fsm_cmd_maskLastTriggerComb),{_zz_b2m_fsm_cmd_maskLast_1,{_zz_b2m_fsm_cmd_maskLast_2,_zz_b2m_fsm_cmd_maskLast_3}}}}}}}}; + if(io_write_cmd_fire) begin + b2m_fsm_beatCounter <= (b2m_fsm_beatCounter - 8'h01); + end + if(when_DmaSg_l1102) begin + if(_zz_when_1[0]) begin + channels_0_pop_b2m_bytesToSkip <= (b2m_fsm_aggregate_engine_io_output_usedUntil + 4'b0001); + end + end + if(when_DmaSg_l1149) begin + ll_cmd_oh_0 <= channels_0_ll_requestLl; + ll_cmd_oh_1 <= _zz_ll_arbiter_head_1; + end + if(when_DmaSg_l1148) begin + ll_cmd_ptr <= (_zz_ll_cmd_ptr[0] ? channels_0_ll_ptr : channels_1_ll_ptr); + end + if(when_DmaSg_l1148_1) begin + ll_cmd_ptrNext <= (_zz_ll_cmd_ptrNext[0] ? channels_0_ll_ptrNext : channels_1_ll_ptrNext); + end + if(when_DmaSg_l1148_2) begin + ll_cmd_bytesDone <= channels_0_bytesProbe_value; + end + if(when_DmaSg_l1148_3) begin + ll_cmd_endOfPacket <= (_zz_ll_cmd_endOfPacket[0] ? channels_0_ll_packet : channels_1_ll_packet); + end + if(when_DmaSg_l1154) begin + ll_cmd_isJustASink <= ll_arbiter_isJustASink; + end + if(when_DmaSg_l1155) begin + ll_cmd_doDescriptorStall <= ll_arbiter_doDescriptorStall; + end + if(when_DmaSg_l1156) begin + ll_cmd_onSgStream <= ll_arbiter_onSgStream; + end + if(when_DmaSg_l1160) begin + ll_cmd_oh_0 <= channels_0_ll_requestLl; + ll_cmd_oh_1 <= _zz_ll_arbiter_head_1; + if(channels_0_ll_requestLl) begin + channels_0_ll_waitDone <= 1'b1; + channels_0_ll_writeDone <= ll_arbiter_head; + channels_0_ll_justASync <= ll_arbiter_isJustASink; + channels_0_ll_packet <= 1'b0; + channels_0_ll_requireSync <= 1'b0; + if(when_DmaSg_l1169) begin + channels_0_ll_ptr <= channels_0_ll_ptrNext; + end + channels_0_ll_readDone <= ll_arbiter_isJustASink; + end + if(_zz_ll_arbiter_head_1) begin + channels_1_ll_waitDone <= 1'b1; + channels_1_ll_writeDone <= ll_arbiter_head; + channels_1_ll_justASync <= ll_arbiter_isJustASink; + channels_1_ll_packet <= 1'b0; + channels_1_ll_requireSync <= 1'b0; + if(when_DmaSg_l1169_1) begin + channels_1_ll_ptr <= channels_1_ll_ptrNext; + end + channels_1_ll_readDone <= ll_arbiter_isJustASink; + end + ll_cmd_readFired <= ll_arbiter_isJustASink; + ll_cmd_writeFired <= ll_arbiter_head; + end + if(io_sgRead_cmd_fire) begin + ll_cmd_readFired <= 1'b1; + end + if(io_sgWrite_cmd_fire) begin + ll_cmd_writeFired <= 1'b1; + end + if(io_sgRead_rsp_fire) begin + if(when_DmaSg_l1248) begin + if(ll_readRsp_oh_1) begin + channels_1_push_m2b_address <= io_sgRead_rsp_payload_fragment_data[95 : 64]; + end + end + if(when_DmaSg_l1248_1) begin + if(ll_readRsp_oh_0) begin + channels_0_pop_b2m_address <= io_sgRead_rsp_payload_fragment_data[31 : 0]; + end + end + if(when_DmaSg_l1248_2) begin + if(ll_readRsp_oh_0) begin + channels_0_ll_ptrNext <= io_sgRead_rsp_payload_fragment_data[95 : 64]; + end + if(ll_readRsp_oh_1) begin + channels_1_ll_ptrNext <= io_sgRead_rsp_payload_fragment_data[95 : 64]; + end + end + if(when_DmaSg_l1248_3) begin + if(ll_readRsp_oh_0) begin + channels_0_bytes <= io_sgRead_rsp_payload_fragment_data[57 : 32]; + end + if(ll_readRsp_oh_1) begin + channels_1_bytes <= io_sgRead_rsp_payload_fragment_data[57 : 32]; + end + end + if(when_DmaSg_l1248_4) begin + if(ll_readRsp_oh_0) begin + channels_0_ll_controlNoCompletion <= io_sgRead_rsp_payload_fragment_data[63]; + end + if(ll_readRsp_oh_1) begin + channels_1_ll_controlNoCompletion <= io_sgRead_rsp_payload_fragment_data[63]; + end + end + if(when_DmaSg_l1248_5) begin + if(ll_readRsp_oh_1) begin + channels_1_pop_b2s_last <= io_sgRead_rsp_payload_fragment_data[62]; + end + end + if(when_DmaSg_l1248_6) begin + if(ll_readRsp_oh_0) begin + channels_0_ll_gotDescriptorStall <= io_sgRead_rsp_payload_fragment_data[31]; + end + if(ll_readRsp_oh_1) begin + channels_1_ll_gotDescriptorStall <= io_sgRead_rsp_payload_fragment_data[31]; + end + end + if(when_DmaSg_l1271) begin + if(ll_readRsp_oh_0) begin + channels_0_ll_readDone <= 1'b1; + end + if(ll_readRsp_oh_1) begin + channels_1_ll_readDone <= 1'b1; + end + end + end + if(io_sgWrite_rsp_fire) begin + if(ll_writeRsp_oh_0) begin + channels_0_ll_writeDone <= 1'b1; + end + if(ll_writeRsp_oh_1) begin + channels_1_ll_writeDone <= 1'b1; + end + end + case(io_ctrl_PADDR) + 14'h000c : begin + if(ctrl_doWrite) begin + channels_0_push_memory <= io_ctrl_PWDATA[12]; + channels_0_push_s2b_completionOnLast <= io_ctrl_PWDATA[13]; + channels_0_push_s2b_waitFirst <= io_ctrl_PWDATA[14]; + end + end + 14'h001c : begin + if(ctrl_doWrite) begin + channels_0_pop_memory <= io_ctrl_PWDATA[12]; + end + end + 14'h002c : begin + if(ctrl_doWrite) begin + channels_0_channelStop <= io_ctrl_PWDATA[2]; + end + end + 14'h0020 : begin + if(ctrl_doWrite) begin + channels_0_bytes <= io_ctrl_PWDATA[25 : 0]; + end + end + 14'h008c : begin + if(ctrl_doWrite) begin + channels_1_push_memory <= io_ctrl_PWDATA[12]; + end + end + 14'h0098 : begin + if(ctrl_doWrite) begin + channels_1_pop_b2s_sinkId <= io_ctrl_PWDATA[19 : 16]; + end + end + 14'h009c : begin + if(ctrl_doWrite) begin + channels_1_pop_memory <= io_ctrl_PWDATA[12]; + channels_1_pop_b2s_last <= io_ctrl_PWDATA[13]; + end + end + 14'h00ac : begin + if(ctrl_doWrite) begin + channels_1_channelStop <= io_ctrl_PWDATA[2]; + end + end + 14'h00a0 : begin + if(ctrl_doWrite) begin + channels_1_bytes <= io_ctrl_PWDATA[25 : 0]; + end + end + default : begin + end + endcase + if(when_Apb3SlaveFactory_l81) begin + if(ctrl_doWrite) begin + channels_0_pop_b2m_address[31 : 0] <= io_ctrl_PWDATA[31 : 0]; + end + end + if(when_Apb3SlaveFactory_l81_1) begin + if(ctrl_doWrite) begin + channels_0_ll_ptrNext[31 : 0] <= io_ctrl_PWDATA[31 : 0]; + end + end + if(when_Apb3SlaveFactory_l81_2) begin + if(ctrl_doWrite) begin + channels_1_push_m2b_address[31 : 0] <= io_ctrl_PWDATA[31 : 0]; + end + end + if(when_Apb3SlaveFactory_l81_3) begin + if(ctrl_doWrite) begin + channels_1_ll_ptrNext[31 : 0] <= io_ctrl_PWDATA[31 : 0]; + end + end + end + + +endmodule + +module EfxDMA_StreamArbiter_1_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_inputs_0_valid, + output wire io_inputs_0_ready, + input wire io_inputs_0_payload_last, + input wire [0:0] io_inputs_0_payload_fragment_source, + input wire [0:0] io_inputs_0_payload_fragment_opcode, + input wire [31:0] io_inputs_0_payload_fragment_address, + input wire [11:0] io_inputs_0_payload_fragment_length, + input wire [127:0] io_inputs_0_payload_fragment_data, + input wire [15:0] io_inputs_0_payload_fragment_mask, + input wire [12:0] io_inputs_0_payload_fragment_context, + input wire io_inputs_1_valid, + output wire io_inputs_1_ready, + input wire io_inputs_1_payload_last, + input wire [0:0] io_inputs_1_payload_fragment_source, + input wire [0:0] io_inputs_1_payload_fragment_opcode, + input wire [31:0] io_inputs_1_payload_fragment_address, + input wire [11:0] io_inputs_1_payload_fragment_length, + input wire [127:0] io_inputs_1_payload_fragment_data, + input wire [15:0] io_inputs_1_payload_fragment_mask, + input wire [12:0] io_inputs_1_payload_fragment_context, + output wire io_output_valid, + input wire io_output_ready, + output wire io_output_payload_last, + output wire [0:0] io_output_payload_fragment_source, + output wire [0:0] io_output_payload_fragment_opcode, + output wire [31:0] io_output_payload_fragment_address, + output wire [11:0] io_output_payload_fragment_length, + output wire [127:0] io_output_payload_fragment_data, + output wire [15:0] io_output_payload_fragment_mask, + output wire [12:0] io_output_payload_fragment_context, + output wire [0:0] io_chosen, + output wire [1:0] io_chosenOH, + input wire clk, + input wire reset +); + + wire [3:0] _zz__zz_maskProposal_0_2; + wire [3:0] _zz__zz_maskProposal_0_2_1; + wire [1:0] _zz__zz_maskProposal_0_2_2; + reg locked; + wire maskProposal_0; + wire maskProposal_1; + reg maskLocked_0; + reg maskLocked_1; + wire maskRouted_0; + wire maskRouted_1; + wire [1:0] _zz_maskProposal_0; + wire [3:0] _zz_maskProposal_0_1; + wire [3:0] _zz_maskProposal_0_2; + wire [1:0] _zz_maskProposal_0_3; + wire io_output_fire; + wire when_Stream_l683; + wire _zz_io_chosen; + + assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); + assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; + assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; + assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); + assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); + assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; + assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; + assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); + assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); + assign maskProposal_0 = _zz_maskProposal_0_3[0]; + assign maskProposal_1 = _zz_maskProposal_0_3[1]; + assign io_output_fire = (io_output_valid && io_output_ready); + assign when_Stream_l683 = (io_output_fire && io_output_payload_last); + assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); + assign io_output_payload_last = (maskRouted_0 ? io_inputs_0_payload_last : io_inputs_1_payload_last); + assign io_output_payload_fragment_source = (maskRouted_0 ? io_inputs_0_payload_fragment_source : io_inputs_1_payload_fragment_source); + assign io_output_payload_fragment_opcode = (maskRouted_0 ? io_inputs_0_payload_fragment_opcode : io_inputs_1_payload_fragment_opcode); + assign io_output_payload_fragment_address = (maskRouted_0 ? io_inputs_0_payload_fragment_address : io_inputs_1_payload_fragment_address); + assign io_output_payload_fragment_length = (maskRouted_0 ? io_inputs_0_payload_fragment_length : io_inputs_1_payload_fragment_length); + assign io_output_payload_fragment_data = (maskRouted_0 ? io_inputs_0_payload_fragment_data : io_inputs_1_payload_fragment_data); + assign io_output_payload_fragment_mask = (maskRouted_0 ? io_inputs_0_payload_fragment_mask : io_inputs_1_payload_fragment_mask); + assign io_output_payload_fragment_context = (maskRouted_0 ? io_inputs_0_payload_fragment_context : io_inputs_1_payload_fragment_context); + assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); + assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); + assign io_chosenOH = {maskRouted_1,maskRouted_0}; + assign _zz_io_chosen = io_chosenOH[1]; + assign io_chosen = _zz_io_chosen; + always @(posedge clk) begin + if(reset) begin + locked <= 1'b0; + maskLocked_0 <= 1'b0; + maskLocked_1 <= 1'b1; + end else begin + if(io_output_valid) begin + maskLocked_0 <= maskRouted_0; + maskLocked_1 <= maskRouted_1; + end + if(io_output_valid) begin + locked <= 1'b1; + end + if(when_Stream_l683) begin + locked <= 1'b0; + end + end + end + + +endmodule + +module EfxDMA_StreamArbiter_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_inputs_0_valid, + output wire io_inputs_0_ready, + input wire io_inputs_0_payload_last, + input wire [0:0] io_inputs_0_payload_fragment_source, + input wire [0:0] io_inputs_0_payload_fragment_opcode, + input wire [31:0] io_inputs_0_payload_fragment_address, + input wire [11:0] io_inputs_0_payload_fragment_length, + input wire [20:0] io_inputs_0_payload_fragment_context, + input wire io_inputs_1_valid, + output wire io_inputs_1_ready, + input wire io_inputs_1_payload_last, + input wire [0:0] io_inputs_1_payload_fragment_source, + input wire [0:0] io_inputs_1_payload_fragment_opcode, + input wire [31:0] io_inputs_1_payload_fragment_address, + input wire [11:0] io_inputs_1_payload_fragment_length, + input wire [20:0] io_inputs_1_payload_fragment_context, + output wire io_output_valid, + input wire io_output_ready, + output wire io_output_payload_last, + output wire [0:0] io_output_payload_fragment_source, + output wire [0:0] io_output_payload_fragment_opcode, + output wire [31:0] io_output_payload_fragment_address, + output wire [11:0] io_output_payload_fragment_length, + output wire [20:0] io_output_payload_fragment_context, + output wire [0:0] io_chosen, + output wire [1:0] io_chosenOH, + input wire clk, + input wire reset +); + + wire [3:0] _zz__zz_maskProposal_0_2; + wire [3:0] _zz__zz_maskProposal_0_2_1; + wire [1:0] _zz__zz_maskProposal_0_2_2; + reg locked; + wire maskProposal_0; + wire maskProposal_1; + reg maskLocked_0; + reg maskLocked_1; + wire maskRouted_0; + wire maskRouted_1; + wire [1:0] _zz_maskProposal_0; + wire [3:0] _zz_maskProposal_0_1; + wire [3:0] _zz_maskProposal_0_2; + wire [1:0] _zz_maskProposal_0_3; + wire io_output_fire; + wire when_Stream_l683; + wire _zz_io_chosen; + + assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); + assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; + assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; + assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); + assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); + assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; + assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; + assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); + assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); + assign maskProposal_0 = _zz_maskProposal_0_3[0]; + assign maskProposal_1 = _zz_maskProposal_0_3[1]; + assign io_output_fire = (io_output_valid && io_output_ready); + assign when_Stream_l683 = (io_output_fire && io_output_payload_last); + assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); + assign io_output_payload_last = (maskRouted_0 ? io_inputs_0_payload_last : io_inputs_1_payload_last); + assign io_output_payload_fragment_source = (maskRouted_0 ? io_inputs_0_payload_fragment_source : io_inputs_1_payload_fragment_source); + assign io_output_payload_fragment_opcode = (maskRouted_0 ? io_inputs_0_payload_fragment_opcode : io_inputs_1_payload_fragment_opcode); + assign io_output_payload_fragment_address = (maskRouted_0 ? io_inputs_0_payload_fragment_address : io_inputs_1_payload_fragment_address); + assign io_output_payload_fragment_length = (maskRouted_0 ? io_inputs_0_payload_fragment_length : io_inputs_1_payload_fragment_length); + assign io_output_payload_fragment_context = (maskRouted_0 ? io_inputs_0_payload_fragment_context : io_inputs_1_payload_fragment_context); + assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); + assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); + assign io_chosenOH = {maskRouted_1,maskRouted_0}; + assign _zz_io_chosen = io_chosenOH[1]; + assign io_chosen = _zz_io_chosen; + always @(posedge clk) begin + if(reset) begin + locked <= 1'b0; + maskLocked_0 <= 1'b0; + maskLocked_1 <= 1'b1; + end else begin + if(io_output_valid) begin + maskLocked_0 <= maskRouted_0; + maskLocked_1 <= maskRouted_1; + end + if(io_output_valid) begin + locked <= 1'b1; + end + if(when_Stream_l683) begin + locked <= 1'b0; + end + end + end + + +endmodule + +module EfxDMA_BufferCC_5_a048ca8f51874147a1cd65d43e6523ef ( + input wire [4:0] io_dataIn, + output wire [4:0] io_dataOut, + input wire dat1_o_clk, + input wire dat1_o_reset +); + + (* async_reg = "true" *) reg [4:0] buffers_0; + (* async_reg = "true" *) reg [4:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge dat1_o_clk) begin + if(dat1_o_reset) begin + buffers_0 <= 5'h0; + buffers_1 <= 5'h0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +//EfxDMA_BufferCC_4 replaced by EfxDMA_BufferCC_3_a048ca8f51874147a1cd65d43e6523ef + +module EfxDMA_BufferCC_3_a048ca8f51874147a1cd65d43e6523ef ( + input wire [4:0] io_dataIn, + output wire [4:0] io_dataOut, + input wire clk, + input wire reset +); + + (* async_reg = "true" *) reg [4:0] buffers_0; + (* async_reg = "true" *) reg [4:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge clk) begin + if(reset) begin + buffers_0 <= 5'h0; + buffers_1 <= 5'h0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module EfxDMA_BufferCC_2_a048ca8f51874147a1cd65d43e6523ef ( + input wire [4:0] io_dataIn, + output wire [4:0] io_dataOut, + input wire dat0_i_clk, + input wire dat0_i_reset +); + + (* async_reg = "true" *) reg [4:0] buffers_0; + (* async_reg = "true" *) reg [4:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge dat0_i_clk) begin + if(dat0_i_reset) begin + buffers_0 <= 5'h0; + buffers_1 <= 5'h0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module EfxDMA_BmbContextRemover_1_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_input_cmd_valid, + output reg io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [127:0] io_input_cmd_payload_fragment_data, + input wire [15:0] io_input_cmd_payload_fragment_mask, + input wire [13:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [13:0] io_input_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + output wire [127:0] io_output_cmd_payload_fragment_data, + output wire [15:0] io_output_cmd_payload_fragment_mask, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire clk, + input wire reset +); + + reg fifoFork_thrown_translated_fifo_io_pop_ready; + wire fifoFork_thrown_translated_fifo_io_push_ready; + wire fifoFork_thrown_translated_fifo_io_pop_valid; + wire [13:0] fifoFork_thrown_translated_fifo_io_pop_payload_context; + wire [2:0] fifoFork_thrown_translated_fifo_io_occupancy; + wire [2:0] fifoFork_thrown_translated_fifo_io_availability; + wire fifoFork_valid; + reg fifoFork_ready; + wire fifoFork_payload_last; + wire [0:0] fifoFork_payload_fragment_opcode; + wire [31:0] fifoFork_payload_fragment_address; + wire [11:0] fifoFork_payload_fragment_length; + wire [127:0] fifoFork_payload_fragment_data; + wire [15:0] fifoFork_payload_fragment_mask; + wire [13:0] fifoFork_payload_fragment_context; + wire cmdFork_valid; + wire cmdFork_ready; + wire cmdFork_payload_last; + wire [0:0] cmdFork_payload_fragment_opcode; + wire [31:0] cmdFork_payload_fragment_address; + wire [11:0] cmdFork_payload_fragment_length; + wire [127:0] cmdFork_payload_fragment_data; + wire [15:0] cmdFork_payload_fragment_mask; + wire [13:0] cmdFork_payload_fragment_context; + reg io_input_cmd_fork2_logic_linkEnable_0; + reg io_input_cmd_fork2_logic_linkEnable_1; + wire when_Stream_l1063; + wire when_Stream_l1063_1; + wire fifoFork_fire; + wire cmdFork_fire; + wire [13:0] pushCtx_context; + reg fifoFork_payload_first; + wire when_Stream_l445; + reg fifoFork_thrown_valid; + wire fifoFork_thrown_ready; + wire fifoFork_thrown_payload_last; + wire [0:0] fifoFork_thrown_payload_fragment_opcode; + wire [31:0] fifoFork_thrown_payload_fragment_address; + wire [11:0] fifoFork_thrown_payload_fragment_length; + wire [127:0] fifoFork_thrown_payload_fragment_data; + wire [15:0] fifoFork_thrown_payload_fragment_mask; + wire [13:0] fifoFork_thrown_payload_fragment_context; + wire fifoFork_thrown_translated_valid; + wire fifoFork_thrown_translated_ready; + wire [13:0] fifoFork_thrown_translated_payload_context; + wire popCtx_valid; + wire popCtx_ready; + wire [13:0] popCtx_payload_context; + reg fifoFork_thrown_translated_fifo_io_pop_rValid; + reg [13:0] fifoFork_thrown_translated_fifo_io_pop_rData_context; + wire when_Stream_l375; + wire _zz_io_input_rsp_valid; + + EfxDMA_StreamFifo_1_a048ca8f51874147a1cd65d43e6523ef fifoFork_thrown_translated_fifo ( + .io_push_valid (fifoFork_thrown_translated_valid ), //i + .io_push_ready (fifoFork_thrown_translated_fifo_io_push_ready ), //o + .io_push_payload_context (fifoFork_thrown_translated_payload_context[13:0] ), //i + .io_pop_valid (fifoFork_thrown_translated_fifo_io_pop_valid ), //o + .io_pop_ready (fifoFork_thrown_translated_fifo_io_pop_ready ), //i + .io_pop_payload_context (fifoFork_thrown_translated_fifo_io_pop_payload_context[13:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (fifoFork_thrown_translated_fifo_io_occupancy[2:0] ), //o + .io_availability (fifoFork_thrown_translated_fifo_io_availability[2:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + io_input_cmd_ready = 1'b1; + if(when_Stream_l1063) begin + io_input_cmd_ready = 1'b0; + end + if(when_Stream_l1063_1) begin + io_input_cmd_ready = 1'b0; + end + end + + assign when_Stream_l1063 = ((! fifoFork_ready) && io_input_cmd_fork2_logic_linkEnable_0); + assign when_Stream_l1063_1 = ((! cmdFork_ready) && io_input_cmd_fork2_logic_linkEnable_1); + assign fifoFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_0); + assign fifoFork_payload_last = io_input_cmd_payload_last; + assign fifoFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign fifoFork_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign fifoFork_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign fifoFork_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign fifoFork_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign fifoFork_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign fifoFork_fire = (fifoFork_valid && fifoFork_ready); + assign cmdFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_1); + assign cmdFork_payload_last = io_input_cmd_payload_last; + assign cmdFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign cmdFork_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign cmdFork_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign cmdFork_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign cmdFork_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign cmdFork_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign cmdFork_fire = (cmdFork_valid && cmdFork_ready); + assign io_output_cmd_valid = cmdFork_valid; + assign cmdFork_ready = io_output_cmd_ready; + assign io_output_cmd_payload_last = cmdFork_payload_last; + assign io_output_cmd_payload_fragment_opcode = cmdFork_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = cmdFork_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = cmdFork_payload_fragment_length; + assign io_output_cmd_payload_fragment_data = cmdFork_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = cmdFork_payload_fragment_mask; + assign pushCtx_context = fifoFork_payload_fragment_context; + assign when_Stream_l445 = (! fifoFork_payload_first); + always @(*) begin + fifoFork_thrown_valid = fifoFork_valid; + if(when_Stream_l445) begin + fifoFork_thrown_valid = 1'b0; + end + end + + always @(*) begin + fifoFork_ready = fifoFork_thrown_ready; + if(when_Stream_l445) begin + fifoFork_ready = 1'b1; + end + end + + assign fifoFork_thrown_payload_last = fifoFork_payload_last; + assign fifoFork_thrown_payload_fragment_opcode = fifoFork_payload_fragment_opcode; + assign fifoFork_thrown_payload_fragment_address = fifoFork_payload_fragment_address; + assign fifoFork_thrown_payload_fragment_length = fifoFork_payload_fragment_length; + assign fifoFork_thrown_payload_fragment_data = fifoFork_payload_fragment_data; + assign fifoFork_thrown_payload_fragment_mask = fifoFork_payload_fragment_mask; + assign fifoFork_thrown_payload_fragment_context = fifoFork_payload_fragment_context; + assign fifoFork_thrown_translated_valid = fifoFork_thrown_valid; + assign fifoFork_thrown_ready = fifoFork_thrown_translated_ready; + assign fifoFork_thrown_translated_payload_context = pushCtx_context; + assign fifoFork_thrown_translated_ready = fifoFork_thrown_translated_fifo_io_push_ready; + always @(*) begin + fifoFork_thrown_translated_fifo_io_pop_ready = popCtx_ready; + if(when_Stream_l375) begin + fifoFork_thrown_translated_fifo_io_pop_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! popCtx_valid); + assign popCtx_valid = fifoFork_thrown_translated_fifo_io_pop_rValid; + assign popCtx_payload_context = fifoFork_thrown_translated_fifo_io_pop_rData_context; + assign popCtx_ready = ((io_output_rsp_valid && io_output_rsp_payload_last) && io_input_rsp_ready); + assign _zz_io_input_rsp_valid = (! (! popCtx_valid)); + assign io_output_rsp_ready = (io_input_rsp_ready && _zz_io_input_rsp_valid); + assign io_input_rsp_valid = (io_output_rsp_valid && _zz_io_input_rsp_valid); + assign io_input_rsp_payload_last = io_output_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_context = popCtx_payload_context; + always @(posedge clk) begin + if(reset) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; + fifoFork_payload_first <= 1'b1; + fifoFork_thrown_translated_fifo_io_pop_rValid <= 1'b0; + end else begin + if(fifoFork_fire) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdFork_fire) begin + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_cmd_ready) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; + end + if(fifoFork_fire) begin + fifoFork_payload_first <= fifoFork_payload_last; + end + if(fifoFork_thrown_translated_fifo_io_pop_ready) begin + fifoFork_thrown_translated_fifo_io_pop_rValid <= fifoFork_thrown_translated_fifo_io_pop_valid; + end + end + end + + always @(posedge clk) begin + if(fifoFork_thrown_translated_fifo_io_pop_ready) begin + fifoFork_thrown_translated_fifo_io_pop_rData_context <= fifoFork_thrown_translated_fifo_io_pop_payload_context; + end + end + + +endmodule + +module EfxDMA_BmbContextRemover_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_input_cmd_valid, + output reg io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [21:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [127:0] io_input_rsp_payload_fragment_data, + output wire [21:0] io_input_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [127:0] io_output_rsp_payload_fragment_data, + input wire clk, + input wire reset +); + + reg fifoFork_thrown_translated_fifo_io_pop_ready; + wire fifoFork_thrown_translated_fifo_io_push_ready; + wire fifoFork_thrown_translated_fifo_io_pop_valid; + wire [21:0] fifoFork_thrown_translated_fifo_io_pop_payload_context; + wire [2:0] fifoFork_thrown_translated_fifo_io_occupancy; + wire [2:0] fifoFork_thrown_translated_fifo_io_availability; + wire fifoFork_valid; + reg fifoFork_ready; + wire fifoFork_payload_last; + wire [0:0] fifoFork_payload_fragment_opcode; + wire [31:0] fifoFork_payload_fragment_address; + wire [11:0] fifoFork_payload_fragment_length; + wire [21:0] fifoFork_payload_fragment_context; + wire cmdFork_valid; + wire cmdFork_ready; + wire cmdFork_payload_last; + wire [0:0] cmdFork_payload_fragment_opcode; + wire [31:0] cmdFork_payload_fragment_address; + wire [11:0] cmdFork_payload_fragment_length; + wire [21:0] cmdFork_payload_fragment_context; + reg io_input_cmd_fork2_logic_linkEnable_0; + reg io_input_cmd_fork2_logic_linkEnable_1; + wire when_Stream_l1063; + wire when_Stream_l1063_1; + wire fifoFork_fire; + wire cmdFork_fire; + wire [21:0] pushCtx_context; + reg fifoFork_payload_first; + wire when_Stream_l445; + reg fifoFork_thrown_valid; + wire fifoFork_thrown_ready; + wire fifoFork_thrown_payload_last; + wire [0:0] fifoFork_thrown_payload_fragment_opcode; + wire [31:0] fifoFork_thrown_payload_fragment_address; + wire [11:0] fifoFork_thrown_payload_fragment_length; + wire [21:0] fifoFork_thrown_payload_fragment_context; + wire fifoFork_thrown_translated_valid; + wire fifoFork_thrown_translated_ready; + wire [21:0] fifoFork_thrown_translated_payload_context; + wire popCtx_valid; + wire popCtx_ready; + wire [21:0] popCtx_payload_context; + reg fifoFork_thrown_translated_fifo_io_pop_rValid; + reg [21:0] fifoFork_thrown_translated_fifo_io_pop_rData_context; + wire when_Stream_l375; + wire _zz_io_input_rsp_valid; + + EfxDMA_StreamFifo_a048ca8f51874147a1cd65d43e6523ef fifoFork_thrown_translated_fifo ( + .io_push_valid (fifoFork_thrown_translated_valid ), //i + .io_push_ready (fifoFork_thrown_translated_fifo_io_push_ready ), //o + .io_push_payload_context (fifoFork_thrown_translated_payload_context[21:0] ), //i + .io_pop_valid (fifoFork_thrown_translated_fifo_io_pop_valid ), //o + .io_pop_ready (fifoFork_thrown_translated_fifo_io_pop_ready ), //i + .io_pop_payload_context (fifoFork_thrown_translated_fifo_io_pop_payload_context[21:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (fifoFork_thrown_translated_fifo_io_occupancy[2:0] ), //o + .io_availability (fifoFork_thrown_translated_fifo_io_availability[2:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + io_input_cmd_ready = 1'b1; + if(when_Stream_l1063) begin + io_input_cmd_ready = 1'b0; + end + if(when_Stream_l1063_1) begin + io_input_cmd_ready = 1'b0; + end + end + + assign when_Stream_l1063 = ((! fifoFork_ready) && io_input_cmd_fork2_logic_linkEnable_0); + assign when_Stream_l1063_1 = ((! cmdFork_ready) && io_input_cmd_fork2_logic_linkEnable_1); + assign fifoFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_0); + assign fifoFork_payload_last = io_input_cmd_payload_last; + assign fifoFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign fifoFork_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign fifoFork_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign fifoFork_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign fifoFork_fire = (fifoFork_valid && fifoFork_ready); + assign cmdFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_1); + assign cmdFork_payload_last = io_input_cmd_payload_last; + assign cmdFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign cmdFork_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign cmdFork_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign cmdFork_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign cmdFork_fire = (cmdFork_valid && cmdFork_ready); + assign io_output_cmd_valid = cmdFork_valid; + assign cmdFork_ready = io_output_cmd_ready; + assign io_output_cmd_payload_last = cmdFork_payload_last; + assign io_output_cmd_payload_fragment_opcode = cmdFork_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = cmdFork_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = cmdFork_payload_fragment_length; + assign pushCtx_context = fifoFork_payload_fragment_context; + assign when_Stream_l445 = (! fifoFork_payload_first); + always @(*) begin + fifoFork_thrown_valid = fifoFork_valid; + if(when_Stream_l445) begin + fifoFork_thrown_valid = 1'b0; + end + end + + always @(*) begin + fifoFork_ready = fifoFork_thrown_ready; + if(when_Stream_l445) begin + fifoFork_ready = 1'b1; + end + end + + assign fifoFork_thrown_payload_last = fifoFork_payload_last; + assign fifoFork_thrown_payload_fragment_opcode = fifoFork_payload_fragment_opcode; + assign fifoFork_thrown_payload_fragment_address = fifoFork_payload_fragment_address; + assign fifoFork_thrown_payload_fragment_length = fifoFork_payload_fragment_length; + assign fifoFork_thrown_payload_fragment_context = fifoFork_payload_fragment_context; + assign fifoFork_thrown_translated_valid = fifoFork_thrown_valid; + assign fifoFork_thrown_ready = fifoFork_thrown_translated_ready; + assign fifoFork_thrown_translated_payload_context = pushCtx_context; + assign fifoFork_thrown_translated_ready = fifoFork_thrown_translated_fifo_io_push_ready; + always @(*) begin + fifoFork_thrown_translated_fifo_io_pop_ready = popCtx_ready; + if(when_Stream_l375) begin + fifoFork_thrown_translated_fifo_io_pop_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! popCtx_valid); + assign popCtx_valid = fifoFork_thrown_translated_fifo_io_pop_rValid; + assign popCtx_payload_context = fifoFork_thrown_translated_fifo_io_pop_rData_context; + assign popCtx_ready = ((io_output_rsp_valid && io_output_rsp_payload_last) && io_input_rsp_ready); + assign _zz_io_input_rsp_valid = (! (! popCtx_valid)); + assign io_output_rsp_ready = (io_input_rsp_ready && _zz_io_input_rsp_valid); + assign io_input_rsp_valid = (io_output_rsp_valid && _zz_io_input_rsp_valid); + assign io_input_rsp_payload_last = io_output_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = popCtx_payload_context; + always @(posedge clk) begin + if(reset) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; + fifoFork_payload_first <= 1'b1; + fifoFork_thrown_translated_fifo_io_pop_rValid <= 1'b0; + end else begin + if(fifoFork_fire) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdFork_fire) begin + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_cmd_ready) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; + end + if(fifoFork_fire) begin + fifoFork_payload_first <= fifoFork_payload_last; + end + if(fifoFork_thrown_translated_fifo_io_pop_ready) begin + fifoFork_thrown_translated_fifo_io_pop_rValid <= fifoFork_thrown_translated_fifo_io_pop_valid; + end + end + end + + always @(posedge clk) begin + if(fifoFork_thrown_translated_fifo_io_pop_ready) begin + fifoFork_thrown_translated_fifo_io_pop_rData_context <= fifoFork_thrown_translated_fifo_io_pop_payload_context; + end + end + + +endmodule + +module EfxDMA_FlowCCUnsafeByToggle_1_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_input_valid, + input wire [31:0] io_input_payload_PRDATA, + input wire io_input_payload_PSLVERROR, + output wire io_output_valid, + output wire [31:0] io_output_payload_PRDATA, + output wire io_output_payload_PSLVERROR, + input wire clk, + input wire reset, + input wire ctrl_clk, + input wire ctrl_reset +); + + wire inputArea_target_buffercc_io_dataOut; + reg inputArea_target; + reg [31:0] inputArea_data_PRDATA; + reg inputArea_data_PSLVERROR; + wire outputArea_target; + reg outputArea_hit; + wire outputArea_flow_valid; + wire [31:0] outputArea_flow_payload_PRDATA; + wire outputArea_flow_payload_PSLVERROR; + reg outputArea_flow_m2sPipe_valid; + (* async_reg = "true" *) reg [31:0] outputArea_flow_m2sPipe_payload_PRDATA; + (* async_reg = "true" *) reg outputArea_flow_m2sPipe_payload_PSLVERROR; + + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_1_a048ca8f51874147a1cd65d43e6523ef inputArea_target_buffercc ( + .io_dataIn (inputArea_target ), //i + .io_dataOut (inputArea_target_buffercc_io_dataOut), //o + .ctrl_clk (ctrl_clk ), //i + .ctrl_reset (ctrl_reset ) //i + ); + assign outputArea_target = inputArea_target_buffercc_io_dataOut; + assign outputArea_flow_valid = (outputArea_target != outputArea_hit); + assign outputArea_flow_payload_PRDATA = inputArea_data_PRDATA; + assign outputArea_flow_payload_PSLVERROR = inputArea_data_PSLVERROR; + assign io_output_valid = outputArea_flow_m2sPipe_valid; + assign io_output_payload_PRDATA = outputArea_flow_m2sPipe_payload_PRDATA; + assign io_output_payload_PSLVERROR = outputArea_flow_m2sPipe_payload_PSLVERROR; + always @(posedge clk) begin + if(reset) begin + inputArea_target <= 1'b0; + end else begin + if(io_input_valid) begin + inputArea_target <= (! inputArea_target); + end + end + end + + always @(posedge clk) begin + if(io_input_valid) begin + inputArea_data_PRDATA <= io_input_payload_PRDATA; + inputArea_data_PSLVERROR <= io_input_payload_PSLVERROR; + end + end + + always @(posedge ctrl_clk) begin + if(ctrl_reset) begin + outputArea_flow_m2sPipe_valid <= 1'b0; + outputArea_hit <= 1'b0; + end else begin + outputArea_hit <= outputArea_target; + outputArea_flow_m2sPipe_valid <= outputArea_flow_valid; + end + end + + always @(posedge ctrl_clk) begin + if(outputArea_flow_valid) begin + outputArea_flow_m2sPipe_payload_PRDATA <= outputArea_flow_payload_PRDATA; + outputArea_flow_m2sPipe_payload_PSLVERROR <= outputArea_flow_payload_PSLVERROR; + end + end + + +endmodule + +module EfxDMA_FlowCCUnsafeByToggle_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_input_valid, + input wire [13:0] io_input_payload_PADDR, + input wire io_input_payload_PWRITE, + input wire [31:0] io_input_payload_PWDATA, + output wire io_output_valid, + output wire [13:0] io_output_payload_PADDR, + output wire io_output_payload_PWRITE, + output wire [31:0] io_output_payload_PWDATA, + input wire ctrl_clk, + input wire ctrl_reset, + input wire clk, + input wire reset +); + + wire inputArea_target_buffercc_io_dataOut; + reg inputArea_target; + reg [13:0] inputArea_data_PADDR; + reg inputArea_data_PWRITE; + reg [31:0] inputArea_data_PWDATA; + wire outputArea_target; + reg outputArea_hit; + wire outputArea_flow_valid; + wire [13:0] outputArea_flow_payload_PADDR; + wire outputArea_flow_payload_PWRITE; + wire [31:0] outputArea_flow_payload_PWDATA; + + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_a048ca8f51874147a1cd65d43e6523ef inputArea_target_buffercc ( + .io_dataIn (inputArea_target ), //i + .io_dataOut (inputArea_target_buffercc_io_dataOut), //o + .clk (clk ), //i + .reset (reset ) //i + ); + assign outputArea_target = inputArea_target_buffercc_io_dataOut; + assign outputArea_flow_valid = (outputArea_target != outputArea_hit); + assign outputArea_flow_payload_PADDR = inputArea_data_PADDR; + assign outputArea_flow_payload_PWRITE = inputArea_data_PWRITE; + assign outputArea_flow_payload_PWDATA = inputArea_data_PWDATA; + assign io_output_valid = outputArea_flow_valid; + assign io_output_payload_PADDR = outputArea_flow_payload_PADDR; + assign io_output_payload_PWRITE = outputArea_flow_payload_PWRITE; + assign io_output_payload_PWDATA = outputArea_flow_payload_PWDATA; + always @(posedge ctrl_clk) begin + if(ctrl_reset) begin + inputArea_target <= 1'b0; + end else begin + if(io_input_valid) begin + inputArea_target <= (! inputArea_target); + end + end + end + + always @(posedge ctrl_clk) begin + if(io_input_valid) begin + inputArea_data_PADDR <= io_input_payload_PADDR; + inputArea_data_PWRITE <= io_input_payload_PWRITE; + inputArea_data_PWDATA <= io_input_payload_PWDATA; + end + end + + always @(posedge clk) begin + if(reset) begin + outputArea_hit <= 1'b0; + end else begin + outputArea_hit <= outputArea_target; + end + end + + +endmodule + +module EfxDMA_Aggregator_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_input_valid, + output reg io_input_ready, + input wire [127:0] io_input_payload_data, + input wire [15:0] io_input_payload_mask, + output reg [127:0] io_output_data, + output reg [15:0] io_output_mask, + input wire io_output_enough, + input wire io_output_consume, + output wire io_output_consumed, + input wire [3:0] io_output_lastByteUsed, + output wire [3:0] io_output_usedUntil, + input wire io_flush, + input wire [3:0] io_offset, + input wire [11:0] io_burstLength, + input wire clk, + input wire reset +); + + reg [0:0] _zz_s0_countOnesLogic_0_1; + wire [0:0] _zz_s0_countOnesLogic_0_2; + reg [1:0] _zz_s0_countOnesLogic_1_1; + wire [1:0] _zz_s0_countOnesLogic_1_2; + reg [1:0] _zz_s0_countOnesLogic_2_1; + wire [2:0] _zz_s0_countOnesLogic_2_2; + reg [2:0] _zz_s0_countOnesLogic_3_9; + wire [2:0] _zz_s0_countOnesLogic_3_10; + reg [2:0] _zz_s0_countOnesLogic_3_11; + wire [2:0] _zz_s0_countOnesLogic_3_12; + wire [0:0] _zz_s0_countOnesLogic_3_13; + reg [2:0] _zz_s0_countOnesLogic_4_9; + wire [2:0] _zz_s0_countOnesLogic_4_10; + reg [2:0] _zz_s0_countOnesLogic_4_11; + wire [2:0] _zz_s0_countOnesLogic_4_12; + wire [1:0] _zz_s0_countOnesLogic_4_13; + reg [2:0] _zz_s0_countOnesLogic_5_9; + wire [2:0] _zz_s0_countOnesLogic_5_10; + reg [2:0] _zz_s0_countOnesLogic_5_11; + wire [2:0] _zz_s0_countOnesLogic_5_12; + wire [2:0] _zz_s0_countOnesLogic_6_9; + reg [2:0] _zz_s0_countOnesLogic_6_10; + wire [2:0] _zz_s0_countOnesLogic_6_11; + reg [2:0] _zz_s0_countOnesLogic_6_12; + wire [2:0] _zz_s0_countOnesLogic_6_13; + reg [2:0] _zz_s0_countOnesLogic_6_14; + wire [2:0] _zz_s0_countOnesLogic_6_15; + wire [0:0] _zz_s0_countOnesLogic_6_16; + wire [3:0] _zz_s0_countOnesLogic_7_9; + reg [3:0] _zz_s0_countOnesLogic_7_10; + wire [2:0] _zz_s0_countOnesLogic_7_11; + reg [3:0] _zz_s0_countOnesLogic_7_12; + wire [2:0] _zz_s0_countOnesLogic_7_13; + reg [3:0] _zz_s0_countOnesLogic_7_14; + wire [2:0] _zz_s0_countOnesLogic_7_15; + wire [1:0] _zz_s0_countOnesLogic_7_16; + wire [3:0] _zz_s0_countOnesLogic_8_9; + reg [3:0] _zz_s0_countOnesLogic_8_10; + wire [2:0] _zz_s0_countOnesLogic_8_11; + reg [3:0] _zz_s0_countOnesLogic_8_12; + wire [2:0] _zz_s0_countOnesLogic_8_13; + reg [3:0] _zz_s0_countOnesLogic_8_14; + wire [2:0] _zz_s0_countOnesLogic_8_15; + wire [3:0] _zz_s0_countOnesLogic_9_9; + reg [3:0] _zz_s0_countOnesLogic_9_10; + wire [2:0] _zz_s0_countOnesLogic_9_11; + reg [3:0] _zz_s0_countOnesLogic_9_12; + wire [2:0] _zz_s0_countOnesLogic_9_13; + wire [3:0] _zz_s0_countOnesLogic_9_14; + reg [3:0] _zz_s0_countOnesLogic_9_15; + wire [2:0] _zz_s0_countOnesLogic_9_16; + reg [3:0] _zz_s0_countOnesLogic_9_17; + wire [2:0] _zz_s0_countOnesLogic_9_18; + wire [0:0] _zz_s0_countOnesLogic_9_19; + wire [3:0] _zz_s0_countOnesLogic_10_9; + reg [3:0] _zz_s0_countOnesLogic_10_10; + wire [2:0] _zz_s0_countOnesLogic_10_11; + reg [3:0] _zz_s0_countOnesLogic_10_12; + wire [2:0] _zz_s0_countOnesLogic_10_13; + wire [3:0] _zz_s0_countOnesLogic_10_14; + reg [3:0] _zz_s0_countOnesLogic_10_15; + wire [2:0] _zz_s0_countOnesLogic_10_16; + reg [3:0] _zz_s0_countOnesLogic_10_17; + wire [2:0] _zz_s0_countOnesLogic_10_18; + wire [1:0] _zz_s0_countOnesLogic_10_19; + wire [3:0] _zz_s0_countOnesLogic_11_9; + reg [3:0] _zz_s0_countOnesLogic_11_10; + wire [2:0] _zz_s0_countOnesLogic_11_11; + reg [3:0] _zz_s0_countOnesLogic_11_12; + wire [2:0] _zz_s0_countOnesLogic_11_13; + wire [3:0] _zz_s0_countOnesLogic_11_14; + reg [3:0] _zz_s0_countOnesLogic_11_15; + wire [2:0] _zz_s0_countOnesLogic_11_16; + reg [3:0] _zz_s0_countOnesLogic_11_17; + wire [2:0] _zz_s0_countOnesLogic_11_18; + wire [3:0] _zz_s0_countOnesLogic_12_9; + wire [3:0] _zz_s0_countOnesLogic_12_10; + reg [3:0] _zz_s0_countOnesLogic_12_11; + wire [2:0] _zz_s0_countOnesLogic_12_12; + reg [3:0] _zz_s0_countOnesLogic_12_13; + wire [2:0] _zz_s0_countOnesLogic_12_14; + wire [3:0] _zz_s0_countOnesLogic_12_15; + reg [3:0] _zz_s0_countOnesLogic_12_16; + wire [2:0] _zz_s0_countOnesLogic_12_17; + reg [3:0] _zz_s0_countOnesLogic_12_18; + wire [2:0] _zz_s0_countOnesLogic_12_19; + reg [3:0] _zz_s0_countOnesLogic_12_20; + wire [2:0] _zz_s0_countOnesLogic_12_21; + wire [0:0] _zz_s0_countOnesLogic_12_22; + wire [3:0] _zz_s0_countOnesLogic_13_9; + wire [3:0] _zz_s0_countOnesLogic_13_10; + reg [3:0] _zz_s0_countOnesLogic_13_11; + wire [2:0] _zz_s0_countOnesLogic_13_12; + reg [3:0] _zz_s0_countOnesLogic_13_13; + wire [2:0] _zz_s0_countOnesLogic_13_14; + wire [3:0] _zz_s0_countOnesLogic_13_15; + reg [3:0] _zz_s0_countOnesLogic_13_16; + wire [2:0] _zz_s0_countOnesLogic_13_17; + reg [3:0] _zz_s0_countOnesLogic_13_18; + wire [2:0] _zz_s0_countOnesLogic_13_19; + reg [3:0] _zz_s0_countOnesLogic_13_20; + wire [2:0] _zz_s0_countOnesLogic_13_21; + wire [1:0] _zz_s0_countOnesLogic_13_22; + wire [3:0] _zz_s0_countOnesLogic_14_9; + wire [3:0] _zz_s0_countOnesLogic_14_10; + reg [3:0] _zz_s0_countOnesLogic_14_11; + wire [2:0] _zz_s0_countOnesLogic_14_12; + reg [3:0] _zz_s0_countOnesLogic_14_13; + wire [2:0] _zz_s0_countOnesLogic_14_14; + wire [3:0] _zz_s0_countOnesLogic_14_15; + reg [3:0] _zz_s0_countOnesLogic_14_16; + wire [2:0] _zz_s0_countOnesLogic_14_17; + reg [3:0] _zz_s0_countOnesLogic_14_18; + wire [2:0] _zz_s0_countOnesLogic_14_19; + reg [3:0] _zz_s0_countOnesLogic_14_20; + wire [2:0] _zz_s0_countOnesLogic_14_21; + wire [4:0] _zz_s0_countOnesLogic_15_8; + wire [4:0] _zz_s0_countOnesLogic_15_9; + reg [4:0] _zz_s0_countOnesLogic_15_10; + wire [2:0] _zz_s0_countOnesLogic_15_11; + reg [4:0] _zz_s0_countOnesLogic_15_12; + wire [2:0] _zz_s0_countOnesLogic_15_13; + wire [4:0] _zz_s0_countOnesLogic_15_14; + reg [4:0] _zz_s0_countOnesLogic_15_15; + wire [2:0] _zz_s0_countOnesLogic_15_16; + reg [4:0] _zz_s0_countOnesLogic_15_17; + wire [2:0] _zz_s0_countOnesLogic_15_18; + wire [4:0] _zz_s0_countOnesLogic_15_19; + reg [4:0] _zz_s0_countOnesLogic_15_20; + wire [2:0] _zz_s0_countOnesLogic_15_21; + reg [4:0] _zz_s0_countOnesLogic_15_22; + wire [2:0] _zz_s0_countOnesLogic_15_23; + wire [0:0] _zz_s0_countOnesLogic_15_24; + wire [4:0] _zz_s1_offsetNext; + wire [12:0] _zz_s1_byteCounter; + wire [3:0] _zz_s1_inputIndexes_1; + wire [3:0] _zz_s1_inputIndexes_2; + wire [3:0] _zz_s1_inputIndexes_3; + wire [3:0] _zz_s1_inputIndexes_4; + wire [3:0] _zz_s1_inputIndexes_5; + wire [3:0] _zz_s1_inputIndexes_6; + wire [3:0] _zz_s1_inputIndexes_7; + wire [0:0] _zz_s1_outputPayload_selValid_240; + wire [6:0] _zz_s1_outputPayload_selValid_241; + wire [0:0] _zz_s1_outputPayload_selValid_242; + wire [6:0] _zz_s1_outputPayload_selValid_243; + wire [0:0] _zz_s1_outputPayload_selValid_244; + wire [6:0] _zz_s1_outputPayload_selValid_245; + wire [0:0] _zz_s1_outputPayload_selValid_246; + wire [6:0] _zz_s1_outputPayload_selValid_247; + wire [0:0] _zz_s1_outputPayload_selValid_248; + wire [6:0] _zz_s1_outputPayload_selValid_249; + wire [0:0] _zz_s1_outputPayload_selValid_250; + wire [6:0] _zz_s1_outputPayload_selValid_251; + wire [0:0] _zz_s1_outputPayload_selValid_252; + wire [6:0] _zz_s1_outputPayload_selValid_253; + wire [0:0] _zz_s1_outputPayload_selValid_254; + wire [6:0] _zz_s1_outputPayload_selValid_255; + wire [0:0] _zz_s1_outputPayload_selValid_256; + wire [6:0] _zz_s1_outputPayload_selValid_257; + wire [0:0] _zz_s1_outputPayload_selValid_258; + wire [6:0] _zz_s1_outputPayload_selValid_259; + wire [0:0] _zz_s1_outputPayload_selValid_260; + wire [6:0] _zz_s1_outputPayload_selValid_261; + wire [0:0] _zz_s1_outputPayload_selValid_262; + wire [6:0] _zz_s1_outputPayload_selValid_263; + wire [0:0] _zz_s1_outputPayload_selValid_264; + wire [6:0] _zz_s1_outputPayload_selValid_265; + wire [0:0] _zz_s1_outputPayload_selValid_266; + wire [6:0] _zz_s1_outputPayload_selValid_267; + wire [0:0] _zz_s1_outputPayload_selValid_268; + wire [6:0] _zz_s1_outputPayload_selValid_269; + wire [0:0] _zz_s1_outputPayload_selValid_270; + wire [6:0] _zz_s1_outputPayload_selValid_271; + wire [12:0] _zz_when_DmaSg_l1464; + reg [7:0] _zz_s2_byteLogic_0_inputData; + reg [7:0] _zz_s2_byteLogic_1_inputData; + reg [7:0] _zz_s2_byteLogic_2_inputData; + reg [7:0] _zz_s2_byteLogic_3_inputData; + reg [7:0] _zz_s2_byteLogic_4_inputData; + reg [7:0] _zz_s2_byteLogic_5_inputData; + reg [7:0] _zz_s2_byteLogic_6_inputData; + reg [7:0] _zz_s2_byteLogic_7_inputData; + reg [7:0] _zz_s2_byteLogic_8_inputData; + reg [7:0] _zz_s2_byteLogic_9_inputData; + reg [7:0] _zz_s2_byteLogic_10_inputData; + reg [7:0] _zz_s2_byteLogic_11_inputData; + reg [7:0] _zz_s2_byteLogic_12_inputData; + reg [7:0] _zz_s2_byteLogic_13_inputData; + reg [7:0] _zz_s2_byteLogic_14_inputData; + reg [7:0] _zz_s2_byteLogic_15_inputData; + reg [3:0] _zz_io_output_usedUntil_4; + wire [3:0] _zz_io_output_usedUntil_5; + wire s0_input_valid; + wire s0_input_ready; + wire [127:0] s0_input_payload_data; + wire [15:0] s0_input_payload_mask; + reg io_input_rValid; + reg [127:0] io_input_rData_data; + reg [15:0] io_input_rData_mask; + wire when_Stream_l375; + wire _zz_s0_countOnesLogic_0; + wire _zz_s0_countOnesLogic_1; + wire _zz_s0_countOnesLogic_2; + wire _zz_s0_countOnesLogic_3; + wire _zz_s0_countOnesLogic_4; + wire _zz_s0_countOnesLogic_5; + wire _zz_s0_countOnesLogic_6; + wire _zz_s0_countOnesLogic_7; + wire _zz_s0_countOnesLogic_8; + wire _zz_s0_countOnesLogic_9; + wire _zz_s0_countOnesLogic_10; + wire _zz_s0_countOnesLogic_11; + wire _zz_s0_countOnesLogic_12; + wire _zz_s0_countOnesLogic_13; + wire _zz_s0_countOnesLogic_14; + wire [0:0] s0_countOnesLogic_0; + wire [1:0] s0_countOnesLogic_1; + wire [1:0] s0_countOnesLogic_2; + wire [2:0] _zz_s0_countOnesLogic_3_1; + wire [2:0] _zz_s0_countOnesLogic_3_2; + wire [2:0] _zz_s0_countOnesLogic_3_3; + wire [2:0] _zz_s0_countOnesLogic_3_4; + wire [2:0] _zz_s0_countOnesLogic_3_5; + wire [2:0] _zz_s0_countOnesLogic_3_6; + wire [2:0] _zz_s0_countOnesLogic_3_7; + wire [2:0] _zz_s0_countOnesLogic_3_8; + wire [2:0] s0_countOnesLogic_3; + wire [2:0] _zz_s0_countOnesLogic_4_1; + wire [2:0] _zz_s0_countOnesLogic_4_2; + wire [2:0] _zz_s0_countOnesLogic_4_3; + wire [2:0] _zz_s0_countOnesLogic_4_4; + wire [2:0] _zz_s0_countOnesLogic_4_5; + wire [2:0] _zz_s0_countOnesLogic_4_6; + wire [2:0] _zz_s0_countOnesLogic_4_7; + wire [2:0] _zz_s0_countOnesLogic_4_8; + wire [2:0] s0_countOnesLogic_4; + wire [2:0] _zz_s0_countOnesLogic_5_1; + wire [2:0] _zz_s0_countOnesLogic_5_2; + wire [2:0] _zz_s0_countOnesLogic_5_3; + wire [2:0] _zz_s0_countOnesLogic_5_4; + wire [2:0] _zz_s0_countOnesLogic_5_5; + wire [2:0] _zz_s0_countOnesLogic_5_6; + wire [2:0] _zz_s0_countOnesLogic_5_7; + wire [2:0] _zz_s0_countOnesLogic_5_8; + wire [2:0] s0_countOnesLogic_5; + wire [2:0] _zz_s0_countOnesLogic_6_1; + wire [2:0] _zz_s0_countOnesLogic_6_2; + wire [2:0] _zz_s0_countOnesLogic_6_3; + wire [2:0] _zz_s0_countOnesLogic_6_4; + wire [2:0] _zz_s0_countOnesLogic_6_5; + wire [2:0] _zz_s0_countOnesLogic_6_6; + wire [2:0] _zz_s0_countOnesLogic_6_7; + wire [2:0] _zz_s0_countOnesLogic_6_8; + wire [2:0] s0_countOnesLogic_6; + wire [3:0] _zz_s0_countOnesLogic_7_1; + wire [3:0] _zz_s0_countOnesLogic_7_2; + wire [3:0] _zz_s0_countOnesLogic_7_3; + wire [3:0] _zz_s0_countOnesLogic_7_4; + wire [3:0] _zz_s0_countOnesLogic_7_5; + wire [3:0] _zz_s0_countOnesLogic_7_6; + wire [3:0] _zz_s0_countOnesLogic_7_7; + wire [3:0] _zz_s0_countOnesLogic_7_8; + wire [3:0] s0_countOnesLogic_7; + wire [3:0] _zz_s0_countOnesLogic_8_1; + wire [3:0] _zz_s0_countOnesLogic_8_2; + wire [3:0] _zz_s0_countOnesLogic_8_3; + wire [3:0] _zz_s0_countOnesLogic_8_4; + wire [3:0] _zz_s0_countOnesLogic_8_5; + wire [3:0] _zz_s0_countOnesLogic_8_6; + wire [3:0] _zz_s0_countOnesLogic_8_7; + wire [3:0] _zz_s0_countOnesLogic_8_8; + wire [3:0] s0_countOnesLogic_8; + wire [3:0] _zz_s0_countOnesLogic_9_1; + wire [3:0] _zz_s0_countOnesLogic_9_2; + wire [3:0] _zz_s0_countOnesLogic_9_3; + wire [3:0] _zz_s0_countOnesLogic_9_4; + wire [3:0] _zz_s0_countOnesLogic_9_5; + wire [3:0] _zz_s0_countOnesLogic_9_6; + wire [3:0] _zz_s0_countOnesLogic_9_7; + wire [3:0] _zz_s0_countOnesLogic_9_8; + wire [3:0] s0_countOnesLogic_9; + wire [3:0] _zz_s0_countOnesLogic_10_1; + wire [3:0] _zz_s0_countOnesLogic_10_2; + wire [3:0] _zz_s0_countOnesLogic_10_3; + wire [3:0] _zz_s0_countOnesLogic_10_4; + wire [3:0] _zz_s0_countOnesLogic_10_5; + wire [3:0] _zz_s0_countOnesLogic_10_6; + wire [3:0] _zz_s0_countOnesLogic_10_7; + wire [3:0] _zz_s0_countOnesLogic_10_8; + wire [3:0] s0_countOnesLogic_10; + wire [3:0] _zz_s0_countOnesLogic_11_1; + wire [3:0] _zz_s0_countOnesLogic_11_2; + wire [3:0] _zz_s0_countOnesLogic_11_3; + wire [3:0] _zz_s0_countOnesLogic_11_4; + wire [3:0] _zz_s0_countOnesLogic_11_5; + wire [3:0] _zz_s0_countOnesLogic_11_6; + wire [3:0] _zz_s0_countOnesLogic_11_7; + wire [3:0] _zz_s0_countOnesLogic_11_8; + wire [3:0] s0_countOnesLogic_11; + wire [3:0] _zz_s0_countOnesLogic_12_1; + wire [3:0] _zz_s0_countOnesLogic_12_2; + wire [3:0] _zz_s0_countOnesLogic_12_3; + wire [3:0] _zz_s0_countOnesLogic_12_4; + wire [3:0] _zz_s0_countOnesLogic_12_5; + wire [3:0] _zz_s0_countOnesLogic_12_6; + wire [3:0] _zz_s0_countOnesLogic_12_7; + wire [3:0] _zz_s0_countOnesLogic_12_8; + wire [3:0] s0_countOnesLogic_12; + wire [3:0] _zz_s0_countOnesLogic_13_1; + wire [3:0] _zz_s0_countOnesLogic_13_2; + wire [3:0] _zz_s0_countOnesLogic_13_3; + wire [3:0] _zz_s0_countOnesLogic_13_4; + wire [3:0] _zz_s0_countOnesLogic_13_5; + wire [3:0] _zz_s0_countOnesLogic_13_6; + wire [3:0] _zz_s0_countOnesLogic_13_7; + wire [3:0] _zz_s0_countOnesLogic_13_8; + wire [3:0] s0_countOnesLogic_13; + wire [3:0] _zz_s0_countOnesLogic_14_1; + wire [3:0] _zz_s0_countOnesLogic_14_2; + wire [3:0] _zz_s0_countOnesLogic_14_3; + wire [3:0] _zz_s0_countOnesLogic_14_4; + wire [3:0] _zz_s0_countOnesLogic_14_5; + wire [3:0] _zz_s0_countOnesLogic_14_6; + wire [3:0] _zz_s0_countOnesLogic_14_7; + wire [3:0] _zz_s0_countOnesLogic_14_8; + wire [3:0] s0_countOnesLogic_14; + wire [4:0] _zz_s0_countOnesLogic_15; + wire [4:0] _zz_s0_countOnesLogic_15_1; + wire [4:0] _zz_s0_countOnesLogic_15_2; + wire [4:0] _zz_s0_countOnesLogic_15_3; + wire [4:0] _zz_s0_countOnesLogic_15_4; + wire [4:0] _zz_s0_countOnesLogic_15_5; + wire [4:0] _zz_s0_countOnesLogic_15_6; + wire [4:0] _zz_s0_countOnesLogic_15_7; + wire [4:0] s0_countOnesLogic_15; + wire [127:0] s0_outputPayload_cmd_data; + wire [15:0] s0_outputPayload_cmd_mask; + wire [0:0] s0_outputPayload_countOnes_0; + wire [1:0] s0_outputPayload_countOnes_1; + wire [1:0] s0_outputPayload_countOnes_2; + wire [2:0] s0_outputPayload_countOnes_3; + wire [2:0] s0_outputPayload_countOnes_4; + wire [2:0] s0_outputPayload_countOnes_5; + wire [2:0] s0_outputPayload_countOnes_6; + wire [3:0] s0_outputPayload_countOnes_7; + wire [3:0] s0_outputPayload_countOnes_8; + wire [3:0] s0_outputPayload_countOnes_9; + wire [3:0] s0_outputPayload_countOnes_10; + wire [3:0] s0_outputPayload_countOnes_11; + wire [3:0] s0_outputPayload_countOnes_12; + wire [3:0] s0_outputPayload_countOnes_13; + wire [3:0] s0_outputPayload_countOnes_14; + wire [4:0] s0_outputPayload_countOnes_15; + wire s0_output_valid; + reg s0_output_ready; + wire [127:0] s0_output_payload_cmd_data; + wire [15:0] s0_output_payload_cmd_mask; + wire [0:0] s0_output_payload_countOnes_0; + wire [1:0] s0_output_payload_countOnes_1; + wire [1:0] s0_output_payload_countOnes_2; + wire [2:0] s0_output_payload_countOnes_3; + wire [2:0] s0_output_payload_countOnes_4; + wire [2:0] s0_output_payload_countOnes_5; + wire [2:0] s0_output_payload_countOnes_6; + wire [3:0] s0_output_payload_countOnes_7; + wire [3:0] s0_output_payload_countOnes_8; + wire [3:0] s0_output_payload_countOnes_9; + wire [3:0] s0_output_payload_countOnes_10; + wire [3:0] s0_output_payload_countOnes_11; + wire [3:0] s0_output_payload_countOnes_12; + wire [3:0] s0_output_payload_countOnes_13; + wire [3:0] s0_output_payload_countOnes_14; + wire [4:0] s0_output_payload_countOnes_15; + wire s1_input_valid; + wire s1_input_ready; + wire [127:0] s1_input_payload_cmd_data; + wire [15:0] s1_input_payload_cmd_mask; + wire [0:0] s1_input_payload_countOnes_0; + wire [1:0] s1_input_payload_countOnes_1; + wire [1:0] s1_input_payload_countOnes_2; + wire [2:0] s1_input_payload_countOnes_3; + wire [2:0] s1_input_payload_countOnes_4; + wire [2:0] s1_input_payload_countOnes_5; + wire [2:0] s1_input_payload_countOnes_6; + wire [3:0] s1_input_payload_countOnes_7; + wire [3:0] s1_input_payload_countOnes_8; + wire [3:0] s1_input_payload_countOnes_9; + wire [3:0] s1_input_payload_countOnes_10; + wire [3:0] s1_input_payload_countOnes_11; + wire [3:0] s1_input_payload_countOnes_12; + wire [3:0] s1_input_payload_countOnes_13; + wire [3:0] s1_input_payload_countOnes_14; + wire [4:0] s1_input_payload_countOnes_15; + reg s0_output_rValid; + reg [127:0] s0_output_rData_cmd_data; + reg [15:0] s0_output_rData_cmd_mask; + reg [0:0] s0_output_rData_countOnes_0; + reg [1:0] s0_output_rData_countOnes_1; + reg [1:0] s0_output_rData_countOnes_2; + reg [2:0] s0_output_rData_countOnes_3; + reg [2:0] s0_output_rData_countOnes_4; + reg [2:0] s0_output_rData_countOnes_5; + reg [2:0] s0_output_rData_countOnes_6; + reg [3:0] s0_output_rData_countOnes_7; + reg [3:0] s0_output_rData_countOnes_8; + reg [3:0] s0_output_rData_countOnes_9; + reg [3:0] s0_output_rData_countOnes_10; + reg [3:0] s0_output_rData_countOnes_11; + reg [3:0] s0_output_rData_countOnes_12; + reg [3:0] s0_output_rData_countOnes_13; + reg [3:0] s0_output_rData_countOnes_14; + reg [4:0] s0_output_rData_countOnes_15; + wire when_Stream_l375_1; + reg [3:0] s1_offset; + wire [4:0] s1_offsetNext; + wire s1_input_fire; + reg [12:0] s1_byteCounter; + wire [3:0] s1_inputIndexes_0; + wire [3:0] s1_inputIndexes_1; + wire [3:0] s1_inputIndexes_2; + wire [3:0] s1_inputIndexes_3; + wire [3:0] s1_inputIndexes_4; + wire [3:0] s1_inputIndexes_5; + wire [3:0] s1_inputIndexes_6; + wire [3:0] s1_inputIndexes_7; + wire [3:0] s1_inputIndexes_8; + wire [3:0] s1_inputIndexes_9; + wire [3:0] s1_inputIndexes_10; + wire [3:0] s1_inputIndexes_11; + wire [3:0] s1_inputIndexes_12; + wire [3:0] s1_inputIndexes_13; + wire [3:0] s1_inputIndexes_14; + wire [3:0] s1_inputIndexes_15; + wire [127:0] s1_outputPayload_cmd_data; + wire [15:0] s1_outputPayload_cmd_mask; + wire [3:0] s1_outputPayload_index_0; + wire [3:0] s1_outputPayload_index_1; + wire [3:0] s1_outputPayload_index_2; + wire [3:0] s1_outputPayload_index_3; + wire [3:0] s1_outputPayload_index_4; + wire [3:0] s1_outputPayload_index_5; + wire [3:0] s1_outputPayload_index_6; + wire [3:0] s1_outputPayload_index_7; + wire [3:0] s1_outputPayload_index_8; + wire [3:0] s1_outputPayload_index_9; + wire [3:0] s1_outputPayload_index_10; + wire [3:0] s1_outputPayload_index_11; + wire [3:0] s1_outputPayload_index_12; + wire [3:0] s1_outputPayload_index_13; + wire [3:0] s1_outputPayload_index_14; + wire [3:0] s1_outputPayload_index_15; + wire s1_outputPayload_last; + wire [3:0] s1_outputPayload_sel_0; + wire [3:0] s1_outputPayload_sel_1; + wire [3:0] s1_outputPayload_sel_2; + wire [3:0] s1_outputPayload_sel_3; + wire [3:0] s1_outputPayload_sel_4; + wire [3:0] s1_outputPayload_sel_5; + wire [3:0] s1_outputPayload_sel_6; + wire [3:0] s1_outputPayload_sel_7; + wire [3:0] s1_outputPayload_sel_8; + wire [3:0] s1_outputPayload_sel_9; + wire [3:0] s1_outputPayload_sel_10; + wire [3:0] s1_outputPayload_sel_11; + wire [3:0] s1_outputPayload_sel_12; + wire [3:0] s1_outputPayload_sel_13; + wire [3:0] s1_outputPayload_sel_14; + wire [3:0] s1_outputPayload_sel_15; + reg [15:0] s1_outputPayload_selValid; + wire _zz_s1_outputPayload_selValid; + wire _zz_s1_outputPayload_selValid_1; + wire _zz_s1_outputPayload_selValid_2; + wire _zz_s1_outputPayload_selValid_3; + wire _zz_s1_outputPayload_selValid_4; + wire _zz_s1_outputPayload_selValid_5; + wire _zz_s1_outputPayload_selValid_6; + wire _zz_s1_outputPayload_selValid_7; + wire _zz_s1_outputPayload_selValid_8; + wire _zz_s1_outputPayload_selValid_9; + wire _zz_s1_outputPayload_selValid_10; + wire _zz_s1_outputPayload_selValid_11; + wire _zz_s1_outputPayload_selValid_12; + wire _zz_s1_outputPayload_selValid_13; + wire _zz_s1_outputPayload_selValid_14; + wire _zz_s1_outputPayload_sel_0; + wire _zz_s1_outputPayload_sel_0_1; + wire _zz_s1_outputPayload_sel_0_2; + wire _zz_s1_outputPayload_sel_0_3; + wire _zz_s1_outputPayload_selValid_15; + wire _zz_s1_outputPayload_selValid_16; + wire _zz_s1_outputPayload_selValid_17; + wire _zz_s1_outputPayload_selValid_18; + wire _zz_s1_outputPayload_selValid_19; + wire _zz_s1_outputPayload_selValid_20; + wire _zz_s1_outputPayload_selValid_21; + wire _zz_s1_outputPayload_selValid_22; + wire _zz_s1_outputPayload_selValid_23; + wire _zz_s1_outputPayload_selValid_24; + wire _zz_s1_outputPayload_selValid_25; + wire _zz_s1_outputPayload_selValid_26; + wire _zz_s1_outputPayload_selValid_27; + wire _zz_s1_outputPayload_selValid_28; + wire _zz_s1_outputPayload_selValid_29; + wire _zz_s1_outputPayload_sel_1; + wire _zz_s1_outputPayload_sel_1_1; + wire _zz_s1_outputPayload_sel_1_2; + wire _zz_s1_outputPayload_sel_1_3; + wire _zz_s1_outputPayload_selValid_30; + wire _zz_s1_outputPayload_selValid_31; + wire _zz_s1_outputPayload_selValid_32; + wire _zz_s1_outputPayload_selValid_33; + wire _zz_s1_outputPayload_selValid_34; + wire _zz_s1_outputPayload_selValid_35; + wire _zz_s1_outputPayload_selValid_36; + wire _zz_s1_outputPayload_selValid_37; + wire _zz_s1_outputPayload_selValid_38; + wire _zz_s1_outputPayload_selValid_39; + wire _zz_s1_outputPayload_selValid_40; + wire _zz_s1_outputPayload_selValid_41; + wire _zz_s1_outputPayload_selValid_42; + wire _zz_s1_outputPayload_selValid_43; + wire _zz_s1_outputPayload_selValid_44; + wire _zz_s1_outputPayload_sel_2; + wire _zz_s1_outputPayload_sel_2_1; + wire _zz_s1_outputPayload_sel_2_2; + wire _zz_s1_outputPayload_sel_2_3; + wire _zz_s1_outputPayload_selValid_45; + wire _zz_s1_outputPayload_selValid_46; + wire _zz_s1_outputPayload_selValid_47; + wire _zz_s1_outputPayload_selValid_48; + wire _zz_s1_outputPayload_selValid_49; + wire _zz_s1_outputPayload_selValid_50; + wire _zz_s1_outputPayload_selValid_51; + wire _zz_s1_outputPayload_selValid_52; + wire _zz_s1_outputPayload_selValid_53; + wire _zz_s1_outputPayload_selValid_54; + wire _zz_s1_outputPayload_selValid_55; + wire _zz_s1_outputPayload_selValid_56; + wire _zz_s1_outputPayload_selValid_57; + wire _zz_s1_outputPayload_selValid_58; + wire _zz_s1_outputPayload_selValid_59; + wire _zz_s1_outputPayload_sel_3; + wire _zz_s1_outputPayload_sel_3_1; + wire _zz_s1_outputPayload_sel_3_2; + wire _zz_s1_outputPayload_sel_3_3; + wire _zz_s1_outputPayload_selValid_60; + wire _zz_s1_outputPayload_selValid_61; + wire _zz_s1_outputPayload_selValid_62; + wire _zz_s1_outputPayload_selValid_63; + wire _zz_s1_outputPayload_selValid_64; + wire _zz_s1_outputPayload_selValid_65; + wire _zz_s1_outputPayload_selValid_66; + wire _zz_s1_outputPayload_selValid_67; + wire _zz_s1_outputPayload_selValid_68; + wire _zz_s1_outputPayload_selValid_69; + wire _zz_s1_outputPayload_selValid_70; + wire _zz_s1_outputPayload_selValid_71; + wire _zz_s1_outputPayload_selValid_72; + wire _zz_s1_outputPayload_selValid_73; + wire _zz_s1_outputPayload_selValid_74; + wire _zz_s1_outputPayload_sel_4; + wire _zz_s1_outputPayload_sel_4_1; + wire _zz_s1_outputPayload_sel_4_2; + wire _zz_s1_outputPayload_sel_4_3; + wire _zz_s1_outputPayload_selValid_75; + wire _zz_s1_outputPayload_selValid_76; + wire _zz_s1_outputPayload_selValid_77; + wire _zz_s1_outputPayload_selValid_78; + wire _zz_s1_outputPayload_selValid_79; + wire _zz_s1_outputPayload_selValid_80; + wire _zz_s1_outputPayload_selValid_81; + wire _zz_s1_outputPayload_selValid_82; + wire _zz_s1_outputPayload_selValid_83; + wire _zz_s1_outputPayload_selValid_84; + wire _zz_s1_outputPayload_selValid_85; + wire _zz_s1_outputPayload_selValid_86; + wire _zz_s1_outputPayload_selValid_87; + wire _zz_s1_outputPayload_selValid_88; + wire _zz_s1_outputPayload_selValid_89; + wire _zz_s1_outputPayload_sel_5; + wire _zz_s1_outputPayload_sel_5_1; + wire _zz_s1_outputPayload_sel_5_2; + wire _zz_s1_outputPayload_sel_5_3; + wire _zz_s1_outputPayload_selValid_90; + wire _zz_s1_outputPayload_selValid_91; + wire _zz_s1_outputPayload_selValid_92; + wire _zz_s1_outputPayload_selValid_93; + wire _zz_s1_outputPayload_selValid_94; + wire _zz_s1_outputPayload_selValid_95; + wire _zz_s1_outputPayload_selValid_96; + wire _zz_s1_outputPayload_selValid_97; + wire _zz_s1_outputPayload_selValid_98; + wire _zz_s1_outputPayload_selValid_99; + wire _zz_s1_outputPayload_selValid_100; + wire _zz_s1_outputPayload_selValid_101; + wire _zz_s1_outputPayload_selValid_102; + wire _zz_s1_outputPayload_selValid_103; + wire _zz_s1_outputPayload_selValid_104; + wire _zz_s1_outputPayload_sel_6; + wire _zz_s1_outputPayload_sel_6_1; + wire _zz_s1_outputPayload_sel_6_2; + wire _zz_s1_outputPayload_sel_6_3; + wire _zz_s1_outputPayload_selValid_105; + wire _zz_s1_outputPayload_selValid_106; + wire _zz_s1_outputPayload_selValid_107; + wire _zz_s1_outputPayload_selValid_108; + wire _zz_s1_outputPayload_selValid_109; + wire _zz_s1_outputPayload_selValid_110; + wire _zz_s1_outputPayload_selValid_111; + wire _zz_s1_outputPayload_selValid_112; + wire _zz_s1_outputPayload_selValid_113; + wire _zz_s1_outputPayload_selValid_114; + wire _zz_s1_outputPayload_selValid_115; + wire _zz_s1_outputPayload_selValid_116; + wire _zz_s1_outputPayload_selValid_117; + wire _zz_s1_outputPayload_selValid_118; + wire _zz_s1_outputPayload_selValid_119; + wire _zz_s1_outputPayload_sel_7; + wire _zz_s1_outputPayload_sel_7_1; + wire _zz_s1_outputPayload_sel_7_2; + wire _zz_s1_outputPayload_sel_7_3; + wire _zz_s1_outputPayload_selValid_120; + wire _zz_s1_outputPayload_selValid_121; + wire _zz_s1_outputPayload_selValid_122; + wire _zz_s1_outputPayload_selValid_123; + wire _zz_s1_outputPayload_selValid_124; + wire _zz_s1_outputPayload_selValid_125; + wire _zz_s1_outputPayload_selValid_126; + wire _zz_s1_outputPayload_selValid_127; + wire _zz_s1_outputPayload_selValid_128; + wire _zz_s1_outputPayload_selValid_129; + wire _zz_s1_outputPayload_selValid_130; + wire _zz_s1_outputPayload_selValid_131; + wire _zz_s1_outputPayload_selValid_132; + wire _zz_s1_outputPayload_selValid_133; + wire _zz_s1_outputPayload_selValid_134; + wire _zz_s1_outputPayload_sel_8; + wire _zz_s1_outputPayload_sel_8_1; + wire _zz_s1_outputPayload_sel_8_2; + wire _zz_s1_outputPayload_sel_8_3; + wire _zz_s1_outputPayload_selValid_135; + wire _zz_s1_outputPayload_selValid_136; + wire _zz_s1_outputPayload_selValid_137; + wire _zz_s1_outputPayload_selValid_138; + wire _zz_s1_outputPayload_selValid_139; + wire _zz_s1_outputPayload_selValid_140; + wire _zz_s1_outputPayload_selValid_141; + wire _zz_s1_outputPayload_selValid_142; + wire _zz_s1_outputPayload_selValid_143; + wire _zz_s1_outputPayload_selValid_144; + wire _zz_s1_outputPayload_selValid_145; + wire _zz_s1_outputPayload_selValid_146; + wire _zz_s1_outputPayload_selValid_147; + wire _zz_s1_outputPayload_selValid_148; + wire _zz_s1_outputPayload_selValid_149; + wire _zz_s1_outputPayload_sel_9; + wire _zz_s1_outputPayload_sel_9_1; + wire _zz_s1_outputPayload_sel_9_2; + wire _zz_s1_outputPayload_sel_9_3; + wire _zz_s1_outputPayload_selValid_150; + wire _zz_s1_outputPayload_selValid_151; + wire _zz_s1_outputPayload_selValid_152; + wire _zz_s1_outputPayload_selValid_153; + wire _zz_s1_outputPayload_selValid_154; + wire _zz_s1_outputPayload_selValid_155; + wire _zz_s1_outputPayload_selValid_156; + wire _zz_s1_outputPayload_selValid_157; + wire _zz_s1_outputPayload_selValid_158; + wire _zz_s1_outputPayload_selValid_159; + wire _zz_s1_outputPayload_selValid_160; + wire _zz_s1_outputPayload_selValid_161; + wire _zz_s1_outputPayload_selValid_162; + wire _zz_s1_outputPayload_selValid_163; + wire _zz_s1_outputPayload_selValid_164; + wire _zz_s1_outputPayload_sel_10; + wire _zz_s1_outputPayload_sel_10_1; + wire _zz_s1_outputPayload_sel_10_2; + wire _zz_s1_outputPayload_sel_10_3; + wire _zz_s1_outputPayload_selValid_165; + wire _zz_s1_outputPayload_selValid_166; + wire _zz_s1_outputPayload_selValid_167; + wire _zz_s1_outputPayload_selValid_168; + wire _zz_s1_outputPayload_selValid_169; + wire _zz_s1_outputPayload_selValid_170; + wire _zz_s1_outputPayload_selValid_171; + wire _zz_s1_outputPayload_selValid_172; + wire _zz_s1_outputPayload_selValid_173; + wire _zz_s1_outputPayload_selValid_174; + wire _zz_s1_outputPayload_selValid_175; + wire _zz_s1_outputPayload_selValid_176; + wire _zz_s1_outputPayload_selValid_177; + wire _zz_s1_outputPayload_selValid_178; + wire _zz_s1_outputPayload_selValid_179; + wire _zz_s1_outputPayload_sel_11; + wire _zz_s1_outputPayload_sel_11_1; + wire _zz_s1_outputPayload_sel_11_2; + wire _zz_s1_outputPayload_sel_11_3; + wire _zz_s1_outputPayload_selValid_180; + wire _zz_s1_outputPayload_selValid_181; + wire _zz_s1_outputPayload_selValid_182; + wire _zz_s1_outputPayload_selValid_183; + wire _zz_s1_outputPayload_selValid_184; + wire _zz_s1_outputPayload_selValid_185; + wire _zz_s1_outputPayload_selValid_186; + wire _zz_s1_outputPayload_selValid_187; + wire _zz_s1_outputPayload_selValid_188; + wire _zz_s1_outputPayload_selValid_189; + wire _zz_s1_outputPayload_selValid_190; + wire _zz_s1_outputPayload_selValid_191; + wire _zz_s1_outputPayload_selValid_192; + wire _zz_s1_outputPayload_selValid_193; + wire _zz_s1_outputPayload_selValid_194; + wire _zz_s1_outputPayload_sel_12; + wire _zz_s1_outputPayload_sel_12_1; + wire _zz_s1_outputPayload_sel_12_2; + wire _zz_s1_outputPayload_sel_12_3; + wire _zz_s1_outputPayload_selValid_195; + wire _zz_s1_outputPayload_selValid_196; + wire _zz_s1_outputPayload_selValid_197; + wire _zz_s1_outputPayload_selValid_198; + wire _zz_s1_outputPayload_selValid_199; + wire _zz_s1_outputPayload_selValid_200; + wire _zz_s1_outputPayload_selValid_201; + wire _zz_s1_outputPayload_selValid_202; + wire _zz_s1_outputPayload_selValid_203; + wire _zz_s1_outputPayload_selValid_204; + wire _zz_s1_outputPayload_selValid_205; + wire _zz_s1_outputPayload_selValid_206; + wire _zz_s1_outputPayload_selValid_207; + wire _zz_s1_outputPayload_selValid_208; + wire _zz_s1_outputPayload_selValid_209; + wire _zz_s1_outputPayload_sel_13; + wire _zz_s1_outputPayload_sel_13_1; + wire _zz_s1_outputPayload_sel_13_2; + wire _zz_s1_outputPayload_sel_13_3; + wire _zz_s1_outputPayload_selValid_210; + wire _zz_s1_outputPayload_selValid_211; + wire _zz_s1_outputPayload_selValid_212; + wire _zz_s1_outputPayload_selValid_213; + wire _zz_s1_outputPayload_selValid_214; + wire _zz_s1_outputPayload_selValid_215; + wire _zz_s1_outputPayload_selValid_216; + wire _zz_s1_outputPayload_selValid_217; + wire _zz_s1_outputPayload_selValid_218; + wire _zz_s1_outputPayload_selValid_219; + wire _zz_s1_outputPayload_selValid_220; + wire _zz_s1_outputPayload_selValid_221; + wire _zz_s1_outputPayload_selValid_222; + wire _zz_s1_outputPayload_selValid_223; + wire _zz_s1_outputPayload_selValid_224; + wire _zz_s1_outputPayload_sel_14; + wire _zz_s1_outputPayload_sel_14_1; + wire _zz_s1_outputPayload_sel_14_2; + wire _zz_s1_outputPayload_sel_14_3; + wire _zz_s1_outputPayload_selValid_225; + wire _zz_s1_outputPayload_selValid_226; + wire _zz_s1_outputPayload_selValid_227; + wire _zz_s1_outputPayload_selValid_228; + wire _zz_s1_outputPayload_selValid_229; + wire _zz_s1_outputPayload_selValid_230; + wire _zz_s1_outputPayload_selValid_231; + wire _zz_s1_outputPayload_selValid_232; + wire _zz_s1_outputPayload_selValid_233; + wire _zz_s1_outputPayload_selValid_234; + wire _zz_s1_outputPayload_selValid_235; + wire _zz_s1_outputPayload_selValid_236; + wire _zz_s1_outputPayload_selValid_237; + wire _zz_s1_outputPayload_selValid_238; + wire _zz_s1_outputPayload_selValid_239; + wire _zz_s1_outputPayload_sel_15; + wire _zz_s1_outputPayload_sel_15_1; + wire _zz_s1_outputPayload_sel_15_2; + wire _zz_s1_outputPayload_sel_15_3; + wire s1_output_valid; + reg s1_output_ready; + wire [127:0] s1_output_payload_cmd_data; + wire [15:0] s1_output_payload_cmd_mask; + wire [3:0] s1_output_payload_index_0; + wire [3:0] s1_output_payload_index_1; + wire [3:0] s1_output_payload_index_2; + wire [3:0] s1_output_payload_index_3; + wire [3:0] s1_output_payload_index_4; + wire [3:0] s1_output_payload_index_5; + wire [3:0] s1_output_payload_index_6; + wire [3:0] s1_output_payload_index_7; + wire [3:0] s1_output_payload_index_8; + wire [3:0] s1_output_payload_index_9; + wire [3:0] s1_output_payload_index_10; + wire [3:0] s1_output_payload_index_11; + wire [3:0] s1_output_payload_index_12; + wire [3:0] s1_output_payload_index_13; + wire [3:0] s1_output_payload_index_14; + wire [3:0] s1_output_payload_index_15; + wire s1_output_payload_last; + wire [3:0] s1_output_payload_sel_0; + wire [3:0] s1_output_payload_sel_1; + wire [3:0] s1_output_payload_sel_2; + wire [3:0] s1_output_payload_sel_3; + wire [3:0] s1_output_payload_sel_4; + wire [3:0] s1_output_payload_sel_5; + wire [3:0] s1_output_payload_sel_6; + wire [3:0] s1_output_payload_sel_7; + wire [3:0] s1_output_payload_sel_8; + wire [3:0] s1_output_payload_sel_9; + wire [3:0] s1_output_payload_sel_10; + wire [3:0] s1_output_payload_sel_11; + wire [3:0] s1_output_payload_sel_12; + wire [3:0] s1_output_payload_sel_13; + wire [3:0] s1_output_payload_sel_14; + wire [3:0] s1_output_payload_sel_15; + wire [15:0] s1_output_payload_selValid; + wire s2_input_valid; + reg s2_input_ready; + wire [127:0] s2_input_payload_cmd_data; + wire [15:0] s2_input_payload_cmd_mask; + wire [3:0] s2_input_payload_index_0; + wire [3:0] s2_input_payload_index_1; + wire [3:0] s2_input_payload_index_2; + wire [3:0] s2_input_payload_index_3; + wire [3:0] s2_input_payload_index_4; + wire [3:0] s2_input_payload_index_5; + wire [3:0] s2_input_payload_index_6; + wire [3:0] s2_input_payload_index_7; + wire [3:0] s2_input_payload_index_8; + wire [3:0] s2_input_payload_index_9; + wire [3:0] s2_input_payload_index_10; + wire [3:0] s2_input_payload_index_11; + wire [3:0] s2_input_payload_index_12; + wire [3:0] s2_input_payload_index_13; + wire [3:0] s2_input_payload_index_14; + wire [3:0] s2_input_payload_index_15; + wire s2_input_payload_last; + wire [3:0] s2_input_payload_sel_0; + wire [3:0] s2_input_payload_sel_1; + wire [3:0] s2_input_payload_sel_2; + wire [3:0] s2_input_payload_sel_3; + wire [3:0] s2_input_payload_sel_4; + wire [3:0] s2_input_payload_sel_5; + wire [3:0] s2_input_payload_sel_6; + wire [3:0] s2_input_payload_sel_7; + wire [3:0] s2_input_payload_sel_8; + wire [3:0] s2_input_payload_sel_9; + wire [3:0] s2_input_payload_sel_10; + wire [3:0] s2_input_payload_sel_11; + wire [3:0] s2_input_payload_sel_12; + wire [3:0] s2_input_payload_sel_13; + wire [3:0] s2_input_payload_sel_14; + wire [3:0] s2_input_payload_sel_15; + wire [15:0] s2_input_payload_selValid; + reg s1_output_rValid; + reg [127:0] s1_output_rData_cmd_data; + reg [15:0] s1_output_rData_cmd_mask; + reg [3:0] s1_output_rData_index_0; + reg [3:0] s1_output_rData_index_1; + reg [3:0] s1_output_rData_index_2; + reg [3:0] s1_output_rData_index_3; + reg [3:0] s1_output_rData_index_4; + reg [3:0] s1_output_rData_index_5; + reg [3:0] s1_output_rData_index_6; + reg [3:0] s1_output_rData_index_7; + reg [3:0] s1_output_rData_index_8; + reg [3:0] s1_output_rData_index_9; + reg [3:0] s1_output_rData_index_10; + reg [3:0] s1_output_rData_index_11; + reg [3:0] s1_output_rData_index_12; + reg [3:0] s1_output_rData_index_13; + reg [3:0] s1_output_rData_index_14; + reg [3:0] s1_output_rData_index_15; + reg s1_output_rData_last; + reg [3:0] s1_output_rData_sel_0; + reg [3:0] s1_output_rData_sel_1; + reg [3:0] s1_output_rData_sel_2; + reg [3:0] s1_output_rData_sel_3; + reg [3:0] s1_output_rData_sel_4; + reg [3:0] s1_output_rData_sel_5; + reg [3:0] s1_output_rData_sel_6; + reg [3:0] s1_output_rData_sel_7; + reg [3:0] s1_output_rData_sel_8; + reg [3:0] s1_output_rData_sel_9; + reg [3:0] s1_output_rData_sel_10; + reg [3:0] s1_output_rData_sel_11; + reg [3:0] s1_output_rData_sel_12; + reg [3:0] s1_output_rData_sel_13; + reg [3:0] s1_output_rData_sel_14; + reg [3:0] s1_output_rData_sel_15; + reg [15:0] s1_output_rData_selValid; + wire when_Stream_l375_2; + wire when_DmaSg_l1464; + wire s2_input_fire; + wire [7:0] s2_inputDataBytes_0; + wire [7:0] s2_inputDataBytes_1; + wire [7:0] s2_inputDataBytes_2; + wire [7:0] s2_inputDataBytes_3; + wire [7:0] s2_inputDataBytes_4; + wire [7:0] s2_inputDataBytes_5; + wire [7:0] s2_inputDataBytes_6; + wire [7:0] s2_inputDataBytes_7; + wire [7:0] s2_inputDataBytes_8; + wire [7:0] s2_inputDataBytes_9; + wire [7:0] s2_inputDataBytes_10; + wire [7:0] s2_inputDataBytes_11; + wire [7:0] s2_inputDataBytes_12; + wire [7:0] s2_inputDataBytes_13; + wire [7:0] s2_inputDataBytes_14; + wire [7:0] s2_inputDataBytes_15; + reg s2_byteLogic_0_buffer_valid; + reg [7:0] s2_byteLogic_0_buffer_data; + wire s2_byteLogic_0_lastUsed; + wire s2_byteLogic_0_inputMask; + wire [7:0] s2_byteLogic_0_inputData; + wire s2_byteLogic_0_outputMask; + wire [7:0] s2_byteLogic_0_outputData; + wire when_DmaSg_l1493; + reg s2_byteLogic_1_buffer_valid; + reg [7:0] s2_byteLogic_1_buffer_data; + wire s2_byteLogic_1_lastUsed; + wire s2_byteLogic_1_inputMask; + wire [7:0] s2_byteLogic_1_inputData; + wire s2_byteLogic_1_outputMask; + wire [7:0] s2_byteLogic_1_outputData; + wire when_DmaSg_l1493_1; + reg s2_byteLogic_2_buffer_valid; + reg [7:0] s2_byteLogic_2_buffer_data; + wire s2_byteLogic_2_lastUsed; + wire s2_byteLogic_2_inputMask; + wire [7:0] s2_byteLogic_2_inputData; + wire s2_byteLogic_2_outputMask; + wire [7:0] s2_byteLogic_2_outputData; + wire when_DmaSg_l1493_2; + reg s2_byteLogic_3_buffer_valid; + reg [7:0] s2_byteLogic_3_buffer_data; + wire s2_byteLogic_3_lastUsed; + wire s2_byteLogic_3_inputMask; + wire [7:0] s2_byteLogic_3_inputData; + wire s2_byteLogic_3_outputMask; + wire [7:0] s2_byteLogic_3_outputData; + wire when_DmaSg_l1493_3; + reg s2_byteLogic_4_buffer_valid; + reg [7:0] s2_byteLogic_4_buffer_data; + wire s2_byteLogic_4_lastUsed; + wire s2_byteLogic_4_inputMask; + wire [7:0] s2_byteLogic_4_inputData; + wire s2_byteLogic_4_outputMask; + wire [7:0] s2_byteLogic_4_outputData; + wire when_DmaSg_l1493_4; + reg s2_byteLogic_5_buffer_valid; + reg [7:0] s2_byteLogic_5_buffer_data; + wire s2_byteLogic_5_lastUsed; + wire s2_byteLogic_5_inputMask; + wire [7:0] s2_byteLogic_5_inputData; + wire s2_byteLogic_5_outputMask; + wire [7:0] s2_byteLogic_5_outputData; + wire when_DmaSg_l1493_5; + reg s2_byteLogic_6_buffer_valid; + reg [7:0] s2_byteLogic_6_buffer_data; + wire s2_byteLogic_6_lastUsed; + wire s2_byteLogic_6_inputMask; + wire [7:0] s2_byteLogic_6_inputData; + wire s2_byteLogic_6_outputMask; + wire [7:0] s2_byteLogic_6_outputData; + wire when_DmaSg_l1493_6; + reg s2_byteLogic_7_buffer_valid; + reg [7:0] s2_byteLogic_7_buffer_data; + wire s2_byteLogic_7_lastUsed; + wire s2_byteLogic_7_inputMask; + wire [7:0] s2_byteLogic_7_inputData; + wire s2_byteLogic_7_outputMask; + wire [7:0] s2_byteLogic_7_outputData; + wire when_DmaSg_l1493_7; + reg s2_byteLogic_8_buffer_valid; + reg [7:0] s2_byteLogic_8_buffer_data; + wire s2_byteLogic_8_lastUsed; + wire s2_byteLogic_8_inputMask; + wire [7:0] s2_byteLogic_8_inputData; + wire s2_byteLogic_8_outputMask; + wire [7:0] s2_byteLogic_8_outputData; + wire when_DmaSg_l1493_8; + reg s2_byteLogic_9_buffer_valid; + reg [7:0] s2_byteLogic_9_buffer_data; + wire s2_byteLogic_9_lastUsed; + wire s2_byteLogic_9_inputMask; + wire [7:0] s2_byteLogic_9_inputData; + wire s2_byteLogic_9_outputMask; + wire [7:0] s2_byteLogic_9_outputData; + wire when_DmaSg_l1493_9; + reg s2_byteLogic_10_buffer_valid; + reg [7:0] s2_byteLogic_10_buffer_data; + wire s2_byteLogic_10_lastUsed; + wire s2_byteLogic_10_inputMask; + wire [7:0] s2_byteLogic_10_inputData; + wire s2_byteLogic_10_outputMask; + wire [7:0] s2_byteLogic_10_outputData; + wire when_DmaSg_l1493_10; + reg s2_byteLogic_11_buffer_valid; + reg [7:0] s2_byteLogic_11_buffer_data; + wire s2_byteLogic_11_lastUsed; + wire s2_byteLogic_11_inputMask; + wire [7:0] s2_byteLogic_11_inputData; + wire s2_byteLogic_11_outputMask; + wire [7:0] s2_byteLogic_11_outputData; + wire when_DmaSg_l1493_11; + reg s2_byteLogic_12_buffer_valid; + reg [7:0] s2_byteLogic_12_buffer_data; + wire s2_byteLogic_12_lastUsed; + wire s2_byteLogic_12_inputMask; + wire [7:0] s2_byteLogic_12_inputData; + wire s2_byteLogic_12_outputMask; + wire [7:0] s2_byteLogic_12_outputData; + wire when_DmaSg_l1493_12; + reg s2_byteLogic_13_buffer_valid; + reg [7:0] s2_byteLogic_13_buffer_data; + wire s2_byteLogic_13_lastUsed; + wire s2_byteLogic_13_inputMask; + wire [7:0] s2_byteLogic_13_inputData; + wire s2_byteLogic_13_outputMask; + wire [7:0] s2_byteLogic_13_outputData; + wire when_DmaSg_l1493_13; + reg s2_byteLogic_14_buffer_valid; + reg [7:0] s2_byteLogic_14_buffer_data; + wire s2_byteLogic_14_lastUsed; + wire s2_byteLogic_14_inputMask; + wire [7:0] s2_byteLogic_14_inputData; + wire s2_byteLogic_14_outputMask; + wire [7:0] s2_byteLogic_14_outputData; + wire when_DmaSg_l1493_14; + reg s2_byteLogic_15_buffer_valid; + reg [7:0] s2_byteLogic_15_buffer_data; + wire s2_byteLogic_15_lastUsed; + wire s2_byteLogic_15_inputMask; + wire [7:0] s2_byteLogic_15_inputData; + wire s2_byteLogic_15_outputMask; + wire [7:0] s2_byteLogic_15_outputData; + wire when_DmaSg_l1493_15; + wire _zz_io_output_usedUntil; + wire _zz_io_output_usedUntil_1; + wire _zz_io_output_usedUntil_2; + wire _zz_io_output_usedUntil_3; + + assign _zz_s0_countOnesLogic_3_13 = _zz_s0_countOnesLogic_3; + assign _zz_s0_countOnesLogic_3_12 = {2'd0, _zz_s0_countOnesLogic_3_13}; + assign _zz_s0_countOnesLogic_4_13 = {_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}; + assign _zz_s0_countOnesLogic_4_12 = {1'd0, _zz_s0_countOnesLogic_4_13}; + assign _zz_s0_countOnesLogic_6_9 = (_zz_s0_countOnesLogic_6_10 + _zz_s0_countOnesLogic_6_12); + assign _zz_s0_countOnesLogic_6_16 = _zz_s0_countOnesLogic_6; + assign _zz_s0_countOnesLogic_6_15 = {2'd0, _zz_s0_countOnesLogic_6_16}; + assign _zz_s0_countOnesLogic_7_9 = (_zz_s0_countOnesLogic_7_10 + _zz_s0_countOnesLogic_7_12); + assign _zz_s0_countOnesLogic_7_16 = {_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}; + assign _zz_s0_countOnesLogic_7_15 = {1'd0, _zz_s0_countOnesLogic_7_16}; + assign _zz_s0_countOnesLogic_8_9 = (_zz_s0_countOnesLogic_8_10 + _zz_s0_countOnesLogic_8_12); + assign _zz_s0_countOnesLogic_9_9 = (_zz_s0_countOnesLogic_9_10 + _zz_s0_countOnesLogic_9_12); + assign _zz_s0_countOnesLogic_9_14 = (_zz_s0_countOnesLogic_9_15 + _zz_s0_countOnesLogic_9_17); + assign _zz_s0_countOnesLogic_9_19 = _zz_s0_countOnesLogic_9; + assign _zz_s0_countOnesLogic_9_18 = {2'd0, _zz_s0_countOnesLogic_9_19}; + assign _zz_s0_countOnesLogic_10_9 = (_zz_s0_countOnesLogic_10_10 + _zz_s0_countOnesLogic_10_12); + assign _zz_s0_countOnesLogic_10_14 = (_zz_s0_countOnesLogic_10_15 + _zz_s0_countOnesLogic_10_17); + assign _zz_s0_countOnesLogic_10_19 = {_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}; + assign _zz_s0_countOnesLogic_10_18 = {1'd0, _zz_s0_countOnesLogic_10_19}; + assign _zz_s0_countOnesLogic_11_9 = (_zz_s0_countOnesLogic_11_10 + _zz_s0_countOnesLogic_11_12); + assign _zz_s0_countOnesLogic_11_14 = (_zz_s0_countOnesLogic_11_15 + _zz_s0_countOnesLogic_11_17); + assign _zz_s0_countOnesLogic_12_9 = (_zz_s0_countOnesLogic_12_10 + _zz_s0_countOnesLogic_12_15); + assign _zz_s0_countOnesLogic_12_10 = (_zz_s0_countOnesLogic_12_11 + _zz_s0_countOnesLogic_12_13); + assign _zz_s0_countOnesLogic_12_15 = (_zz_s0_countOnesLogic_12_16 + _zz_s0_countOnesLogic_12_18); + assign _zz_s0_countOnesLogic_12_22 = _zz_s0_countOnesLogic_12; + assign _zz_s0_countOnesLogic_12_21 = {2'd0, _zz_s0_countOnesLogic_12_22}; + assign _zz_s0_countOnesLogic_13_9 = (_zz_s0_countOnesLogic_13_10 + _zz_s0_countOnesLogic_13_15); + assign _zz_s0_countOnesLogic_13_10 = (_zz_s0_countOnesLogic_13_11 + _zz_s0_countOnesLogic_13_13); + assign _zz_s0_countOnesLogic_13_15 = (_zz_s0_countOnesLogic_13_16 + _zz_s0_countOnesLogic_13_18); + assign _zz_s0_countOnesLogic_13_22 = {_zz_s0_countOnesLogic_13,_zz_s0_countOnesLogic_12}; + assign _zz_s0_countOnesLogic_13_21 = {1'd0, _zz_s0_countOnesLogic_13_22}; + assign _zz_s0_countOnesLogic_14_9 = (_zz_s0_countOnesLogic_14_10 + _zz_s0_countOnesLogic_14_15); + assign _zz_s0_countOnesLogic_14_10 = (_zz_s0_countOnesLogic_14_11 + _zz_s0_countOnesLogic_14_13); + assign _zz_s0_countOnesLogic_14_15 = (_zz_s0_countOnesLogic_14_16 + _zz_s0_countOnesLogic_14_18); + assign _zz_s0_countOnesLogic_15_8 = (_zz_s0_countOnesLogic_15_9 + _zz_s0_countOnesLogic_15_14); + assign _zz_s0_countOnesLogic_15_9 = (_zz_s0_countOnesLogic_15_10 + _zz_s0_countOnesLogic_15_12); + assign _zz_s0_countOnesLogic_15_14 = (_zz_s0_countOnesLogic_15_15 + _zz_s0_countOnesLogic_15_17); + assign _zz_s0_countOnesLogic_15_19 = (_zz_s0_countOnesLogic_15_20 + _zz_s0_countOnesLogic_15_22); + assign _zz_s0_countOnesLogic_15_24 = s0_input_payload_mask[15]; + assign _zz_s0_countOnesLogic_15_23 = {2'd0, _zz_s0_countOnesLogic_15_24}; + assign _zz_s1_offsetNext = {1'd0, s1_offset}; + assign _zz_s1_byteCounter = {8'd0, s1_input_payload_countOnes_15}; + assign _zz_s1_inputIndexes_1 = {3'd0, s1_input_payload_countOnes_0}; + assign _zz_s1_inputIndexes_2 = {2'd0, s1_input_payload_countOnes_1}; + assign _zz_s1_inputIndexes_3 = {2'd0, s1_input_payload_countOnes_2}; + assign _zz_s1_inputIndexes_4 = {1'd0, s1_input_payload_countOnes_3}; + assign _zz_s1_inputIndexes_5 = {1'd0, s1_input_payload_countOnes_4}; + assign _zz_s1_inputIndexes_6 = {1'd0, s1_input_payload_countOnes_5}; + assign _zz_s1_inputIndexes_7 = {1'd0, s1_input_payload_countOnes_6}; + assign _zz_when_DmaSg_l1464 = {1'd0, io_burstLength}; + assign _zz_s0_countOnesLogic_0_2 = _zz_s0_countOnesLogic_0; + assign _zz_s0_countOnesLogic_1_2 = {_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}; + assign _zz_s0_countOnesLogic_2_2 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_3_10 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_4_10 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_5_10 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_5_12 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_6_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_6_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_7_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_7_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_8_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_8_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_8_15 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_9_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_9_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_9_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_10_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_10_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_10_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_11_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_11_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_11_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_11_18 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; + assign _zz_s0_countOnesLogic_12_12 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_12_14 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_12_17 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_12_19 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; + assign _zz_s0_countOnesLogic_13_12 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_13_14 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_13_17 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_13_19 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; + assign _zz_s0_countOnesLogic_14_12 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_14_14 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_14_17 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_14_19 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; + assign _zz_s0_countOnesLogic_14_21 = {_zz_s0_countOnesLogic_14,{_zz_s0_countOnesLogic_13,_zz_s0_countOnesLogic_12}}; + assign _zz_s0_countOnesLogic_15_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_15_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_15_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_15_18 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; + assign _zz_s0_countOnesLogic_15_21 = {_zz_s0_countOnesLogic_14,{_zz_s0_countOnesLogic_13,_zz_s0_countOnesLogic_12}}; + assign _zz_io_output_usedUntil_5 = {_zz_io_output_usedUntil_3,{_zz_io_output_usedUntil_2,{_zz_io_output_usedUntil_1,_zz_io_output_usedUntil}}}; + assign _zz_s1_outputPayload_selValid_240 = _zz_s1_outputPayload_selValid_6; + assign _zz_s1_outputPayload_selValid_241 = {_zz_s1_outputPayload_selValid_5,{_zz_s1_outputPayload_selValid_4,{_zz_s1_outputPayload_selValid_3,{_zz_s1_outputPayload_selValid_2,{_zz_s1_outputPayload_selValid_1,{_zz_s1_outputPayload_selValid,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0000))}}}}}}; + assign _zz_s1_outputPayload_selValid_242 = _zz_s1_outputPayload_selValid_21; + assign _zz_s1_outputPayload_selValid_243 = {_zz_s1_outputPayload_selValid_20,{_zz_s1_outputPayload_selValid_19,{_zz_s1_outputPayload_selValid_18,{_zz_s1_outputPayload_selValid_17,{_zz_s1_outputPayload_selValid_16,{_zz_s1_outputPayload_selValid_15,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0001))}}}}}}; + assign _zz_s1_outputPayload_selValid_244 = _zz_s1_outputPayload_selValid_36; + assign _zz_s1_outputPayload_selValid_245 = {_zz_s1_outputPayload_selValid_35,{_zz_s1_outputPayload_selValid_34,{_zz_s1_outputPayload_selValid_33,{_zz_s1_outputPayload_selValid_32,{_zz_s1_outputPayload_selValid_31,{_zz_s1_outputPayload_selValid_30,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0010))}}}}}}; + assign _zz_s1_outputPayload_selValid_246 = _zz_s1_outputPayload_selValid_51; + assign _zz_s1_outputPayload_selValid_247 = {_zz_s1_outputPayload_selValid_50,{_zz_s1_outputPayload_selValid_49,{_zz_s1_outputPayload_selValid_48,{_zz_s1_outputPayload_selValid_47,{_zz_s1_outputPayload_selValid_46,{_zz_s1_outputPayload_selValid_45,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0011))}}}}}}; + assign _zz_s1_outputPayload_selValid_248 = _zz_s1_outputPayload_selValid_66; + assign _zz_s1_outputPayload_selValid_249 = {_zz_s1_outputPayload_selValid_65,{_zz_s1_outputPayload_selValid_64,{_zz_s1_outputPayload_selValid_63,{_zz_s1_outputPayload_selValid_62,{_zz_s1_outputPayload_selValid_61,{_zz_s1_outputPayload_selValid_60,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0100))}}}}}}; + assign _zz_s1_outputPayload_selValid_250 = _zz_s1_outputPayload_selValid_81; + assign _zz_s1_outputPayload_selValid_251 = {_zz_s1_outputPayload_selValid_80,{_zz_s1_outputPayload_selValid_79,{_zz_s1_outputPayload_selValid_78,{_zz_s1_outputPayload_selValid_77,{_zz_s1_outputPayload_selValid_76,{_zz_s1_outputPayload_selValid_75,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0101))}}}}}}; + assign _zz_s1_outputPayload_selValid_252 = _zz_s1_outputPayload_selValid_96; + assign _zz_s1_outputPayload_selValid_253 = {_zz_s1_outputPayload_selValid_95,{_zz_s1_outputPayload_selValid_94,{_zz_s1_outputPayload_selValid_93,{_zz_s1_outputPayload_selValid_92,{_zz_s1_outputPayload_selValid_91,{_zz_s1_outputPayload_selValid_90,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0110))}}}}}}; + assign _zz_s1_outputPayload_selValid_254 = _zz_s1_outputPayload_selValid_111; + assign _zz_s1_outputPayload_selValid_255 = {_zz_s1_outputPayload_selValid_110,{_zz_s1_outputPayload_selValid_109,{_zz_s1_outputPayload_selValid_108,{_zz_s1_outputPayload_selValid_107,{_zz_s1_outputPayload_selValid_106,{_zz_s1_outputPayload_selValid_105,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0111))}}}}}}; + assign _zz_s1_outputPayload_selValid_256 = _zz_s1_outputPayload_selValid_126; + assign _zz_s1_outputPayload_selValid_257 = {_zz_s1_outputPayload_selValid_125,{_zz_s1_outputPayload_selValid_124,{_zz_s1_outputPayload_selValid_123,{_zz_s1_outputPayload_selValid_122,{_zz_s1_outputPayload_selValid_121,{_zz_s1_outputPayload_selValid_120,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1000))}}}}}}; + assign _zz_s1_outputPayload_selValid_258 = _zz_s1_outputPayload_selValid_141; + assign _zz_s1_outputPayload_selValid_259 = {_zz_s1_outputPayload_selValid_140,{_zz_s1_outputPayload_selValid_139,{_zz_s1_outputPayload_selValid_138,{_zz_s1_outputPayload_selValid_137,{_zz_s1_outputPayload_selValid_136,{_zz_s1_outputPayload_selValid_135,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1001))}}}}}}; + assign _zz_s1_outputPayload_selValid_260 = _zz_s1_outputPayload_selValid_156; + assign _zz_s1_outputPayload_selValid_261 = {_zz_s1_outputPayload_selValid_155,{_zz_s1_outputPayload_selValid_154,{_zz_s1_outputPayload_selValid_153,{_zz_s1_outputPayload_selValid_152,{_zz_s1_outputPayload_selValid_151,{_zz_s1_outputPayload_selValid_150,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1010))}}}}}}; + assign _zz_s1_outputPayload_selValid_262 = _zz_s1_outputPayload_selValid_171; + assign _zz_s1_outputPayload_selValid_263 = {_zz_s1_outputPayload_selValid_170,{_zz_s1_outputPayload_selValid_169,{_zz_s1_outputPayload_selValid_168,{_zz_s1_outputPayload_selValid_167,{_zz_s1_outputPayload_selValid_166,{_zz_s1_outputPayload_selValid_165,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1011))}}}}}}; + assign _zz_s1_outputPayload_selValid_264 = _zz_s1_outputPayload_selValid_186; + assign _zz_s1_outputPayload_selValid_265 = {_zz_s1_outputPayload_selValid_185,{_zz_s1_outputPayload_selValid_184,{_zz_s1_outputPayload_selValid_183,{_zz_s1_outputPayload_selValid_182,{_zz_s1_outputPayload_selValid_181,{_zz_s1_outputPayload_selValid_180,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1100))}}}}}}; + assign _zz_s1_outputPayload_selValid_266 = _zz_s1_outputPayload_selValid_201; + assign _zz_s1_outputPayload_selValid_267 = {_zz_s1_outputPayload_selValid_200,{_zz_s1_outputPayload_selValid_199,{_zz_s1_outputPayload_selValid_198,{_zz_s1_outputPayload_selValid_197,{_zz_s1_outputPayload_selValid_196,{_zz_s1_outputPayload_selValid_195,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1101))}}}}}}; + assign _zz_s1_outputPayload_selValid_268 = _zz_s1_outputPayload_selValid_216; + assign _zz_s1_outputPayload_selValid_269 = {_zz_s1_outputPayload_selValid_215,{_zz_s1_outputPayload_selValid_214,{_zz_s1_outputPayload_selValid_213,{_zz_s1_outputPayload_selValid_212,{_zz_s1_outputPayload_selValid_211,{_zz_s1_outputPayload_selValid_210,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1110))}}}}}}; + assign _zz_s1_outputPayload_selValid_270 = _zz_s1_outputPayload_selValid_231; + assign _zz_s1_outputPayload_selValid_271 = {_zz_s1_outputPayload_selValid_230,{_zz_s1_outputPayload_selValid_229,{_zz_s1_outputPayload_selValid_228,{_zz_s1_outputPayload_selValid_227,{_zz_s1_outputPayload_selValid_226,{_zz_s1_outputPayload_selValid_225,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1111))}}}}}}; + always @(*) begin + case(_zz_s0_countOnesLogic_0_2) + 1'b0 : _zz_s0_countOnesLogic_0_1 = 1'b0; + default : _zz_s0_countOnesLogic_0_1 = 1'b1; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_1_2) + 2'b00 : _zz_s0_countOnesLogic_1_1 = 2'b00; + 2'b01 : _zz_s0_countOnesLogic_1_1 = 2'b01; + 2'b10 : _zz_s0_countOnesLogic_1_1 = 2'b01; + default : _zz_s0_countOnesLogic_1_1 = 2'b10; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_2_2) + 3'b000 : _zz_s0_countOnesLogic_2_1 = 2'b00; + 3'b001 : _zz_s0_countOnesLogic_2_1 = 2'b01; + 3'b010 : _zz_s0_countOnesLogic_2_1 = 2'b01; + 3'b011 : _zz_s0_countOnesLogic_2_1 = 2'b10; + 3'b100 : _zz_s0_countOnesLogic_2_1 = 2'b01; + 3'b101 : _zz_s0_countOnesLogic_2_1 = 2'b10; + 3'b110 : _zz_s0_countOnesLogic_2_1 = 2'b10; + default : _zz_s0_countOnesLogic_2_1 = 2'b11; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_3_10) + 3'b000 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_1; + 3'b001 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_2; + 3'b010 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_3; + 3'b011 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_4; + 3'b100 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_5; + 3'b101 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_6; + 3'b110 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_7; + default : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_3_12) + 3'b000 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_1; + 3'b001 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_2; + 3'b010 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_3; + 3'b011 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_4; + 3'b100 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_5; + 3'b101 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_6; + 3'b110 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_7; + default : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_4_10) + 3'b000 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_1; + 3'b001 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_2; + 3'b010 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_3; + 3'b011 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_4; + 3'b100 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_5; + 3'b101 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_6; + 3'b110 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_7; + default : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_4_12) + 3'b000 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_1; + 3'b001 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_2; + 3'b010 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_3; + 3'b011 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_4; + 3'b100 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_5; + 3'b101 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_6; + 3'b110 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_7; + default : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_5_10) + 3'b000 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_1; + 3'b001 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_2; + 3'b010 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_3; + 3'b011 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_4; + 3'b100 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_5; + 3'b101 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_6; + 3'b110 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_7; + default : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_5_12) + 3'b000 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_1; + 3'b001 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_2; + 3'b010 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_3; + 3'b011 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_4; + 3'b100 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_5; + 3'b101 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_6; + 3'b110 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_7; + default : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_6_11) + 3'b000 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_1; + 3'b001 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_2; + 3'b010 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_3; + 3'b011 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_4; + 3'b100 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_5; + 3'b101 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_6; + 3'b110 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_7; + default : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_6_13) + 3'b000 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_1; + 3'b001 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_2; + 3'b010 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_3; + 3'b011 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_4; + 3'b100 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_5; + 3'b101 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_6; + 3'b110 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_7; + default : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_6_15) + 3'b000 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_1; + 3'b001 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_2; + 3'b010 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_3; + 3'b011 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_4; + 3'b100 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_5; + 3'b101 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_6; + 3'b110 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_7; + default : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_7_11) + 3'b000 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_1; + 3'b001 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_2; + 3'b010 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_3; + 3'b011 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_4; + 3'b100 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_5; + 3'b101 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_6; + 3'b110 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_7; + default : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_7_13) + 3'b000 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_1; + 3'b001 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_2; + 3'b010 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_3; + 3'b011 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_4; + 3'b100 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_5; + 3'b101 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_6; + 3'b110 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_7; + default : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_7_15) + 3'b000 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_1; + 3'b001 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_2; + 3'b010 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_3; + 3'b011 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_4; + 3'b100 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_5; + 3'b101 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_6; + 3'b110 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_7; + default : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_8_11) + 3'b000 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_1; + 3'b001 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_2; + 3'b010 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_3; + 3'b011 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_4; + 3'b100 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_5; + 3'b101 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_6; + 3'b110 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_7; + default : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_8_13) + 3'b000 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_1; + 3'b001 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_2; + 3'b010 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_3; + 3'b011 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_4; + 3'b100 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_5; + 3'b101 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_6; + 3'b110 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_7; + default : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_8_15) + 3'b000 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_1; + 3'b001 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_2; + 3'b010 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_3; + 3'b011 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_4; + 3'b100 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_5; + 3'b101 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_6; + 3'b110 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_7; + default : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_9_11) + 3'b000 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_1; + 3'b001 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_2; + 3'b010 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_3; + 3'b011 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_4; + 3'b100 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_5; + 3'b101 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_6; + 3'b110 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_7; + default : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_9_13) + 3'b000 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_1; + 3'b001 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_2; + 3'b010 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_3; + 3'b011 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_4; + 3'b100 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_5; + 3'b101 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_6; + 3'b110 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_7; + default : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_9_16) + 3'b000 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_1; + 3'b001 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_2; + 3'b010 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_3; + 3'b011 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_4; + 3'b100 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_5; + 3'b101 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_6; + 3'b110 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_7; + default : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_9_18) + 3'b000 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_1; + 3'b001 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_2; + 3'b010 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_3; + 3'b011 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_4; + 3'b100 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_5; + 3'b101 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_6; + 3'b110 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_7; + default : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_10_11) + 3'b000 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_1; + 3'b001 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_2; + 3'b010 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_3; + 3'b011 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_4; + 3'b100 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_5; + 3'b101 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_6; + 3'b110 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_7; + default : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_10_13) + 3'b000 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_1; + 3'b001 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_2; + 3'b010 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_3; + 3'b011 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_4; + 3'b100 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_5; + 3'b101 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_6; + 3'b110 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_7; + default : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_10_16) + 3'b000 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_1; + 3'b001 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_2; + 3'b010 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_3; + 3'b011 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_4; + 3'b100 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_5; + 3'b101 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_6; + 3'b110 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_7; + default : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_10_18) + 3'b000 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_1; + 3'b001 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_2; + 3'b010 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_3; + 3'b011 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_4; + 3'b100 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_5; + 3'b101 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_6; + 3'b110 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_7; + default : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_11_11) + 3'b000 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_1; + 3'b001 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_2; + 3'b010 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_3; + 3'b011 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_4; + 3'b100 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_5; + 3'b101 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_6; + 3'b110 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_7; + default : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_11_13) + 3'b000 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_1; + 3'b001 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_2; + 3'b010 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_3; + 3'b011 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_4; + 3'b100 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_5; + 3'b101 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_6; + 3'b110 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_7; + default : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_11_16) + 3'b000 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_1; + 3'b001 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_2; + 3'b010 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_3; + 3'b011 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_4; + 3'b100 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_5; + 3'b101 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_6; + 3'b110 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_7; + default : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_11_18) + 3'b000 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_1; + 3'b001 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_2; + 3'b010 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_3; + 3'b011 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_4; + 3'b100 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_5; + 3'b101 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_6; + 3'b110 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_7; + default : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_12_12) + 3'b000 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_1; + 3'b001 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_2; + 3'b010 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_3; + 3'b011 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_4; + 3'b100 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_5; + 3'b101 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_6; + 3'b110 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_7; + default : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_12_14) + 3'b000 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_1; + 3'b001 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_2; + 3'b010 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_3; + 3'b011 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_4; + 3'b100 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_5; + 3'b101 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_6; + 3'b110 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_7; + default : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_12_17) + 3'b000 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_1; + 3'b001 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_2; + 3'b010 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_3; + 3'b011 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_4; + 3'b100 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_5; + 3'b101 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_6; + 3'b110 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_7; + default : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_12_19) + 3'b000 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_1; + 3'b001 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_2; + 3'b010 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_3; + 3'b011 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_4; + 3'b100 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_5; + 3'b101 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_6; + 3'b110 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_7; + default : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_12_21) + 3'b000 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_1; + 3'b001 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_2; + 3'b010 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_3; + 3'b011 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_4; + 3'b100 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_5; + 3'b101 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_6; + 3'b110 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_7; + default : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_13_12) + 3'b000 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_1; + 3'b001 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_2; + 3'b010 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_3; + 3'b011 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_4; + 3'b100 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_5; + 3'b101 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_6; + 3'b110 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_7; + default : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_13_14) + 3'b000 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_1; + 3'b001 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_2; + 3'b010 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_3; + 3'b011 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_4; + 3'b100 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_5; + 3'b101 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_6; + 3'b110 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_7; + default : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_13_17) + 3'b000 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_1; + 3'b001 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_2; + 3'b010 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_3; + 3'b011 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_4; + 3'b100 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_5; + 3'b101 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_6; + 3'b110 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_7; + default : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_13_19) + 3'b000 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_1; + 3'b001 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_2; + 3'b010 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_3; + 3'b011 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_4; + 3'b100 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_5; + 3'b101 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_6; + 3'b110 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_7; + default : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_13_21) + 3'b000 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_1; + 3'b001 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_2; + 3'b010 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_3; + 3'b011 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_4; + 3'b100 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_5; + 3'b101 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_6; + 3'b110 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_7; + default : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_14_12) + 3'b000 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_1; + 3'b001 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_2; + 3'b010 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_3; + 3'b011 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_4; + 3'b100 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_5; + 3'b101 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_6; + 3'b110 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_7; + default : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_14_14) + 3'b000 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_1; + 3'b001 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_2; + 3'b010 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_3; + 3'b011 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_4; + 3'b100 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_5; + 3'b101 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_6; + 3'b110 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_7; + default : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_14_17) + 3'b000 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_1; + 3'b001 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_2; + 3'b010 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_3; + 3'b011 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_4; + 3'b100 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_5; + 3'b101 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_6; + 3'b110 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_7; + default : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_14_19) + 3'b000 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_1; + 3'b001 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_2; + 3'b010 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_3; + 3'b011 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_4; + 3'b100 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_5; + 3'b101 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_6; + 3'b110 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_7; + default : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_14_21) + 3'b000 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_1; + 3'b001 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_2; + 3'b010 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_3; + 3'b011 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_4; + 3'b100 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_5; + 3'b101 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_6; + 3'b110 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_7; + default : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_11) + 3'b000 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_13) + 3'b000 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_16) + 3'b000 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_18) + 3'b000 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_21) + 3'b000 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_23) + 3'b000 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_0) + 4'b0000 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_1) + 4'b0000 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_2) + 4'b0000 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_3) + 4'b0000 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_4) + 4'b0000 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_5) + 4'b0000 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_6) + 4'b0000 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_7) + 4'b0000 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_8) + 4'b0000 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_9) + 4'b0000 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_10) + 4'b0000 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_11) + 4'b0000 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_12) + 4'b0000 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_13) + 4'b0000 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_14) + 4'b0000 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_15) + 4'b0000 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(_zz_io_output_usedUntil_5) + 4'b0000 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_0; + 4'b0001 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_1; + 4'b0010 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_2; + 4'b0011 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_3; + 4'b0100 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_4; + 4'b0101 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_5; + 4'b0110 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_6; + 4'b0111 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_7; + 4'b1000 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_8; + 4'b1001 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_9; + 4'b1010 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_10; + 4'b1011 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_11; + 4'b1100 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_12; + 4'b1101 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_13; + 4'b1110 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_14; + default : _zz_io_output_usedUntil_4 = s2_input_payload_sel_15; + endcase + end + + always @(*) begin + io_input_ready = s0_input_ready; + if(when_Stream_l375) begin + io_input_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! s0_input_valid); + assign s0_input_valid = io_input_rValid; + assign s0_input_payload_data = io_input_rData_data; + assign s0_input_payload_mask = io_input_rData_mask; + assign _zz_s0_countOnesLogic_0 = s0_input_payload_mask[0]; + assign _zz_s0_countOnesLogic_1 = s0_input_payload_mask[1]; + assign _zz_s0_countOnesLogic_2 = s0_input_payload_mask[2]; + assign _zz_s0_countOnesLogic_3 = s0_input_payload_mask[3]; + assign _zz_s0_countOnesLogic_4 = s0_input_payload_mask[4]; + assign _zz_s0_countOnesLogic_5 = s0_input_payload_mask[5]; + assign _zz_s0_countOnesLogic_6 = s0_input_payload_mask[6]; + assign _zz_s0_countOnesLogic_7 = s0_input_payload_mask[7]; + assign _zz_s0_countOnesLogic_8 = s0_input_payload_mask[8]; + assign _zz_s0_countOnesLogic_9 = s0_input_payload_mask[9]; + assign _zz_s0_countOnesLogic_10 = s0_input_payload_mask[10]; + assign _zz_s0_countOnesLogic_11 = s0_input_payload_mask[11]; + assign _zz_s0_countOnesLogic_12 = s0_input_payload_mask[12]; + assign _zz_s0_countOnesLogic_13 = s0_input_payload_mask[13]; + assign _zz_s0_countOnesLogic_14 = s0_input_payload_mask[14]; + assign s0_countOnesLogic_0 = _zz_s0_countOnesLogic_0_1; + assign s0_countOnesLogic_1 = _zz_s0_countOnesLogic_1_1; + assign s0_countOnesLogic_2 = _zz_s0_countOnesLogic_2_1; + assign _zz_s0_countOnesLogic_3_1 = 3'b000; + assign _zz_s0_countOnesLogic_3_2 = 3'b001; + assign _zz_s0_countOnesLogic_3_3 = 3'b001; + assign _zz_s0_countOnesLogic_3_4 = 3'b010; + assign _zz_s0_countOnesLogic_3_5 = 3'b001; + assign _zz_s0_countOnesLogic_3_6 = 3'b010; + assign _zz_s0_countOnesLogic_3_7 = 3'b010; + assign _zz_s0_countOnesLogic_3_8 = 3'b011; + assign s0_countOnesLogic_3 = (_zz_s0_countOnesLogic_3_9 + _zz_s0_countOnesLogic_3_11); + assign _zz_s0_countOnesLogic_4_1 = 3'b000; + assign _zz_s0_countOnesLogic_4_2 = 3'b001; + assign _zz_s0_countOnesLogic_4_3 = 3'b001; + assign _zz_s0_countOnesLogic_4_4 = 3'b010; + assign _zz_s0_countOnesLogic_4_5 = 3'b001; + assign _zz_s0_countOnesLogic_4_6 = 3'b010; + assign _zz_s0_countOnesLogic_4_7 = 3'b010; + assign _zz_s0_countOnesLogic_4_8 = 3'b011; + assign s0_countOnesLogic_4 = (_zz_s0_countOnesLogic_4_9 + _zz_s0_countOnesLogic_4_11); + assign _zz_s0_countOnesLogic_5_1 = 3'b000; + assign _zz_s0_countOnesLogic_5_2 = 3'b001; + assign _zz_s0_countOnesLogic_5_3 = 3'b001; + assign _zz_s0_countOnesLogic_5_4 = 3'b010; + assign _zz_s0_countOnesLogic_5_5 = 3'b001; + assign _zz_s0_countOnesLogic_5_6 = 3'b010; + assign _zz_s0_countOnesLogic_5_7 = 3'b010; + assign _zz_s0_countOnesLogic_5_8 = 3'b011; + assign s0_countOnesLogic_5 = (_zz_s0_countOnesLogic_5_9 + _zz_s0_countOnesLogic_5_11); + assign _zz_s0_countOnesLogic_6_1 = 3'b000; + assign _zz_s0_countOnesLogic_6_2 = 3'b001; + assign _zz_s0_countOnesLogic_6_3 = 3'b001; + assign _zz_s0_countOnesLogic_6_4 = 3'b010; + assign _zz_s0_countOnesLogic_6_5 = 3'b001; + assign _zz_s0_countOnesLogic_6_6 = 3'b010; + assign _zz_s0_countOnesLogic_6_7 = 3'b010; + assign _zz_s0_countOnesLogic_6_8 = 3'b011; + assign s0_countOnesLogic_6 = (_zz_s0_countOnesLogic_6_9 + _zz_s0_countOnesLogic_6_14); + assign _zz_s0_countOnesLogic_7_1 = 4'b0000; + assign _zz_s0_countOnesLogic_7_2 = 4'b0001; + assign _zz_s0_countOnesLogic_7_3 = 4'b0001; + assign _zz_s0_countOnesLogic_7_4 = 4'b0010; + assign _zz_s0_countOnesLogic_7_5 = 4'b0001; + assign _zz_s0_countOnesLogic_7_6 = 4'b0010; + assign _zz_s0_countOnesLogic_7_7 = 4'b0010; + assign _zz_s0_countOnesLogic_7_8 = 4'b0011; + assign s0_countOnesLogic_7 = (_zz_s0_countOnesLogic_7_9 + _zz_s0_countOnesLogic_7_14); + assign _zz_s0_countOnesLogic_8_1 = 4'b0000; + assign _zz_s0_countOnesLogic_8_2 = 4'b0001; + assign _zz_s0_countOnesLogic_8_3 = 4'b0001; + assign _zz_s0_countOnesLogic_8_4 = 4'b0010; + assign _zz_s0_countOnesLogic_8_5 = 4'b0001; + assign _zz_s0_countOnesLogic_8_6 = 4'b0010; + assign _zz_s0_countOnesLogic_8_7 = 4'b0010; + assign _zz_s0_countOnesLogic_8_8 = 4'b0011; + assign s0_countOnesLogic_8 = (_zz_s0_countOnesLogic_8_9 + _zz_s0_countOnesLogic_8_14); + assign _zz_s0_countOnesLogic_9_1 = 4'b0000; + assign _zz_s0_countOnesLogic_9_2 = 4'b0001; + assign _zz_s0_countOnesLogic_9_3 = 4'b0001; + assign _zz_s0_countOnesLogic_9_4 = 4'b0010; + assign _zz_s0_countOnesLogic_9_5 = 4'b0001; + assign _zz_s0_countOnesLogic_9_6 = 4'b0010; + assign _zz_s0_countOnesLogic_9_7 = 4'b0010; + assign _zz_s0_countOnesLogic_9_8 = 4'b0011; + assign s0_countOnesLogic_9 = (_zz_s0_countOnesLogic_9_9 + _zz_s0_countOnesLogic_9_14); + assign _zz_s0_countOnesLogic_10_1 = 4'b0000; + assign _zz_s0_countOnesLogic_10_2 = 4'b0001; + assign _zz_s0_countOnesLogic_10_3 = 4'b0001; + assign _zz_s0_countOnesLogic_10_4 = 4'b0010; + assign _zz_s0_countOnesLogic_10_5 = 4'b0001; + assign _zz_s0_countOnesLogic_10_6 = 4'b0010; + assign _zz_s0_countOnesLogic_10_7 = 4'b0010; + assign _zz_s0_countOnesLogic_10_8 = 4'b0011; + assign s0_countOnesLogic_10 = (_zz_s0_countOnesLogic_10_9 + _zz_s0_countOnesLogic_10_14); + assign _zz_s0_countOnesLogic_11_1 = 4'b0000; + assign _zz_s0_countOnesLogic_11_2 = 4'b0001; + assign _zz_s0_countOnesLogic_11_3 = 4'b0001; + assign _zz_s0_countOnesLogic_11_4 = 4'b0010; + assign _zz_s0_countOnesLogic_11_5 = 4'b0001; + assign _zz_s0_countOnesLogic_11_6 = 4'b0010; + assign _zz_s0_countOnesLogic_11_7 = 4'b0010; + assign _zz_s0_countOnesLogic_11_8 = 4'b0011; + assign s0_countOnesLogic_11 = (_zz_s0_countOnesLogic_11_9 + _zz_s0_countOnesLogic_11_14); + assign _zz_s0_countOnesLogic_12_1 = 4'b0000; + assign _zz_s0_countOnesLogic_12_2 = 4'b0001; + assign _zz_s0_countOnesLogic_12_3 = 4'b0001; + assign _zz_s0_countOnesLogic_12_4 = 4'b0010; + assign _zz_s0_countOnesLogic_12_5 = 4'b0001; + assign _zz_s0_countOnesLogic_12_6 = 4'b0010; + assign _zz_s0_countOnesLogic_12_7 = 4'b0010; + assign _zz_s0_countOnesLogic_12_8 = 4'b0011; + assign s0_countOnesLogic_12 = (_zz_s0_countOnesLogic_12_9 + _zz_s0_countOnesLogic_12_20); + assign _zz_s0_countOnesLogic_13_1 = 4'b0000; + assign _zz_s0_countOnesLogic_13_2 = 4'b0001; + assign _zz_s0_countOnesLogic_13_3 = 4'b0001; + assign _zz_s0_countOnesLogic_13_4 = 4'b0010; + assign _zz_s0_countOnesLogic_13_5 = 4'b0001; + assign _zz_s0_countOnesLogic_13_6 = 4'b0010; + assign _zz_s0_countOnesLogic_13_7 = 4'b0010; + assign _zz_s0_countOnesLogic_13_8 = 4'b0011; + assign s0_countOnesLogic_13 = (_zz_s0_countOnesLogic_13_9 + _zz_s0_countOnesLogic_13_20); + assign _zz_s0_countOnesLogic_14_1 = 4'b0000; + assign _zz_s0_countOnesLogic_14_2 = 4'b0001; + assign _zz_s0_countOnesLogic_14_3 = 4'b0001; + assign _zz_s0_countOnesLogic_14_4 = 4'b0010; + assign _zz_s0_countOnesLogic_14_5 = 4'b0001; + assign _zz_s0_countOnesLogic_14_6 = 4'b0010; + assign _zz_s0_countOnesLogic_14_7 = 4'b0010; + assign _zz_s0_countOnesLogic_14_8 = 4'b0011; + assign s0_countOnesLogic_14 = (_zz_s0_countOnesLogic_14_9 + _zz_s0_countOnesLogic_14_20); + assign _zz_s0_countOnesLogic_15 = 5'h0; + assign _zz_s0_countOnesLogic_15_1 = 5'h01; + assign _zz_s0_countOnesLogic_15_2 = 5'h01; + assign _zz_s0_countOnesLogic_15_3 = 5'h02; + assign _zz_s0_countOnesLogic_15_4 = 5'h01; + assign _zz_s0_countOnesLogic_15_5 = 5'h02; + assign _zz_s0_countOnesLogic_15_6 = 5'h02; + assign _zz_s0_countOnesLogic_15_7 = 5'h03; + assign s0_countOnesLogic_15 = (_zz_s0_countOnesLogic_15_8 + _zz_s0_countOnesLogic_15_19); + assign s0_outputPayload_cmd_data = s0_input_payload_data; + assign s0_outputPayload_cmd_mask = s0_input_payload_mask; + assign s0_outputPayload_countOnes_0 = s0_countOnesLogic_0; + assign s0_outputPayload_countOnes_1 = s0_countOnesLogic_1; + assign s0_outputPayload_countOnes_2 = s0_countOnesLogic_2; + assign s0_outputPayload_countOnes_3 = s0_countOnesLogic_3; + assign s0_outputPayload_countOnes_4 = s0_countOnesLogic_4; + assign s0_outputPayload_countOnes_5 = s0_countOnesLogic_5; + assign s0_outputPayload_countOnes_6 = s0_countOnesLogic_6; + assign s0_outputPayload_countOnes_7 = s0_countOnesLogic_7; + assign s0_outputPayload_countOnes_8 = s0_countOnesLogic_8; + assign s0_outputPayload_countOnes_9 = s0_countOnesLogic_9; + assign s0_outputPayload_countOnes_10 = s0_countOnesLogic_10; + assign s0_outputPayload_countOnes_11 = s0_countOnesLogic_11; + assign s0_outputPayload_countOnes_12 = s0_countOnesLogic_12; + assign s0_outputPayload_countOnes_13 = s0_countOnesLogic_13; + assign s0_outputPayload_countOnes_14 = s0_countOnesLogic_14; + assign s0_outputPayload_countOnes_15 = s0_countOnesLogic_15; + assign s0_output_valid = s0_input_valid; + assign s0_input_ready = s0_output_ready; + assign s0_output_payload_cmd_data = s0_outputPayload_cmd_data; + assign s0_output_payload_cmd_mask = s0_outputPayload_cmd_mask; + assign s0_output_payload_countOnes_0 = s0_outputPayload_countOnes_0; + assign s0_output_payload_countOnes_1 = s0_outputPayload_countOnes_1; + assign s0_output_payload_countOnes_2 = s0_outputPayload_countOnes_2; + assign s0_output_payload_countOnes_3 = s0_outputPayload_countOnes_3; + assign s0_output_payload_countOnes_4 = s0_outputPayload_countOnes_4; + assign s0_output_payload_countOnes_5 = s0_outputPayload_countOnes_5; + assign s0_output_payload_countOnes_6 = s0_outputPayload_countOnes_6; + assign s0_output_payload_countOnes_7 = s0_outputPayload_countOnes_7; + assign s0_output_payload_countOnes_8 = s0_outputPayload_countOnes_8; + assign s0_output_payload_countOnes_9 = s0_outputPayload_countOnes_9; + assign s0_output_payload_countOnes_10 = s0_outputPayload_countOnes_10; + assign s0_output_payload_countOnes_11 = s0_outputPayload_countOnes_11; + assign s0_output_payload_countOnes_12 = s0_outputPayload_countOnes_12; + assign s0_output_payload_countOnes_13 = s0_outputPayload_countOnes_13; + assign s0_output_payload_countOnes_14 = s0_outputPayload_countOnes_14; + assign s0_output_payload_countOnes_15 = s0_outputPayload_countOnes_15; + always @(*) begin + s0_output_ready = s1_input_ready; + if(when_Stream_l375_1) begin + s0_output_ready = 1'b1; + end + end + + assign when_Stream_l375_1 = (! s1_input_valid); + assign s1_input_valid = s0_output_rValid; + assign s1_input_payload_cmd_data = s0_output_rData_cmd_data; + assign s1_input_payload_cmd_mask = s0_output_rData_cmd_mask; + assign s1_input_payload_countOnes_0 = s0_output_rData_countOnes_0; + assign s1_input_payload_countOnes_1 = s0_output_rData_countOnes_1; + assign s1_input_payload_countOnes_2 = s0_output_rData_countOnes_2; + assign s1_input_payload_countOnes_3 = s0_output_rData_countOnes_3; + assign s1_input_payload_countOnes_4 = s0_output_rData_countOnes_4; + assign s1_input_payload_countOnes_5 = s0_output_rData_countOnes_5; + assign s1_input_payload_countOnes_6 = s0_output_rData_countOnes_6; + assign s1_input_payload_countOnes_7 = s0_output_rData_countOnes_7; + assign s1_input_payload_countOnes_8 = s0_output_rData_countOnes_8; + assign s1_input_payload_countOnes_9 = s0_output_rData_countOnes_9; + assign s1_input_payload_countOnes_10 = s0_output_rData_countOnes_10; + assign s1_input_payload_countOnes_11 = s0_output_rData_countOnes_11; + assign s1_input_payload_countOnes_12 = s0_output_rData_countOnes_12; + assign s1_input_payload_countOnes_13 = s0_output_rData_countOnes_13; + assign s1_input_payload_countOnes_14 = s0_output_rData_countOnes_14; + assign s1_input_payload_countOnes_15 = s0_output_rData_countOnes_15; + assign s1_offsetNext = (_zz_s1_offsetNext + s1_input_payload_countOnes_15); + assign s1_input_fire = (s1_input_valid && s1_input_ready); + assign s1_inputIndexes_0 = (4'b0000 + s1_offset); + assign s1_inputIndexes_1 = (_zz_s1_inputIndexes_1 + s1_offset); + assign s1_inputIndexes_2 = (_zz_s1_inputIndexes_2 + s1_offset); + assign s1_inputIndexes_3 = (_zz_s1_inputIndexes_3 + s1_offset); + assign s1_inputIndexes_4 = (_zz_s1_inputIndexes_4 + s1_offset); + assign s1_inputIndexes_5 = (_zz_s1_inputIndexes_5 + s1_offset); + assign s1_inputIndexes_6 = (_zz_s1_inputIndexes_6 + s1_offset); + assign s1_inputIndexes_7 = (_zz_s1_inputIndexes_7 + s1_offset); + assign s1_inputIndexes_8 = (s1_input_payload_countOnes_7 + s1_offset); + assign s1_inputIndexes_9 = (s1_input_payload_countOnes_8 + s1_offset); + assign s1_inputIndexes_10 = (s1_input_payload_countOnes_9 + s1_offset); + assign s1_inputIndexes_11 = (s1_input_payload_countOnes_10 + s1_offset); + assign s1_inputIndexes_12 = (s1_input_payload_countOnes_11 + s1_offset); + assign s1_inputIndexes_13 = (s1_input_payload_countOnes_12 + s1_offset); + assign s1_inputIndexes_14 = (s1_input_payload_countOnes_13 + s1_offset); + assign s1_inputIndexes_15 = (s1_input_payload_countOnes_14 + s1_offset); + assign s1_outputPayload_cmd_data = s1_input_payload_cmd_data; + assign s1_outputPayload_cmd_mask = s1_input_payload_cmd_mask; + assign s1_outputPayload_index_0 = s1_inputIndexes_0; + assign s1_outputPayload_index_1 = s1_inputIndexes_1; + assign s1_outputPayload_index_2 = s1_inputIndexes_2; + assign s1_outputPayload_index_3 = s1_inputIndexes_3; + assign s1_outputPayload_index_4 = s1_inputIndexes_4; + assign s1_outputPayload_index_5 = s1_inputIndexes_5; + assign s1_outputPayload_index_6 = s1_inputIndexes_6; + assign s1_outputPayload_index_7 = s1_inputIndexes_7; + assign s1_outputPayload_index_8 = s1_inputIndexes_8; + assign s1_outputPayload_index_9 = s1_inputIndexes_9; + assign s1_outputPayload_index_10 = s1_inputIndexes_10; + assign s1_outputPayload_index_11 = s1_inputIndexes_11; + assign s1_outputPayload_index_12 = s1_inputIndexes_12; + assign s1_outputPayload_index_13 = s1_inputIndexes_13; + assign s1_outputPayload_index_14 = s1_inputIndexes_14; + assign s1_outputPayload_index_15 = s1_inputIndexes_15; + assign s1_outputPayload_last = s1_offsetNext[4]; + assign _zz_s1_outputPayload_selValid = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_1 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_2 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_3 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_4 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_5 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_6 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_7 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_8 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_9 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_10 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_11 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_12 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_13 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_14 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0000)); + assign _zz_s1_outputPayload_sel_0 = (((((((_zz_s1_outputPayload_selValid || _zz_s1_outputPayload_selValid_2) || _zz_s1_outputPayload_selValid_4) || _zz_s1_outputPayload_selValid_6) || _zz_s1_outputPayload_selValid_8) || _zz_s1_outputPayload_selValid_10) || _zz_s1_outputPayload_selValid_12) || _zz_s1_outputPayload_selValid_14); + assign _zz_s1_outputPayload_sel_0_1 = (((((((_zz_s1_outputPayload_selValid_1 || _zz_s1_outputPayload_selValid_2) || _zz_s1_outputPayload_selValid_5) || _zz_s1_outputPayload_selValid_6) || _zz_s1_outputPayload_selValid_9) || _zz_s1_outputPayload_selValid_10) || _zz_s1_outputPayload_selValid_13) || _zz_s1_outputPayload_selValid_14); + assign _zz_s1_outputPayload_sel_0_2 = (((((((_zz_s1_outputPayload_selValid_3 || _zz_s1_outputPayload_selValid_4) || _zz_s1_outputPayload_selValid_5) || _zz_s1_outputPayload_selValid_6) || _zz_s1_outputPayload_selValid_11) || _zz_s1_outputPayload_selValid_12) || _zz_s1_outputPayload_selValid_13) || _zz_s1_outputPayload_selValid_14); + assign _zz_s1_outputPayload_sel_0_3 = (((((((_zz_s1_outputPayload_selValid_7 || _zz_s1_outputPayload_selValid_8) || _zz_s1_outputPayload_selValid_9) || _zz_s1_outputPayload_selValid_10) || _zz_s1_outputPayload_selValid_11) || _zz_s1_outputPayload_selValid_12) || _zz_s1_outputPayload_selValid_13) || _zz_s1_outputPayload_selValid_14); + assign s1_outputPayload_sel_0 = {_zz_s1_outputPayload_sel_0_3,{_zz_s1_outputPayload_sel_0_2,{_zz_s1_outputPayload_sel_0_1,_zz_s1_outputPayload_sel_0}}}; + always @(*) begin + s1_outputPayload_selValid[0] = ((|{_zz_s1_outputPayload_selValid_14,{_zz_s1_outputPayload_selValid_13,{_zz_s1_outputPayload_selValid_12,{_zz_s1_outputPayload_selValid_11,{_zz_s1_outputPayload_selValid_10,{_zz_s1_outputPayload_selValid_9,{_zz_s1_outputPayload_selValid_8,{_zz_s1_outputPayload_selValid_7,{_zz_s1_outputPayload_selValid_240,_zz_s1_outputPayload_selValid_241}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_0]); + s1_outputPayload_selValid[1] = ((|{_zz_s1_outputPayload_selValid_29,{_zz_s1_outputPayload_selValid_28,{_zz_s1_outputPayload_selValid_27,{_zz_s1_outputPayload_selValid_26,{_zz_s1_outputPayload_selValid_25,{_zz_s1_outputPayload_selValid_24,{_zz_s1_outputPayload_selValid_23,{_zz_s1_outputPayload_selValid_22,{_zz_s1_outputPayload_selValid_242,_zz_s1_outputPayload_selValid_243}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_1]); + s1_outputPayload_selValid[2] = ((|{_zz_s1_outputPayload_selValid_44,{_zz_s1_outputPayload_selValid_43,{_zz_s1_outputPayload_selValid_42,{_zz_s1_outputPayload_selValid_41,{_zz_s1_outputPayload_selValid_40,{_zz_s1_outputPayload_selValid_39,{_zz_s1_outputPayload_selValid_38,{_zz_s1_outputPayload_selValid_37,{_zz_s1_outputPayload_selValid_244,_zz_s1_outputPayload_selValid_245}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_2]); + s1_outputPayload_selValid[3] = ((|{_zz_s1_outputPayload_selValid_59,{_zz_s1_outputPayload_selValid_58,{_zz_s1_outputPayload_selValid_57,{_zz_s1_outputPayload_selValid_56,{_zz_s1_outputPayload_selValid_55,{_zz_s1_outputPayload_selValid_54,{_zz_s1_outputPayload_selValid_53,{_zz_s1_outputPayload_selValid_52,{_zz_s1_outputPayload_selValid_246,_zz_s1_outputPayload_selValid_247}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_3]); + s1_outputPayload_selValid[4] = ((|{_zz_s1_outputPayload_selValid_74,{_zz_s1_outputPayload_selValid_73,{_zz_s1_outputPayload_selValid_72,{_zz_s1_outputPayload_selValid_71,{_zz_s1_outputPayload_selValid_70,{_zz_s1_outputPayload_selValid_69,{_zz_s1_outputPayload_selValid_68,{_zz_s1_outputPayload_selValid_67,{_zz_s1_outputPayload_selValid_248,_zz_s1_outputPayload_selValid_249}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_4]); + s1_outputPayload_selValid[5] = ((|{_zz_s1_outputPayload_selValid_89,{_zz_s1_outputPayload_selValid_88,{_zz_s1_outputPayload_selValid_87,{_zz_s1_outputPayload_selValid_86,{_zz_s1_outputPayload_selValid_85,{_zz_s1_outputPayload_selValid_84,{_zz_s1_outputPayload_selValid_83,{_zz_s1_outputPayload_selValid_82,{_zz_s1_outputPayload_selValid_250,_zz_s1_outputPayload_selValid_251}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_5]); + s1_outputPayload_selValid[6] = ((|{_zz_s1_outputPayload_selValid_104,{_zz_s1_outputPayload_selValid_103,{_zz_s1_outputPayload_selValid_102,{_zz_s1_outputPayload_selValid_101,{_zz_s1_outputPayload_selValid_100,{_zz_s1_outputPayload_selValid_99,{_zz_s1_outputPayload_selValid_98,{_zz_s1_outputPayload_selValid_97,{_zz_s1_outputPayload_selValid_252,_zz_s1_outputPayload_selValid_253}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_6]); + s1_outputPayload_selValid[7] = ((|{_zz_s1_outputPayload_selValid_119,{_zz_s1_outputPayload_selValid_118,{_zz_s1_outputPayload_selValid_117,{_zz_s1_outputPayload_selValid_116,{_zz_s1_outputPayload_selValid_115,{_zz_s1_outputPayload_selValid_114,{_zz_s1_outputPayload_selValid_113,{_zz_s1_outputPayload_selValid_112,{_zz_s1_outputPayload_selValid_254,_zz_s1_outputPayload_selValid_255}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_7]); + s1_outputPayload_selValid[8] = ((|{_zz_s1_outputPayload_selValid_134,{_zz_s1_outputPayload_selValid_133,{_zz_s1_outputPayload_selValid_132,{_zz_s1_outputPayload_selValid_131,{_zz_s1_outputPayload_selValid_130,{_zz_s1_outputPayload_selValid_129,{_zz_s1_outputPayload_selValid_128,{_zz_s1_outputPayload_selValid_127,{_zz_s1_outputPayload_selValid_256,_zz_s1_outputPayload_selValid_257}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_8]); + s1_outputPayload_selValid[9] = ((|{_zz_s1_outputPayload_selValid_149,{_zz_s1_outputPayload_selValid_148,{_zz_s1_outputPayload_selValid_147,{_zz_s1_outputPayload_selValid_146,{_zz_s1_outputPayload_selValid_145,{_zz_s1_outputPayload_selValid_144,{_zz_s1_outputPayload_selValid_143,{_zz_s1_outputPayload_selValid_142,{_zz_s1_outputPayload_selValid_258,_zz_s1_outputPayload_selValid_259}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_9]); + s1_outputPayload_selValid[10] = ((|{_zz_s1_outputPayload_selValid_164,{_zz_s1_outputPayload_selValid_163,{_zz_s1_outputPayload_selValid_162,{_zz_s1_outputPayload_selValid_161,{_zz_s1_outputPayload_selValid_160,{_zz_s1_outputPayload_selValid_159,{_zz_s1_outputPayload_selValid_158,{_zz_s1_outputPayload_selValid_157,{_zz_s1_outputPayload_selValid_260,_zz_s1_outputPayload_selValid_261}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_10]); + s1_outputPayload_selValid[11] = ((|{_zz_s1_outputPayload_selValid_179,{_zz_s1_outputPayload_selValid_178,{_zz_s1_outputPayload_selValid_177,{_zz_s1_outputPayload_selValid_176,{_zz_s1_outputPayload_selValid_175,{_zz_s1_outputPayload_selValid_174,{_zz_s1_outputPayload_selValid_173,{_zz_s1_outputPayload_selValid_172,{_zz_s1_outputPayload_selValid_262,_zz_s1_outputPayload_selValid_263}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_11]); + s1_outputPayload_selValid[12] = ((|{_zz_s1_outputPayload_selValid_194,{_zz_s1_outputPayload_selValid_193,{_zz_s1_outputPayload_selValid_192,{_zz_s1_outputPayload_selValid_191,{_zz_s1_outputPayload_selValid_190,{_zz_s1_outputPayload_selValid_189,{_zz_s1_outputPayload_selValid_188,{_zz_s1_outputPayload_selValid_187,{_zz_s1_outputPayload_selValid_264,_zz_s1_outputPayload_selValid_265}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_12]); + s1_outputPayload_selValid[13] = ((|{_zz_s1_outputPayload_selValid_209,{_zz_s1_outputPayload_selValid_208,{_zz_s1_outputPayload_selValid_207,{_zz_s1_outputPayload_selValid_206,{_zz_s1_outputPayload_selValid_205,{_zz_s1_outputPayload_selValid_204,{_zz_s1_outputPayload_selValid_203,{_zz_s1_outputPayload_selValid_202,{_zz_s1_outputPayload_selValid_266,_zz_s1_outputPayload_selValid_267}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_13]); + s1_outputPayload_selValid[14] = ((|{_zz_s1_outputPayload_selValid_224,{_zz_s1_outputPayload_selValid_223,{_zz_s1_outputPayload_selValid_222,{_zz_s1_outputPayload_selValid_221,{_zz_s1_outputPayload_selValid_220,{_zz_s1_outputPayload_selValid_219,{_zz_s1_outputPayload_selValid_218,{_zz_s1_outputPayload_selValid_217,{_zz_s1_outputPayload_selValid_268,_zz_s1_outputPayload_selValid_269}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_14]); + s1_outputPayload_selValid[15] = ((|{_zz_s1_outputPayload_selValid_239,{_zz_s1_outputPayload_selValid_238,{_zz_s1_outputPayload_selValid_237,{_zz_s1_outputPayload_selValid_236,{_zz_s1_outputPayload_selValid_235,{_zz_s1_outputPayload_selValid_234,{_zz_s1_outputPayload_selValid_233,{_zz_s1_outputPayload_selValid_232,{_zz_s1_outputPayload_selValid_270,_zz_s1_outputPayload_selValid_271}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_15]); + end + + assign _zz_s1_outputPayload_selValid_15 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_16 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_17 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_18 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_19 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_20 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_21 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_22 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_23 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_24 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_25 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_26 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_27 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_28 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_29 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0001)); + assign _zz_s1_outputPayload_sel_1 = (((((((_zz_s1_outputPayload_selValid_15 || _zz_s1_outputPayload_selValid_17) || _zz_s1_outputPayload_selValid_19) || _zz_s1_outputPayload_selValid_21) || _zz_s1_outputPayload_selValid_23) || _zz_s1_outputPayload_selValid_25) || _zz_s1_outputPayload_selValid_27) || _zz_s1_outputPayload_selValid_29); + assign _zz_s1_outputPayload_sel_1_1 = (((((((_zz_s1_outputPayload_selValid_16 || _zz_s1_outputPayload_selValid_17) || _zz_s1_outputPayload_selValid_20) || _zz_s1_outputPayload_selValid_21) || _zz_s1_outputPayload_selValid_24) || _zz_s1_outputPayload_selValid_25) || _zz_s1_outputPayload_selValid_28) || _zz_s1_outputPayload_selValid_29); + assign _zz_s1_outputPayload_sel_1_2 = (((((((_zz_s1_outputPayload_selValid_18 || _zz_s1_outputPayload_selValid_19) || _zz_s1_outputPayload_selValid_20) || _zz_s1_outputPayload_selValid_21) || _zz_s1_outputPayload_selValid_26) || _zz_s1_outputPayload_selValid_27) || _zz_s1_outputPayload_selValid_28) || _zz_s1_outputPayload_selValid_29); + assign _zz_s1_outputPayload_sel_1_3 = (((((((_zz_s1_outputPayload_selValid_22 || _zz_s1_outputPayload_selValid_23) || _zz_s1_outputPayload_selValid_24) || _zz_s1_outputPayload_selValid_25) || _zz_s1_outputPayload_selValid_26) || _zz_s1_outputPayload_selValid_27) || _zz_s1_outputPayload_selValid_28) || _zz_s1_outputPayload_selValid_29); + assign s1_outputPayload_sel_1 = {_zz_s1_outputPayload_sel_1_3,{_zz_s1_outputPayload_sel_1_2,{_zz_s1_outputPayload_sel_1_1,_zz_s1_outputPayload_sel_1}}}; + assign _zz_s1_outputPayload_selValid_30 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_31 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_32 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_33 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_34 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_35 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_36 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_37 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_38 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_39 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_40 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_41 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_42 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_43 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_44 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0010)); + assign _zz_s1_outputPayload_sel_2 = (((((((_zz_s1_outputPayload_selValid_30 || _zz_s1_outputPayload_selValid_32) || _zz_s1_outputPayload_selValid_34) || _zz_s1_outputPayload_selValid_36) || _zz_s1_outputPayload_selValid_38) || _zz_s1_outputPayload_selValid_40) || _zz_s1_outputPayload_selValid_42) || _zz_s1_outputPayload_selValid_44); + assign _zz_s1_outputPayload_sel_2_1 = (((((((_zz_s1_outputPayload_selValid_31 || _zz_s1_outputPayload_selValid_32) || _zz_s1_outputPayload_selValid_35) || _zz_s1_outputPayload_selValid_36) || _zz_s1_outputPayload_selValid_39) || _zz_s1_outputPayload_selValid_40) || _zz_s1_outputPayload_selValid_43) || _zz_s1_outputPayload_selValid_44); + assign _zz_s1_outputPayload_sel_2_2 = (((((((_zz_s1_outputPayload_selValid_33 || _zz_s1_outputPayload_selValid_34) || _zz_s1_outputPayload_selValid_35) || _zz_s1_outputPayload_selValid_36) || _zz_s1_outputPayload_selValid_41) || _zz_s1_outputPayload_selValid_42) || _zz_s1_outputPayload_selValid_43) || _zz_s1_outputPayload_selValid_44); + assign _zz_s1_outputPayload_sel_2_3 = (((((((_zz_s1_outputPayload_selValid_37 || _zz_s1_outputPayload_selValid_38) || _zz_s1_outputPayload_selValid_39) || _zz_s1_outputPayload_selValid_40) || _zz_s1_outputPayload_selValid_41) || _zz_s1_outputPayload_selValid_42) || _zz_s1_outputPayload_selValid_43) || _zz_s1_outputPayload_selValid_44); + assign s1_outputPayload_sel_2 = {_zz_s1_outputPayload_sel_2_3,{_zz_s1_outputPayload_sel_2_2,{_zz_s1_outputPayload_sel_2_1,_zz_s1_outputPayload_sel_2}}}; + assign _zz_s1_outputPayload_selValid_45 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_46 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_47 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_48 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_49 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_50 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_51 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_52 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_53 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_54 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_55 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_56 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_57 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_58 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_59 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0011)); + assign _zz_s1_outputPayload_sel_3 = (((((((_zz_s1_outputPayload_selValid_45 || _zz_s1_outputPayload_selValid_47) || _zz_s1_outputPayload_selValid_49) || _zz_s1_outputPayload_selValid_51) || _zz_s1_outputPayload_selValid_53) || _zz_s1_outputPayload_selValid_55) || _zz_s1_outputPayload_selValid_57) || _zz_s1_outputPayload_selValid_59); + assign _zz_s1_outputPayload_sel_3_1 = (((((((_zz_s1_outputPayload_selValid_46 || _zz_s1_outputPayload_selValid_47) || _zz_s1_outputPayload_selValid_50) || _zz_s1_outputPayload_selValid_51) || _zz_s1_outputPayload_selValid_54) || _zz_s1_outputPayload_selValid_55) || _zz_s1_outputPayload_selValid_58) || _zz_s1_outputPayload_selValid_59); + assign _zz_s1_outputPayload_sel_3_2 = (((((((_zz_s1_outputPayload_selValid_48 || _zz_s1_outputPayload_selValid_49) || _zz_s1_outputPayload_selValid_50) || _zz_s1_outputPayload_selValid_51) || _zz_s1_outputPayload_selValid_56) || _zz_s1_outputPayload_selValid_57) || _zz_s1_outputPayload_selValid_58) || _zz_s1_outputPayload_selValid_59); + assign _zz_s1_outputPayload_sel_3_3 = (((((((_zz_s1_outputPayload_selValid_52 || _zz_s1_outputPayload_selValid_53) || _zz_s1_outputPayload_selValid_54) || _zz_s1_outputPayload_selValid_55) || _zz_s1_outputPayload_selValid_56) || _zz_s1_outputPayload_selValid_57) || _zz_s1_outputPayload_selValid_58) || _zz_s1_outputPayload_selValid_59); + assign s1_outputPayload_sel_3 = {_zz_s1_outputPayload_sel_3_3,{_zz_s1_outputPayload_sel_3_2,{_zz_s1_outputPayload_sel_3_1,_zz_s1_outputPayload_sel_3}}}; + assign _zz_s1_outputPayload_selValid_60 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_61 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_62 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_63 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_64 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_65 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_66 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_67 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_68 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_69 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_70 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_71 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_72 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_73 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_74 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0100)); + assign _zz_s1_outputPayload_sel_4 = (((((((_zz_s1_outputPayload_selValid_60 || _zz_s1_outputPayload_selValid_62) || _zz_s1_outputPayload_selValid_64) || _zz_s1_outputPayload_selValid_66) || _zz_s1_outputPayload_selValid_68) || _zz_s1_outputPayload_selValid_70) || _zz_s1_outputPayload_selValid_72) || _zz_s1_outputPayload_selValid_74); + assign _zz_s1_outputPayload_sel_4_1 = (((((((_zz_s1_outputPayload_selValid_61 || _zz_s1_outputPayload_selValid_62) || _zz_s1_outputPayload_selValid_65) || _zz_s1_outputPayload_selValid_66) || _zz_s1_outputPayload_selValid_69) || _zz_s1_outputPayload_selValid_70) || _zz_s1_outputPayload_selValid_73) || _zz_s1_outputPayload_selValid_74); + assign _zz_s1_outputPayload_sel_4_2 = (((((((_zz_s1_outputPayload_selValid_63 || _zz_s1_outputPayload_selValid_64) || _zz_s1_outputPayload_selValid_65) || _zz_s1_outputPayload_selValid_66) || _zz_s1_outputPayload_selValid_71) || _zz_s1_outputPayload_selValid_72) || _zz_s1_outputPayload_selValid_73) || _zz_s1_outputPayload_selValid_74); + assign _zz_s1_outputPayload_sel_4_3 = (((((((_zz_s1_outputPayload_selValid_67 || _zz_s1_outputPayload_selValid_68) || _zz_s1_outputPayload_selValid_69) || _zz_s1_outputPayload_selValid_70) || _zz_s1_outputPayload_selValid_71) || _zz_s1_outputPayload_selValid_72) || _zz_s1_outputPayload_selValid_73) || _zz_s1_outputPayload_selValid_74); + assign s1_outputPayload_sel_4 = {_zz_s1_outputPayload_sel_4_3,{_zz_s1_outputPayload_sel_4_2,{_zz_s1_outputPayload_sel_4_1,_zz_s1_outputPayload_sel_4}}}; + assign _zz_s1_outputPayload_selValid_75 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_76 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_77 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_78 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_79 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_80 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_81 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_82 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_83 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_84 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_85 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_86 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_87 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_88 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_89 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0101)); + assign _zz_s1_outputPayload_sel_5 = (((((((_zz_s1_outputPayload_selValid_75 || _zz_s1_outputPayload_selValid_77) || _zz_s1_outputPayload_selValid_79) || _zz_s1_outputPayload_selValid_81) || _zz_s1_outputPayload_selValid_83) || _zz_s1_outputPayload_selValid_85) || _zz_s1_outputPayload_selValid_87) || _zz_s1_outputPayload_selValid_89); + assign _zz_s1_outputPayload_sel_5_1 = (((((((_zz_s1_outputPayload_selValid_76 || _zz_s1_outputPayload_selValid_77) || _zz_s1_outputPayload_selValid_80) || _zz_s1_outputPayload_selValid_81) || _zz_s1_outputPayload_selValid_84) || _zz_s1_outputPayload_selValid_85) || _zz_s1_outputPayload_selValid_88) || _zz_s1_outputPayload_selValid_89); + assign _zz_s1_outputPayload_sel_5_2 = (((((((_zz_s1_outputPayload_selValid_78 || _zz_s1_outputPayload_selValid_79) || _zz_s1_outputPayload_selValid_80) || _zz_s1_outputPayload_selValid_81) || _zz_s1_outputPayload_selValid_86) || _zz_s1_outputPayload_selValid_87) || _zz_s1_outputPayload_selValid_88) || _zz_s1_outputPayload_selValid_89); + assign _zz_s1_outputPayload_sel_5_3 = (((((((_zz_s1_outputPayload_selValid_82 || _zz_s1_outputPayload_selValid_83) || _zz_s1_outputPayload_selValid_84) || _zz_s1_outputPayload_selValid_85) || _zz_s1_outputPayload_selValid_86) || _zz_s1_outputPayload_selValid_87) || _zz_s1_outputPayload_selValid_88) || _zz_s1_outputPayload_selValid_89); + assign s1_outputPayload_sel_5 = {_zz_s1_outputPayload_sel_5_3,{_zz_s1_outputPayload_sel_5_2,{_zz_s1_outputPayload_sel_5_1,_zz_s1_outputPayload_sel_5}}}; + assign _zz_s1_outputPayload_selValid_90 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_91 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_92 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_93 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_94 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_95 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_96 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_97 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_98 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_99 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_100 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_101 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_102 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_103 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_104 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0110)); + assign _zz_s1_outputPayload_sel_6 = (((((((_zz_s1_outputPayload_selValid_90 || _zz_s1_outputPayload_selValid_92) || _zz_s1_outputPayload_selValid_94) || _zz_s1_outputPayload_selValid_96) || _zz_s1_outputPayload_selValid_98) || _zz_s1_outputPayload_selValid_100) || _zz_s1_outputPayload_selValid_102) || _zz_s1_outputPayload_selValid_104); + assign _zz_s1_outputPayload_sel_6_1 = (((((((_zz_s1_outputPayload_selValid_91 || _zz_s1_outputPayload_selValid_92) || _zz_s1_outputPayload_selValid_95) || _zz_s1_outputPayload_selValid_96) || _zz_s1_outputPayload_selValid_99) || _zz_s1_outputPayload_selValid_100) || _zz_s1_outputPayload_selValid_103) || _zz_s1_outputPayload_selValid_104); + assign _zz_s1_outputPayload_sel_6_2 = (((((((_zz_s1_outputPayload_selValid_93 || _zz_s1_outputPayload_selValid_94) || _zz_s1_outputPayload_selValid_95) || _zz_s1_outputPayload_selValid_96) || _zz_s1_outputPayload_selValid_101) || _zz_s1_outputPayload_selValid_102) || _zz_s1_outputPayload_selValid_103) || _zz_s1_outputPayload_selValid_104); + assign _zz_s1_outputPayload_sel_6_3 = (((((((_zz_s1_outputPayload_selValid_97 || _zz_s1_outputPayload_selValid_98) || _zz_s1_outputPayload_selValid_99) || _zz_s1_outputPayload_selValid_100) || _zz_s1_outputPayload_selValid_101) || _zz_s1_outputPayload_selValid_102) || _zz_s1_outputPayload_selValid_103) || _zz_s1_outputPayload_selValid_104); + assign s1_outputPayload_sel_6 = {_zz_s1_outputPayload_sel_6_3,{_zz_s1_outputPayload_sel_6_2,{_zz_s1_outputPayload_sel_6_1,_zz_s1_outputPayload_sel_6}}}; + assign _zz_s1_outputPayload_selValid_105 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_106 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_107 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_108 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_109 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_110 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_111 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_112 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_113 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_114 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_115 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_116 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_117 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_118 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_119 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0111)); + assign _zz_s1_outputPayload_sel_7 = (((((((_zz_s1_outputPayload_selValid_105 || _zz_s1_outputPayload_selValid_107) || _zz_s1_outputPayload_selValid_109) || _zz_s1_outputPayload_selValid_111) || _zz_s1_outputPayload_selValid_113) || _zz_s1_outputPayload_selValid_115) || _zz_s1_outputPayload_selValid_117) || _zz_s1_outputPayload_selValid_119); + assign _zz_s1_outputPayload_sel_7_1 = (((((((_zz_s1_outputPayload_selValid_106 || _zz_s1_outputPayload_selValid_107) || _zz_s1_outputPayload_selValid_110) || _zz_s1_outputPayload_selValid_111) || _zz_s1_outputPayload_selValid_114) || _zz_s1_outputPayload_selValid_115) || _zz_s1_outputPayload_selValid_118) || _zz_s1_outputPayload_selValid_119); + assign _zz_s1_outputPayload_sel_7_2 = (((((((_zz_s1_outputPayload_selValid_108 || _zz_s1_outputPayload_selValid_109) || _zz_s1_outputPayload_selValid_110) || _zz_s1_outputPayload_selValid_111) || _zz_s1_outputPayload_selValid_116) || _zz_s1_outputPayload_selValid_117) || _zz_s1_outputPayload_selValid_118) || _zz_s1_outputPayload_selValid_119); + assign _zz_s1_outputPayload_sel_7_3 = (((((((_zz_s1_outputPayload_selValid_112 || _zz_s1_outputPayload_selValid_113) || _zz_s1_outputPayload_selValid_114) || _zz_s1_outputPayload_selValid_115) || _zz_s1_outputPayload_selValid_116) || _zz_s1_outputPayload_selValid_117) || _zz_s1_outputPayload_selValid_118) || _zz_s1_outputPayload_selValid_119); + assign s1_outputPayload_sel_7 = {_zz_s1_outputPayload_sel_7_3,{_zz_s1_outputPayload_sel_7_2,{_zz_s1_outputPayload_sel_7_1,_zz_s1_outputPayload_sel_7}}}; + assign _zz_s1_outputPayload_selValid_120 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_121 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_122 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_123 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_124 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_125 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_126 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_127 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_128 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_129 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_130 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_131 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_132 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_133 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_134 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1000)); + assign _zz_s1_outputPayload_sel_8 = (((((((_zz_s1_outputPayload_selValid_120 || _zz_s1_outputPayload_selValid_122) || _zz_s1_outputPayload_selValid_124) || _zz_s1_outputPayload_selValid_126) || _zz_s1_outputPayload_selValid_128) || _zz_s1_outputPayload_selValid_130) || _zz_s1_outputPayload_selValid_132) || _zz_s1_outputPayload_selValid_134); + assign _zz_s1_outputPayload_sel_8_1 = (((((((_zz_s1_outputPayload_selValid_121 || _zz_s1_outputPayload_selValid_122) || _zz_s1_outputPayload_selValid_125) || _zz_s1_outputPayload_selValid_126) || _zz_s1_outputPayload_selValid_129) || _zz_s1_outputPayload_selValid_130) || _zz_s1_outputPayload_selValid_133) || _zz_s1_outputPayload_selValid_134); + assign _zz_s1_outputPayload_sel_8_2 = (((((((_zz_s1_outputPayload_selValid_123 || _zz_s1_outputPayload_selValid_124) || _zz_s1_outputPayload_selValid_125) || _zz_s1_outputPayload_selValid_126) || _zz_s1_outputPayload_selValid_131) || _zz_s1_outputPayload_selValid_132) || _zz_s1_outputPayload_selValid_133) || _zz_s1_outputPayload_selValid_134); + assign _zz_s1_outputPayload_sel_8_3 = (((((((_zz_s1_outputPayload_selValid_127 || _zz_s1_outputPayload_selValid_128) || _zz_s1_outputPayload_selValid_129) || _zz_s1_outputPayload_selValid_130) || _zz_s1_outputPayload_selValid_131) || _zz_s1_outputPayload_selValid_132) || _zz_s1_outputPayload_selValid_133) || _zz_s1_outputPayload_selValid_134); + assign s1_outputPayload_sel_8 = {_zz_s1_outputPayload_sel_8_3,{_zz_s1_outputPayload_sel_8_2,{_zz_s1_outputPayload_sel_8_1,_zz_s1_outputPayload_sel_8}}}; + assign _zz_s1_outputPayload_selValid_135 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_136 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_137 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_138 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_139 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_140 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_141 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_142 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_143 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_144 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_145 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_146 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_147 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_148 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_149 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1001)); + assign _zz_s1_outputPayload_sel_9 = (((((((_zz_s1_outputPayload_selValid_135 || _zz_s1_outputPayload_selValid_137) || _zz_s1_outputPayload_selValid_139) || _zz_s1_outputPayload_selValid_141) || _zz_s1_outputPayload_selValid_143) || _zz_s1_outputPayload_selValid_145) || _zz_s1_outputPayload_selValid_147) || _zz_s1_outputPayload_selValid_149); + assign _zz_s1_outputPayload_sel_9_1 = (((((((_zz_s1_outputPayload_selValid_136 || _zz_s1_outputPayload_selValid_137) || _zz_s1_outputPayload_selValid_140) || _zz_s1_outputPayload_selValid_141) || _zz_s1_outputPayload_selValid_144) || _zz_s1_outputPayload_selValid_145) || _zz_s1_outputPayload_selValid_148) || _zz_s1_outputPayload_selValid_149); + assign _zz_s1_outputPayload_sel_9_2 = (((((((_zz_s1_outputPayload_selValid_138 || _zz_s1_outputPayload_selValid_139) || _zz_s1_outputPayload_selValid_140) || _zz_s1_outputPayload_selValid_141) || _zz_s1_outputPayload_selValid_146) || _zz_s1_outputPayload_selValid_147) || _zz_s1_outputPayload_selValid_148) || _zz_s1_outputPayload_selValid_149); + assign _zz_s1_outputPayload_sel_9_3 = (((((((_zz_s1_outputPayload_selValid_142 || _zz_s1_outputPayload_selValid_143) || _zz_s1_outputPayload_selValid_144) || _zz_s1_outputPayload_selValid_145) || _zz_s1_outputPayload_selValid_146) || _zz_s1_outputPayload_selValid_147) || _zz_s1_outputPayload_selValid_148) || _zz_s1_outputPayload_selValid_149); + assign s1_outputPayload_sel_9 = {_zz_s1_outputPayload_sel_9_3,{_zz_s1_outputPayload_sel_9_2,{_zz_s1_outputPayload_sel_9_1,_zz_s1_outputPayload_sel_9}}}; + assign _zz_s1_outputPayload_selValid_150 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_151 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_152 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_153 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_154 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_155 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_156 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_157 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_158 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_159 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_160 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_161 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_162 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_163 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_164 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1010)); + assign _zz_s1_outputPayload_sel_10 = (((((((_zz_s1_outputPayload_selValid_150 || _zz_s1_outputPayload_selValid_152) || _zz_s1_outputPayload_selValid_154) || _zz_s1_outputPayload_selValid_156) || _zz_s1_outputPayload_selValid_158) || _zz_s1_outputPayload_selValid_160) || _zz_s1_outputPayload_selValid_162) || _zz_s1_outputPayload_selValid_164); + assign _zz_s1_outputPayload_sel_10_1 = (((((((_zz_s1_outputPayload_selValid_151 || _zz_s1_outputPayload_selValid_152) || _zz_s1_outputPayload_selValid_155) || _zz_s1_outputPayload_selValid_156) || _zz_s1_outputPayload_selValid_159) || _zz_s1_outputPayload_selValid_160) || _zz_s1_outputPayload_selValid_163) || _zz_s1_outputPayload_selValid_164); + assign _zz_s1_outputPayload_sel_10_2 = (((((((_zz_s1_outputPayload_selValid_153 || _zz_s1_outputPayload_selValid_154) || _zz_s1_outputPayload_selValid_155) || _zz_s1_outputPayload_selValid_156) || _zz_s1_outputPayload_selValid_161) || _zz_s1_outputPayload_selValid_162) || _zz_s1_outputPayload_selValid_163) || _zz_s1_outputPayload_selValid_164); + assign _zz_s1_outputPayload_sel_10_3 = (((((((_zz_s1_outputPayload_selValid_157 || _zz_s1_outputPayload_selValid_158) || _zz_s1_outputPayload_selValid_159) || _zz_s1_outputPayload_selValid_160) || _zz_s1_outputPayload_selValid_161) || _zz_s1_outputPayload_selValid_162) || _zz_s1_outputPayload_selValid_163) || _zz_s1_outputPayload_selValid_164); + assign s1_outputPayload_sel_10 = {_zz_s1_outputPayload_sel_10_3,{_zz_s1_outputPayload_sel_10_2,{_zz_s1_outputPayload_sel_10_1,_zz_s1_outputPayload_sel_10}}}; + assign _zz_s1_outputPayload_selValid_165 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_166 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_167 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_168 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_169 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_170 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_171 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_172 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_173 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_174 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_175 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_176 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_177 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_178 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_179 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1011)); + assign _zz_s1_outputPayload_sel_11 = (((((((_zz_s1_outputPayload_selValid_165 || _zz_s1_outputPayload_selValid_167) || _zz_s1_outputPayload_selValid_169) || _zz_s1_outputPayload_selValid_171) || _zz_s1_outputPayload_selValid_173) || _zz_s1_outputPayload_selValid_175) || _zz_s1_outputPayload_selValid_177) || _zz_s1_outputPayload_selValid_179); + assign _zz_s1_outputPayload_sel_11_1 = (((((((_zz_s1_outputPayload_selValid_166 || _zz_s1_outputPayload_selValid_167) || _zz_s1_outputPayload_selValid_170) || _zz_s1_outputPayload_selValid_171) || _zz_s1_outputPayload_selValid_174) || _zz_s1_outputPayload_selValid_175) || _zz_s1_outputPayload_selValid_178) || _zz_s1_outputPayload_selValid_179); + assign _zz_s1_outputPayload_sel_11_2 = (((((((_zz_s1_outputPayload_selValid_168 || _zz_s1_outputPayload_selValid_169) || _zz_s1_outputPayload_selValid_170) || _zz_s1_outputPayload_selValid_171) || _zz_s1_outputPayload_selValid_176) || _zz_s1_outputPayload_selValid_177) || _zz_s1_outputPayload_selValid_178) || _zz_s1_outputPayload_selValid_179); + assign _zz_s1_outputPayload_sel_11_3 = (((((((_zz_s1_outputPayload_selValid_172 || _zz_s1_outputPayload_selValid_173) || _zz_s1_outputPayload_selValid_174) || _zz_s1_outputPayload_selValid_175) || _zz_s1_outputPayload_selValid_176) || _zz_s1_outputPayload_selValid_177) || _zz_s1_outputPayload_selValid_178) || _zz_s1_outputPayload_selValid_179); + assign s1_outputPayload_sel_11 = {_zz_s1_outputPayload_sel_11_3,{_zz_s1_outputPayload_sel_11_2,{_zz_s1_outputPayload_sel_11_1,_zz_s1_outputPayload_sel_11}}}; + assign _zz_s1_outputPayload_selValid_180 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_181 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_182 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_183 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_184 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_185 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_186 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_187 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_188 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_189 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_190 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_191 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_192 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_193 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_194 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1100)); + assign _zz_s1_outputPayload_sel_12 = (((((((_zz_s1_outputPayload_selValid_180 || _zz_s1_outputPayload_selValid_182) || _zz_s1_outputPayload_selValid_184) || _zz_s1_outputPayload_selValid_186) || _zz_s1_outputPayload_selValid_188) || _zz_s1_outputPayload_selValid_190) || _zz_s1_outputPayload_selValid_192) || _zz_s1_outputPayload_selValid_194); + assign _zz_s1_outputPayload_sel_12_1 = (((((((_zz_s1_outputPayload_selValid_181 || _zz_s1_outputPayload_selValid_182) || _zz_s1_outputPayload_selValid_185) || _zz_s1_outputPayload_selValid_186) || _zz_s1_outputPayload_selValid_189) || _zz_s1_outputPayload_selValid_190) || _zz_s1_outputPayload_selValid_193) || _zz_s1_outputPayload_selValid_194); + assign _zz_s1_outputPayload_sel_12_2 = (((((((_zz_s1_outputPayload_selValid_183 || _zz_s1_outputPayload_selValid_184) || _zz_s1_outputPayload_selValid_185) || _zz_s1_outputPayload_selValid_186) || _zz_s1_outputPayload_selValid_191) || _zz_s1_outputPayload_selValid_192) || _zz_s1_outputPayload_selValid_193) || _zz_s1_outputPayload_selValid_194); + assign _zz_s1_outputPayload_sel_12_3 = (((((((_zz_s1_outputPayload_selValid_187 || _zz_s1_outputPayload_selValid_188) || _zz_s1_outputPayload_selValid_189) || _zz_s1_outputPayload_selValid_190) || _zz_s1_outputPayload_selValid_191) || _zz_s1_outputPayload_selValid_192) || _zz_s1_outputPayload_selValid_193) || _zz_s1_outputPayload_selValid_194); + assign s1_outputPayload_sel_12 = {_zz_s1_outputPayload_sel_12_3,{_zz_s1_outputPayload_sel_12_2,{_zz_s1_outputPayload_sel_12_1,_zz_s1_outputPayload_sel_12}}}; + assign _zz_s1_outputPayload_selValid_195 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_196 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_197 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_198 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_199 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_200 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_201 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_202 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_203 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_204 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_205 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_206 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_207 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_208 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_209 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1101)); + assign _zz_s1_outputPayload_sel_13 = (((((((_zz_s1_outputPayload_selValid_195 || _zz_s1_outputPayload_selValid_197) || _zz_s1_outputPayload_selValid_199) || _zz_s1_outputPayload_selValid_201) || _zz_s1_outputPayload_selValid_203) || _zz_s1_outputPayload_selValid_205) || _zz_s1_outputPayload_selValid_207) || _zz_s1_outputPayload_selValid_209); + assign _zz_s1_outputPayload_sel_13_1 = (((((((_zz_s1_outputPayload_selValid_196 || _zz_s1_outputPayload_selValid_197) || _zz_s1_outputPayload_selValid_200) || _zz_s1_outputPayload_selValid_201) || _zz_s1_outputPayload_selValid_204) || _zz_s1_outputPayload_selValid_205) || _zz_s1_outputPayload_selValid_208) || _zz_s1_outputPayload_selValid_209); + assign _zz_s1_outputPayload_sel_13_2 = (((((((_zz_s1_outputPayload_selValid_198 || _zz_s1_outputPayload_selValid_199) || _zz_s1_outputPayload_selValid_200) || _zz_s1_outputPayload_selValid_201) || _zz_s1_outputPayload_selValid_206) || _zz_s1_outputPayload_selValid_207) || _zz_s1_outputPayload_selValid_208) || _zz_s1_outputPayload_selValid_209); + assign _zz_s1_outputPayload_sel_13_3 = (((((((_zz_s1_outputPayload_selValid_202 || _zz_s1_outputPayload_selValid_203) || _zz_s1_outputPayload_selValid_204) || _zz_s1_outputPayload_selValid_205) || _zz_s1_outputPayload_selValid_206) || _zz_s1_outputPayload_selValid_207) || _zz_s1_outputPayload_selValid_208) || _zz_s1_outputPayload_selValid_209); + assign s1_outputPayload_sel_13 = {_zz_s1_outputPayload_sel_13_3,{_zz_s1_outputPayload_sel_13_2,{_zz_s1_outputPayload_sel_13_1,_zz_s1_outputPayload_sel_13}}}; + assign _zz_s1_outputPayload_selValid_210 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_211 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_212 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_213 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_214 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_215 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_216 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_217 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_218 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_219 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_220 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_221 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_222 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_223 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_224 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1110)); + assign _zz_s1_outputPayload_sel_14 = (((((((_zz_s1_outputPayload_selValid_210 || _zz_s1_outputPayload_selValid_212) || _zz_s1_outputPayload_selValid_214) || _zz_s1_outputPayload_selValid_216) || _zz_s1_outputPayload_selValid_218) || _zz_s1_outputPayload_selValid_220) || _zz_s1_outputPayload_selValid_222) || _zz_s1_outputPayload_selValid_224); + assign _zz_s1_outputPayload_sel_14_1 = (((((((_zz_s1_outputPayload_selValid_211 || _zz_s1_outputPayload_selValid_212) || _zz_s1_outputPayload_selValid_215) || _zz_s1_outputPayload_selValid_216) || _zz_s1_outputPayload_selValid_219) || _zz_s1_outputPayload_selValid_220) || _zz_s1_outputPayload_selValid_223) || _zz_s1_outputPayload_selValid_224); + assign _zz_s1_outputPayload_sel_14_2 = (((((((_zz_s1_outputPayload_selValid_213 || _zz_s1_outputPayload_selValid_214) || _zz_s1_outputPayload_selValid_215) || _zz_s1_outputPayload_selValid_216) || _zz_s1_outputPayload_selValid_221) || _zz_s1_outputPayload_selValid_222) || _zz_s1_outputPayload_selValid_223) || _zz_s1_outputPayload_selValid_224); + assign _zz_s1_outputPayload_sel_14_3 = (((((((_zz_s1_outputPayload_selValid_217 || _zz_s1_outputPayload_selValid_218) || _zz_s1_outputPayload_selValid_219) || _zz_s1_outputPayload_selValid_220) || _zz_s1_outputPayload_selValid_221) || _zz_s1_outputPayload_selValid_222) || _zz_s1_outputPayload_selValid_223) || _zz_s1_outputPayload_selValid_224); + assign s1_outputPayload_sel_14 = {_zz_s1_outputPayload_sel_14_3,{_zz_s1_outputPayload_sel_14_2,{_zz_s1_outputPayload_sel_14_1,_zz_s1_outputPayload_sel_14}}}; + assign _zz_s1_outputPayload_selValid_225 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_226 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_227 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_228 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_229 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_230 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_231 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_232 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_233 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_234 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_235 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_236 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_237 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_238 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_239 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1111)); + assign _zz_s1_outputPayload_sel_15 = (((((((_zz_s1_outputPayload_selValid_225 || _zz_s1_outputPayload_selValid_227) || _zz_s1_outputPayload_selValid_229) || _zz_s1_outputPayload_selValid_231) || _zz_s1_outputPayload_selValid_233) || _zz_s1_outputPayload_selValid_235) || _zz_s1_outputPayload_selValid_237) || _zz_s1_outputPayload_selValid_239); + assign _zz_s1_outputPayload_sel_15_1 = (((((((_zz_s1_outputPayload_selValid_226 || _zz_s1_outputPayload_selValid_227) || _zz_s1_outputPayload_selValid_230) || _zz_s1_outputPayload_selValid_231) || _zz_s1_outputPayload_selValid_234) || _zz_s1_outputPayload_selValid_235) || _zz_s1_outputPayload_selValid_238) || _zz_s1_outputPayload_selValid_239); + assign _zz_s1_outputPayload_sel_15_2 = (((((((_zz_s1_outputPayload_selValid_228 || _zz_s1_outputPayload_selValid_229) || _zz_s1_outputPayload_selValid_230) || _zz_s1_outputPayload_selValid_231) || _zz_s1_outputPayload_selValid_236) || _zz_s1_outputPayload_selValid_237) || _zz_s1_outputPayload_selValid_238) || _zz_s1_outputPayload_selValid_239); + assign _zz_s1_outputPayload_sel_15_3 = (((((((_zz_s1_outputPayload_selValid_232 || _zz_s1_outputPayload_selValid_233) || _zz_s1_outputPayload_selValid_234) || _zz_s1_outputPayload_selValid_235) || _zz_s1_outputPayload_selValid_236) || _zz_s1_outputPayload_selValid_237) || _zz_s1_outputPayload_selValid_238) || _zz_s1_outputPayload_selValid_239); + assign s1_outputPayload_sel_15 = {_zz_s1_outputPayload_sel_15_3,{_zz_s1_outputPayload_sel_15_2,{_zz_s1_outputPayload_sel_15_1,_zz_s1_outputPayload_sel_15}}}; + assign s1_output_valid = s1_input_valid; + assign s1_input_ready = s1_output_ready; + assign s1_output_payload_cmd_data = s1_outputPayload_cmd_data; + assign s1_output_payload_cmd_mask = s1_outputPayload_cmd_mask; + assign s1_output_payload_index_0 = s1_outputPayload_index_0; + assign s1_output_payload_index_1 = s1_outputPayload_index_1; + assign s1_output_payload_index_2 = s1_outputPayload_index_2; + assign s1_output_payload_index_3 = s1_outputPayload_index_3; + assign s1_output_payload_index_4 = s1_outputPayload_index_4; + assign s1_output_payload_index_5 = s1_outputPayload_index_5; + assign s1_output_payload_index_6 = s1_outputPayload_index_6; + assign s1_output_payload_index_7 = s1_outputPayload_index_7; + assign s1_output_payload_index_8 = s1_outputPayload_index_8; + assign s1_output_payload_index_9 = s1_outputPayload_index_9; + assign s1_output_payload_index_10 = s1_outputPayload_index_10; + assign s1_output_payload_index_11 = s1_outputPayload_index_11; + assign s1_output_payload_index_12 = s1_outputPayload_index_12; + assign s1_output_payload_index_13 = s1_outputPayload_index_13; + assign s1_output_payload_index_14 = s1_outputPayload_index_14; + assign s1_output_payload_index_15 = s1_outputPayload_index_15; + assign s1_output_payload_last = s1_outputPayload_last; + assign s1_output_payload_sel_0 = s1_outputPayload_sel_0; + assign s1_output_payload_sel_1 = s1_outputPayload_sel_1; + assign s1_output_payload_sel_2 = s1_outputPayload_sel_2; + assign s1_output_payload_sel_3 = s1_outputPayload_sel_3; + assign s1_output_payload_sel_4 = s1_outputPayload_sel_4; + assign s1_output_payload_sel_5 = s1_outputPayload_sel_5; + assign s1_output_payload_sel_6 = s1_outputPayload_sel_6; + assign s1_output_payload_sel_7 = s1_outputPayload_sel_7; + assign s1_output_payload_sel_8 = s1_outputPayload_sel_8; + assign s1_output_payload_sel_9 = s1_outputPayload_sel_9; + assign s1_output_payload_sel_10 = s1_outputPayload_sel_10; + assign s1_output_payload_sel_11 = s1_outputPayload_sel_11; + assign s1_output_payload_sel_12 = s1_outputPayload_sel_12; + assign s1_output_payload_sel_13 = s1_outputPayload_sel_13; + assign s1_output_payload_sel_14 = s1_outputPayload_sel_14; + assign s1_output_payload_sel_15 = s1_outputPayload_sel_15; + assign s1_output_payload_selValid = s1_outputPayload_selValid; + always @(*) begin + s1_output_ready = s2_input_ready; + if(when_Stream_l375_2) begin + s1_output_ready = 1'b1; + end + end + + assign when_Stream_l375_2 = (! s2_input_valid); + assign s2_input_valid = s1_output_rValid; + assign s2_input_payload_cmd_data = s1_output_rData_cmd_data; + assign s2_input_payload_cmd_mask = s1_output_rData_cmd_mask; + assign s2_input_payload_index_0 = s1_output_rData_index_0; + assign s2_input_payload_index_1 = s1_output_rData_index_1; + assign s2_input_payload_index_2 = s1_output_rData_index_2; + assign s2_input_payload_index_3 = s1_output_rData_index_3; + assign s2_input_payload_index_4 = s1_output_rData_index_4; + assign s2_input_payload_index_5 = s1_output_rData_index_5; + assign s2_input_payload_index_6 = s1_output_rData_index_6; + assign s2_input_payload_index_7 = s1_output_rData_index_7; + assign s2_input_payload_index_8 = s1_output_rData_index_8; + assign s2_input_payload_index_9 = s1_output_rData_index_9; + assign s2_input_payload_index_10 = s1_output_rData_index_10; + assign s2_input_payload_index_11 = s1_output_rData_index_11; + assign s2_input_payload_index_12 = s1_output_rData_index_12; + assign s2_input_payload_index_13 = s1_output_rData_index_13; + assign s2_input_payload_index_14 = s1_output_rData_index_14; + assign s2_input_payload_index_15 = s1_output_rData_index_15; + assign s2_input_payload_last = s1_output_rData_last; + assign s2_input_payload_sel_0 = s1_output_rData_sel_0; + assign s2_input_payload_sel_1 = s1_output_rData_sel_1; + assign s2_input_payload_sel_2 = s1_output_rData_sel_2; + assign s2_input_payload_sel_3 = s1_output_rData_sel_3; + assign s2_input_payload_sel_4 = s1_output_rData_sel_4; + assign s2_input_payload_sel_5 = s1_output_rData_sel_5; + assign s2_input_payload_sel_6 = s1_output_rData_sel_6; + assign s2_input_payload_sel_7 = s1_output_rData_sel_7; + assign s2_input_payload_sel_8 = s1_output_rData_sel_8; + assign s2_input_payload_sel_9 = s1_output_rData_sel_9; + assign s2_input_payload_sel_10 = s1_output_rData_sel_10; + assign s2_input_payload_sel_11 = s1_output_rData_sel_11; + assign s2_input_payload_sel_12 = s1_output_rData_sel_12; + assign s2_input_payload_sel_13 = s1_output_rData_sel_13; + assign s2_input_payload_sel_14 = s1_output_rData_sel_14; + assign s2_input_payload_sel_15 = s1_output_rData_sel_15; + assign s2_input_payload_selValid = s1_output_rData_selValid; + always @(*) begin + s2_input_ready = ((! io_output_enough) || io_output_consume); + if(when_DmaSg_l1464) begin + s2_input_ready = 1'b0; + end + end + + assign when_DmaSg_l1464 = (_zz_when_DmaSg_l1464 < s1_byteCounter); + assign s2_input_fire = (s2_input_valid && s2_input_ready); + assign io_output_consumed = s2_input_fire; + assign s2_inputDataBytes_0 = s2_input_payload_cmd_data[7 : 0]; + assign s2_inputDataBytes_1 = s2_input_payload_cmd_data[15 : 8]; + assign s2_inputDataBytes_2 = s2_input_payload_cmd_data[23 : 16]; + assign s2_inputDataBytes_3 = s2_input_payload_cmd_data[31 : 24]; + assign s2_inputDataBytes_4 = s2_input_payload_cmd_data[39 : 32]; + assign s2_inputDataBytes_5 = s2_input_payload_cmd_data[47 : 40]; + assign s2_inputDataBytes_6 = s2_input_payload_cmd_data[55 : 48]; + assign s2_inputDataBytes_7 = s2_input_payload_cmd_data[63 : 56]; + assign s2_inputDataBytes_8 = s2_input_payload_cmd_data[71 : 64]; + assign s2_inputDataBytes_9 = s2_input_payload_cmd_data[79 : 72]; + assign s2_inputDataBytes_10 = s2_input_payload_cmd_data[87 : 80]; + assign s2_inputDataBytes_11 = s2_input_payload_cmd_data[95 : 88]; + assign s2_inputDataBytes_12 = s2_input_payload_cmd_data[103 : 96]; + assign s2_inputDataBytes_13 = s2_input_payload_cmd_data[111 : 104]; + assign s2_inputDataBytes_14 = s2_input_payload_cmd_data[119 : 112]; + assign s2_inputDataBytes_15 = s2_input_payload_cmd_data[127 : 120]; + assign s2_byteLogic_0_lastUsed = (4'b0000 == io_output_lastByteUsed); + assign s2_byteLogic_0_inputMask = s2_input_payload_selValid[0]; + assign s2_byteLogic_0_inputData = _zz_s2_byteLogic_0_inputData; + assign s2_byteLogic_0_outputMask = (s2_byteLogic_0_buffer_valid || (s2_input_valid && s2_byteLogic_0_inputMask)); + assign s2_byteLogic_0_outputData = (s2_byteLogic_0_buffer_valid ? s2_byteLogic_0_buffer_data : s2_byteLogic_0_inputData); + always @(*) begin + io_output_mask[0] = s2_byteLogic_0_outputMask; + io_output_mask[1] = s2_byteLogic_1_outputMask; + io_output_mask[2] = s2_byteLogic_2_outputMask; + io_output_mask[3] = s2_byteLogic_3_outputMask; + io_output_mask[4] = s2_byteLogic_4_outputMask; + io_output_mask[5] = s2_byteLogic_5_outputMask; + io_output_mask[6] = s2_byteLogic_6_outputMask; + io_output_mask[7] = s2_byteLogic_7_outputMask; + io_output_mask[8] = s2_byteLogic_8_outputMask; + io_output_mask[9] = s2_byteLogic_9_outputMask; + io_output_mask[10] = s2_byteLogic_10_outputMask; + io_output_mask[11] = s2_byteLogic_11_outputMask; + io_output_mask[12] = s2_byteLogic_12_outputMask; + io_output_mask[13] = s2_byteLogic_13_outputMask; + io_output_mask[14] = s2_byteLogic_14_outputMask; + io_output_mask[15] = s2_byteLogic_15_outputMask; + end + + always @(*) begin + io_output_data[7 : 0] = s2_byteLogic_0_outputData; + io_output_data[15 : 8] = s2_byteLogic_1_outputData; + io_output_data[23 : 16] = s2_byteLogic_2_outputData; + io_output_data[31 : 24] = s2_byteLogic_3_outputData; + io_output_data[39 : 32] = s2_byteLogic_4_outputData; + io_output_data[47 : 40] = s2_byteLogic_5_outputData; + io_output_data[55 : 48] = s2_byteLogic_6_outputData; + io_output_data[63 : 56] = s2_byteLogic_7_outputData; + io_output_data[71 : 64] = s2_byteLogic_8_outputData; + io_output_data[79 : 72] = s2_byteLogic_9_outputData; + io_output_data[87 : 80] = s2_byteLogic_10_outputData; + io_output_data[95 : 88] = s2_byteLogic_11_outputData; + io_output_data[103 : 96] = s2_byteLogic_12_outputData; + io_output_data[111 : 104] = s2_byteLogic_13_outputData; + io_output_data[119 : 112] = s2_byteLogic_14_outputData; + io_output_data[127 : 120] = s2_byteLogic_15_outputData; + end + + assign when_DmaSg_l1493 = (s2_byteLogic_0_inputMask && ((! io_output_consume) || s2_byteLogic_0_buffer_valid)); + assign s2_byteLogic_1_lastUsed = (4'b0001 == io_output_lastByteUsed); + assign s2_byteLogic_1_inputMask = s2_input_payload_selValid[1]; + assign s2_byteLogic_1_inputData = _zz_s2_byteLogic_1_inputData; + assign s2_byteLogic_1_outputMask = (s2_byteLogic_1_buffer_valid || (s2_input_valid && s2_byteLogic_1_inputMask)); + assign s2_byteLogic_1_outputData = (s2_byteLogic_1_buffer_valid ? s2_byteLogic_1_buffer_data : s2_byteLogic_1_inputData); + assign when_DmaSg_l1493_1 = (s2_byteLogic_1_inputMask && ((! io_output_consume) || s2_byteLogic_1_buffer_valid)); + assign s2_byteLogic_2_lastUsed = (4'b0010 == io_output_lastByteUsed); + assign s2_byteLogic_2_inputMask = s2_input_payload_selValid[2]; + assign s2_byteLogic_2_inputData = _zz_s2_byteLogic_2_inputData; + assign s2_byteLogic_2_outputMask = (s2_byteLogic_2_buffer_valid || (s2_input_valid && s2_byteLogic_2_inputMask)); + assign s2_byteLogic_2_outputData = (s2_byteLogic_2_buffer_valid ? s2_byteLogic_2_buffer_data : s2_byteLogic_2_inputData); + assign when_DmaSg_l1493_2 = (s2_byteLogic_2_inputMask && ((! io_output_consume) || s2_byteLogic_2_buffer_valid)); + assign s2_byteLogic_3_lastUsed = (4'b0011 == io_output_lastByteUsed); + assign s2_byteLogic_3_inputMask = s2_input_payload_selValid[3]; + assign s2_byteLogic_3_inputData = _zz_s2_byteLogic_3_inputData; + assign s2_byteLogic_3_outputMask = (s2_byteLogic_3_buffer_valid || (s2_input_valid && s2_byteLogic_3_inputMask)); + assign s2_byteLogic_3_outputData = (s2_byteLogic_3_buffer_valid ? s2_byteLogic_3_buffer_data : s2_byteLogic_3_inputData); + assign when_DmaSg_l1493_3 = (s2_byteLogic_3_inputMask && ((! io_output_consume) || s2_byteLogic_3_buffer_valid)); + assign s2_byteLogic_4_lastUsed = (4'b0100 == io_output_lastByteUsed); + assign s2_byteLogic_4_inputMask = s2_input_payload_selValid[4]; + assign s2_byteLogic_4_inputData = _zz_s2_byteLogic_4_inputData; + assign s2_byteLogic_4_outputMask = (s2_byteLogic_4_buffer_valid || (s2_input_valid && s2_byteLogic_4_inputMask)); + assign s2_byteLogic_4_outputData = (s2_byteLogic_4_buffer_valid ? s2_byteLogic_4_buffer_data : s2_byteLogic_4_inputData); + assign when_DmaSg_l1493_4 = (s2_byteLogic_4_inputMask && ((! io_output_consume) || s2_byteLogic_4_buffer_valid)); + assign s2_byteLogic_5_lastUsed = (4'b0101 == io_output_lastByteUsed); + assign s2_byteLogic_5_inputMask = s2_input_payload_selValid[5]; + assign s2_byteLogic_5_inputData = _zz_s2_byteLogic_5_inputData; + assign s2_byteLogic_5_outputMask = (s2_byteLogic_5_buffer_valid || (s2_input_valid && s2_byteLogic_5_inputMask)); + assign s2_byteLogic_5_outputData = (s2_byteLogic_5_buffer_valid ? s2_byteLogic_5_buffer_data : s2_byteLogic_5_inputData); + assign when_DmaSg_l1493_5 = (s2_byteLogic_5_inputMask && ((! io_output_consume) || s2_byteLogic_5_buffer_valid)); + assign s2_byteLogic_6_lastUsed = (4'b0110 == io_output_lastByteUsed); + assign s2_byteLogic_6_inputMask = s2_input_payload_selValid[6]; + assign s2_byteLogic_6_inputData = _zz_s2_byteLogic_6_inputData; + assign s2_byteLogic_6_outputMask = (s2_byteLogic_6_buffer_valid || (s2_input_valid && s2_byteLogic_6_inputMask)); + assign s2_byteLogic_6_outputData = (s2_byteLogic_6_buffer_valid ? s2_byteLogic_6_buffer_data : s2_byteLogic_6_inputData); + assign when_DmaSg_l1493_6 = (s2_byteLogic_6_inputMask && ((! io_output_consume) || s2_byteLogic_6_buffer_valid)); + assign s2_byteLogic_7_lastUsed = (4'b0111 == io_output_lastByteUsed); + assign s2_byteLogic_7_inputMask = s2_input_payload_selValid[7]; + assign s2_byteLogic_7_inputData = _zz_s2_byteLogic_7_inputData; + assign s2_byteLogic_7_outputMask = (s2_byteLogic_7_buffer_valid || (s2_input_valid && s2_byteLogic_7_inputMask)); + assign s2_byteLogic_7_outputData = (s2_byteLogic_7_buffer_valid ? s2_byteLogic_7_buffer_data : s2_byteLogic_7_inputData); + assign when_DmaSg_l1493_7 = (s2_byteLogic_7_inputMask && ((! io_output_consume) || s2_byteLogic_7_buffer_valid)); + assign s2_byteLogic_8_lastUsed = (4'b1000 == io_output_lastByteUsed); + assign s2_byteLogic_8_inputMask = s2_input_payload_selValid[8]; + assign s2_byteLogic_8_inputData = _zz_s2_byteLogic_8_inputData; + assign s2_byteLogic_8_outputMask = (s2_byteLogic_8_buffer_valid || (s2_input_valid && s2_byteLogic_8_inputMask)); + assign s2_byteLogic_8_outputData = (s2_byteLogic_8_buffer_valid ? s2_byteLogic_8_buffer_data : s2_byteLogic_8_inputData); + assign when_DmaSg_l1493_8 = (s2_byteLogic_8_inputMask && ((! io_output_consume) || s2_byteLogic_8_buffer_valid)); + assign s2_byteLogic_9_lastUsed = (4'b1001 == io_output_lastByteUsed); + assign s2_byteLogic_9_inputMask = s2_input_payload_selValid[9]; + assign s2_byteLogic_9_inputData = _zz_s2_byteLogic_9_inputData; + assign s2_byteLogic_9_outputMask = (s2_byteLogic_9_buffer_valid || (s2_input_valid && s2_byteLogic_9_inputMask)); + assign s2_byteLogic_9_outputData = (s2_byteLogic_9_buffer_valid ? s2_byteLogic_9_buffer_data : s2_byteLogic_9_inputData); + assign when_DmaSg_l1493_9 = (s2_byteLogic_9_inputMask && ((! io_output_consume) || s2_byteLogic_9_buffer_valid)); + assign s2_byteLogic_10_lastUsed = (4'b1010 == io_output_lastByteUsed); + assign s2_byteLogic_10_inputMask = s2_input_payload_selValid[10]; + assign s2_byteLogic_10_inputData = _zz_s2_byteLogic_10_inputData; + assign s2_byteLogic_10_outputMask = (s2_byteLogic_10_buffer_valid || (s2_input_valid && s2_byteLogic_10_inputMask)); + assign s2_byteLogic_10_outputData = (s2_byteLogic_10_buffer_valid ? s2_byteLogic_10_buffer_data : s2_byteLogic_10_inputData); + assign when_DmaSg_l1493_10 = (s2_byteLogic_10_inputMask && ((! io_output_consume) || s2_byteLogic_10_buffer_valid)); + assign s2_byteLogic_11_lastUsed = (4'b1011 == io_output_lastByteUsed); + assign s2_byteLogic_11_inputMask = s2_input_payload_selValid[11]; + assign s2_byteLogic_11_inputData = _zz_s2_byteLogic_11_inputData; + assign s2_byteLogic_11_outputMask = (s2_byteLogic_11_buffer_valid || (s2_input_valid && s2_byteLogic_11_inputMask)); + assign s2_byteLogic_11_outputData = (s2_byteLogic_11_buffer_valid ? s2_byteLogic_11_buffer_data : s2_byteLogic_11_inputData); + assign when_DmaSg_l1493_11 = (s2_byteLogic_11_inputMask && ((! io_output_consume) || s2_byteLogic_11_buffer_valid)); + assign s2_byteLogic_12_lastUsed = (4'b1100 == io_output_lastByteUsed); + assign s2_byteLogic_12_inputMask = s2_input_payload_selValid[12]; + assign s2_byteLogic_12_inputData = _zz_s2_byteLogic_12_inputData; + assign s2_byteLogic_12_outputMask = (s2_byteLogic_12_buffer_valid || (s2_input_valid && s2_byteLogic_12_inputMask)); + assign s2_byteLogic_12_outputData = (s2_byteLogic_12_buffer_valid ? s2_byteLogic_12_buffer_data : s2_byteLogic_12_inputData); + assign when_DmaSg_l1493_12 = (s2_byteLogic_12_inputMask && ((! io_output_consume) || s2_byteLogic_12_buffer_valid)); + assign s2_byteLogic_13_lastUsed = (4'b1101 == io_output_lastByteUsed); + assign s2_byteLogic_13_inputMask = s2_input_payload_selValid[13]; + assign s2_byteLogic_13_inputData = _zz_s2_byteLogic_13_inputData; + assign s2_byteLogic_13_outputMask = (s2_byteLogic_13_buffer_valid || (s2_input_valid && s2_byteLogic_13_inputMask)); + assign s2_byteLogic_13_outputData = (s2_byteLogic_13_buffer_valid ? s2_byteLogic_13_buffer_data : s2_byteLogic_13_inputData); + assign when_DmaSg_l1493_13 = (s2_byteLogic_13_inputMask && ((! io_output_consume) || s2_byteLogic_13_buffer_valid)); + assign s2_byteLogic_14_lastUsed = (4'b1110 == io_output_lastByteUsed); + assign s2_byteLogic_14_inputMask = s2_input_payload_selValid[14]; + assign s2_byteLogic_14_inputData = _zz_s2_byteLogic_14_inputData; + assign s2_byteLogic_14_outputMask = (s2_byteLogic_14_buffer_valid || (s2_input_valid && s2_byteLogic_14_inputMask)); + assign s2_byteLogic_14_outputData = (s2_byteLogic_14_buffer_valid ? s2_byteLogic_14_buffer_data : s2_byteLogic_14_inputData); + assign when_DmaSg_l1493_14 = (s2_byteLogic_14_inputMask && ((! io_output_consume) || s2_byteLogic_14_buffer_valid)); + assign s2_byteLogic_15_lastUsed = (4'b1111 == io_output_lastByteUsed); + assign s2_byteLogic_15_inputMask = s2_input_payload_selValid[15]; + assign s2_byteLogic_15_inputData = _zz_s2_byteLogic_15_inputData; + assign s2_byteLogic_15_outputMask = (s2_byteLogic_15_buffer_valid || (s2_input_valid && s2_byteLogic_15_inputMask)); + assign s2_byteLogic_15_outputData = (s2_byteLogic_15_buffer_valid ? s2_byteLogic_15_buffer_data : s2_byteLogic_15_inputData); + assign when_DmaSg_l1493_15 = (s2_byteLogic_15_inputMask && ((! io_output_consume) || s2_byteLogic_15_buffer_valid)); + assign _zz_io_output_usedUntil = (((((((s2_byteLogic_1_lastUsed || s2_byteLogic_3_lastUsed) || s2_byteLogic_5_lastUsed) || s2_byteLogic_7_lastUsed) || s2_byteLogic_9_lastUsed) || s2_byteLogic_11_lastUsed) || s2_byteLogic_13_lastUsed) || s2_byteLogic_15_lastUsed); + assign _zz_io_output_usedUntil_1 = (((((((s2_byteLogic_2_lastUsed || s2_byteLogic_3_lastUsed) || s2_byteLogic_6_lastUsed) || s2_byteLogic_7_lastUsed) || s2_byteLogic_10_lastUsed) || s2_byteLogic_11_lastUsed) || s2_byteLogic_14_lastUsed) || s2_byteLogic_15_lastUsed); + assign _zz_io_output_usedUntil_2 = (((((((s2_byteLogic_4_lastUsed || s2_byteLogic_5_lastUsed) || s2_byteLogic_6_lastUsed) || s2_byteLogic_7_lastUsed) || s2_byteLogic_12_lastUsed) || s2_byteLogic_13_lastUsed) || s2_byteLogic_14_lastUsed) || s2_byteLogic_15_lastUsed); + assign _zz_io_output_usedUntil_3 = (((((((s2_byteLogic_8_lastUsed || s2_byteLogic_9_lastUsed) || s2_byteLogic_10_lastUsed) || s2_byteLogic_11_lastUsed) || s2_byteLogic_12_lastUsed) || s2_byteLogic_13_lastUsed) || s2_byteLogic_14_lastUsed) || s2_byteLogic_15_lastUsed); + assign io_output_usedUntil = _zz_io_output_usedUntil_4; + always @(posedge clk) begin + if(reset) begin + io_input_rValid <= 1'b0; + s0_output_rValid <= 1'b0; + s1_output_rValid <= 1'b0; + end else begin + if(io_input_ready) begin + io_input_rValid <= io_input_valid; + end + if(io_flush) begin + io_input_rValid <= 1'b0; + end + if(s0_output_ready) begin + s0_output_rValid <= s0_output_valid; + end + if(io_flush) begin + s0_output_rValid <= 1'b0; + end + if(s1_output_ready) begin + s1_output_rValid <= s1_output_valid; + end + if(io_flush) begin + s1_output_rValid <= 1'b0; + end + end + end + + always @(posedge clk) begin + if(io_input_ready) begin + io_input_rData_data <= io_input_payload_data; + io_input_rData_mask <= io_input_payload_mask; + end + if(s0_output_ready) begin + s0_output_rData_cmd_data <= s0_output_payload_cmd_data; + s0_output_rData_cmd_mask <= s0_output_payload_cmd_mask; + s0_output_rData_countOnes_0 <= s0_output_payload_countOnes_0; + s0_output_rData_countOnes_1 <= s0_output_payload_countOnes_1; + s0_output_rData_countOnes_2 <= s0_output_payload_countOnes_2; + s0_output_rData_countOnes_3 <= s0_output_payload_countOnes_3; + s0_output_rData_countOnes_4 <= s0_output_payload_countOnes_4; + s0_output_rData_countOnes_5 <= s0_output_payload_countOnes_5; + s0_output_rData_countOnes_6 <= s0_output_payload_countOnes_6; + s0_output_rData_countOnes_7 <= s0_output_payload_countOnes_7; + s0_output_rData_countOnes_8 <= s0_output_payload_countOnes_8; + s0_output_rData_countOnes_9 <= s0_output_payload_countOnes_9; + s0_output_rData_countOnes_10 <= s0_output_payload_countOnes_10; + s0_output_rData_countOnes_11 <= s0_output_payload_countOnes_11; + s0_output_rData_countOnes_12 <= s0_output_payload_countOnes_12; + s0_output_rData_countOnes_13 <= s0_output_payload_countOnes_13; + s0_output_rData_countOnes_14 <= s0_output_payload_countOnes_14; + s0_output_rData_countOnes_15 <= s0_output_payload_countOnes_15; + end + if(s1_input_fire) begin + s1_offset <= s1_offsetNext[3:0]; + end + if(io_flush) begin + s1_offset <= io_offset; + end + if(s1_input_fire) begin + s1_byteCounter <= (s1_byteCounter + _zz_s1_byteCounter); + end + if(io_flush) begin + s1_byteCounter <= 13'h0; + end + if(s1_output_ready) begin + s1_output_rData_cmd_data <= s1_output_payload_cmd_data; + s1_output_rData_cmd_mask <= s1_output_payload_cmd_mask; + s1_output_rData_index_0 <= s1_output_payload_index_0; + s1_output_rData_index_1 <= s1_output_payload_index_1; + s1_output_rData_index_2 <= s1_output_payload_index_2; + s1_output_rData_index_3 <= s1_output_payload_index_3; + s1_output_rData_index_4 <= s1_output_payload_index_4; + s1_output_rData_index_5 <= s1_output_payload_index_5; + s1_output_rData_index_6 <= s1_output_payload_index_6; + s1_output_rData_index_7 <= s1_output_payload_index_7; + s1_output_rData_index_8 <= s1_output_payload_index_8; + s1_output_rData_index_9 <= s1_output_payload_index_9; + s1_output_rData_index_10 <= s1_output_payload_index_10; + s1_output_rData_index_11 <= s1_output_payload_index_11; + s1_output_rData_index_12 <= s1_output_payload_index_12; + s1_output_rData_index_13 <= s1_output_payload_index_13; + s1_output_rData_index_14 <= s1_output_payload_index_14; + s1_output_rData_index_15 <= s1_output_payload_index_15; + s1_output_rData_last <= s1_output_payload_last; + s1_output_rData_sel_0 <= s1_output_payload_sel_0; + s1_output_rData_sel_1 <= s1_output_payload_sel_1; + s1_output_rData_sel_2 <= s1_output_payload_sel_2; + s1_output_rData_sel_3 <= s1_output_payload_sel_3; + s1_output_rData_sel_4 <= s1_output_payload_sel_4; + s1_output_rData_sel_5 <= s1_output_payload_sel_5; + s1_output_rData_sel_6 <= s1_output_payload_sel_6; + s1_output_rData_sel_7 <= s1_output_payload_sel_7; + s1_output_rData_sel_8 <= s1_output_payload_sel_8; + s1_output_rData_sel_9 <= s1_output_payload_sel_9; + s1_output_rData_sel_10 <= s1_output_payload_sel_10; + s1_output_rData_sel_11 <= s1_output_payload_sel_11; + s1_output_rData_sel_12 <= s1_output_payload_sel_12; + s1_output_rData_sel_13 <= s1_output_payload_sel_13; + s1_output_rData_sel_14 <= s1_output_payload_sel_14; + s1_output_rData_sel_15 <= s1_output_payload_sel_15; + s1_output_rData_selValid <= s1_output_payload_selValid; + end + if(io_output_consume) begin + s2_byteLogic_0_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_0_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493) begin + s2_byteLogic_0_buffer_valid <= 1'b1; + s2_byteLogic_0_buffer_data <= s2_byteLogic_0_inputData; + end + end + if(io_flush) begin + s2_byteLogic_0_buffer_valid <= (4'b0000 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_1_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_1_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_1) begin + s2_byteLogic_1_buffer_valid <= 1'b1; + s2_byteLogic_1_buffer_data <= s2_byteLogic_1_inputData; + end + end + if(io_flush) begin + s2_byteLogic_1_buffer_valid <= (4'b0001 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_2_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_2_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_2) begin + s2_byteLogic_2_buffer_valid <= 1'b1; + s2_byteLogic_2_buffer_data <= s2_byteLogic_2_inputData; + end + end + if(io_flush) begin + s2_byteLogic_2_buffer_valid <= (4'b0010 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_3_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_3_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_3) begin + s2_byteLogic_3_buffer_valid <= 1'b1; + s2_byteLogic_3_buffer_data <= s2_byteLogic_3_inputData; + end + end + if(io_flush) begin + s2_byteLogic_3_buffer_valid <= (4'b0011 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_4_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_4_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_4) begin + s2_byteLogic_4_buffer_valid <= 1'b1; + s2_byteLogic_4_buffer_data <= s2_byteLogic_4_inputData; + end + end + if(io_flush) begin + s2_byteLogic_4_buffer_valid <= (4'b0100 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_5_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_5_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_5) begin + s2_byteLogic_5_buffer_valid <= 1'b1; + s2_byteLogic_5_buffer_data <= s2_byteLogic_5_inputData; + end + end + if(io_flush) begin + s2_byteLogic_5_buffer_valid <= (4'b0101 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_6_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_6_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_6) begin + s2_byteLogic_6_buffer_valid <= 1'b1; + s2_byteLogic_6_buffer_data <= s2_byteLogic_6_inputData; + end + end + if(io_flush) begin + s2_byteLogic_6_buffer_valid <= (4'b0110 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_7_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_7_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_7) begin + s2_byteLogic_7_buffer_valid <= 1'b1; + s2_byteLogic_7_buffer_data <= s2_byteLogic_7_inputData; + end + end + if(io_flush) begin + s2_byteLogic_7_buffer_valid <= (4'b0111 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_8_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_8_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_8) begin + s2_byteLogic_8_buffer_valid <= 1'b1; + s2_byteLogic_8_buffer_data <= s2_byteLogic_8_inputData; + end + end + if(io_flush) begin + s2_byteLogic_8_buffer_valid <= (4'b1000 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_9_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_9_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_9) begin + s2_byteLogic_9_buffer_valid <= 1'b1; + s2_byteLogic_9_buffer_data <= s2_byteLogic_9_inputData; + end + end + if(io_flush) begin + s2_byteLogic_9_buffer_valid <= (4'b1001 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_10_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_10_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_10) begin + s2_byteLogic_10_buffer_valid <= 1'b1; + s2_byteLogic_10_buffer_data <= s2_byteLogic_10_inputData; + end + end + if(io_flush) begin + s2_byteLogic_10_buffer_valid <= (4'b1010 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_11_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_11_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_11) begin + s2_byteLogic_11_buffer_valid <= 1'b1; + s2_byteLogic_11_buffer_data <= s2_byteLogic_11_inputData; + end + end + if(io_flush) begin + s2_byteLogic_11_buffer_valid <= (4'b1011 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_12_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_12_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_12) begin + s2_byteLogic_12_buffer_valid <= 1'b1; + s2_byteLogic_12_buffer_data <= s2_byteLogic_12_inputData; + end + end + if(io_flush) begin + s2_byteLogic_12_buffer_valid <= (4'b1100 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_13_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_13_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_13) begin + s2_byteLogic_13_buffer_valid <= 1'b1; + s2_byteLogic_13_buffer_data <= s2_byteLogic_13_inputData; + end + end + if(io_flush) begin + s2_byteLogic_13_buffer_valid <= (4'b1101 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_14_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_14_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_14) begin + s2_byteLogic_14_buffer_valid <= 1'b1; + s2_byteLogic_14_buffer_data <= s2_byteLogic_14_inputData; + end + end + if(io_flush) begin + s2_byteLogic_14_buffer_valid <= (4'b1110 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_15_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_15_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_15) begin + s2_byteLogic_15_buffer_valid <= 1'b1; + s2_byteLogic_15_buffer_data <= s2_byteLogic_15_inputData; + end + end + if(io_flush) begin + s2_byteLogic_15_buffer_valid <= (4'b1111 < io_offset); + end + end + + +endmodule + +module EfxDMA_DmaMemoryCore_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_writes_0_cmd_valid, + output wire io_writes_0_cmd_ready, + input wire [9:0] io_writes_0_cmd_payload_address, + input wire [63:0] io_writes_0_cmd_payload_data, + input wire [7:0] io_writes_0_cmd_payload_mask, + input wire [1:0] io_writes_0_cmd_payload_priority, + input wire [6:0] io_writes_0_cmd_payload_context, + output wire io_writes_0_rsp_valid, + output wire [6:0] io_writes_0_rsp_payload_context, + input wire io_writes_1_cmd_valid, + output wire io_writes_1_cmd_ready, + input wire [9:0] io_writes_1_cmd_payload_address, + input wire [127:0] io_writes_1_cmd_payload_data, + input wire [15:0] io_writes_1_cmd_payload_mask, + input wire [6:0] io_writes_1_cmd_payload_context, + output wire io_writes_1_rsp_valid, + output wire [6:0] io_writes_1_rsp_payload_context, + input wire io_reads_0_cmd_valid, + output wire io_reads_0_cmd_ready, + input wire [9:0] io_reads_0_cmd_payload_address, + input wire [1:0] io_reads_0_cmd_payload_priority, + input wire [2:0] io_reads_0_cmd_payload_context, + output wire io_reads_0_rsp_valid, + input wire io_reads_0_rsp_ready, + output wire [63:0] io_reads_0_rsp_payload_data, + output wire [7:0] io_reads_0_rsp_payload_mask, + output wire [2:0] io_reads_0_rsp_payload_context, + input wire io_reads_1_cmd_valid, + output wire io_reads_1_cmd_ready, + input wire [9:0] io_reads_1_cmd_payload_address, + input wire [11:0] io_reads_1_cmd_payload_context, + output wire io_reads_1_rsp_valid, + input wire io_reads_1_rsp_ready, + output wire [127:0] io_reads_1_rsp_payload_data, + output wire [15:0] io_reads_1_rsp_payload_mask, + output wire [11:0] io_reads_1_rsp_payload_context, + input wire clk, + input wire reset +); + + reg [71:0] banks_0_ram_spinal_port1; + reg [71:0] banks_1_ram_spinal_port1; + wire [71:0] _zz_banks_0_ram_port; + wire [71:0] _zz_banks_1_ram_port; + wire [3:0] _zz_write_ports_0_priority_value; + wire [9:0] _zz_when_MemoryCore_l136; + wire [9:0] _zz_when_MemoryCore_l136_1; + reg [63:0] _zz_read_ports_0_buffer_bufferIn_payload_data; + reg [7:0] _zz_read_ports_0_buffer_bufferIn_payload_mask; + wire [3:0] _zz_read_ports_0_priority_value; + wire [9:0] _zz_when_MemoryCore_l221; + wire [9:0] _zz_when_MemoryCore_l221_1; + reg _zz_1; + reg _zz_2; + reg banks_0_write_valid; + reg [8:0] banks_0_write_payload_address; + reg [63:0] banks_0_write_payload_data_data; + reg [7:0] banks_0_write_payload_data_mask; + wire banks_0_read_cmd_valid; + wire [8:0] banks_0_read_cmd_payload; + wire [63:0] banks_0_read_rsp_data; + wire [7:0] banks_0_read_rsp_mask; + wire [71:0] _zz_banks_0_read_rsp_data; + wire banks_0_writeOr_value_valid; + wire [8:0] banks_0_writeOr_value_payload_address; + wire [63:0] banks_0_writeOr_value_payload_data_data; + wire [7:0] banks_0_writeOr_value_payload_data_mask; + wire banks_0_readOr_value_valid; + wire [8:0] banks_0_readOr_value_payload; + reg banks_1_write_valid; + reg [8:0] banks_1_write_payload_address; + reg [63:0] banks_1_write_payload_data_data; + reg [7:0] banks_1_write_payload_data_mask; + wire banks_1_read_cmd_valid; + wire [8:0] banks_1_read_cmd_payload; + wire [63:0] banks_1_read_rsp_data; + wire [7:0] banks_1_read_rsp_mask; + wire [71:0] _zz_banks_1_read_rsp_data; + wire banks_1_writeOr_value_valid; + wire [8:0] banks_1_writeOr_value_payload_address; + wire [63:0] banks_1_writeOr_value_payload_data_data; + wire [7:0] banks_1_writeOr_value_payload_data_mask; + wire banks_1_readOr_value_valid; + wire [8:0] banks_1_readOr_value_payload; + reg [3:0] write_ports_0_priority_value; + wire write_nodes_0_0_priority; + wire write_nodes_0_0_conflict; + wire write_nodes_0_1_priority; + wire write_nodes_0_1_conflict; + wire write_nodes_1_0_priority; + wire write_nodes_1_0_conflict; + wire write_nodes_1_1_priority; + wire write_nodes_1_1_conflict; + wire [0:0] write_arbiter_0_losedAgainst; + reg write_arbiter_0_doIt; + reg _zz_banks_0_writeOr_value_valid; + reg [8:0] _zz_banks_0_writeOr_value_valid_1; + reg [63:0] _zz_banks_0_writeOr_value_valid_2; + reg [7:0] _zz_banks_0_writeOr_value_valid_3; + wire when_MemoryCore_l136; + reg _zz_banks_1_writeOr_value_valid; + reg [8:0] _zz_banks_1_writeOr_value_valid_1; + reg [63:0] _zz_banks_1_writeOr_value_valid_2; + reg [7:0] _zz_banks_1_writeOr_value_valid_3; + wire when_MemoryCore_l136_1; + reg write_arbiter_0_doIt_regNext; + reg [6:0] io_writes_0_cmd_payload_context_regNext; + wire [0:0] write_arbiter_1_losedAgainst; + reg write_arbiter_1_doIt; + reg _zz_banks_0_writeOr_value_valid_4; + reg [8:0] _zz_banks_0_writeOr_value_valid_5; + reg [63:0] _zz_banks_0_writeOr_value_valid_6; + reg [7:0] _zz_banks_0_writeOr_value_valid_7; + wire when_MemoryCore_l136_2; + reg _zz_banks_1_writeOr_value_valid_4; + reg [8:0] _zz_banks_1_writeOr_value_valid_5; + reg [63:0] _zz_banks_1_writeOr_value_valid_6; + reg [7:0] _zz_banks_1_writeOr_value_valid_7; + wire when_MemoryCore_l136_3; + reg write_arbiter_1_doIt_regNext; + reg [6:0] io_writes_1_cmd_payload_context_regNext; + wire read_ports_0_buffer_s0_valid; + wire [2:0] read_ports_0_buffer_s0_payload_context; + wire [9:0] read_ports_0_buffer_s0_payload_address; + reg read_ports_0_buffer_s1_valid; + reg [2:0] read_ports_0_buffer_s1_payload_context; + reg [9:0] read_ports_0_buffer_s1_payload_address; + wire [0:0] read_ports_0_buffer_groupSel; + wire read_ports_0_buffer_bufferIn_valid; + wire read_ports_0_buffer_bufferIn_ready; + wire [63:0] read_ports_0_buffer_bufferIn_payload_data; + wire [7:0] read_ports_0_buffer_bufferIn_payload_mask; + wire [2:0] read_ports_0_buffer_bufferIn_payload_context; + wire read_ports_0_buffer_bufferOut_valid; + wire read_ports_0_buffer_bufferOut_ready; + wire [63:0] read_ports_0_buffer_bufferOut_payload_data; + wire [7:0] read_ports_0_buffer_bufferOut_payload_mask; + wire [2:0] read_ports_0_buffer_bufferOut_payload_context; + reg read_ports_0_buffer_bufferIn_rValidN; + reg [63:0] read_ports_0_buffer_bufferIn_rData_data; + reg [7:0] read_ports_0_buffer_bufferIn_rData_mask; + reg [2:0] read_ports_0_buffer_bufferIn_rData_context; + wire read_ports_0_buffer_full; + wire _zz_io_reads_0_cmd_ready; + wire read_ports_0_cmd_valid; + wire read_ports_0_cmd_ready; + wire [9:0] read_ports_0_cmd_payload_address; + wire [1:0] read_ports_0_cmd_payload_priority; + wire [2:0] read_ports_0_cmd_payload_context; + reg [3:0] read_ports_0_priority_value; + wire read_ports_1_buffer_s0_valid; + wire [11:0] read_ports_1_buffer_s0_payload_context; + wire [9:0] read_ports_1_buffer_s0_payload_address; + reg read_ports_1_buffer_s1_valid; + reg [11:0] read_ports_1_buffer_s1_payload_context; + reg [9:0] read_ports_1_buffer_s1_payload_address; + wire read_ports_1_buffer_bufferIn_valid; + wire read_ports_1_buffer_bufferIn_ready; + wire [127:0] read_ports_1_buffer_bufferIn_payload_data; + wire [15:0] read_ports_1_buffer_bufferIn_payload_mask; + wire [11:0] read_ports_1_buffer_bufferIn_payload_context; + wire read_ports_1_buffer_bufferOut_valid; + wire read_ports_1_buffer_bufferOut_ready; + wire [127:0] read_ports_1_buffer_bufferOut_payload_data; + wire [15:0] read_ports_1_buffer_bufferOut_payload_mask; + wire [11:0] read_ports_1_buffer_bufferOut_payload_context; + reg read_ports_1_buffer_bufferIn_rValidN; + reg [127:0] read_ports_1_buffer_bufferIn_rData_data; + reg [15:0] read_ports_1_buffer_bufferIn_rData_mask; + reg [11:0] read_ports_1_buffer_bufferIn_rData_context; + wire read_ports_1_buffer_full; + wire _zz_io_reads_1_cmd_ready; + wire read_ports_1_cmd_valid; + wire read_ports_1_cmd_ready; + wire [9:0] read_ports_1_cmd_payload_address; + wire [11:0] read_ports_1_cmd_payload_context; + wire read_nodes_0_0_priority; + wire read_nodes_0_0_conflict; + wire read_nodes_0_1_priority; + wire read_nodes_0_1_conflict; + wire read_nodes_1_0_priority; + wire read_nodes_1_0_conflict; + wire read_nodes_1_1_priority; + wire read_nodes_1_1_conflict; + wire [0:0] read_arbiter_0_losedAgainst; + wire read_arbiter_0_doIt; + reg _zz_banks_0_readOr_value_valid; + reg [8:0] _zz_banks_0_readOr_value_valid_1; + wire when_MemoryCore_l221; + reg _zz_banks_1_readOr_value_valid; + reg [8:0] _zz_banks_1_readOr_value_valid_1; + wire when_MemoryCore_l221_1; + wire [0:0] read_arbiter_1_losedAgainst; + wire read_arbiter_1_doIt; + reg _zz_banks_0_readOr_value_valid_2; + reg [8:0] _zz_banks_0_readOr_value_valid_3; + wire when_MemoryCore_l221_2; + reg _zz_banks_1_readOr_value_valid_2; + reg [8:0] _zz_banks_1_readOr_value_valid_3; + wire when_MemoryCore_l221_3; + reg [9:0] initialiser_counter; + wire initialiser_done; + wire when_MemoryCore_l239; + wire [71:0] _zz_banks_0_write_payload_data_data; + wire [71:0] _zz_banks_1_write_payload_data_data; + wire [81:0] _zz_banks_0_writeOr_value_valid_8; + wire [80:0] _zz_banks_0_writeOr_value_payload_address; + wire [71:0] _zz_banks_0_writeOr_value_payload_data_data; + wire [9:0] _zz_banks_0_readOr_value_valid_4; + wire [81:0] _zz_banks_1_writeOr_value_valid_8; + wire [80:0] _zz_banks_1_writeOr_value_payload_address; + wire [71:0] _zz_banks_1_writeOr_value_payload_data_data; + wire [9:0] _zz_banks_1_readOr_value_valid_4; + (* ram_style = "block" *) reg [71:0] banks_0_ram [0:511]; + (* ram_style = "block" *) reg [71:0] banks_1_ram [0:511]; + + assign _zz_write_ports_0_priority_value = {2'd0, io_writes_0_cmd_payload_priority}; + assign _zz_when_MemoryCore_l136 = (io_writes_0_cmd_payload_address ^ 10'h0); + assign _zz_when_MemoryCore_l136_1 = (io_writes_0_cmd_payload_address ^ 10'h001); + assign _zz_read_ports_0_priority_value = {2'd0, read_ports_0_cmd_payload_priority}; + assign _zz_when_MemoryCore_l221 = (read_ports_0_cmd_payload_address ^ 10'h0); + assign _zz_when_MemoryCore_l221_1 = (read_ports_0_cmd_payload_address ^ 10'h001); + assign _zz_banks_0_ram_port = {banks_0_write_payload_data_mask,banks_0_write_payload_data_data}; + assign _zz_banks_1_ram_port = {banks_1_write_payload_data_mask,banks_1_write_payload_data_data}; + always @(posedge clk) begin + if(_zz_2) begin + banks_0_ram[banks_0_write_payload_address] <= _zz_banks_0_ram_port; + end + end + + always @(posedge clk) begin + if(banks_0_read_cmd_valid) begin + banks_0_ram_spinal_port1 <= banks_0_ram[banks_0_read_cmd_payload]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin + banks_1_ram[banks_1_write_payload_address] <= _zz_banks_1_ram_port; + end + end + + always @(posedge clk) begin + if(banks_1_read_cmd_valid) begin + banks_1_ram_spinal_port1 <= banks_1_ram[banks_1_read_cmd_payload]; + end + end + + initial begin + `ifndef SYNTHESIS + write_ports_0_priority_value = {$urandom}; + read_ports_0_priority_value = {$urandom}; + `endif + end + + always @(*) begin + case(read_ports_0_buffer_groupSel) + 1'b0 : begin + _zz_read_ports_0_buffer_bufferIn_payload_data = banks_0_read_rsp_data; + _zz_read_ports_0_buffer_bufferIn_payload_mask = banks_0_read_rsp_mask; + end + default : begin + _zz_read_ports_0_buffer_bufferIn_payload_data = banks_1_read_rsp_data; + _zz_read_ports_0_buffer_bufferIn_payload_mask = banks_1_read_rsp_mask; + end + endcase + end + + always @(*) begin + _zz_1 = 1'b0; + if(banks_1_write_valid) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + _zz_2 = 1'b0; + if(banks_0_write_valid) begin + _zz_2 = 1'b1; + end + end + + assign _zz_banks_0_read_rsp_data = banks_0_ram_spinal_port1; + assign banks_0_read_rsp_data = _zz_banks_0_read_rsp_data[63 : 0]; + assign banks_0_read_rsp_mask = _zz_banks_0_read_rsp_data[71 : 64]; + always @(*) begin + banks_0_write_valid = banks_0_writeOr_value_valid; + if(when_MemoryCore_l239) begin + banks_0_write_valid = 1'b1; + end + end + + always @(*) begin + banks_0_write_payload_address = banks_0_writeOr_value_payload_address; + if(when_MemoryCore_l239) begin + banks_0_write_payload_address = initialiser_counter[8:0]; + end + end + + always @(*) begin + banks_0_write_payload_data_data = banks_0_writeOr_value_payload_data_data; + if(when_MemoryCore_l239) begin + banks_0_write_payload_data_data = _zz_banks_0_write_payload_data_data[63 : 0]; + end + end + + always @(*) begin + banks_0_write_payload_data_mask = banks_0_writeOr_value_payload_data_mask; + if(when_MemoryCore_l239) begin + banks_0_write_payload_data_mask = _zz_banks_0_write_payload_data_data[71 : 64]; + end + end + + assign banks_0_read_cmd_valid = banks_0_readOr_value_valid; + assign banks_0_read_cmd_payload = banks_0_readOr_value_payload; + assign _zz_banks_1_read_rsp_data = banks_1_ram_spinal_port1; + assign banks_1_read_rsp_data = _zz_banks_1_read_rsp_data[63 : 0]; + assign banks_1_read_rsp_mask = _zz_banks_1_read_rsp_data[71 : 64]; + always @(*) begin + banks_1_write_valid = banks_1_writeOr_value_valid; + if(when_MemoryCore_l239) begin + banks_1_write_valid = 1'b1; + end + end + + always @(*) begin + banks_1_write_payload_address = banks_1_writeOr_value_payload_address; + if(when_MemoryCore_l239) begin + banks_1_write_payload_address = initialiser_counter[8:0]; + end + end + + always @(*) begin + banks_1_write_payload_data_data = banks_1_writeOr_value_payload_data_data; + if(when_MemoryCore_l239) begin + banks_1_write_payload_data_data = _zz_banks_1_write_payload_data_data[63 : 0]; + end + end + + always @(*) begin + banks_1_write_payload_data_mask = banks_1_writeOr_value_payload_data_mask; + if(when_MemoryCore_l239) begin + banks_1_write_payload_data_mask = _zz_banks_1_write_payload_data_data[71 : 64]; + end + end + + assign banks_1_read_cmd_valid = banks_1_readOr_value_valid; + assign banks_1_read_cmd_payload = banks_1_readOr_value_payload; + assign write_nodes_0_1_priority = 1'b0; + assign write_nodes_1_0_priority = 1'b1; + assign write_nodes_0_1_conflict = ((io_writes_0_cmd_valid && io_writes_1_cmd_valid) && (((io_writes_0_cmd_payload_address ^ io_writes_1_cmd_payload_address) & 10'h0) == 10'h0)); + assign write_nodes_1_0_conflict = write_nodes_0_1_conflict; + assign write_arbiter_0_losedAgainst = (write_nodes_0_1_conflict && (! write_nodes_0_1_priority)); + always @(*) begin + write_arbiter_0_doIt = (io_writes_0_cmd_valid && (write_arbiter_0_losedAgainst == 1'b0)); + if(when_MemoryCore_l239) begin + write_arbiter_0_doIt = 1'b0; + end + end + + assign when_MemoryCore_l136 = (write_arbiter_0_doIt && (_zz_when_MemoryCore_l136[0 : 0] == 1'b0)); + always @(*) begin + if(when_MemoryCore_l136) begin + _zz_banks_0_writeOr_value_valid = 1'b1; + end else begin + _zz_banks_0_writeOr_value_valid = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l136) begin + _zz_banks_0_writeOr_value_valid_1 = (io_writes_0_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_0_writeOr_value_valid_1 = 9'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136) begin + _zz_banks_0_writeOr_value_valid_2 = io_writes_0_cmd_payload_data[63 : 0]; + end else begin + _zz_banks_0_writeOr_value_valid_2 = 64'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136) begin + _zz_banks_0_writeOr_value_valid_3 = io_writes_0_cmd_payload_mask[7 : 0]; + end else begin + _zz_banks_0_writeOr_value_valid_3 = 8'h0; + end + end + + assign when_MemoryCore_l136_1 = (write_arbiter_0_doIt && (_zz_when_MemoryCore_l136_1[0 : 0] == 1'b0)); + always @(*) begin + if(when_MemoryCore_l136_1) begin + _zz_banks_1_writeOr_value_valid = 1'b1; + end else begin + _zz_banks_1_writeOr_value_valid = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_1) begin + _zz_banks_1_writeOr_value_valid_1 = (io_writes_0_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_1_writeOr_value_valid_1 = 9'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_1) begin + _zz_banks_1_writeOr_value_valid_2 = io_writes_0_cmd_payload_data[63 : 0]; + end else begin + _zz_banks_1_writeOr_value_valid_2 = 64'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_1) begin + _zz_banks_1_writeOr_value_valid_3 = io_writes_0_cmd_payload_mask[7 : 0]; + end else begin + _zz_banks_1_writeOr_value_valid_3 = 8'h0; + end + end + + assign io_writes_0_cmd_ready = write_arbiter_0_doIt; + assign io_writes_0_rsp_valid = write_arbiter_0_doIt_regNext; + assign io_writes_0_rsp_payload_context = io_writes_0_cmd_payload_context_regNext; + assign write_arbiter_1_losedAgainst = (write_nodes_1_0_conflict && (! write_nodes_1_0_priority)); + always @(*) begin + write_arbiter_1_doIt = (io_writes_1_cmd_valid && (write_arbiter_1_losedAgainst == 1'b0)); + if(when_MemoryCore_l239) begin + write_arbiter_1_doIt = 1'b0; + end + end + + assign when_MemoryCore_l136_2 = (write_arbiter_1_doIt && 1'b1); + always @(*) begin + if(when_MemoryCore_l136_2) begin + _zz_banks_0_writeOr_value_valid_4 = 1'b1; + end else begin + _zz_banks_0_writeOr_value_valid_4 = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_2) begin + _zz_banks_0_writeOr_value_valid_5 = (io_writes_1_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_0_writeOr_value_valid_5 = 9'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_2) begin + _zz_banks_0_writeOr_value_valid_6 = io_writes_1_cmd_payload_data[63 : 0]; + end else begin + _zz_banks_0_writeOr_value_valid_6 = 64'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_2) begin + _zz_banks_0_writeOr_value_valid_7 = io_writes_1_cmd_payload_mask[7 : 0]; + end else begin + _zz_banks_0_writeOr_value_valid_7 = 8'h0; + end + end + + assign when_MemoryCore_l136_3 = (write_arbiter_1_doIt && 1'b1); + always @(*) begin + if(when_MemoryCore_l136_3) begin + _zz_banks_1_writeOr_value_valid_4 = 1'b1; + end else begin + _zz_banks_1_writeOr_value_valid_4 = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_3) begin + _zz_banks_1_writeOr_value_valid_5 = (io_writes_1_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_1_writeOr_value_valid_5 = 9'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_3) begin + _zz_banks_1_writeOr_value_valid_6 = io_writes_1_cmd_payload_data[127 : 64]; + end else begin + _zz_banks_1_writeOr_value_valid_6 = 64'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_3) begin + _zz_banks_1_writeOr_value_valid_7 = io_writes_1_cmd_payload_mask[15 : 8]; + end else begin + _zz_banks_1_writeOr_value_valid_7 = 8'h0; + end + end + + assign io_writes_1_cmd_ready = write_arbiter_1_doIt; + assign io_writes_1_rsp_valid = write_arbiter_1_doIt_regNext; + assign io_writes_1_rsp_payload_context = io_writes_1_cmd_payload_context_regNext; + assign read_ports_0_buffer_groupSel = read_ports_0_buffer_s1_payload_address[0 : 0]; + assign read_ports_0_buffer_bufferIn_valid = read_ports_0_buffer_s1_valid; + assign read_ports_0_buffer_bufferIn_payload_context = read_ports_0_buffer_s1_payload_context; + assign read_ports_0_buffer_bufferIn_payload_data = _zz_read_ports_0_buffer_bufferIn_payload_data; + assign read_ports_0_buffer_bufferIn_payload_mask = _zz_read_ports_0_buffer_bufferIn_payload_mask; + assign read_ports_0_buffer_bufferIn_ready = read_ports_0_buffer_bufferIn_rValidN; + assign read_ports_0_buffer_bufferOut_valid = (read_ports_0_buffer_bufferIn_valid || (! read_ports_0_buffer_bufferIn_rValidN)); + assign read_ports_0_buffer_bufferOut_payload_data = (read_ports_0_buffer_bufferIn_rValidN ? read_ports_0_buffer_bufferIn_payload_data : read_ports_0_buffer_bufferIn_rData_data); + assign read_ports_0_buffer_bufferOut_payload_mask = (read_ports_0_buffer_bufferIn_rValidN ? read_ports_0_buffer_bufferIn_payload_mask : read_ports_0_buffer_bufferIn_rData_mask); + assign read_ports_0_buffer_bufferOut_payload_context = (read_ports_0_buffer_bufferIn_rValidN ? read_ports_0_buffer_bufferIn_payload_context : read_ports_0_buffer_bufferIn_rData_context); + assign io_reads_0_rsp_valid = read_ports_0_buffer_bufferOut_valid; + assign read_ports_0_buffer_bufferOut_ready = io_reads_0_rsp_ready; + assign io_reads_0_rsp_payload_data = read_ports_0_buffer_bufferOut_payload_data; + assign io_reads_0_rsp_payload_mask = read_ports_0_buffer_bufferOut_payload_mask; + assign io_reads_0_rsp_payload_context = read_ports_0_buffer_bufferOut_payload_context; + assign read_ports_0_buffer_full = (read_ports_0_buffer_bufferOut_valid && (! read_ports_0_buffer_bufferOut_ready)); + assign _zz_io_reads_0_cmd_ready = (! read_ports_0_buffer_full); + assign read_ports_0_cmd_valid = (io_reads_0_cmd_valid && _zz_io_reads_0_cmd_ready); + assign io_reads_0_cmd_ready = (read_ports_0_cmd_ready && _zz_io_reads_0_cmd_ready); + assign read_ports_0_cmd_payload_address = io_reads_0_cmd_payload_address; + assign read_ports_0_cmd_payload_priority = io_reads_0_cmd_payload_priority; + assign read_ports_0_cmd_payload_context = io_reads_0_cmd_payload_context; + assign read_ports_1_buffer_bufferIn_valid = read_ports_1_buffer_s1_valid; + assign read_ports_1_buffer_bufferIn_payload_context = read_ports_1_buffer_s1_payload_context; + assign read_ports_1_buffer_bufferIn_payload_data = {banks_1_read_rsp_data,banks_0_read_rsp_data}; + assign read_ports_1_buffer_bufferIn_payload_mask = {banks_1_read_rsp_mask,banks_0_read_rsp_mask}; + assign read_ports_1_buffer_bufferIn_ready = read_ports_1_buffer_bufferIn_rValidN; + assign read_ports_1_buffer_bufferOut_valid = (read_ports_1_buffer_bufferIn_valid || (! read_ports_1_buffer_bufferIn_rValidN)); + assign read_ports_1_buffer_bufferOut_payload_data = (read_ports_1_buffer_bufferIn_rValidN ? read_ports_1_buffer_bufferIn_payload_data : read_ports_1_buffer_bufferIn_rData_data); + assign read_ports_1_buffer_bufferOut_payload_mask = (read_ports_1_buffer_bufferIn_rValidN ? read_ports_1_buffer_bufferIn_payload_mask : read_ports_1_buffer_bufferIn_rData_mask); + assign read_ports_1_buffer_bufferOut_payload_context = (read_ports_1_buffer_bufferIn_rValidN ? read_ports_1_buffer_bufferIn_payload_context : read_ports_1_buffer_bufferIn_rData_context); + assign io_reads_1_rsp_valid = read_ports_1_buffer_bufferOut_valid; + assign read_ports_1_buffer_bufferOut_ready = io_reads_1_rsp_ready; + assign io_reads_1_rsp_payload_data = read_ports_1_buffer_bufferOut_payload_data; + assign io_reads_1_rsp_payload_mask = read_ports_1_buffer_bufferOut_payload_mask; + assign io_reads_1_rsp_payload_context = read_ports_1_buffer_bufferOut_payload_context; + assign read_ports_1_buffer_full = (read_ports_1_buffer_bufferOut_valid && (! read_ports_1_buffer_bufferOut_ready)); + assign _zz_io_reads_1_cmd_ready = (! read_ports_1_buffer_full); + assign read_ports_1_cmd_valid = (io_reads_1_cmd_valid && _zz_io_reads_1_cmd_ready); + assign io_reads_1_cmd_ready = (read_ports_1_cmd_ready && _zz_io_reads_1_cmd_ready); + assign read_ports_1_cmd_payload_address = io_reads_1_cmd_payload_address; + assign read_ports_1_cmd_payload_context = io_reads_1_cmd_payload_context; + assign read_nodes_0_1_priority = 1'b0; + assign read_nodes_1_0_priority = 1'b1; + assign read_nodes_0_1_conflict = ((read_ports_0_cmd_valid && read_ports_1_cmd_valid) && (((read_ports_0_cmd_payload_address ^ io_reads_1_cmd_payload_address) & 10'h0) == 10'h0)); + assign read_nodes_1_0_conflict = read_nodes_0_1_conflict; + assign read_arbiter_0_losedAgainst = (read_nodes_0_1_conflict && (! read_nodes_0_1_priority)); + assign read_arbiter_0_doIt = (read_ports_0_cmd_valid && (read_arbiter_0_losedAgainst == 1'b0)); + assign when_MemoryCore_l221 = (read_arbiter_0_doIt && (_zz_when_MemoryCore_l221[0 : 0] == 1'b0)); + always @(*) begin + if(when_MemoryCore_l221) begin + _zz_banks_0_readOr_value_valid = 1'b1; + end else begin + _zz_banks_0_readOr_value_valid = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l221) begin + _zz_banks_0_readOr_value_valid_1 = (read_ports_0_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_0_readOr_value_valid_1 = 9'h0; + end + end + + assign when_MemoryCore_l221_1 = (read_arbiter_0_doIt && (_zz_when_MemoryCore_l221_1[0 : 0] == 1'b0)); + always @(*) begin + if(when_MemoryCore_l221_1) begin + _zz_banks_1_readOr_value_valid = 1'b1; + end else begin + _zz_banks_1_readOr_value_valid = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l221_1) begin + _zz_banks_1_readOr_value_valid_1 = (read_ports_0_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_1_readOr_value_valid_1 = 9'h0; + end + end + + assign read_ports_0_cmd_ready = read_arbiter_0_doIt; + assign read_ports_0_buffer_s0_valid = read_arbiter_0_doIt; + assign read_ports_0_buffer_s0_payload_context = read_ports_0_cmd_payload_context; + assign read_ports_0_buffer_s0_payload_address = read_ports_0_cmd_payload_address; + assign read_arbiter_1_losedAgainst = (read_nodes_1_0_conflict && (! read_nodes_1_0_priority)); + assign read_arbiter_1_doIt = (read_ports_1_cmd_valid && (read_arbiter_1_losedAgainst == 1'b0)); + assign when_MemoryCore_l221_2 = (read_arbiter_1_doIt && 1'b1); + always @(*) begin + if(when_MemoryCore_l221_2) begin + _zz_banks_0_readOr_value_valid_2 = 1'b1; + end else begin + _zz_banks_0_readOr_value_valid_2 = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l221_2) begin + _zz_banks_0_readOr_value_valid_3 = (read_ports_1_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_0_readOr_value_valid_3 = 9'h0; + end + end + + assign when_MemoryCore_l221_3 = (read_arbiter_1_doIt && 1'b1); + always @(*) begin + if(when_MemoryCore_l221_3) begin + _zz_banks_1_readOr_value_valid_2 = 1'b1; + end else begin + _zz_banks_1_readOr_value_valid_2 = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l221_3) begin + _zz_banks_1_readOr_value_valid_3 = (read_ports_1_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_1_readOr_value_valid_3 = 9'h0; + end + end + + assign read_ports_1_cmd_ready = read_arbiter_1_doIt; + assign read_ports_1_buffer_s0_valid = read_arbiter_1_doIt; + assign read_ports_1_buffer_s0_payload_context = read_ports_1_cmd_payload_context; + assign read_ports_1_buffer_s0_payload_address = read_ports_1_cmd_payload_address; + assign initialiser_done = initialiser_counter[9]; + assign when_MemoryCore_l239 = (! initialiser_done); + assign _zz_banks_0_write_payload_data_data = 72'h0; + assign _zz_banks_1_write_payload_data_data = 72'h0; + assign _zz_banks_0_writeOr_value_valid_8 = ({{{_zz_banks_0_writeOr_value_valid_3,_zz_banks_0_writeOr_value_valid_2},_zz_banks_0_writeOr_value_valid_1},_zz_banks_0_writeOr_value_valid} | {{{_zz_banks_0_writeOr_value_valid_7,_zz_banks_0_writeOr_value_valid_6},_zz_banks_0_writeOr_value_valid_5},_zz_banks_0_writeOr_value_valid_4}); + assign banks_0_writeOr_value_valid = _zz_banks_0_writeOr_value_valid_8[0]; + assign _zz_banks_0_writeOr_value_payload_address = _zz_banks_0_writeOr_value_valid_8[81 : 1]; + assign banks_0_writeOr_value_payload_address = _zz_banks_0_writeOr_value_payload_address[8 : 0]; + assign _zz_banks_0_writeOr_value_payload_data_data = _zz_banks_0_writeOr_value_payload_address[80 : 9]; + assign banks_0_writeOr_value_payload_data_data = _zz_banks_0_writeOr_value_payload_data_data[63 : 0]; + assign banks_0_writeOr_value_payload_data_mask = _zz_banks_0_writeOr_value_payload_data_data[71 : 64]; + assign _zz_banks_0_readOr_value_valid_4 = ({_zz_banks_0_readOr_value_valid_1,_zz_banks_0_readOr_value_valid} | {_zz_banks_0_readOr_value_valid_3,_zz_banks_0_readOr_value_valid_2}); + assign banks_0_readOr_value_valid = _zz_banks_0_readOr_value_valid_4[0]; + assign banks_0_readOr_value_payload = _zz_banks_0_readOr_value_valid_4[9 : 1]; + assign _zz_banks_1_writeOr_value_valid_8 = ({{{_zz_banks_1_writeOr_value_valid_3,_zz_banks_1_writeOr_value_valid_2},_zz_banks_1_writeOr_value_valid_1},_zz_banks_1_writeOr_value_valid} | {{{_zz_banks_1_writeOr_value_valid_7,_zz_banks_1_writeOr_value_valid_6},_zz_banks_1_writeOr_value_valid_5},_zz_banks_1_writeOr_value_valid_4}); + assign banks_1_writeOr_value_valid = _zz_banks_1_writeOr_value_valid_8[0]; + assign _zz_banks_1_writeOr_value_payload_address = _zz_banks_1_writeOr_value_valid_8[81 : 1]; + assign banks_1_writeOr_value_payload_address = _zz_banks_1_writeOr_value_payload_address[8 : 0]; + assign _zz_banks_1_writeOr_value_payload_data_data = _zz_banks_1_writeOr_value_payload_address[80 : 9]; + assign banks_1_writeOr_value_payload_data_data = _zz_banks_1_writeOr_value_payload_data_data[63 : 0]; + assign banks_1_writeOr_value_payload_data_mask = _zz_banks_1_writeOr_value_payload_data_data[71 : 64]; + assign _zz_banks_1_readOr_value_valid_4 = ({_zz_banks_1_readOr_value_valid_1,_zz_banks_1_readOr_value_valid} | {_zz_banks_1_readOr_value_valid_3,_zz_banks_1_readOr_value_valid_2}); + assign banks_1_readOr_value_valid = _zz_banks_1_readOr_value_valid_4[0]; + assign banks_1_readOr_value_payload = _zz_banks_1_readOr_value_valid_4[9 : 1]; + always @(posedge clk) begin + if(io_writes_0_cmd_valid) begin + write_ports_0_priority_value <= (write_ports_0_priority_value + _zz_write_ports_0_priority_value); + if(io_writes_0_cmd_ready) begin + write_ports_0_priority_value <= 4'b0000; + end + end + io_writes_0_cmd_payload_context_regNext <= io_writes_0_cmd_payload_context; + io_writes_1_cmd_payload_context_regNext <= io_writes_1_cmd_payload_context; + read_ports_0_buffer_s1_payload_context <= read_ports_0_buffer_s0_payload_context; + read_ports_0_buffer_s1_payload_address <= read_ports_0_buffer_s0_payload_address; + if(read_ports_0_buffer_bufferIn_ready) begin + read_ports_0_buffer_bufferIn_rData_data <= read_ports_0_buffer_bufferIn_payload_data; + read_ports_0_buffer_bufferIn_rData_mask <= read_ports_0_buffer_bufferIn_payload_mask; + read_ports_0_buffer_bufferIn_rData_context <= read_ports_0_buffer_bufferIn_payload_context; + end + if(read_ports_0_cmd_valid) begin + read_ports_0_priority_value <= (read_ports_0_priority_value + _zz_read_ports_0_priority_value); + if(read_ports_0_cmd_ready) begin + read_ports_0_priority_value <= 4'b0000; + end + end + read_ports_1_buffer_s1_payload_context <= read_ports_1_buffer_s0_payload_context; + read_ports_1_buffer_s1_payload_address <= read_ports_1_buffer_s0_payload_address; + if(read_ports_1_buffer_bufferIn_ready) begin + read_ports_1_buffer_bufferIn_rData_data <= read_ports_1_buffer_bufferIn_payload_data; + read_ports_1_buffer_bufferIn_rData_mask <= read_ports_1_buffer_bufferIn_payload_mask; + read_ports_1_buffer_bufferIn_rData_context <= read_ports_1_buffer_bufferIn_payload_context; + end + end + + always @(posedge clk) begin + if(reset) begin + write_arbiter_0_doIt_regNext <= 1'b0; + write_arbiter_1_doIt_regNext <= 1'b0; + read_ports_0_buffer_s1_valid <= 1'b0; + read_ports_0_buffer_bufferIn_rValidN <= 1'b1; + read_ports_1_buffer_s1_valid <= 1'b0; + read_ports_1_buffer_bufferIn_rValidN <= 1'b1; + initialiser_counter <= 10'h0; + end else begin + write_arbiter_0_doIt_regNext <= write_arbiter_0_doIt; + write_arbiter_1_doIt_regNext <= write_arbiter_1_doIt; + read_ports_0_buffer_s1_valid <= read_ports_0_buffer_s0_valid; + if(read_ports_0_buffer_bufferIn_valid) begin + read_ports_0_buffer_bufferIn_rValidN <= 1'b0; + end + if(read_ports_0_buffer_bufferOut_ready) begin + read_ports_0_buffer_bufferIn_rValidN <= 1'b1; + end + read_ports_1_buffer_s1_valid <= read_ports_1_buffer_s0_valid; + if(read_ports_1_buffer_bufferIn_valid) begin + read_ports_1_buffer_bufferIn_rValidN <= 1'b0; + end + if(read_ports_1_buffer_bufferOut_ready) begin + read_ports_1_buffer_bufferIn_rValidN <= 1'b1; + end + if(when_MemoryCore_l239) begin + initialiser_counter <= (initialiser_counter + 10'h001); + end + end + end + + +endmodule + +module EfxDMA_StreamFifo_1_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_push_valid, + output wire io_push_ready, + input wire [13:0] io_push_payload_context, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [13:0] io_pop_payload_context, + input wire io_flush, + output wire [2:0] io_occupancy, + output wire [2:0] io_availability, + input wire clk, + input wire reset +); + + reg [13:0] logic_ram_spinal_port1; + wire [2:0] _zz_logic_ptr_notPow2_counter; + wire [2:0] _zz_logic_ptr_notPow2_counter_1; + wire [0:0] _zz_logic_ptr_notPow2_counter_2; + wire [2:0] _zz_logic_ptr_notPow2_counter_3; + wire [0:0] _zz_logic_ptr_notPow2_counter_4; + reg _zz_1; + wire logic_ptr_doPush; + wire logic_ptr_doPop; + wire logic_ptr_full; + wire logic_ptr_empty; + reg [2:0] logic_ptr_push; + reg [2:0] logic_ptr_pop; + wire [2:0] logic_ptr_occupancy; + wire [2:0] logic_ptr_popOnIo; + wire when_Stream_l1248; + reg logic_ptr_wentUp; + wire when_Stream_l1283; + wire when_Stream_l1287; + reg [2:0] logic_ptr_notPow2_counter; + wire io_push_fire; + wire io_pop_fire; + wire logic_push_onRam_write_valid; + wire [2:0] logic_push_onRam_write_payload_address; + wire [13:0] logic_push_onRam_write_payload_data_context; + wire logic_pop_addressGen_valid; + reg logic_pop_addressGen_ready; + wire [2:0] logic_pop_addressGen_payload; + wire logic_pop_addressGen_fire; + wire logic_pop_sync_readArbitation_valid; + wire logic_pop_sync_readArbitation_ready; + wire [2:0] logic_pop_sync_readArbitation_payload; + reg logic_pop_addressGen_rValid; + reg [2:0] logic_pop_addressGen_rData; + wire when_Stream_l375; + wire logic_pop_sync_readPort_cmd_valid; + wire [2:0] logic_pop_sync_readPort_cmd_payload; + wire [13:0] logic_pop_sync_readPort_rsp_context; + wire logic_pop_sync_readArbitation_translated_valid; + wire logic_pop_sync_readArbitation_translated_ready; + wire [13:0] logic_pop_sync_readArbitation_translated_payload_context; + wire logic_pop_sync_readArbitation_fire; + reg [2:0] logic_pop_sync_popReg; + reg [13:0] logic_ram [0:6]; + + assign _zz_logic_ptr_notPow2_counter = (logic_ptr_notPow2_counter + _zz_logic_ptr_notPow2_counter_1); + assign _zz_logic_ptr_notPow2_counter_2 = io_push_fire; + assign _zz_logic_ptr_notPow2_counter_1 = {2'd0, _zz_logic_ptr_notPow2_counter_2}; + assign _zz_logic_ptr_notPow2_counter_4 = io_pop_fire; + assign _zz_logic_ptr_notPow2_counter_3 = {2'd0, _zz_logic_ptr_notPow2_counter_4}; + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data_context; + end + end + + always @(posedge clk) begin + if(logic_pop_sync_readPort_cmd_valid) begin + logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_push_onRam_write_valid) begin + _zz_1 = 1'b1; + end + end + + assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); + assign logic_ptr_full = ((logic_ptr_push == logic_ptr_popOnIo) && logic_ptr_wentUp); + assign logic_ptr_empty = ((logic_ptr_push == logic_ptr_pop) && (! logic_ptr_wentUp)); + assign when_Stream_l1283 = (logic_ptr_push == 3'b110); + assign when_Stream_l1287 = (logic_ptr_pop == 3'b110); + assign io_push_fire = (io_push_valid && io_push_ready); + assign io_pop_fire = (io_pop_valid && io_pop_ready); + assign logic_ptr_occupancy = logic_ptr_notPow2_counter; + assign io_push_ready = (! logic_ptr_full); + assign logic_ptr_doPush = io_push_fire; + assign logic_push_onRam_write_valid = io_push_fire; + assign logic_push_onRam_write_payload_address = logic_ptr_push; + assign logic_push_onRam_write_payload_data_context = io_push_payload_context; + assign logic_pop_addressGen_valid = (! logic_ptr_empty); + assign logic_pop_addressGen_payload = logic_ptr_pop; + assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); + assign logic_ptr_doPop = logic_pop_addressGen_fire; + always @(*) begin + logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; + if(when_Stream_l375) begin + logic_pop_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); + assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; + assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; + assign logic_pop_sync_readPort_rsp_context = logic_ram_spinal_port1[13 : 0]; + assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; + assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; + assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; + assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; + assign logic_pop_sync_readArbitation_translated_payload_context = logic_pop_sync_readPort_rsp_context; + assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; + assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_context = logic_pop_sync_readArbitation_translated_payload_context; + assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); + assign logic_ptr_popOnIo = logic_pop_sync_popReg; + assign io_occupancy = logic_ptr_occupancy; + assign io_availability = (3'b111 - logic_ptr_occupancy); + always @(posedge clk) begin + if(reset) begin + logic_ptr_push <= 3'b000; + logic_ptr_pop <= 3'b000; + logic_ptr_wentUp <= 1'b0; + logic_ptr_notPow2_counter <= 3'b000; + logic_pop_addressGen_rValid <= 1'b0; + logic_pop_sync_popReg <= 3'b000; + end else begin + if(when_Stream_l1248) begin + logic_ptr_wentUp <= logic_ptr_doPush; + end + if(io_flush) begin + logic_ptr_wentUp <= 1'b0; + end + if(logic_ptr_doPush) begin + logic_ptr_push <= (logic_ptr_push + 3'b001); + if(when_Stream_l1283) begin + logic_ptr_push <= 3'b000; + end + end + if(logic_ptr_doPop) begin + logic_ptr_pop <= (logic_ptr_pop + 3'b001); + if(when_Stream_l1287) begin + logic_ptr_pop <= 3'b000; + end + end + if(io_flush) begin + logic_ptr_push <= 3'b000; + logic_ptr_pop <= 3'b000; + end + logic_ptr_notPow2_counter <= (_zz_logic_ptr_notPow2_counter - _zz_logic_ptr_notPow2_counter_3); + if(io_flush) begin + logic_ptr_notPow2_counter <= 3'b000; + end + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; + end + if(io_flush) begin + logic_pop_addressGen_rValid <= 1'b0; + end + if(logic_pop_sync_readArbitation_fire) begin + logic_pop_sync_popReg <= logic_ptr_pop; + end + if(io_flush) begin + logic_pop_sync_popReg <= 3'b000; + end + end + end + + always @(posedge clk) begin + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rData <= logic_pop_addressGen_payload; + end + end + + +endmodule + +module EfxDMA_StreamFifo_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_push_valid, + output wire io_push_ready, + input wire [21:0] io_push_payload_context, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [21:0] io_pop_payload_context, + input wire io_flush, + output wire [2:0] io_occupancy, + output wire [2:0] io_availability, + input wire clk, + input wire reset +); + + reg [21:0] logic_ram_spinal_port1; + wire [2:0] _zz_logic_ptr_notPow2_counter; + wire [2:0] _zz_logic_ptr_notPow2_counter_1; + wire [0:0] _zz_logic_ptr_notPow2_counter_2; + wire [2:0] _zz_logic_ptr_notPow2_counter_3; + wire [0:0] _zz_logic_ptr_notPow2_counter_4; + reg _zz_1; + wire logic_ptr_doPush; + wire logic_ptr_doPop; + wire logic_ptr_full; + wire logic_ptr_empty; + reg [2:0] logic_ptr_push; + reg [2:0] logic_ptr_pop; + wire [2:0] logic_ptr_occupancy; + wire [2:0] logic_ptr_popOnIo; + wire when_Stream_l1248; + reg logic_ptr_wentUp; + wire when_Stream_l1283; + wire when_Stream_l1287; + reg [2:0] logic_ptr_notPow2_counter; + wire io_push_fire; + wire io_pop_fire; + wire logic_push_onRam_write_valid; + wire [2:0] logic_push_onRam_write_payload_address; + wire [21:0] logic_push_onRam_write_payload_data_context; + wire logic_pop_addressGen_valid; + reg logic_pop_addressGen_ready; + wire [2:0] logic_pop_addressGen_payload; + wire logic_pop_addressGen_fire; + wire logic_pop_sync_readArbitation_valid; + wire logic_pop_sync_readArbitation_ready; + wire [2:0] logic_pop_sync_readArbitation_payload; + reg logic_pop_addressGen_rValid; + reg [2:0] logic_pop_addressGen_rData; + wire when_Stream_l375; + wire logic_pop_sync_readPort_cmd_valid; + wire [2:0] logic_pop_sync_readPort_cmd_payload; + wire [21:0] logic_pop_sync_readPort_rsp_context; + wire logic_pop_sync_readArbitation_translated_valid; + wire logic_pop_sync_readArbitation_translated_ready; + wire [21:0] logic_pop_sync_readArbitation_translated_payload_context; + wire logic_pop_sync_readArbitation_fire; + reg [2:0] logic_pop_sync_popReg; + reg [21:0] logic_ram [0:6]; + + assign _zz_logic_ptr_notPow2_counter = (logic_ptr_notPow2_counter + _zz_logic_ptr_notPow2_counter_1); + assign _zz_logic_ptr_notPow2_counter_2 = io_push_fire; + assign _zz_logic_ptr_notPow2_counter_1 = {2'd0, _zz_logic_ptr_notPow2_counter_2}; + assign _zz_logic_ptr_notPow2_counter_4 = io_pop_fire; + assign _zz_logic_ptr_notPow2_counter_3 = {2'd0, _zz_logic_ptr_notPow2_counter_4}; + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data_context; + end + end + + always @(posedge clk) begin + if(logic_pop_sync_readPort_cmd_valid) begin + logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_push_onRam_write_valid) begin + _zz_1 = 1'b1; + end + end + + assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); + assign logic_ptr_full = ((logic_ptr_push == logic_ptr_popOnIo) && logic_ptr_wentUp); + assign logic_ptr_empty = ((logic_ptr_push == logic_ptr_pop) && (! logic_ptr_wentUp)); + assign when_Stream_l1283 = (logic_ptr_push == 3'b110); + assign when_Stream_l1287 = (logic_ptr_pop == 3'b110); + assign io_push_fire = (io_push_valid && io_push_ready); + assign io_pop_fire = (io_pop_valid && io_pop_ready); + assign logic_ptr_occupancy = logic_ptr_notPow2_counter; + assign io_push_ready = (! logic_ptr_full); + assign logic_ptr_doPush = io_push_fire; + assign logic_push_onRam_write_valid = io_push_fire; + assign logic_push_onRam_write_payload_address = logic_ptr_push; + assign logic_push_onRam_write_payload_data_context = io_push_payload_context; + assign logic_pop_addressGen_valid = (! logic_ptr_empty); + assign logic_pop_addressGen_payload = logic_ptr_pop; + assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); + assign logic_ptr_doPop = logic_pop_addressGen_fire; + always @(*) begin + logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; + if(when_Stream_l375) begin + logic_pop_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); + assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; + assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; + assign logic_pop_sync_readPort_rsp_context = logic_ram_spinal_port1[21 : 0]; + assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; + assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; + assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; + assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; + assign logic_pop_sync_readArbitation_translated_payload_context = logic_pop_sync_readPort_rsp_context; + assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; + assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_context = logic_pop_sync_readArbitation_translated_payload_context; + assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); + assign logic_ptr_popOnIo = logic_pop_sync_popReg; + assign io_occupancy = logic_ptr_occupancy; + assign io_availability = (3'b111 - logic_ptr_occupancy); + always @(posedge clk) begin + if(reset) begin + logic_ptr_push <= 3'b000; + logic_ptr_pop <= 3'b000; + logic_ptr_wentUp <= 1'b0; + logic_ptr_notPow2_counter <= 3'b000; + logic_pop_addressGen_rValid <= 1'b0; + logic_pop_sync_popReg <= 3'b000; + end else begin + if(when_Stream_l1248) begin + logic_ptr_wentUp <= logic_ptr_doPush; + end + if(io_flush) begin + logic_ptr_wentUp <= 1'b0; + end + if(logic_ptr_doPush) begin + logic_ptr_push <= (logic_ptr_push + 3'b001); + if(when_Stream_l1283) begin + logic_ptr_push <= 3'b000; + end + end + if(logic_ptr_doPop) begin + logic_ptr_pop <= (logic_ptr_pop + 3'b001); + if(when_Stream_l1287) begin + logic_ptr_pop <= 3'b000; + end + end + if(io_flush) begin + logic_ptr_push <= 3'b000; + logic_ptr_pop <= 3'b000; + end + logic_ptr_notPow2_counter <= (_zz_logic_ptr_notPow2_counter - _zz_logic_ptr_notPow2_counter_3); + if(io_flush) begin + logic_ptr_notPow2_counter <= 3'b000; + end + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; + end + if(io_flush) begin + logic_pop_addressGen_rValid <= 1'b0; + end + if(logic_pop_sync_readArbitation_fire) begin + logic_pop_sync_popReg <= logic_ptr_pop; + end + if(io_flush) begin + logic_pop_sync_popReg <= 3'b000; + end + end + end + + always @(posedge clk) begin + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rData <= logic_pop_addressGen_payload; + end + end + + +endmodule + +module EfxDMA_BufferCC_1_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_dataIn, + output wire io_dataOut, + input wire ctrl_clk, + input wire ctrl_reset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge ctrl_clk) begin + if(ctrl_reset) begin + buffers_0 <= 1'b0; + buffers_1 <= 1'b0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module EfxDMA_BufferCC_a048ca8f51874147a1cd65d43e6523ef ( + input wire io_dataIn, + output wire io_dataOut, + input wire clk, + input wire reset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge clk) begin + if(reset) begin + buffers_0 <= 1'b0; + buffers_1 <= 1'b0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Ti375C529_devkit/ip/gDMA/gDMA_define.vh b/Ti375C529_devkit/ip/gDMA/gDMA_define.vh new file mode 100644 index 0000000..9ddbd8e --- /dev/null +++ b/Ti375C529_devkit/ip/gDMA/gDMA_define.vh @@ -0,0 +1,45 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 6.4.2 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + diff --git a/Ti375C529_devkit/ip/gDMA/gDMA_tmpl.v b/Ti375C529_devkit/ip/gDMA/gDMA_tmpl.v new file mode 100644 index 0000000..a24f50a --- /dev/null +++ b/Ti375C529_devkit/ip/gDMA/gDMA_tmpl.v @@ -0,0 +1,114 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 6.4.2 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +gDMA u_gDMA +( + .clk ( clk ), + .ctrl_reset ( ctrl_reset ), + .reset ( reset ), + .ctrl_clk ( ctrl_clk ), + .ctrl_PADDR ( ctrl_PADDR ), + .ctrl_PREADY ( ctrl_PREADY ), + .ctrl_PENABLE ( ctrl_PENABLE ), + .ctrl_PSEL ( ctrl_PSEL ), + .ctrl_PWRITE ( ctrl_PWRITE ), + .ctrl_PWDATA ( ctrl_PWDATA ), + .ctrl_PRDATA ( ctrl_PRDATA ), + .ctrl_PSLVERROR ( ctrl_PSLVERROR ), + .ctrl_interrupts ( ctrl_interrupts ), + .read_arvalid ( read_arvalid ), + .read_araddr ( read_araddr ), + .read_arready ( read_arready ), + .read_arregion ( read_arregion ), + .read_arlen ( read_arlen ), + .read_arsize ( read_arsize ), + .read_arburst ( read_arburst ), + .read_arlock ( read_arlock ), + .read_arcache ( read_arcache ), + .read_arqos ( read_arqos ), + .read_arprot ( read_arprot ), + .read_rready ( read_rready ), + .read_rvalid ( read_rvalid ), + .read_rdata ( read_rdata ), + .read_rlast ( read_rlast ), + .write_awvalid ( write_awvalid ), + .write_awready ( write_awready ), + .write_awaddr ( write_awaddr ), + .write_awregion ( write_awregion ), + .write_awlen ( write_awlen ), + .write_awsize ( write_awsize ), + .write_awburst ( write_awburst ), + .write_awlock ( write_awlock ), + .write_awcache ( write_awcache ), + .write_awqos ( write_awqos ), + .write_awprot ( write_awprot ), + .write_wvalid ( write_wvalid ), + .write_wready ( write_wready ), + .write_wdata ( write_wdata ), + .write_wstrb ( write_wstrb ), + .write_wlast ( write_wlast ), + .write_bvalid ( write_bvalid ), + .write_bready ( write_bready ), + .write_bresp ( write_bresp ), + .dat1_o_tvalid ( dat1_o_tvalid ), + .dat1_o_tready ( dat1_o_tready ), + .dat1_o_tdata ( dat1_o_tdata ), + .dat1_o_tkeep ( dat1_o_tkeep ), + .dat1_o_tdest ( dat1_o_tdest ), + .dat1_o_tlast ( dat1_o_tlast ), + .io_0_descriptorUpdate ( io_0_descriptorUpdate ), + .dat1_o_clk ( dat1_o_clk ), + .dat1_o_reset ( dat1_o_reset ), + .dat0_i_clk ( dat0_i_clk ), + .dat0_i_reset ( dat0_i_reset ), + .dat0_i_tvalid ( dat0_i_tvalid ), + .dat0_i_tready ( dat0_i_tready ), + .dat0_i_tdata ( dat0_i_tdata ), + .dat0_i_tkeep ( dat0_i_tkeep ), + .dat0_i_tdest ( dat0_i_tdest ), + .dat0_i_tlast ( dat0_i_tlast ), + .read_rresp ( read_rresp ), + .io_1_descriptorUpdate ( io_1_descriptorUpdate ) +); diff --git a/Ti375C529_devkit/ip/gDMA/gDMA_tmpl.vhd b/Ti375C529_devkit/ip/gDMA/gDMA_tmpl.vhd new file mode 100644 index 0000000..3f0c81e --- /dev/null +++ b/Ti375C529_devkit/ip/gDMA/gDMA_tmpl.vhd @@ -0,0 +1,183 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +component gDMA is +port ( + clk : in std_logic; + ctrl_reset : in std_logic; + reset : in std_logic; + ctrl_clk : in std_logic; + ctrl_PADDR : in std_logic_vector(13 downto 0); + ctrl_PREADY : out std_logic; + ctrl_PENABLE : in std_logic; + ctrl_PSEL : in std_logic; + ctrl_PWRITE : in std_logic; + ctrl_PWDATA : in std_logic_vector(31 downto 0); + ctrl_PRDATA : out std_logic_vector(31 downto 0); + ctrl_PSLVERROR : out std_logic; + ctrl_interrupts : out std_logic_vector(1 downto 0); + read_arvalid : out std_logic; + read_araddr : out std_logic_vector(31 downto 0); + read_arready : in std_logic; + read_arregion : out std_logic_vector(3 downto 0); + read_arlen : out std_logic_vector(7 downto 0); + read_arsize : out std_logic_vector(2 downto 0); + read_arburst : out std_logic_vector(1 downto 0); + read_arlock : out std_logic; + read_arcache : out std_logic_vector(3 downto 0); + read_arqos : out std_logic_vector(3 downto 0); + read_arprot : out std_logic_vector(2 downto 0); + read_rready : out std_logic; + read_rvalid : in std_logic; + read_rdata : in std_logic_vector(127 downto 0); + read_rlast : in std_logic; + write_awvalid : out std_logic; + write_awready : in std_logic; + write_awaddr : out std_logic_vector(31 downto 0); + write_awregion : out std_logic_vector(3 downto 0); + write_awlen : out std_logic_vector(7 downto 0); + write_awsize : out std_logic_vector(2 downto 0); + write_awburst : out std_logic_vector(1 downto 0); + write_awlock : out std_logic; + write_awcache : out std_logic_vector(3 downto 0); + write_awqos : out std_logic_vector(3 downto 0); + write_awprot : out std_logic_vector(2 downto 0); + write_wvalid : out std_logic; + write_wready : in std_logic; + write_wdata : out std_logic_vector(127 downto 0); + write_wstrb : out std_logic_vector(15 downto 0); + write_wlast : out std_logic; + write_bvalid : in std_logic; + write_bready : out std_logic; + write_bresp : in std_logic_vector(1 downto 0); + dat1_o_tvalid : out std_logic; + dat1_o_tready : in std_logic; + dat1_o_tdata : out std_logic_vector(7 downto 0); + dat1_o_tkeep : out std_logic_vector(0 to 0); + dat1_o_tdest : out std_logic_vector(3 downto 0); + dat1_o_tlast : out std_logic; + io_0_descriptorUpdate : out std_logic; + dat1_o_clk : in std_logic; + dat1_o_reset : in std_logic; + dat0_i_clk : in std_logic; + dat0_i_reset : in std_logic; + dat0_i_tvalid : in std_logic; + dat0_i_tready : out std_logic; + dat0_i_tdata : in std_logic_vector(7 downto 0); + dat0_i_tkeep : in std_logic_vector(0 to 0); + dat0_i_tdest : in std_logic_vector(3 downto 0); + dat0_i_tlast : in std_logic; + read_rresp : in std_logic_vector(1 downto 0); + io_1_descriptorUpdate : out std_logic +); +end component gDMA; + +---------------------- End COMPONENT Declaration ------------ +------------- Begin Cut here for INSTANTIATION Template ----- +u_gDMA : gDMA +port map ( + clk => clk, + ctrl_reset => ctrl_reset, + reset => reset, + ctrl_clk => ctrl_clk, + ctrl_PADDR => ctrl_PADDR, + ctrl_PREADY => ctrl_PREADY, + ctrl_PENABLE => ctrl_PENABLE, + ctrl_PSEL => ctrl_PSEL, + ctrl_PWRITE => ctrl_PWRITE, + ctrl_PWDATA => ctrl_PWDATA, + ctrl_PRDATA => ctrl_PRDATA, + ctrl_PSLVERROR => ctrl_PSLVERROR, + ctrl_interrupts => ctrl_interrupts, + read_arvalid => read_arvalid, + read_araddr => read_araddr, + read_arready => read_arready, + read_arregion => read_arregion, + read_arlen => read_arlen, + read_arsize => read_arsize, + read_arburst => read_arburst, + read_arlock => read_arlock, + read_arcache => read_arcache, + read_arqos => read_arqos, + read_arprot => read_arprot, + read_rready => read_rready, + read_rvalid => read_rvalid, + read_rdata => read_rdata, + read_rlast => read_rlast, + write_awvalid => write_awvalid, + write_awready => write_awready, + write_awaddr => write_awaddr, + write_awregion => write_awregion, + write_awlen => write_awlen, + write_awsize => write_awsize, + write_awburst => write_awburst, + write_awlock => write_awlock, + write_awcache => write_awcache, + write_awqos => write_awqos, + write_awprot => write_awprot, + write_wvalid => write_wvalid, + write_wready => write_wready, + write_wdata => write_wdata, + write_wstrb => write_wstrb, + write_wlast => write_wlast, + write_bvalid => write_bvalid, + write_bready => write_bready, + write_bresp => write_bresp, + dat1_o_tvalid => dat1_o_tvalid, + dat1_o_tready => dat1_o_tready, + dat1_o_tdata => dat1_o_tdata, + dat1_o_tkeep => dat1_o_tkeep, + dat1_o_tdest => dat1_o_tdest, + dat1_o_tlast => dat1_o_tlast, + io_0_descriptorUpdate => io_0_descriptorUpdate, + dat1_o_clk => dat1_o_clk, + dat1_o_reset => dat1_o_reset, + dat0_i_clk => dat0_i_clk, + dat0_i_reset => dat0_i_reset, + dat0_i_tvalid => dat0_i_tvalid, + dat0_i_tready => dat0_i_tready, + dat0_i_tdata => dat0_i_tdata, + dat0_i_tkeep => dat0_i_tkeep, + dat0_i_tdest => dat0_i_tdest, + dat0_i_tlast => dat0_i_tlast, + read_rresp => read_rresp, + io_1_descriptorUpdate => io_1_descriptorUpdate +); + +------------------------ End INSTANTIATION Template --------- diff --git a/Ti375C529_devkit/ip/gDMA/ipm/component.pickle b/Ti375C529_devkit/ip/gDMA/ipm/component.pickle new file mode 100644 index 0000000..d3113f8 Binary files /dev/null and b/Ti375C529_devkit/ip/gDMA/ipm/component.pickle differ diff --git a/Ti375C529_devkit/ip/gDMA/ipm/graph.pickle b/Ti375C529_devkit/ip/gDMA/ipm/graph.pickle new file mode 100644 index 0000000..5031dee Binary files /dev/null and b/Ti375C529_devkit/ip/gDMA/ipm/graph.pickle differ diff --git a/Ti375C529_devkit/ip/gDMA/settings.json b/Ti375C529_devkit/ip/gDMA/settings.json new file mode 100644 index 0000000..7d11253 --- /dev/null +++ b/Ti375C529_devkit/ip/gDMA/settings.json @@ -0,0 +1,126 @@ +{ + "args": [ + "-o", + "gDMA", + "--base_path", + "/projects/SSE/llching/repo/efx_IP_master/efx_IP/efx_hard_soc/fpga/Ti375C529_devkit/ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "bridges_and_adaptors", + "name": "efx_dma", + "version": "6.4.2" + } + ], + "conf": { + "PriorityEncode": "1'b0", + "WrQueue": "1'b0", + "CTRL_ASYNC_MODE": "1'b1", + "EfinixDDR": "1'b0", + "RdQueue": "1'b0", + "BufferWidth": "64", + "BufferWords": "512", + "MemExtWidth": "128", + "CH0_SGMode": "1'b1", + "CH0_Output": "1'b0", + "CH0_Input": "1'b1", + "CH4_Input": "1'b1", + "CH4_Width": "32", + "CH4_Output": "1'b1", + "CH4_SGMode": "1'b0", + "CH4_SR": "1'b0", + "CH5_BurstSize": "64", + "CH5_BufferSize": "1024", + "CH5_SR": "1'b0", + "CH6_Output": "1'b1", + "CH6_SGMode": "1'b0", + "CH6_SR": "1'b0", + "CH7_Output": "1'b1", + "CH7_SGMode": "1'b0", + "CH7_SR": "1'b0", + "CH7_Input": "1'b1", + "CH7_Width": "32", + "CH7_BurstSize": "64", + "CH7_BufferSize": "1024", + "CH6_Width": "32", + "CH6_Input": "1'b1", + "CH6_BurstSize": "64", + "CH6_BufferSize": "1024", + "CH5_Width": "32", + "CH5_Output": "1'b1", + "CH5_SGMode": "1'b0", + "CH5_Input": "1'b1", + "CH4_BurstSize": "64", + "CH4_BufferSize": "1024", + "CH3_SR": "1'b0", + "CH3_SGMode": "1'b0", + "CH3_Output": "1'b1", + "CH3_Width": "32", + "CH3_Input": "1'b1", + "CH3_BufferSize": "1024", + "CH3_BurstSize": "64", + "BufferCount": "2", + "CH0_Enable": "1'b1", + "CH1_Enable": "1'b1", + "CH1_AsyncMode": "1'b1", + "CH6_AsyncMode": "1'b0", + "CH5_AsyncMode": "1'b0", + "CH7_AsyncMode": "1'b0", + "CH0_AsyncMode": "1'b1", + "CH3_AsyncMode": "1'b0", + "CH2_AsyncMode": "1'b0", + "CH4_AsyncMode": "1'b0", + "CH0_BufferSize": "4096", + "CH0_BurstSize": "1024", + "CH0_SR": "1'b0", + "CH0_Width": "8", + "CH1_Input": "1'b0", + "CH1_Width": "8", + "CH1_Output": "1'b1", + "CH1_SGMode": "1'b1", + "CH1_SR": "1'b0", + "CH2_BufferSize": "1024", + "CH2_BurstSize": "64", + "CH2_Width": "32", + "CH2_SR": "1'b0", + "CH2_SGMode": "1'b0", + "CH2_Output": "1'b1", + "CH2_Input": "1'b1", + "CH1_BufferSize": "4096", + "CH1_BurstSize": "1024", + "CH2_Enable_user": "1'b0", + "CH2_Enable_default": "1'b0", + "CH3_Enable_default": "1'b0", + "CH3_Enable_user": "1'b0", + "CH4_Enable_default": "1'b0", + "CH4_Enable_user": "1'b0", + "CH5_Enable_user": "1'b0", + "CH5_Enable_default": "1'b0", + "CH6_Enable_user": "1'b0", + "CH6_Enable_default": "1'b0", + "CH7_Enable_user": "1'b0", + "CH7_Enable_default": "1'b0", + "CustomSGBus": "1'b0", + "CH0_MemMode": "1'b0", + "CH1_MemMode": "1'b0", + "CH2_MemMode": "1'b0", + "CH3_MemMode": "1'b0", + "CH4_MemMode": "1'b0", + "CH5_MemMode": "1'b0", + "CH6_MemMode": "1'b0", + "CH7_MemMode": "1'b0" + }, + "output": { + "external_script_generator": [], + "external_source_source": [ + "gDMA/gDMA_define.vh", + "gDMA/gDMA.v", + "gDMA/gDMA_tmpl.v", + "gDMA/gDMA_tmpl.vhd" + ], + "external_script_script": [] + }, + "ooc_synthesis": {}, + "sw_version": "2025.2.272", + "generated_date": "2025-10-16T09:35:15.778966+00:00" +} \ No newline at end of file diff --git a/Ti375C529_devkit/ip/gDMA/source/EfxDMA.v b/Ti375C529_devkit/ip/gDMA/source/EfxDMA.v new file mode 100644 index 0000000..c77644c --- /dev/null +++ b/Ti375C529_devkit/ip/gDMA/source/EfxDMA.v @@ -0,0 +1,11449 @@ +// Generator : SpinalHDL dev git head : a69f4b9a329be784802c37cd8038b7dc9aec3094 +// Component : EfxDMA + +`timescale 1ns/1ps + +module EfxDMA ( + input wire [13:0] ctrl_PADDR, + input wire [0:0] ctrl_PSEL, + input wire ctrl_PENABLE, + output wire ctrl_PREADY, + input wire ctrl_PWRITE, + input wire [31:0] ctrl_PWDATA, + output wire [31:0] ctrl_PRDATA, + output wire ctrl_PSLVERROR, + output wire [1:0] ctrl_interrupts, + output wire read_arvalid, + input wire read_arready, + output wire [31:0] read_araddr, + output wire [3:0] read_arregion, + output wire [7:0] read_arlen, + output wire [2:0] read_arsize, + output wire [1:0] read_arburst, + output wire [0:0] read_arlock, + output wire [3:0] read_arcache, + output wire [3:0] read_arqos, + output wire [2:0] read_arprot, + input wire read_rvalid, + output wire read_rready, + input wire [127:0] read_rdata, + input wire [1:0] read_rresp, + input wire read_rlast, + output wire write_awvalid, + input wire write_awready, + output wire [31:0] write_awaddr, + output wire [3:0] write_awregion, + output wire [7:0] write_awlen, + output wire [2:0] write_awsize, + output wire [1:0] write_awburst, + output wire [0:0] write_awlock, + output wire [3:0] write_awcache, + output wire [3:0] write_awqos, + output wire [2:0] write_awprot, + output wire write_wvalid, + input wire write_wready, + output wire [127:0] write_wdata, + output wire [15:0] write_wstrb, + output wire write_wlast, + input wire write_bvalid, + output wire write_bready, + input wire [1:0] write_bresp, + input wire dat0_i_tvalid, + output wire dat0_i_tready, + input wire [7:0] dat0_i_tdata, + input wire [0:0] dat0_i_tkeep, + input wire [3:0] dat0_i_tdest, + input wire dat0_i_tlast, + output wire dat1_o_tvalid, + input wire dat1_o_tready, + output wire [7:0] dat1_o_tdata, + output wire [0:0] dat1_o_tkeep, + output wire [3:0] dat1_o_tdest, + output wire dat1_o_tlast, + output wire io_0_descriptorUpdate, + output wire io_1_descriptorUpdate, + input wire clk, + input wire reset, + input wire ctrl_clk, + input wire ctrl_reset, + input wire dat0_i_clk, + input wire dat0_i_reset, + input wire dat1_o_clk, + input wire dat1_o_reset +); + + wire core_io_sgRead_cmd_valid; + wire core_io_sgRead_cmd_payload_last; + wire [0:0] core_io_sgRead_cmd_payload_fragment_opcode; + wire [31:0] core_io_sgRead_cmd_payload_fragment_address; + wire [4:0] core_io_sgRead_cmd_payload_fragment_length; + wire [0:0] core_io_sgRead_cmd_payload_fragment_context; + wire core_io_sgRead_rsp_ready; + wire core_io_sgWrite_cmd_valid; + wire core_io_sgWrite_cmd_payload_last; + wire [0:0] core_io_sgWrite_cmd_payload_fragment_opcode; + wire [31:0] core_io_sgWrite_cmd_payload_fragment_address; + wire [1:0] core_io_sgWrite_cmd_payload_fragment_length; + wire [127:0] core_io_sgWrite_cmd_payload_fragment_data; + wire [15:0] core_io_sgWrite_cmd_payload_fragment_mask; + wire [0:0] core_io_sgWrite_cmd_payload_fragment_context; + wire core_io_sgWrite_rsp_ready; + wire core_io_read_cmd_valid; + wire core_io_read_cmd_payload_last; + wire [0:0] core_io_read_cmd_payload_fragment_opcode; + wire [31:0] core_io_read_cmd_payload_fragment_address; + wire [11:0] core_io_read_cmd_payload_fragment_length; + wire [20:0] core_io_read_cmd_payload_fragment_context; + wire core_io_read_rsp_ready; + wire core_io_write_cmd_valid; + wire core_io_write_cmd_payload_last; + wire [0:0] core_io_write_cmd_payload_fragment_opcode; + wire [31:0] core_io_write_cmd_payload_fragment_address; + wire [11:0] core_io_write_cmd_payload_fragment_length; + wire [127:0] core_io_write_cmd_payload_fragment_data; + wire [15:0] core_io_write_cmd_payload_fragment_mask; + wire [12:0] core_io_write_cmd_payload_fragment_context; + wire core_io_write_rsp_ready; + wire core_io_outputs_0_valid; + wire [63:0] core_io_outputs_0_payload_data; + wire [7:0] core_io_outputs_0_payload_mask; + wire [3:0] core_io_outputs_0_payload_sink; + wire core_io_outputs_0_payload_last; + wire core_io_inputs_0_ready; + wire [1:0] core_io_interrupts; + wire core_io_ctrl_PREADY; + wire [31:0] core_io_ctrl_PRDATA; + wire core_io_ctrl_PSLVERROR; + wire core_ll_0_descriptorUpdate; + wire core_ll_1_descriptorUpdate; + wire withCtrlCc_apbCc_io_input_PREADY; + wire [31:0] withCtrlCc_apbCc_io_input_PRDATA; + wire withCtrlCc_apbCc_io_input_PSLVERROR; + wire [13:0] withCtrlCc_apbCc_io_output_PADDR; + wire [0:0] withCtrlCc_apbCc_io_output_PSEL; + wire withCtrlCc_apbCc_io_output_PENABLE; + wire withCtrlCc_apbCc_io_output_PWRITE; + wire [31:0] withCtrlCc_apbCc_io_output_PWDATA; + wire [1:0] io_interrupts_buffercc_io_dataOut; + wire readLogic_sourceRemover_io_input_cmd_ready; + wire readLogic_sourceRemover_io_input_rsp_valid; + wire readLogic_sourceRemover_io_input_rsp_payload_last; + wire [0:0] readLogic_sourceRemover_io_input_rsp_payload_fragment_source; + wire [0:0] readLogic_sourceRemover_io_input_rsp_payload_fragment_opcode; + wire [127:0] readLogic_sourceRemover_io_input_rsp_payload_fragment_data; + wire [20:0] readLogic_sourceRemover_io_input_rsp_payload_fragment_context; + wire readLogic_sourceRemover_io_output_cmd_valid; + wire readLogic_sourceRemover_io_output_cmd_payload_last; + wire [0:0] readLogic_sourceRemover_io_output_cmd_payload_fragment_opcode; + wire [31:0] readLogic_sourceRemover_io_output_cmd_payload_fragment_address; + wire [11:0] readLogic_sourceRemover_io_output_cmd_payload_fragment_length; + wire [21:0] readLogic_sourceRemover_io_output_cmd_payload_fragment_context; + wire readLogic_sourceRemover_io_output_rsp_ready; + wire readLogic_bridge_io_input_cmd_ready; + wire readLogic_bridge_io_input_rsp_valid; + wire readLogic_bridge_io_input_rsp_payload_last; + wire [0:0] readLogic_bridge_io_input_rsp_payload_fragment_opcode; + wire [127:0] readLogic_bridge_io_input_rsp_payload_fragment_data; + wire [21:0] readLogic_bridge_io_input_rsp_payload_fragment_context; + wire readLogic_bridge_io_output_ar_valid; + wire [31:0] readLogic_bridge_io_output_ar_payload_addr; + wire [7:0] readLogic_bridge_io_output_ar_payload_len; + wire [2:0] readLogic_bridge_io_output_ar_payload_size; + wire [3:0] readLogic_bridge_io_output_ar_payload_cache; + wire [2:0] readLogic_bridge_io_output_ar_payload_prot; + wire readLogic_bridge_io_output_r_ready; + wire writeLogic_sourceRemover_io_input_cmd_ready; + wire writeLogic_sourceRemover_io_input_rsp_valid; + wire writeLogic_sourceRemover_io_input_rsp_payload_last; + wire [0:0] writeLogic_sourceRemover_io_input_rsp_payload_fragment_source; + wire [0:0] writeLogic_sourceRemover_io_input_rsp_payload_fragment_opcode; + wire [12:0] writeLogic_sourceRemover_io_input_rsp_payload_fragment_context; + wire writeLogic_sourceRemover_io_output_cmd_valid; + wire writeLogic_sourceRemover_io_output_cmd_payload_last; + wire [0:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_opcode; + wire [31:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_address; + wire [11:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_length; + wire [127:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_data; + wire [15:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_mask; + wire [13:0] writeLogic_sourceRemover_io_output_cmd_payload_fragment_context; + wire writeLogic_sourceRemover_io_output_rsp_ready; + wire writeLogic_bridge_io_input_cmd_ready; + wire writeLogic_bridge_io_input_rsp_valid; + wire writeLogic_bridge_io_input_rsp_payload_last; + wire [0:0] writeLogic_bridge_io_input_rsp_payload_fragment_opcode; + wire [13:0] writeLogic_bridge_io_input_rsp_payload_fragment_context; + wire writeLogic_bridge_io_output_aw_valid; + wire [31:0] writeLogic_bridge_io_output_aw_payload_addr; + wire [7:0] writeLogic_bridge_io_output_aw_payload_len; + wire [2:0] writeLogic_bridge_io_output_aw_payload_size; + wire [3:0] writeLogic_bridge_io_output_aw_payload_cache; + wire [2:0] writeLogic_bridge_io_output_aw_payload_prot; + wire writeLogic_bridge_io_output_w_valid; + wire [127:0] writeLogic_bridge_io_output_w_payload_data; + wire [15:0] writeLogic_bridge_io_output_w_payload_strb; + wire writeLogic_bridge_io_output_w_payload_last; + wire writeLogic_bridge_io_output_b_ready; + wire inputsAdapter_0_upsizer_logic_io_input_ready; + wire inputsAdapter_0_upsizer_logic_io_output_valid; + wire [63:0] inputsAdapter_0_upsizer_logic_io_output_payload_data; + wire [7:0] inputsAdapter_0_upsizer_logic_io_output_payload_mask; + wire [3:0] inputsAdapter_0_upsizer_logic_io_output_payload_sink; + wire inputsAdapter_0_upsizer_logic_io_output_payload_last; + wire inputsAdapter_0_crossclock_fifo_io_push_ready; + wire inputsAdapter_0_crossclock_fifo_io_pop_valid; + wire [63:0] inputsAdapter_0_crossclock_fifo_io_pop_payload_data; + wire [7:0] inputsAdapter_0_crossclock_fifo_io_pop_payload_mask; + wire [3:0] inputsAdapter_0_crossclock_fifo_io_pop_payload_sink; + wire inputsAdapter_0_crossclock_fifo_io_pop_payload_last; + wire [4:0] inputsAdapter_0_crossclock_fifo_io_pushOccupancy; + wire [4:0] inputsAdapter_0_crossclock_fifo_io_popOccupancy; + wire outputsAdapter_0_crossclock_fifo_io_push_ready; + wire outputsAdapter_0_crossclock_fifo_io_pop_valid; + wire [63:0] outputsAdapter_0_crossclock_fifo_io_pop_payload_data; + wire [7:0] outputsAdapter_0_crossclock_fifo_io_pop_payload_mask; + wire [3:0] outputsAdapter_0_crossclock_fifo_io_pop_payload_sink; + wire outputsAdapter_0_crossclock_fifo_io_pop_payload_last; + wire [4:0] outputsAdapter_0_crossclock_fifo_io_pushOccupancy; + wire [4:0] outputsAdapter_0_crossclock_fifo_io_popOccupancy; + wire outputsAdapter_0_sparseDownsizer_logic_io_input_ready; + wire outputsAdapter_0_sparseDownsizer_logic_io_output_valid; + wire [7:0] outputsAdapter_0_sparseDownsizer_logic_io_output_payload_data; + wire [0:0] outputsAdapter_0_sparseDownsizer_logic_io_output_payload_mask; + wire [3:0] outputsAdapter_0_sparseDownsizer_logic_io_output_payload_sink; + wire outputsAdapter_0_sparseDownsizer_logic_io_output_payload_last; + wire interconnect_read_aggregated_arbiter_io_inputs_0_cmd_ready; + wire interconnect_read_aggregated_arbiter_io_inputs_0_rsp_valid; + wire interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_last; + wire [0:0] interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode; + wire [127:0] interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_data; + wire [0:0] interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context; + wire interconnect_read_aggregated_arbiter_io_inputs_1_cmd_ready; + wire interconnect_read_aggregated_arbiter_io_inputs_1_rsp_valid; + wire interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_last; + wire [0:0] interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode; + wire [127:0] interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_data; + wire [20:0] interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context; + wire interconnect_read_aggregated_arbiter_io_output_cmd_valid; + wire interconnect_read_aggregated_arbiter_io_output_cmd_payload_last; + wire [0:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_source; + wire [0:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_opcode; + wire [31:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_address; + wire [11:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_length; + wire [20:0] interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_context; + wire interconnect_read_aggregated_arbiter_io_output_rsp_ready; + wire interconnect_write_aggregated_arbiter_io_inputs_0_cmd_ready; + wire interconnect_write_aggregated_arbiter_io_inputs_0_rsp_valid; + wire interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_last; + wire [0:0] interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode; + wire [0:0] interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context; + wire interconnect_write_aggregated_arbiter_io_inputs_1_cmd_ready; + wire interconnect_write_aggregated_arbiter_io_inputs_1_rsp_valid; + wire interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_last; + wire [0:0] interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode; + wire [12:0] interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context; + wire interconnect_write_aggregated_arbiter_io_output_cmd_valid; + wire interconnect_write_aggregated_arbiter_io_output_cmd_payload_last; + wire [0:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_source; + wire [0:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_opcode; + wire [31:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_address; + wire [11:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_length; + wire [127:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_data; + wire [15:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_mask; + wire [12:0] interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_context; + wire interconnect_write_aggregated_arbiter_io_output_rsp_ready; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode; + wire [31:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address; + wire [11:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length; + wire [20:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode; + wire [127:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_data; + wire [20:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode; + wire [31:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address; + wire [4:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready; + wire interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode; + wire [127:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data; + wire [0:0] interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode; + wire [31:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address; + wire [11:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length; + wire [127:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_data; + wire [15:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_mask; + wire [12:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode; + wire [12:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context; + wire io_write_cmd_s2mPipe_valid; + reg io_write_cmd_s2mPipe_ready; + wire io_write_cmd_s2mPipe_payload_last; + wire [0:0] io_write_cmd_s2mPipe_payload_fragment_opcode; + wire [31:0] io_write_cmd_s2mPipe_payload_fragment_address; + wire [11:0] io_write_cmd_s2mPipe_payload_fragment_length; + wire [127:0] io_write_cmd_s2mPipe_payload_fragment_data; + wire [15:0] io_write_cmd_s2mPipe_payload_fragment_mask; + wire [12:0] io_write_cmd_s2mPipe_payload_fragment_context; + reg io_write_cmd_rValidN; + reg io_write_cmd_rData_last; + reg [0:0] io_write_cmd_rData_fragment_opcode; + reg [31:0] io_write_cmd_rData_fragment_address; + reg [11:0] io_write_cmd_rData_fragment_length; + reg [127:0] io_write_cmd_rData_fragment_data; + reg [15:0] io_write_cmd_rData_fragment_mask; + reg [12:0] io_write_cmd_rData_fragment_context; + wire io_write_cmd_s2mPipe_m2sPipe_valid; + wire io_write_cmd_s2mPipe_m2sPipe_ready; + wire io_write_cmd_s2mPipe_m2sPipe_payload_last; + wire [0:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_opcode; + wire [31:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_address; + wire [11:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_length; + wire [127:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_data; + wire [15:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_mask; + wire [12:0] io_write_cmd_s2mPipe_m2sPipe_payload_fragment_context; + reg io_write_cmd_s2mPipe_rValid; + reg io_write_cmd_s2mPipe_rData_last; + reg [0:0] io_write_cmd_s2mPipe_rData_fragment_opcode; + reg [31:0] io_write_cmd_s2mPipe_rData_fragment_address; + reg [11:0] io_write_cmd_s2mPipe_rData_fragment_length; + reg [127:0] io_write_cmd_s2mPipe_rData_fragment_data; + reg [15:0] io_write_cmd_s2mPipe_rData_fragment_mask; + reg [12:0] io_write_cmd_s2mPipe_rData_fragment_context; + wire when_Stream_l375; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode; + wire [31:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address; + wire [1:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length; + wire [127:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data; + wire [15:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready; + wire interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode; + wire [0:0] interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context; + wire interconnect_read_aggregated_cmd_valid; + wire interconnect_read_aggregated_cmd_ready; + wire interconnect_read_aggregated_cmd_payload_last; + wire [0:0] interconnect_read_aggregated_cmd_payload_fragment_source; + wire [0:0] interconnect_read_aggregated_cmd_payload_fragment_opcode; + wire [31:0] interconnect_read_aggregated_cmd_payload_fragment_address; + wire [11:0] interconnect_read_aggregated_cmd_payload_fragment_length; + wire [20:0] interconnect_read_aggregated_cmd_payload_fragment_context; + wire interconnect_read_aggregated_rsp_valid; + wire interconnect_read_aggregated_rsp_ready; + wire interconnect_read_aggregated_rsp_payload_last; + wire [0:0] interconnect_read_aggregated_rsp_payload_fragment_source; + wire [0:0] interconnect_read_aggregated_rsp_payload_fragment_opcode; + wire [127:0] interconnect_read_aggregated_rsp_payload_fragment_data; + wire [20:0] interconnect_read_aggregated_rsp_payload_fragment_context; + wire interconnect_write_aggregated_cmd_valid; + reg interconnect_write_aggregated_cmd_ready; + wire interconnect_write_aggregated_cmd_payload_last; + wire [0:0] interconnect_write_aggregated_cmd_payload_fragment_source; + wire [0:0] interconnect_write_aggregated_cmd_payload_fragment_opcode; + wire [31:0] interconnect_write_aggregated_cmd_payload_fragment_address; + wire [11:0] interconnect_write_aggregated_cmd_payload_fragment_length; + wire [127:0] interconnect_write_aggregated_cmd_payload_fragment_data; + wire [15:0] interconnect_write_aggregated_cmd_payload_fragment_mask; + wire [12:0] interconnect_write_aggregated_cmd_payload_fragment_context; + wire interconnect_write_aggregated_rsp_valid; + wire interconnect_write_aggregated_rsp_ready; + wire interconnect_write_aggregated_rsp_payload_last; + wire [0:0] interconnect_write_aggregated_rsp_payload_fragment_source; + wire [0:0] interconnect_write_aggregated_rsp_payload_fragment_opcode; + wire [12:0] interconnect_write_aggregated_rsp_payload_fragment_context; + wire readLogic_resized_cmd_valid; + wire readLogic_resized_cmd_ready; + wire readLogic_resized_cmd_payload_last; + wire [0:0] readLogic_resized_cmd_payload_fragment_source; + wire [0:0] readLogic_resized_cmd_payload_fragment_opcode; + wire [31:0] readLogic_resized_cmd_payload_fragment_address; + wire [11:0] readLogic_resized_cmd_payload_fragment_length; + wire [20:0] readLogic_resized_cmd_payload_fragment_context; + wire readLogic_resized_rsp_valid; + wire readLogic_resized_rsp_ready; + wire readLogic_resized_rsp_payload_last; + wire [0:0] readLogic_resized_rsp_payload_fragment_source; + wire [0:0] readLogic_resized_rsp_payload_fragment_opcode; + wire [127:0] readLogic_resized_rsp_payload_fragment_data; + wire [20:0] readLogic_resized_rsp_payload_fragment_context; + wire interconnect_read_aggregated_cmd_halfPipe_valid; + wire interconnect_read_aggregated_cmd_halfPipe_ready; + wire interconnect_read_aggregated_cmd_halfPipe_payload_last; + wire [0:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_source; + wire [0:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_opcode; + wire [31:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_address; + wire [11:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_length; + wire [20:0] interconnect_read_aggregated_cmd_halfPipe_payload_fragment_context; + reg interconnect_read_aggregated_cmd_rValid; + wire interconnect_read_aggregated_cmd_halfPipe_fire; + reg interconnect_read_aggregated_cmd_rData_last; + reg [0:0] interconnect_read_aggregated_cmd_rData_fragment_source; + reg [0:0] interconnect_read_aggregated_cmd_rData_fragment_opcode; + reg [31:0] interconnect_read_aggregated_cmd_rData_fragment_address; + reg [11:0] interconnect_read_aggregated_cmd_rData_fragment_length; + reg [20:0] interconnect_read_aggregated_cmd_rData_fragment_context; + wire readLogic_resized_rsp_combStage_valid; + wire readLogic_resized_rsp_combStage_ready; + wire readLogic_resized_rsp_combStage_payload_last; + wire [0:0] readLogic_resized_rsp_combStage_payload_fragment_source; + wire [0:0] readLogic_resized_rsp_combStage_payload_fragment_opcode; + wire [127:0] readLogic_resized_rsp_combStage_payload_fragment_data; + wire [20:0] readLogic_resized_rsp_combStage_payload_fragment_context; + wire readLogic_adapter_ar_valid; + wire readLogic_adapter_ar_ready; + wire [31:0] readLogic_adapter_ar_payload_addr; + wire [3:0] readLogic_adapter_ar_payload_region; + wire [7:0] readLogic_adapter_ar_payload_len; + wire [2:0] readLogic_adapter_ar_payload_size; + wire [1:0] readLogic_adapter_ar_payload_burst; + wire [0:0] readLogic_adapter_ar_payload_lock; + wire [3:0] readLogic_adapter_ar_payload_cache; + wire [3:0] readLogic_adapter_ar_payload_qos; + wire [2:0] readLogic_adapter_ar_payload_prot; + wire readLogic_adapter_r_valid; + wire readLogic_adapter_r_ready; + wire [127:0] readLogic_adapter_r_payload_data; + wire [1:0] readLogic_adapter_r_payload_resp; + wire readLogic_adapter_r_payload_last; + wire [3:0] _zz_readLogic_adapter_ar_payload_region; + wire readLogic_adapter_ar_halfPipe_valid; + wire readLogic_adapter_ar_halfPipe_ready; + wire [31:0] readLogic_adapter_ar_halfPipe_payload_addr; + wire [3:0] readLogic_adapter_ar_halfPipe_payload_region; + wire [7:0] readLogic_adapter_ar_halfPipe_payload_len; + wire [2:0] readLogic_adapter_ar_halfPipe_payload_size; + wire [1:0] readLogic_adapter_ar_halfPipe_payload_burst; + wire [0:0] readLogic_adapter_ar_halfPipe_payload_lock; + wire [3:0] readLogic_adapter_ar_halfPipe_payload_cache; + wire [3:0] readLogic_adapter_ar_halfPipe_payload_qos; + wire [2:0] readLogic_adapter_ar_halfPipe_payload_prot; + reg readLogic_adapter_ar_rValid; + wire readLogic_adapter_ar_halfPipe_fire; + reg [31:0] readLogic_adapter_ar_rData_addr; + reg [3:0] readLogic_adapter_ar_rData_region; + reg [7:0] readLogic_adapter_ar_rData_len; + reg [2:0] readLogic_adapter_ar_rData_size; + reg [1:0] readLogic_adapter_ar_rData_burst; + reg [0:0] readLogic_adapter_ar_rData_lock; + reg [3:0] readLogic_adapter_ar_rData_cache; + reg [3:0] readLogic_adapter_ar_rData_qos; + reg [2:0] readLogic_adapter_ar_rData_prot; + wire read_r_s2mPipe_valid; + reg read_r_s2mPipe_ready; + wire [127:0] read_r_s2mPipe_payload_data; + wire [1:0] read_r_s2mPipe_payload_resp; + wire read_r_s2mPipe_payload_last; + reg read_r_rValidN; + reg [127:0] read_r_rData_data; + reg [1:0] read_r_rData_resp; + reg read_r_rData_last; + wire readLogic_beforeQueue_valid; + wire readLogic_beforeQueue_ready; + wire [127:0] readLogic_beforeQueue_payload_data; + wire [1:0] readLogic_beforeQueue_payload_resp; + wire readLogic_beforeQueue_payload_last; + reg read_r_s2mPipe_rValid; + reg [127:0] read_r_s2mPipe_rData_data; + reg [1:0] read_r_s2mPipe_rData_resp; + reg read_r_s2mPipe_rData_last; + wire when_Stream_l375_1; + wire writeLogic_resized_cmd_valid; + wire writeLogic_resized_cmd_ready; + wire writeLogic_resized_cmd_payload_last; + wire [0:0] writeLogic_resized_cmd_payload_fragment_source; + wire [0:0] writeLogic_resized_cmd_payload_fragment_opcode; + wire [31:0] writeLogic_resized_cmd_payload_fragment_address; + wire [11:0] writeLogic_resized_cmd_payload_fragment_length; + wire [127:0] writeLogic_resized_cmd_payload_fragment_data; + wire [15:0] writeLogic_resized_cmd_payload_fragment_mask; + wire [12:0] writeLogic_resized_cmd_payload_fragment_context; + wire writeLogic_resized_rsp_valid; + wire writeLogic_resized_rsp_ready; + wire writeLogic_resized_rsp_payload_last; + wire [0:0] writeLogic_resized_rsp_payload_fragment_source; + wire [0:0] writeLogic_resized_rsp_payload_fragment_opcode; + wire [12:0] writeLogic_resized_rsp_payload_fragment_context; + wire interconnect_write_aggregated_cmd_m2sPipe_valid; + wire interconnect_write_aggregated_cmd_m2sPipe_ready; + wire interconnect_write_aggregated_cmd_m2sPipe_payload_last; + wire [0:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_source; + wire [0:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_opcode; + wire [31:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_address; + wire [11:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_length; + wire [127:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_data; + wire [15:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_mask; + wire [12:0] interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_context; + reg interconnect_write_aggregated_cmd_rValid; + reg interconnect_write_aggregated_cmd_rData_last; + reg [0:0] interconnect_write_aggregated_cmd_rData_fragment_source; + reg [0:0] interconnect_write_aggregated_cmd_rData_fragment_opcode; + reg [31:0] interconnect_write_aggregated_cmd_rData_fragment_address; + reg [11:0] interconnect_write_aggregated_cmd_rData_fragment_length; + reg [127:0] interconnect_write_aggregated_cmd_rData_fragment_data; + reg [15:0] interconnect_write_aggregated_cmd_rData_fragment_mask; + reg [12:0] interconnect_write_aggregated_cmd_rData_fragment_context; + wire when_Stream_l375_2; + wire writeLogic_resized_rsp_combStage_valid; + wire writeLogic_resized_rsp_combStage_ready; + wire writeLogic_resized_rsp_combStage_payload_last; + wire [0:0] writeLogic_resized_rsp_combStage_payload_fragment_source; + wire [0:0] writeLogic_resized_rsp_combStage_payload_fragment_opcode; + wire [12:0] writeLogic_resized_rsp_combStage_payload_fragment_context; + wire writeLogic_adapter_aw_valid; + wire writeLogic_adapter_aw_ready; + wire [31:0] writeLogic_adapter_aw_payload_addr; + wire [3:0] writeLogic_adapter_aw_payload_region; + wire [7:0] writeLogic_adapter_aw_payload_len; + wire [2:0] writeLogic_adapter_aw_payload_size; + wire [1:0] writeLogic_adapter_aw_payload_burst; + wire [0:0] writeLogic_adapter_aw_payload_lock; + wire [3:0] writeLogic_adapter_aw_payload_cache; + wire [3:0] writeLogic_adapter_aw_payload_qos; + wire [2:0] writeLogic_adapter_aw_payload_prot; + wire writeLogic_adapter_w_valid; + wire writeLogic_adapter_w_ready; + wire [127:0] writeLogic_adapter_w_payload_data; + wire [15:0] writeLogic_adapter_w_payload_strb; + wire writeLogic_adapter_w_payload_last; + wire writeLogic_adapter_b_valid; + wire writeLogic_adapter_b_ready; + wire [1:0] writeLogic_adapter_b_payload_resp; + wire [3:0] _zz_writeLogic_adapter_aw_payload_region; + wire writeLogic_adapter_aw_halfPipe_valid; + wire writeLogic_adapter_aw_halfPipe_ready; + wire [31:0] writeLogic_adapter_aw_halfPipe_payload_addr; + wire [3:0] writeLogic_adapter_aw_halfPipe_payload_region; + wire [7:0] writeLogic_adapter_aw_halfPipe_payload_len; + wire [2:0] writeLogic_adapter_aw_halfPipe_payload_size; + wire [1:0] writeLogic_adapter_aw_halfPipe_payload_burst; + wire [0:0] writeLogic_adapter_aw_halfPipe_payload_lock; + wire [3:0] writeLogic_adapter_aw_halfPipe_payload_cache; + wire [3:0] writeLogic_adapter_aw_halfPipe_payload_qos; + wire [2:0] writeLogic_adapter_aw_halfPipe_payload_prot; + reg writeLogic_adapter_aw_rValid; + wire writeLogic_adapter_aw_halfPipe_fire; + reg [31:0] writeLogic_adapter_aw_rData_addr; + reg [3:0] writeLogic_adapter_aw_rData_region; + reg [7:0] writeLogic_adapter_aw_rData_len; + reg [2:0] writeLogic_adapter_aw_rData_size; + reg [1:0] writeLogic_adapter_aw_rData_burst; + reg [0:0] writeLogic_adapter_aw_rData_lock; + reg [3:0] writeLogic_adapter_aw_rData_cache; + reg [3:0] writeLogic_adapter_aw_rData_qos; + reg [2:0] writeLogic_adapter_aw_rData_prot; + wire writeLogic_adapter_w_s2mPipe_valid; + reg writeLogic_adapter_w_s2mPipe_ready; + wire [127:0] writeLogic_adapter_w_s2mPipe_payload_data; + wire [15:0] writeLogic_adapter_w_s2mPipe_payload_strb; + wire writeLogic_adapter_w_s2mPipe_payload_last; + reg writeLogic_adapter_w_rValidN; + reg [127:0] writeLogic_adapter_w_rData_data; + reg [15:0] writeLogic_adapter_w_rData_strb; + reg writeLogic_adapter_w_rData_last; + wire writeLogic_adapter_w_s2mPipe_m2sPipe_valid; + wire writeLogic_adapter_w_s2mPipe_m2sPipe_ready; + wire [127:0] writeLogic_adapter_w_s2mPipe_m2sPipe_payload_data; + wire [15:0] writeLogic_adapter_w_s2mPipe_m2sPipe_payload_strb; + wire writeLogic_adapter_w_s2mPipe_m2sPipe_payload_last; + reg writeLogic_adapter_w_s2mPipe_rValid; + reg [127:0] writeLogic_adapter_w_s2mPipe_rData_data; + reg [15:0] writeLogic_adapter_w_s2mPipe_rData_strb; + reg writeLogic_adapter_w_s2mPipe_rData_last; + wire when_Stream_l375_3; + wire write_b_halfPipe_valid; + wire write_b_halfPipe_ready; + wire [1:0] write_b_halfPipe_payload_resp; + reg write_b_rValid; + wire write_b_halfPipe_fire; + reg [1:0] write_b_rData_resp; + wire io_pop_s2mPipe_valid; + reg io_pop_s2mPipe_ready; + wire [63:0] io_pop_s2mPipe_payload_data; + wire [7:0] io_pop_s2mPipe_payload_mask; + wire [3:0] io_pop_s2mPipe_payload_sink; + wire io_pop_s2mPipe_payload_last; + reg io_pop_rValidN; + reg [63:0] io_pop_rData_data; + reg [7:0] io_pop_rData_mask; + reg [3:0] io_pop_rData_sink; + reg io_pop_rData_last; + wire io_pop_s2mPipe_m2sPipe_valid; + wire io_pop_s2mPipe_m2sPipe_ready; + wire [63:0] io_pop_s2mPipe_m2sPipe_payload_data; + wire [7:0] io_pop_s2mPipe_m2sPipe_payload_mask; + wire [3:0] io_pop_s2mPipe_m2sPipe_payload_sink; + wire io_pop_s2mPipe_m2sPipe_payload_last; + reg io_pop_s2mPipe_rValid; + reg [63:0] io_pop_s2mPipe_rData_data; + reg [7:0] io_pop_s2mPipe_rData_mask; + reg [3:0] io_pop_s2mPipe_rData_sink; + reg io_pop_s2mPipe_rData_last; + wire when_Stream_l375_4; + wire io_outputs_0_s2mPipe_valid; + reg io_outputs_0_s2mPipe_ready; + wire [63:0] io_outputs_0_s2mPipe_payload_data; + wire [7:0] io_outputs_0_s2mPipe_payload_mask; + wire [3:0] io_outputs_0_s2mPipe_payload_sink; + wire io_outputs_0_s2mPipe_payload_last; + reg io_outputs_0_rValidN; + reg [63:0] io_outputs_0_rData_data; + reg [7:0] io_outputs_0_rData_mask; + reg [3:0] io_outputs_0_rData_sink; + reg io_outputs_0_rData_last; + wire outputsAdapter_0_ptr_valid; + wire outputsAdapter_0_ptr_ready; + wire [63:0] outputsAdapter_0_ptr_payload_data; + wire [7:0] outputsAdapter_0_ptr_payload_mask; + wire [3:0] outputsAdapter_0_ptr_payload_sink; + wire outputsAdapter_0_ptr_payload_last; + reg io_outputs_0_s2mPipe_rValid; + reg [63:0] io_outputs_0_s2mPipe_rData_data; + reg [7:0] io_outputs_0_s2mPipe_rData_mask; + reg [3:0] io_outputs_0_s2mPipe_rData_sink; + reg io_outputs_0_s2mPipe_rData_last; + wire when_Stream_l375_5; + + EfxDMA_Core core ( + .io_sgRead_cmd_valid (core_io_sgRead_cmd_valid ), //o + .io_sgRead_cmd_ready (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready ), //i + .io_sgRead_cmd_payload_last (core_io_sgRead_cmd_payload_last ), //o + .io_sgRead_cmd_payload_fragment_opcode (core_io_sgRead_cmd_payload_fragment_opcode ), //o + .io_sgRead_cmd_payload_fragment_address (core_io_sgRead_cmd_payload_fragment_address[31:0] ), //o + .io_sgRead_cmd_payload_fragment_length (core_io_sgRead_cmd_payload_fragment_length[4:0] ), //o + .io_sgRead_cmd_payload_fragment_context (core_io_sgRead_cmd_payload_fragment_context ), //o + .io_sgRead_rsp_valid (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid ), //i + .io_sgRead_rsp_ready (core_io_sgRead_rsp_ready ), //o + .io_sgRead_rsp_payload_last (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last ), //i + .io_sgRead_rsp_payload_fragment_opcode (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode ), //i + .io_sgRead_rsp_payload_fragment_data (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data[127:0] ), //i + .io_sgRead_rsp_payload_fragment_context (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context ), //i + .io_sgWrite_cmd_valid (core_io_sgWrite_cmd_valid ), //o + .io_sgWrite_cmd_ready (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready ), //i + .io_sgWrite_cmd_payload_last (core_io_sgWrite_cmd_payload_last ), //o + .io_sgWrite_cmd_payload_fragment_opcode (core_io_sgWrite_cmd_payload_fragment_opcode ), //o + .io_sgWrite_cmd_payload_fragment_address (core_io_sgWrite_cmd_payload_fragment_address[31:0] ), //o + .io_sgWrite_cmd_payload_fragment_length (core_io_sgWrite_cmd_payload_fragment_length[1:0] ), //o + .io_sgWrite_cmd_payload_fragment_data (core_io_sgWrite_cmd_payload_fragment_data[127:0] ), //o + .io_sgWrite_cmd_payload_fragment_mask (core_io_sgWrite_cmd_payload_fragment_mask[15:0] ), //o + .io_sgWrite_cmd_payload_fragment_context (core_io_sgWrite_cmd_payload_fragment_context ), //o + .io_sgWrite_rsp_valid (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid ), //i + .io_sgWrite_rsp_ready (core_io_sgWrite_rsp_ready ), //o + .io_sgWrite_rsp_payload_last (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last ), //i + .io_sgWrite_rsp_payload_fragment_opcode (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode ), //i + .io_sgWrite_rsp_payload_fragment_context (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context ), //i + .io_read_cmd_valid (core_io_read_cmd_valid ), //o + .io_read_cmd_ready (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready ), //i + .io_read_cmd_payload_last (core_io_read_cmd_payload_last ), //o + .io_read_cmd_payload_fragment_opcode (core_io_read_cmd_payload_fragment_opcode ), //o + .io_read_cmd_payload_fragment_address (core_io_read_cmd_payload_fragment_address[31:0] ), //o + .io_read_cmd_payload_fragment_length (core_io_read_cmd_payload_fragment_length[11:0] ), //o + .io_read_cmd_payload_fragment_context (core_io_read_cmd_payload_fragment_context[20:0] ), //o + .io_read_rsp_valid (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid ), //i + .io_read_rsp_ready (core_io_read_rsp_ready ), //o + .io_read_rsp_payload_last (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last ), //i + .io_read_rsp_payload_fragment_opcode (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode ), //i + .io_read_rsp_payload_fragment_data (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_data[127:0] ), //i + .io_read_rsp_payload_fragment_context (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context[20:0] ), //i + .io_write_cmd_valid (core_io_write_cmd_valid ), //o + .io_write_cmd_ready (io_write_cmd_rValidN ), //i + .io_write_cmd_payload_last (core_io_write_cmd_payload_last ), //o + .io_write_cmd_payload_fragment_opcode (core_io_write_cmd_payload_fragment_opcode ), //o + .io_write_cmd_payload_fragment_address (core_io_write_cmd_payload_fragment_address[31:0] ), //o + .io_write_cmd_payload_fragment_length (core_io_write_cmd_payload_fragment_length[11:0] ), //o + .io_write_cmd_payload_fragment_data (core_io_write_cmd_payload_fragment_data[127:0] ), //o + .io_write_cmd_payload_fragment_mask (core_io_write_cmd_payload_fragment_mask[15:0] ), //o + .io_write_cmd_payload_fragment_context (core_io_write_cmd_payload_fragment_context[12:0] ), //o + .io_write_rsp_valid (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid ), //i + .io_write_rsp_ready (core_io_write_rsp_ready ), //o + .io_write_rsp_payload_last (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last ), //i + .io_write_rsp_payload_fragment_opcode (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode ), //i + .io_write_rsp_payload_fragment_context (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context[12:0]), //i + .io_outputs_0_valid (core_io_outputs_0_valid ), //o + .io_outputs_0_ready (io_outputs_0_rValidN ), //i + .io_outputs_0_payload_data (core_io_outputs_0_payload_data[63:0] ), //o + .io_outputs_0_payload_mask (core_io_outputs_0_payload_mask[7:0] ), //o + .io_outputs_0_payload_sink (core_io_outputs_0_payload_sink[3:0] ), //o + .io_outputs_0_payload_last (core_io_outputs_0_payload_last ), //o + .io_inputs_0_valid (io_pop_s2mPipe_m2sPipe_valid ), //i + .io_inputs_0_ready (core_io_inputs_0_ready ), //o + .io_inputs_0_payload_data (io_pop_s2mPipe_m2sPipe_payload_data[63:0] ), //i + .io_inputs_0_payload_mask (io_pop_s2mPipe_m2sPipe_payload_mask[7:0] ), //i + .io_inputs_0_payload_sink (io_pop_s2mPipe_m2sPipe_payload_sink[3:0] ), //i + .io_inputs_0_payload_last (io_pop_s2mPipe_m2sPipe_payload_last ), //i + .io_interrupts (core_io_interrupts[1:0] ), //o + .io_ctrl_PADDR (withCtrlCc_apbCc_io_output_PADDR[13:0] ), //i + .io_ctrl_PSEL (withCtrlCc_apbCc_io_output_PSEL ), //i + .io_ctrl_PENABLE (withCtrlCc_apbCc_io_output_PENABLE ), //i + .io_ctrl_PREADY (core_io_ctrl_PREADY ), //o + .io_ctrl_PWRITE (withCtrlCc_apbCc_io_output_PWRITE ), //i + .io_ctrl_PWDATA (withCtrlCc_apbCc_io_output_PWDATA[31:0] ), //i + .io_ctrl_PRDATA (core_io_ctrl_PRDATA[31:0] ), //o + .io_ctrl_PSLVERROR (core_io_ctrl_PSLVERROR ), //o + .ll_0_descriptorUpdate (core_ll_0_descriptorUpdate ), //o + .ll_1_descriptorUpdate (core_ll_1_descriptorUpdate ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_Apb3CC withCtrlCc_apbCc ( + .io_input_PADDR (ctrl_PADDR[13:0] ), //i + .io_input_PSEL (ctrl_PSEL ), //i + .io_input_PENABLE (ctrl_PENABLE ), //i + .io_input_PREADY (withCtrlCc_apbCc_io_input_PREADY ), //o + .io_input_PWRITE (ctrl_PWRITE ), //i + .io_input_PWDATA (ctrl_PWDATA[31:0] ), //i + .io_input_PRDATA (withCtrlCc_apbCc_io_input_PRDATA[31:0] ), //o + .io_input_PSLVERROR (withCtrlCc_apbCc_io_input_PSLVERROR ), //o + .io_output_PADDR (withCtrlCc_apbCc_io_output_PADDR[13:0] ), //o + .io_output_PSEL (withCtrlCc_apbCc_io_output_PSEL ), //o + .io_output_PENABLE (withCtrlCc_apbCc_io_output_PENABLE ), //o + .io_output_PREADY (core_io_ctrl_PREADY ), //i + .io_output_PWRITE (withCtrlCc_apbCc_io_output_PWRITE ), //o + .io_output_PWDATA (withCtrlCc_apbCc_io_output_PWDATA[31:0]), //o + .io_output_PRDATA (core_io_ctrl_PRDATA[31:0] ), //i + .io_output_PSLVERROR (core_io_ctrl_PSLVERROR ), //i + .ctrl_clk (ctrl_clk ), //i + .ctrl_reset (ctrl_reset ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_6 io_interrupts_buffercc ( + .io_dataIn (core_io_interrupts[1:0] ), //i + .io_dataOut (io_interrupts_buffercc_io_dataOut[1:0]), //o + .ctrl_clk (ctrl_clk ), //i + .ctrl_reset (ctrl_reset ) //i + ); + EfxDMA_BmbSourceRemover readLogic_sourceRemover ( + .io_input_cmd_valid (readLogic_resized_cmd_valid ), //i + .io_input_cmd_ready (readLogic_sourceRemover_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (readLogic_resized_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (readLogic_resized_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (readLogic_resized_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (readLogic_resized_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (readLogic_resized_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_context (readLogic_resized_cmd_payload_fragment_context[20:0] ), //i + .io_input_rsp_valid (readLogic_sourceRemover_io_input_rsp_valid ), //o + .io_input_rsp_ready (readLogic_resized_rsp_ready ), //i + .io_input_rsp_payload_last (readLogic_sourceRemover_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (readLogic_sourceRemover_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (readLogic_sourceRemover_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (readLogic_sourceRemover_io_input_rsp_payload_fragment_data[127:0] ), //o + .io_input_rsp_payload_fragment_context (readLogic_sourceRemover_io_input_rsp_payload_fragment_context[20:0] ), //o + .io_output_cmd_valid (readLogic_sourceRemover_io_output_cmd_valid ), //o + .io_output_cmd_ready (readLogic_bridge_io_input_cmd_ready ), //i + .io_output_cmd_payload_last (readLogic_sourceRemover_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (readLogic_sourceRemover_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (readLogic_sourceRemover_io_output_cmd_payload_fragment_address[31:0]), //o + .io_output_cmd_payload_fragment_length (readLogic_sourceRemover_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_cmd_payload_fragment_context (readLogic_sourceRemover_io_output_cmd_payload_fragment_context[21:0]), //o + .io_output_rsp_valid (readLogic_bridge_io_input_rsp_valid ), //i + .io_output_rsp_ready (readLogic_sourceRemover_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (readLogic_bridge_io_input_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (readLogic_bridge_io_input_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (readLogic_bridge_io_input_rsp_payload_fragment_data[127:0] ), //i + .io_output_rsp_payload_fragment_context (readLogic_bridge_io_input_rsp_payload_fragment_context[21:0] ) //i + ); + EfxDMA_BmbToAxi4ReadOnlyBridge readLogic_bridge ( + .io_input_cmd_valid (readLogic_sourceRemover_io_output_cmd_valid ), //i + .io_input_cmd_ready (readLogic_bridge_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (readLogic_sourceRemover_io_output_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (readLogic_sourceRemover_io_output_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (readLogic_sourceRemover_io_output_cmd_payload_fragment_address[31:0]), //i + .io_input_cmd_payload_fragment_length (readLogic_sourceRemover_io_output_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_context (readLogic_sourceRemover_io_output_cmd_payload_fragment_context[21:0]), //i + .io_input_rsp_valid (readLogic_bridge_io_input_rsp_valid ), //o + .io_input_rsp_ready (readLogic_sourceRemover_io_output_rsp_ready ), //i + .io_input_rsp_payload_last (readLogic_bridge_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (readLogic_bridge_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (readLogic_bridge_io_input_rsp_payload_fragment_data[127:0] ), //o + .io_input_rsp_payload_fragment_context (readLogic_bridge_io_input_rsp_payload_fragment_context[21:0] ), //o + .io_output_ar_valid (readLogic_bridge_io_output_ar_valid ), //o + .io_output_ar_ready (readLogic_adapter_ar_ready ), //i + .io_output_ar_payload_addr (readLogic_bridge_io_output_ar_payload_addr[31:0] ), //o + .io_output_ar_payload_len (readLogic_bridge_io_output_ar_payload_len[7:0] ), //o + .io_output_ar_payload_size (readLogic_bridge_io_output_ar_payload_size[2:0] ), //o + .io_output_ar_payload_cache (readLogic_bridge_io_output_ar_payload_cache[3:0] ), //o + .io_output_ar_payload_prot (readLogic_bridge_io_output_ar_payload_prot[2:0] ), //o + .io_output_r_valid (readLogic_adapter_r_valid ), //i + .io_output_r_ready (readLogic_bridge_io_output_r_ready ), //o + .io_output_r_payload_data (readLogic_adapter_r_payload_data[127:0] ), //i + .io_output_r_payload_resp (readLogic_adapter_r_payload_resp[1:0] ), //i + .io_output_r_payload_last (readLogic_adapter_r_payload_last ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_BmbSourceRemover_1 writeLogic_sourceRemover ( + .io_input_cmd_valid (writeLogic_resized_cmd_valid ), //i + .io_input_cmd_ready (writeLogic_sourceRemover_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (writeLogic_resized_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_source (writeLogic_resized_cmd_payload_fragment_source ), //i + .io_input_cmd_payload_fragment_opcode (writeLogic_resized_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (writeLogic_resized_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (writeLogic_resized_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_data (writeLogic_resized_cmd_payload_fragment_data[127:0] ), //i + .io_input_cmd_payload_fragment_mask (writeLogic_resized_cmd_payload_fragment_mask[15:0] ), //i + .io_input_cmd_payload_fragment_context (writeLogic_resized_cmd_payload_fragment_context[12:0] ), //i + .io_input_rsp_valid (writeLogic_sourceRemover_io_input_rsp_valid ), //o + .io_input_rsp_ready (writeLogic_resized_rsp_ready ), //i + .io_input_rsp_payload_last (writeLogic_sourceRemover_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_source (writeLogic_sourceRemover_io_input_rsp_payload_fragment_source ), //o + .io_input_rsp_payload_fragment_opcode (writeLogic_sourceRemover_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_context (writeLogic_sourceRemover_io_input_rsp_payload_fragment_context[12:0] ), //o + .io_output_cmd_valid (writeLogic_sourceRemover_io_output_cmd_valid ), //o + .io_output_cmd_ready (writeLogic_bridge_io_input_cmd_ready ), //i + .io_output_cmd_payload_last (writeLogic_sourceRemover_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (writeLogic_sourceRemover_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (writeLogic_sourceRemover_io_output_cmd_payload_fragment_address[31:0]), //o + .io_output_cmd_payload_fragment_length (writeLogic_sourceRemover_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_cmd_payload_fragment_data (writeLogic_sourceRemover_io_output_cmd_payload_fragment_data[127:0] ), //o + .io_output_cmd_payload_fragment_mask (writeLogic_sourceRemover_io_output_cmd_payload_fragment_mask[15:0] ), //o + .io_output_cmd_payload_fragment_context (writeLogic_sourceRemover_io_output_cmd_payload_fragment_context[13:0]), //o + .io_output_rsp_valid (writeLogic_bridge_io_input_rsp_valid ), //i + .io_output_rsp_ready (writeLogic_sourceRemover_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (writeLogic_bridge_io_input_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (writeLogic_bridge_io_input_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_context (writeLogic_bridge_io_input_rsp_payload_fragment_context[13:0] ) //i + ); + EfxDMA_BmbToAxi4WriteOnlyBridge writeLogic_bridge ( + .io_input_cmd_valid (writeLogic_sourceRemover_io_output_cmd_valid ), //i + .io_input_cmd_ready (writeLogic_bridge_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (writeLogic_sourceRemover_io_output_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (writeLogic_sourceRemover_io_output_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (writeLogic_sourceRemover_io_output_cmd_payload_fragment_address[31:0]), //i + .io_input_cmd_payload_fragment_length (writeLogic_sourceRemover_io_output_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_data (writeLogic_sourceRemover_io_output_cmd_payload_fragment_data[127:0] ), //i + .io_input_cmd_payload_fragment_mask (writeLogic_sourceRemover_io_output_cmd_payload_fragment_mask[15:0] ), //i + .io_input_cmd_payload_fragment_context (writeLogic_sourceRemover_io_output_cmd_payload_fragment_context[13:0]), //i + .io_input_rsp_valid (writeLogic_bridge_io_input_rsp_valid ), //o + .io_input_rsp_ready (writeLogic_sourceRemover_io_output_rsp_ready ), //i + .io_input_rsp_payload_last (writeLogic_bridge_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (writeLogic_bridge_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_context (writeLogic_bridge_io_input_rsp_payload_fragment_context[13:0] ), //o + .io_output_aw_valid (writeLogic_bridge_io_output_aw_valid ), //o + .io_output_aw_ready (writeLogic_adapter_aw_ready ), //i + .io_output_aw_payload_addr (writeLogic_bridge_io_output_aw_payload_addr[31:0] ), //o + .io_output_aw_payload_len (writeLogic_bridge_io_output_aw_payload_len[7:0] ), //o + .io_output_aw_payload_size (writeLogic_bridge_io_output_aw_payload_size[2:0] ), //o + .io_output_aw_payload_cache (writeLogic_bridge_io_output_aw_payload_cache[3:0] ), //o + .io_output_aw_payload_prot (writeLogic_bridge_io_output_aw_payload_prot[2:0] ), //o + .io_output_w_valid (writeLogic_bridge_io_output_w_valid ), //o + .io_output_w_ready (writeLogic_adapter_w_ready ), //i + .io_output_w_payload_data (writeLogic_bridge_io_output_w_payload_data[127:0] ), //o + .io_output_w_payload_strb (writeLogic_bridge_io_output_w_payload_strb[15:0] ), //o + .io_output_w_payload_last (writeLogic_bridge_io_output_w_payload_last ), //o + .io_output_b_valid (writeLogic_adapter_b_valid ), //i + .io_output_b_ready (writeLogic_bridge_io_output_b_ready ), //o + .io_output_b_payload_resp (writeLogic_adapter_b_payload_resp[1:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_BsbUpSizerDense inputsAdapter_0_upsizer_logic ( + .io_input_valid (dat0_i_tvalid ), //i + .io_input_ready (inputsAdapter_0_upsizer_logic_io_input_ready ), //o + .io_input_payload_data (dat0_i_tdata[7:0] ), //i + .io_input_payload_mask (dat0_i_tkeep ), //i + .io_input_payload_sink (dat0_i_tdest[3:0] ), //i + .io_input_payload_last (dat0_i_tlast ), //i + .io_output_valid (inputsAdapter_0_upsizer_logic_io_output_valid ), //o + .io_output_ready (inputsAdapter_0_crossclock_fifo_io_push_ready ), //i + .io_output_payload_data (inputsAdapter_0_upsizer_logic_io_output_payload_data[63:0]), //o + .io_output_payload_mask (inputsAdapter_0_upsizer_logic_io_output_payload_mask[7:0] ), //o + .io_output_payload_sink (inputsAdapter_0_upsizer_logic_io_output_payload_sink[3:0] ), //o + .io_output_payload_last (inputsAdapter_0_upsizer_logic_io_output_payload_last ), //o + .dat0_i_clk (dat0_i_clk ), //i + .dat0_i_reset (dat0_i_reset ) //i + ); + EfxDMA_StreamFifoCC inputsAdapter_0_crossclock_fifo ( + .io_push_valid (inputsAdapter_0_upsizer_logic_io_output_valid ), //i + .io_push_ready (inputsAdapter_0_crossclock_fifo_io_push_ready ), //o + .io_push_payload_data (inputsAdapter_0_upsizer_logic_io_output_payload_data[63:0]), //i + .io_push_payload_mask (inputsAdapter_0_upsizer_logic_io_output_payload_mask[7:0] ), //i + .io_push_payload_sink (inputsAdapter_0_upsizer_logic_io_output_payload_sink[3:0] ), //i + .io_push_payload_last (inputsAdapter_0_upsizer_logic_io_output_payload_last ), //i + .io_pop_valid (inputsAdapter_0_crossclock_fifo_io_pop_valid ), //o + .io_pop_ready (io_pop_rValidN ), //i + .io_pop_payload_data (inputsAdapter_0_crossclock_fifo_io_pop_payload_data[63:0] ), //o + .io_pop_payload_mask (inputsAdapter_0_crossclock_fifo_io_pop_payload_mask[7:0] ), //o + .io_pop_payload_sink (inputsAdapter_0_crossclock_fifo_io_pop_payload_sink[3:0] ), //o + .io_pop_payload_last (inputsAdapter_0_crossclock_fifo_io_pop_payload_last ), //o + .io_pushOccupancy (inputsAdapter_0_crossclock_fifo_io_pushOccupancy[4:0] ), //o + .io_popOccupancy (inputsAdapter_0_crossclock_fifo_io_popOccupancy[4:0] ), //o + .dat0_i_clk (dat0_i_clk ), //i + .dat0_i_reset (dat0_i_reset ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_StreamFifoCC_1 outputsAdapter_0_crossclock_fifo ( + .io_push_valid (outputsAdapter_0_ptr_valid ), //i + .io_push_ready (outputsAdapter_0_crossclock_fifo_io_push_ready ), //o + .io_push_payload_data (outputsAdapter_0_ptr_payload_data[63:0] ), //i + .io_push_payload_mask (outputsAdapter_0_ptr_payload_mask[7:0] ), //i + .io_push_payload_sink (outputsAdapter_0_ptr_payload_sink[3:0] ), //i + .io_push_payload_last (outputsAdapter_0_ptr_payload_last ), //i + .io_pop_valid (outputsAdapter_0_crossclock_fifo_io_pop_valid ), //o + .io_pop_ready (outputsAdapter_0_sparseDownsizer_logic_io_input_ready ), //i + .io_pop_payload_data (outputsAdapter_0_crossclock_fifo_io_pop_payload_data[63:0]), //o + .io_pop_payload_mask (outputsAdapter_0_crossclock_fifo_io_pop_payload_mask[7:0] ), //o + .io_pop_payload_sink (outputsAdapter_0_crossclock_fifo_io_pop_payload_sink[3:0] ), //o + .io_pop_payload_last (outputsAdapter_0_crossclock_fifo_io_pop_payload_last ), //o + .io_pushOccupancy (outputsAdapter_0_crossclock_fifo_io_pushOccupancy[4:0] ), //o + .io_popOccupancy (outputsAdapter_0_crossclock_fifo_io_popOccupancy[4:0] ), //o + .clk (clk ), //i + .reset (reset ), //i + .dat1_o_clk (dat1_o_clk ), //i + .dat1_o_reset (dat1_o_reset ) //i + ); + EfxDMA_BsbDownSizerSparse outputsAdapter_0_sparseDownsizer_logic ( + .io_input_valid (outputsAdapter_0_crossclock_fifo_io_pop_valid ), //i + .io_input_ready (outputsAdapter_0_sparseDownsizer_logic_io_input_ready ), //o + .io_input_payload_data (outputsAdapter_0_crossclock_fifo_io_pop_payload_data[63:0] ), //i + .io_input_payload_mask (outputsAdapter_0_crossclock_fifo_io_pop_payload_mask[7:0] ), //i + .io_input_payload_sink (outputsAdapter_0_crossclock_fifo_io_pop_payload_sink[3:0] ), //i + .io_input_payload_last (outputsAdapter_0_crossclock_fifo_io_pop_payload_last ), //i + .io_output_valid (outputsAdapter_0_sparseDownsizer_logic_io_output_valid ), //o + .io_output_ready (dat1_o_tready ), //i + .io_output_payload_data (outputsAdapter_0_sparseDownsizer_logic_io_output_payload_data[7:0]), //o + .io_output_payload_mask (outputsAdapter_0_sparseDownsizer_logic_io_output_payload_mask ), //o + .io_output_payload_sink (outputsAdapter_0_sparseDownsizer_logic_io_output_payload_sink[3:0]), //o + .io_output_payload_last (outputsAdapter_0_sparseDownsizer_logic_io_output_payload_last ), //o + .dat1_o_clk (dat1_o_clk ), //i + .dat1_o_reset (dat1_o_reset ) //i + ); + EfxDMA_BmbArbiter interconnect_read_aggregated_arbiter ( + .io_inputs_0_cmd_valid (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid ), //i + .io_inputs_0_cmd_ready (interconnect_read_aggregated_arbiter_io_inputs_0_cmd_ready ), //o + .io_inputs_0_cmd_payload_last (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last ), //i + .io_inputs_0_cmd_payload_fragment_opcode (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode ), //i + .io_inputs_0_cmd_payload_fragment_address (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address[31:0]), //i + .io_inputs_0_cmd_payload_fragment_length (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length[4:0] ), //i + .io_inputs_0_cmd_payload_fragment_context (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context ), //i + .io_inputs_0_rsp_valid (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_valid ), //o + .io_inputs_0_rsp_ready (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready ), //i + .io_inputs_0_rsp_payload_last (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_last ), //o + .io_inputs_0_rsp_payload_fragment_opcode (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode ), //o + .io_inputs_0_rsp_payload_fragment_data (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_data[127:0] ), //o + .io_inputs_0_rsp_payload_fragment_context (interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context ), //o + .io_inputs_1_cmd_valid (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid ), //i + .io_inputs_1_cmd_ready (interconnect_read_aggregated_arbiter_io_inputs_1_cmd_ready ), //o + .io_inputs_1_cmd_payload_last (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last ), //i + .io_inputs_1_cmd_payload_fragment_opcode (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode ), //i + .io_inputs_1_cmd_payload_fragment_address (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address[31:0]), //i + .io_inputs_1_cmd_payload_fragment_length (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length[11:0] ), //i + .io_inputs_1_cmd_payload_fragment_context (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context[20:0]), //i + .io_inputs_1_rsp_valid (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_valid ), //o + .io_inputs_1_rsp_ready (interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready ), //i + .io_inputs_1_rsp_payload_last (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_last ), //o + .io_inputs_1_rsp_payload_fragment_opcode (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //o + .io_inputs_1_rsp_payload_fragment_data (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_data[127:0] ), //o + .io_inputs_1_rsp_payload_fragment_context (interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context[20:0] ), //o + .io_output_cmd_valid (interconnect_read_aggregated_arbiter_io_output_cmd_valid ), //o + .io_output_cmd_ready (interconnect_read_aggregated_cmd_ready ), //i + .io_output_cmd_payload_last (interconnect_read_aggregated_arbiter_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_source (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_source ), //o + .io_output_cmd_payload_fragment_opcode (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_cmd_payload_fragment_context (interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_context[20:0] ), //o + .io_output_rsp_valid (interconnect_read_aggregated_rsp_valid ), //i + .io_output_rsp_ready (interconnect_read_aggregated_arbiter_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (interconnect_read_aggregated_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_source (interconnect_read_aggregated_rsp_payload_fragment_source ), //i + .io_output_rsp_payload_fragment_opcode (interconnect_read_aggregated_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (interconnect_read_aggregated_rsp_payload_fragment_data[127:0] ), //i + .io_output_rsp_payload_fragment_context (interconnect_read_aggregated_rsp_payload_fragment_context[20:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_BmbArbiter_1 interconnect_write_aggregated_arbiter ( + .io_inputs_0_cmd_valid (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid ), //i + .io_inputs_0_cmd_ready (interconnect_write_aggregated_arbiter_io_inputs_0_cmd_ready ), //o + .io_inputs_0_cmd_payload_last (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last ), //i + .io_inputs_0_cmd_payload_fragment_opcode (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode ), //i + .io_inputs_0_cmd_payload_fragment_address (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address[31:0]), //i + .io_inputs_0_cmd_payload_fragment_length (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length[1:0] ), //i + .io_inputs_0_cmd_payload_fragment_data (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data[127:0] ), //i + .io_inputs_0_cmd_payload_fragment_mask (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask[15:0] ), //i + .io_inputs_0_cmd_payload_fragment_context (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context ), //i + .io_inputs_0_rsp_valid (interconnect_write_aggregated_arbiter_io_inputs_0_rsp_valid ), //o + .io_inputs_0_rsp_ready (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready ), //i + .io_inputs_0_rsp_payload_last (interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_last ), //o + .io_inputs_0_rsp_payload_fragment_opcode (interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode ), //o + .io_inputs_0_rsp_payload_fragment_context (interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context ), //o + .io_inputs_1_cmd_valid (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid ), //i + .io_inputs_1_cmd_ready (interconnect_write_aggregated_arbiter_io_inputs_1_cmd_ready ), //o + .io_inputs_1_cmd_payload_last (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last ), //i + .io_inputs_1_cmd_payload_fragment_opcode (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode ), //i + .io_inputs_1_cmd_payload_fragment_address (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address[31:0]), //i + .io_inputs_1_cmd_payload_fragment_length (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length[11:0] ), //i + .io_inputs_1_cmd_payload_fragment_data (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_data[127:0] ), //i + .io_inputs_1_cmd_payload_fragment_mask (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_mask[15:0] ), //i + .io_inputs_1_cmd_payload_fragment_context (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context[12:0]), //i + .io_inputs_1_rsp_valid (interconnect_write_aggregated_arbiter_io_inputs_1_rsp_valid ), //o + .io_inputs_1_rsp_ready (interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready ), //i + .io_inputs_1_rsp_payload_last (interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_last ), //o + .io_inputs_1_rsp_payload_fragment_opcode (interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode ), //o + .io_inputs_1_rsp_payload_fragment_context (interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context[12:0] ), //o + .io_output_cmd_valid (interconnect_write_aggregated_arbiter_io_output_cmd_valid ), //o + .io_output_cmd_ready (interconnect_write_aggregated_cmd_ready ), //i + .io_output_cmd_payload_last (interconnect_write_aggregated_arbiter_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_source (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_source ), //o + .io_output_cmd_payload_fragment_opcode (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_address[31:0] ), //o + .io_output_cmd_payload_fragment_length (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_cmd_payload_fragment_data (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_data[127:0] ), //o + .io_output_cmd_payload_fragment_mask (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_mask[15:0] ), //o + .io_output_cmd_payload_fragment_context (interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_context[12:0] ), //o + .io_output_rsp_valid (interconnect_write_aggregated_rsp_valid ), //i + .io_output_rsp_ready (interconnect_write_aggregated_arbiter_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (interconnect_write_aggregated_rsp_payload_last ), //i + .io_output_rsp_payload_fragment_source (interconnect_write_aggregated_rsp_payload_fragment_source ), //i + .io_output_rsp_payload_fragment_opcode (interconnect_write_aggregated_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_context (interconnect_write_aggregated_rsp_payload_fragment_context[12:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign io_0_descriptorUpdate = core_ll_0_descriptorUpdate; + assign io_1_descriptorUpdate = core_ll_1_descriptorUpdate; + assign ctrl_PREADY = withCtrlCc_apbCc_io_input_PREADY; + assign ctrl_PRDATA = withCtrlCc_apbCc_io_input_PRDATA; + assign ctrl_PSLVERROR = withCtrlCc_apbCc_io_input_PSLVERROR; + assign ctrl_interrupts = io_interrupts_buffercc_io_dataOut; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid = core_io_read_cmd_valid; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready = core_io_read_rsp_ready; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last = core_io_read_cmd_payload_last; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode = core_io_read_cmd_payload_fragment_opcode; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address = core_io_read_cmd_payload_fragment_address; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length = core_io_read_cmd_payload_fragment_length; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context = core_io_read_cmd_payload_fragment_context; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid = core_io_sgRead_cmd_valid; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready = core_io_sgRead_rsp_ready; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last = core_io_sgRead_cmd_payload_last; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode = core_io_sgRead_cmd_payload_fragment_opcode; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address = core_io_sgRead_cmd_payload_fragment_address; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length = core_io_sgRead_cmd_payload_fragment_length; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context = core_io_sgRead_cmd_payload_fragment_context; + assign io_write_cmd_s2mPipe_valid = (core_io_write_cmd_valid || (! io_write_cmd_rValidN)); + assign io_write_cmd_s2mPipe_payload_last = (io_write_cmd_rValidN ? core_io_write_cmd_payload_last : io_write_cmd_rData_last); + assign io_write_cmd_s2mPipe_payload_fragment_opcode = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_opcode : io_write_cmd_rData_fragment_opcode); + assign io_write_cmd_s2mPipe_payload_fragment_address = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_address : io_write_cmd_rData_fragment_address); + assign io_write_cmd_s2mPipe_payload_fragment_length = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_length : io_write_cmd_rData_fragment_length); + assign io_write_cmd_s2mPipe_payload_fragment_data = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_data : io_write_cmd_rData_fragment_data); + assign io_write_cmd_s2mPipe_payload_fragment_mask = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_mask : io_write_cmd_rData_fragment_mask); + assign io_write_cmd_s2mPipe_payload_fragment_context = (io_write_cmd_rValidN ? core_io_write_cmd_payload_fragment_context : io_write_cmd_rData_fragment_context); + always @(*) begin + io_write_cmd_s2mPipe_ready = io_write_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l375) begin + io_write_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! io_write_cmd_s2mPipe_m2sPipe_valid); + assign io_write_cmd_s2mPipe_m2sPipe_valid = io_write_cmd_s2mPipe_rValid; + assign io_write_cmd_s2mPipe_m2sPipe_payload_last = io_write_cmd_s2mPipe_rData_last; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_opcode = io_write_cmd_s2mPipe_rData_fragment_opcode; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_address = io_write_cmd_s2mPipe_rData_fragment_address; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_length = io_write_cmd_s2mPipe_rData_fragment_length; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_data = io_write_cmd_s2mPipe_rData_fragment_data; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_mask = io_write_cmd_s2mPipe_rData_fragment_mask; + assign io_write_cmd_s2mPipe_m2sPipe_payload_fragment_context = io_write_cmd_s2mPipe_rData_fragment_context; + assign io_write_cmd_s2mPipe_m2sPipe_ready = interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_valid = io_write_cmd_s2mPipe_m2sPipe_valid; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_ready = core_io_write_rsp_ready; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_last = io_write_cmd_s2mPipe_m2sPipe_payload_last; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_opcode = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_opcode; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_address = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_address; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_length = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_length; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_data = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_data; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_mask = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_mask; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_payload_fragment_context = io_write_cmd_s2mPipe_m2sPipe_payload_fragment_context; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_valid = core_io_sgWrite_cmd_valid; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_ready = core_io_sgWrite_rsp_ready; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_last = core_io_sgWrite_cmd_payload_last; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_opcode = core_io_sgWrite_cmd_payload_fragment_opcode; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_address = core_io_sgWrite_cmd_payload_fragment_address; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_length = core_io_sgWrite_cmd_payload_fragment_length; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_data = core_io_sgWrite_cmd_payload_fragment_data; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_mask = core_io_sgWrite_cmd_payload_fragment_mask; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_payload_fragment_context = core_io_sgWrite_cmd_payload_fragment_context; + assign interconnect_read_aggregated_cmd_halfPipe_fire = (interconnect_read_aggregated_cmd_halfPipe_valid && interconnect_read_aggregated_cmd_halfPipe_ready); + assign interconnect_read_aggregated_cmd_ready = (! interconnect_read_aggregated_cmd_rValid); + assign interconnect_read_aggregated_cmd_halfPipe_valid = interconnect_read_aggregated_cmd_rValid; + assign interconnect_read_aggregated_cmd_halfPipe_payload_last = interconnect_read_aggregated_cmd_rData_last; + assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_source = interconnect_read_aggregated_cmd_rData_fragment_source; + assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_opcode = interconnect_read_aggregated_cmd_rData_fragment_opcode; + assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_address = interconnect_read_aggregated_cmd_rData_fragment_address; + assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_length = interconnect_read_aggregated_cmd_rData_fragment_length; + assign interconnect_read_aggregated_cmd_halfPipe_payload_fragment_context = interconnect_read_aggregated_cmd_rData_fragment_context; + assign readLogic_resized_cmd_valid = interconnect_read_aggregated_cmd_halfPipe_valid; + assign interconnect_read_aggregated_cmd_halfPipe_ready = readLogic_resized_cmd_ready; + assign readLogic_resized_cmd_payload_last = interconnect_read_aggregated_cmd_halfPipe_payload_last; + assign readLogic_resized_cmd_payload_fragment_source = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_source; + assign readLogic_resized_cmd_payload_fragment_opcode = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_opcode; + assign readLogic_resized_cmd_payload_fragment_address = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_address; + assign readLogic_resized_cmd_payload_fragment_length = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_length; + assign readLogic_resized_cmd_payload_fragment_context = interconnect_read_aggregated_cmd_halfPipe_payload_fragment_context; + assign readLogic_resized_rsp_combStage_valid = readLogic_resized_rsp_valid; + assign readLogic_resized_rsp_ready = readLogic_resized_rsp_combStage_ready; + assign readLogic_resized_rsp_combStage_payload_last = readLogic_resized_rsp_payload_last; + assign readLogic_resized_rsp_combStage_payload_fragment_source = readLogic_resized_rsp_payload_fragment_source; + assign readLogic_resized_rsp_combStage_payload_fragment_opcode = readLogic_resized_rsp_payload_fragment_opcode; + assign readLogic_resized_rsp_combStage_payload_fragment_data = readLogic_resized_rsp_payload_fragment_data; + assign readLogic_resized_rsp_combStage_payload_fragment_context = readLogic_resized_rsp_payload_fragment_context; + assign interconnect_read_aggregated_rsp_valid = readLogic_resized_rsp_combStage_valid; + assign readLogic_resized_rsp_combStage_ready = interconnect_read_aggregated_rsp_ready; + assign interconnect_read_aggregated_rsp_payload_last = readLogic_resized_rsp_combStage_payload_last; + assign interconnect_read_aggregated_rsp_payload_fragment_source = readLogic_resized_rsp_combStage_payload_fragment_source; + assign interconnect_read_aggregated_rsp_payload_fragment_opcode = readLogic_resized_rsp_combStage_payload_fragment_opcode; + assign interconnect_read_aggregated_rsp_payload_fragment_data = readLogic_resized_rsp_combStage_payload_fragment_data; + assign interconnect_read_aggregated_rsp_payload_fragment_context = readLogic_resized_rsp_combStage_payload_fragment_context; + assign readLogic_resized_cmd_ready = readLogic_sourceRemover_io_input_cmd_ready; + assign readLogic_resized_rsp_valid = readLogic_sourceRemover_io_input_rsp_valid; + assign readLogic_resized_rsp_payload_last = readLogic_sourceRemover_io_input_rsp_payload_last; + assign readLogic_resized_rsp_payload_fragment_source = readLogic_sourceRemover_io_input_rsp_payload_fragment_source; + assign readLogic_resized_rsp_payload_fragment_opcode = readLogic_sourceRemover_io_input_rsp_payload_fragment_opcode; + assign readLogic_resized_rsp_payload_fragment_data = readLogic_sourceRemover_io_input_rsp_payload_fragment_data; + assign readLogic_resized_rsp_payload_fragment_context = readLogic_sourceRemover_io_input_rsp_payload_fragment_context; + assign readLogic_adapter_ar_valid = readLogic_bridge_io_output_ar_valid; + assign readLogic_adapter_ar_payload_addr = readLogic_bridge_io_output_ar_payload_addr; + assign _zz_readLogic_adapter_ar_payload_region[3 : 0] = 4'b0000; + assign readLogic_adapter_ar_payload_region = _zz_readLogic_adapter_ar_payload_region; + assign readLogic_adapter_ar_payload_len = readLogic_bridge_io_output_ar_payload_len; + assign readLogic_adapter_ar_payload_size = readLogic_bridge_io_output_ar_payload_size; + assign readLogic_adapter_ar_payload_burst = 2'b01; + assign readLogic_adapter_ar_payload_lock = 1'b0; + assign readLogic_adapter_ar_payload_cache = readLogic_bridge_io_output_ar_payload_cache; + assign readLogic_adapter_ar_payload_qos = 4'b0000; + assign readLogic_adapter_ar_payload_prot = readLogic_bridge_io_output_ar_payload_prot; + assign readLogic_adapter_r_ready = readLogic_bridge_io_output_r_ready; + assign readLogic_adapter_ar_halfPipe_fire = (readLogic_adapter_ar_halfPipe_valid && readLogic_adapter_ar_halfPipe_ready); + assign readLogic_adapter_ar_ready = (! readLogic_adapter_ar_rValid); + assign readLogic_adapter_ar_halfPipe_valid = readLogic_adapter_ar_rValid; + assign readLogic_adapter_ar_halfPipe_payload_addr = readLogic_adapter_ar_rData_addr; + assign readLogic_adapter_ar_halfPipe_payload_region = readLogic_adapter_ar_rData_region; + assign readLogic_adapter_ar_halfPipe_payload_len = readLogic_adapter_ar_rData_len; + assign readLogic_adapter_ar_halfPipe_payload_size = readLogic_adapter_ar_rData_size; + assign readLogic_adapter_ar_halfPipe_payload_burst = readLogic_adapter_ar_rData_burst; + assign readLogic_adapter_ar_halfPipe_payload_lock = readLogic_adapter_ar_rData_lock; + assign readLogic_adapter_ar_halfPipe_payload_cache = readLogic_adapter_ar_rData_cache; + assign readLogic_adapter_ar_halfPipe_payload_qos = readLogic_adapter_ar_rData_qos; + assign readLogic_adapter_ar_halfPipe_payload_prot = readLogic_adapter_ar_rData_prot; + assign read_arvalid = readLogic_adapter_ar_halfPipe_valid; + assign readLogic_adapter_ar_halfPipe_ready = read_arready; + assign read_araddr = readLogic_adapter_ar_halfPipe_payload_addr; + assign read_arregion = readLogic_adapter_ar_halfPipe_payload_region; + assign read_arlen = readLogic_adapter_ar_halfPipe_payload_len; + assign read_arsize = readLogic_adapter_ar_halfPipe_payload_size; + assign read_arburst = readLogic_adapter_ar_halfPipe_payload_burst; + assign read_arlock = readLogic_adapter_ar_halfPipe_payload_lock; + assign read_arcache = readLogic_adapter_ar_halfPipe_payload_cache; + assign read_arqos = readLogic_adapter_ar_halfPipe_payload_qos; + assign read_arprot = readLogic_adapter_ar_halfPipe_payload_prot; + assign read_rready = read_r_rValidN; + assign read_r_s2mPipe_valid = (read_rvalid || (! read_r_rValidN)); + assign read_r_s2mPipe_payload_data = (read_r_rValidN ? read_rdata : read_r_rData_data); + assign read_r_s2mPipe_payload_resp = (read_r_rValidN ? read_rresp : read_r_rData_resp); + assign read_r_s2mPipe_payload_last = (read_r_rValidN ? read_rlast : read_r_rData_last); + always @(*) begin + read_r_s2mPipe_ready = readLogic_beforeQueue_ready; + if(when_Stream_l375_1) begin + read_r_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375_1 = (! readLogic_beforeQueue_valid); + assign readLogic_beforeQueue_valid = read_r_s2mPipe_rValid; + assign readLogic_beforeQueue_payload_data = read_r_s2mPipe_rData_data; + assign readLogic_beforeQueue_payload_resp = read_r_s2mPipe_rData_resp; + assign readLogic_beforeQueue_payload_last = read_r_s2mPipe_rData_last; + assign readLogic_adapter_r_valid = readLogic_beforeQueue_valid; + assign readLogic_beforeQueue_ready = readLogic_adapter_r_ready; + assign readLogic_adapter_r_payload_data = readLogic_beforeQueue_payload_data; + assign readLogic_adapter_r_payload_resp = readLogic_beforeQueue_payload_resp; + assign readLogic_adapter_r_payload_last = readLogic_beforeQueue_payload_last; + always @(*) begin + interconnect_write_aggregated_cmd_ready = interconnect_write_aggregated_cmd_m2sPipe_ready; + if(when_Stream_l375_2) begin + interconnect_write_aggregated_cmd_ready = 1'b1; + end + end + + assign when_Stream_l375_2 = (! interconnect_write_aggregated_cmd_m2sPipe_valid); + assign interconnect_write_aggregated_cmd_m2sPipe_valid = interconnect_write_aggregated_cmd_rValid; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_last = interconnect_write_aggregated_cmd_rData_last; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_source = interconnect_write_aggregated_cmd_rData_fragment_source; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_opcode = interconnect_write_aggregated_cmd_rData_fragment_opcode; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_address = interconnect_write_aggregated_cmd_rData_fragment_address; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_length = interconnect_write_aggregated_cmd_rData_fragment_length; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_data = interconnect_write_aggregated_cmd_rData_fragment_data; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_mask = interconnect_write_aggregated_cmd_rData_fragment_mask; + assign interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_context = interconnect_write_aggregated_cmd_rData_fragment_context; + assign writeLogic_resized_cmd_valid = interconnect_write_aggregated_cmd_m2sPipe_valid; + assign interconnect_write_aggregated_cmd_m2sPipe_ready = writeLogic_resized_cmd_ready; + assign writeLogic_resized_cmd_payload_last = interconnect_write_aggregated_cmd_m2sPipe_payload_last; + assign writeLogic_resized_cmd_payload_fragment_source = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_source; + assign writeLogic_resized_cmd_payload_fragment_opcode = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_opcode; + assign writeLogic_resized_cmd_payload_fragment_address = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_address; + assign writeLogic_resized_cmd_payload_fragment_length = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_length; + assign writeLogic_resized_cmd_payload_fragment_data = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_data; + assign writeLogic_resized_cmd_payload_fragment_mask = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_mask; + assign writeLogic_resized_cmd_payload_fragment_context = interconnect_write_aggregated_cmd_m2sPipe_payload_fragment_context; + assign writeLogic_resized_rsp_combStage_valid = writeLogic_resized_rsp_valid; + assign writeLogic_resized_rsp_ready = writeLogic_resized_rsp_combStage_ready; + assign writeLogic_resized_rsp_combStage_payload_last = writeLogic_resized_rsp_payload_last; + assign writeLogic_resized_rsp_combStage_payload_fragment_source = writeLogic_resized_rsp_payload_fragment_source; + assign writeLogic_resized_rsp_combStage_payload_fragment_opcode = writeLogic_resized_rsp_payload_fragment_opcode; + assign writeLogic_resized_rsp_combStage_payload_fragment_context = writeLogic_resized_rsp_payload_fragment_context; + assign interconnect_write_aggregated_rsp_valid = writeLogic_resized_rsp_combStage_valid; + assign writeLogic_resized_rsp_combStage_ready = interconnect_write_aggregated_rsp_ready; + assign interconnect_write_aggregated_rsp_payload_last = writeLogic_resized_rsp_combStage_payload_last; + assign interconnect_write_aggregated_rsp_payload_fragment_source = writeLogic_resized_rsp_combStage_payload_fragment_source; + assign interconnect_write_aggregated_rsp_payload_fragment_opcode = writeLogic_resized_rsp_combStage_payload_fragment_opcode; + assign interconnect_write_aggregated_rsp_payload_fragment_context = writeLogic_resized_rsp_combStage_payload_fragment_context; + assign writeLogic_resized_cmd_ready = writeLogic_sourceRemover_io_input_cmd_ready; + assign writeLogic_resized_rsp_valid = writeLogic_sourceRemover_io_input_rsp_valid; + assign writeLogic_resized_rsp_payload_last = writeLogic_sourceRemover_io_input_rsp_payload_last; + assign writeLogic_resized_rsp_payload_fragment_source = writeLogic_sourceRemover_io_input_rsp_payload_fragment_source; + assign writeLogic_resized_rsp_payload_fragment_opcode = writeLogic_sourceRemover_io_input_rsp_payload_fragment_opcode; + assign writeLogic_resized_rsp_payload_fragment_context = writeLogic_sourceRemover_io_input_rsp_payload_fragment_context; + assign writeLogic_adapter_aw_valid = writeLogic_bridge_io_output_aw_valid; + assign writeLogic_adapter_aw_payload_addr = writeLogic_bridge_io_output_aw_payload_addr; + assign _zz_writeLogic_adapter_aw_payload_region[3 : 0] = 4'b0000; + assign writeLogic_adapter_aw_payload_region = _zz_writeLogic_adapter_aw_payload_region; + assign writeLogic_adapter_aw_payload_len = writeLogic_bridge_io_output_aw_payload_len; + assign writeLogic_adapter_aw_payload_size = writeLogic_bridge_io_output_aw_payload_size; + assign writeLogic_adapter_aw_payload_burst = 2'b01; + assign writeLogic_adapter_aw_payload_lock = 1'b0; + assign writeLogic_adapter_aw_payload_cache = writeLogic_bridge_io_output_aw_payload_cache; + assign writeLogic_adapter_aw_payload_qos = 4'b0000; + assign writeLogic_adapter_aw_payload_prot = writeLogic_bridge_io_output_aw_payload_prot; + assign writeLogic_adapter_w_valid = writeLogic_bridge_io_output_w_valid; + assign writeLogic_adapter_w_payload_data = writeLogic_bridge_io_output_w_payload_data; + assign writeLogic_adapter_w_payload_strb = writeLogic_bridge_io_output_w_payload_strb; + assign writeLogic_adapter_w_payload_last = writeLogic_bridge_io_output_w_payload_last; + assign writeLogic_adapter_b_ready = writeLogic_bridge_io_output_b_ready; + assign writeLogic_adapter_aw_halfPipe_fire = (writeLogic_adapter_aw_halfPipe_valid && writeLogic_adapter_aw_halfPipe_ready); + assign writeLogic_adapter_aw_ready = (! writeLogic_adapter_aw_rValid); + assign writeLogic_adapter_aw_halfPipe_valid = writeLogic_adapter_aw_rValid; + assign writeLogic_adapter_aw_halfPipe_payload_addr = writeLogic_adapter_aw_rData_addr; + assign writeLogic_adapter_aw_halfPipe_payload_region = writeLogic_adapter_aw_rData_region; + assign writeLogic_adapter_aw_halfPipe_payload_len = writeLogic_adapter_aw_rData_len; + assign writeLogic_adapter_aw_halfPipe_payload_size = writeLogic_adapter_aw_rData_size; + assign writeLogic_adapter_aw_halfPipe_payload_burst = writeLogic_adapter_aw_rData_burst; + assign writeLogic_adapter_aw_halfPipe_payload_lock = writeLogic_adapter_aw_rData_lock; + assign writeLogic_adapter_aw_halfPipe_payload_cache = writeLogic_adapter_aw_rData_cache; + assign writeLogic_adapter_aw_halfPipe_payload_qos = writeLogic_adapter_aw_rData_qos; + assign writeLogic_adapter_aw_halfPipe_payload_prot = writeLogic_adapter_aw_rData_prot; + assign write_awvalid = writeLogic_adapter_aw_halfPipe_valid; + assign writeLogic_adapter_aw_halfPipe_ready = write_awready; + assign write_awaddr = writeLogic_adapter_aw_halfPipe_payload_addr; + assign write_awregion = writeLogic_adapter_aw_halfPipe_payload_region; + assign write_awlen = writeLogic_adapter_aw_halfPipe_payload_len; + assign write_awsize = writeLogic_adapter_aw_halfPipe_payload_size; + assign write_awburst = writeLogic_adapter_aw_halfPipe_payload_burst; + assign write_awlock = writeLogic_adapter_aw_halfPipe_payload_lock; + assign write_awcache = writeLogic_adapter_aw_halfPipe_payload_cache; + assign write_awqos = writeLogic_adapter_aw_halfPipe_payload_qos; + assign write_awprot = writeLogic_adapter_aw_halfPipe_payload_prot; + assign writeLogic_adapter_w_ready = writeLogic_adapter_w_rValidN; + assign writeLogic_adapter_w_s2mPipe_valid = (writeLogic_adapter_w_valid || (! writeLogic_adapter_w_rValidN)); + assign writeLogic_adapter_w_s2mPipe_payload_data = (writeLogic_adapter_w_rValidN ? writeLogic_adapter_w_payload_data : writeLogic_adapter_w_rData_data); + assign writeLogic_adapter_w_s2mPipe_payload_strb = (writeLogic_adapter_w_rValidN ? writeLogic_adapter_w_payload_strb : writeLogic_adapter_w_rData_strb); + assign writeLogic_adapter_w_s2mPipe_payload_last = (writeLogic_adapter_w_rValidN ? writeLogic_adapter_w_payload_last : writeLogic_adapter_w_rData_last); + always @(*) begin + writeLogic_adapter_w_s2mPipe_ready = writeLogic_adapter_w_s2mPipe_m2sPipe_ready; + if(when_Stream_l375_3) begin + writeLogic_adapter_w_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375_3 = (! writeLogic_adapter_w_s2mPipe_m2sPipe_valid); + assign writeLogic_adapter_w_s2mPipe_m2sPipe_valid = writeLogic_adapter_w_s2mPipe_rValid; + assign writeLogic_adapter_w_s2mPipe_m2sPipe_payload_data = writeLogic_adapter_w_s2mPipe_rData_data; + assign writeLogic_adapter_w_s2mPipe_m2sPipe_payload_strb = writeLogic_adapter_w_s2mPipe_rData_strb; + assign writeLogic_adapter_w_s2mPipe_m2sPipe_payload_last = writeLogic_adapter_w_s2mPipe_rData_last; + assign write_wvalid = writeLogic_adapter_w_s2mPipe_m2sPipe_valid; + assign writeLogic_adapter_w_s2mPipe_m2sPipe_ready = write_wready; + assign write_wdata = writeLogic_adapter_w_s2mPipe_m2sPipe_payload_data; + assign write_wstrb = writeLogic_adapter_w_s2mPipe_m2sPipe_payload_strb; + assign write_wlast = writeLogic_adapter_w_s2mPipe_m2sPipe_payload_last; + assign write_b_halfPipe_fire = (write_b_halfPipe_valid && write_b_halfPipe_ready); + assign write_bready = (! write_b_rValid); + assign write_b_halfPipe_valid = write_b_rValid; + assign write_b_halfPipe_payload_resp = write_b_rData_resp; + assign writeLogic_adapter_b_valid = write_b_halfPipe_valid; + assign write_b_halfPipe_ready = writeLogic_adapter_b_ready; + assign writeLogic_adapter_b_payload_resp = write_b_halfPipe_payload_resp; + assign dat0_i_tready = inputsAdapter_0_upsizer_logic_io_input_ready; + assign io_pop_s2mPipe_valid = (inputsAdapter_0_crossclock_fifo_io_pop_valid || (! io_pop_rValidN)); + assign io_pop_s2mPipe_payload_data = (io_pop_rValidN ? inputsAdapter_0_crossclock_fifo_io_pop_payload_data : io_pop_rData_data); + assign io_pop_s2mPipe_payload_mask = (io_pop_rValidN ? inputsAdapter_0_crossclock_fifo_io_pop_payload_mask : io_pop_rData_mask); + assign io_pop_s2mPipe_payload_sink = (io_pop_rValidN ? inputsAdapter_0_crossclock_fifo_io_pop_payload_sink : io_pop_rData_sink); + assign io_pop_s2mPipe_payload_last = (io_pop_rValidN ? inputsAdapter_0_crossclock_fifo_io_pop_payload_last : io_pop_rData_last); + always @(*) begin + io_pop_s2mPipe_ready = io_pop_s2mPipe_m2sPipe_ready; + if(when_Stream_l375_4) begin + io_pop_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375_4 = (! io_pop_s2mPipe_m2sPipe_valid); + assign io_pop_s2mPipe_m2sPipe_valid = io_pop_s2mPipe_rValid; + assign io_pop_s2mPipe_m2sPipe_payload_data = io_pop_s2mPipe_rData_data; + assign io_pop_s2mPipe_m2sPipe_payload_mask = io_pop_s2mPipe_rData_mask; + assign io_pop_s2mPipe_m2sPipe_payload_sink = io_pop_s2mPipe_rData_sink; + assign io_pop_s2mPipe_m2sPipe_payload_last = io_pop_s2mPipe_rData_last; + assign io_pop_s2mPipe_m2sPipe_ready = core_io_inputs_0_ready; + assign io_outputs_0_s2mPipe_valid = (core_io_outputs_0_valid || (! io_outputs_0_rValidN)); + assign io_outputs_0_s2mPipe_payload_data = (io_outputs_0_rValidN ? core_io_outputs_0_payload_data : io_outputs_0_rData_data); + assign io_outputs_0_s2mPipe_payload_mask = (io_outputs_0_rValidN ? core_io_outputs_0_payload_mask : io_outputs_0_rData_mask); + assign io_outputs_0_s2mPipe_payload_sink = (io_outputs_0_rValidN ? core_io_outputs_0_payload_sink : io_outputs_0_rData_sink); + assign io_outputs_0_s2mPipe_payload_last = (io_outputs_0_rValidN ? core_io_outputs_0_payload_last : io_outputs_0_rData_last); + always @(*) begin + io_outputs_0_s2mPipe_ready = outputsAdapter_0_ptr_ready; + if(when_Stream_l375_5) begin + io_outputs_0_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l375_5 = (! outputsAdapter_0_ptr_valid); + assign outputsAdapter_0_ptr_valid = io_outputs_0_s2mPipe_rValid; + assign outputsAdapter_0_ptr_payload_data = io_outputs_0_s2mPipe_rData_data; + assign outputsAdapter_0_ptr_payload_mask = io_outputs_0_s2mPipe_rData_mask; + assign outputsAdapter_0_ptr_payload_sink = io_outputs_0_s2mPipe_rData_sink; + assign outputsAdapter_0_ptr_payload_last = io_outputs_0_s2mPipe_rData_last; + assign outputsAdapter_0_ptr_ready = outputsAdapter_0_crossclock_fifo_io_push_ready; + assign dat1_o_tvalid = outputsAdapter_0_sparseDownsizer_logic_io_output_valid; + assign dat1_o_tdata = outputsAdapter_0_sparseDownsizer_logic_io_output_payload_data; + assign dat1_o_tkeep = outputsAdapter_0_sparseDownsizer_logic_io_output_payload_mask; + assign dat1_o_tdest = outputsAdapter_0_sparseDownsizer_logic_io_output_payload_sink; + assign dat1_o_tlast = outputsAdapter_0_sparseDownsizer_logic_io_output_payload_last; + assign interconnect_read_aggregated_cmd_valid = interconnect_read_aggregated_arbiter_io_output_cmd_valid; + assign interconnect_read_aggregated_rsp_ready = interconnect_read_aggregated_arbiter_io_output_rsp_ready; + assign interconnect_read_aggregated_cmd_payload_last = interconnect_read_aggregated_arbiter_io_output_cmd_payload_last; + assign interconnect_read_aggregated_cmd_payload_fragment_source = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_source; + assign interconnect_read_aggregated_cmd_payload_fragment_opcode = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_opcode; + assign interconnect_read_aggregated_cmd_payload_fragment_address = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_address; + assign interconnect_read_aggregated_cmd_payload_fragment_length = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_length; + assign interconnect_read_aggregated_cmd_payload_fragment_context = interconnect_read_aggregated_arbiter_io_output_cmd_payload_fragment_context; + assign interconnect_write_aggregated_cmd_valid = interconnect_write_aggregated_arbiter_io_output_cmd_valid; + assign interconnect_write_aggregated_rsp_ready = interconnect_write_aggregated_arbiter_io_output_rsp_ready; + assign interconnect_write_aggregated_cmd_payload_last = interconnect_write_aggregated_arbiter_io_output_cmd_payload_last; + assign interconnect_write_aggregated_cmd_payload_fragment_source = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_source; + assign interconnect_write_aggregated_cmd_payload_fragment_opcode = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_opcode; + assign interconnect_write_aggregated_cmd_payload_fragment_address = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_address; + assign interconnect_write_aggregated_cmd_payload_fragment_length = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_length; + assign interconnect_write_aggregated_cmd_payload_fragment_data = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_data; + assign interconnect_write_aggregated_cmd_payload_fragment_mask = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_mask; + assign interconnect_write_aggregated_cmd_payload_fragment_context = interconnect_write_aggregated_arbiter_io_output_cmd_payload_fragment_context; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready = interconnect_read_aggregated_arbiter_io_inputs_0_cmd_ready; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_valid; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_last; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_data = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_data; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context = interconnect_read_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready = interconnect_read_aggregated_arbiter_io_inputs_1_cmd_ready; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_valid; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_last; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_data = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_data; + assign interconnect_read_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context = interconnect_read_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_cmd_ready = interconnect_write_aggregated_arbiter_io_inputs_0_cmd_ready; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_valid = interconnect_write_aggregated_arbiter_io_inputs_0_rsp_valid; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_last = interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_last; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_opcode = interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_opcode; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_0_decoder_rsp_payload_fragment_context = interconnect_write_aggregated_arbiter_io_inputs_0_rsp_payload_fragment_context; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_cmd_ready = interconnect_write_aggregated_arbiter_io_inputs_1_cmd_ready; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_valid = interconnect_write_aggregated_arbiter_io_inputs_1_rsp_valid; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_last = interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_last; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_opcode = interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_opcode; + assign interconnect_write_aggregated_slaveModel_arbiterGen_logic_sorted_1_decoder_rsp_payload_fragment_context = interconnect_write_aggregated_arbiter_io_inputs_1_rsp_payload_fragment_context; + always @(posedge clk) begin + if(reset) begin + io_write_cmd_rValidN <= 1'b1; + io_write_cmd_s2mPipe_rValid <= 1'b0; + interconnect_read_aggregated_cmd_rValid <= 1'b0; + readLogic_adapter_ar_rValid <= 1'b0; + read_r_rValidN <= 1'b1; + read_r_s2mPipe_rValid <= 1'b0; + interconnect_write_aggregated_cmd_rValid <= 1'b0; + writeLogic_adapter_aw_rValid <= 1'b0; + writeLogic_adapter_w_rValidN <= 1'b1; + writeLogic_adapter_w_s2mPipe_rValid <= 1'b0; + write_b_rValid <= 1'b0; + io_pop_rValidN <= 1'b1; + io_pop_s2mPipe_rValid <= 1'b0; + io_outputs_0_rValidN <= 1'b1; + io_outputs_0_s2mPipe_rValid <= 1'b0; + end else begin + if(core_io_write_cmd_valid) begin + io_write_cmd_rValidN <= 1'b0; + end + if(io_write_cmd_s2mPipe_ready) begin + io_write_cmd_rValidN <= 1'b1; + end + if(io_write_cmd_s2mPipe_ready) begin + io_write_cmd_s2mPipe_rValid <= io_write_cmd_s2mPipe_valid; + end + if(interconnect_read_aggregated_cmd_valid) begin + interconnect_read_aggregated_cmd_rValid <= 1'b1; + end + if(interconnect_read_aggregated_cmd_halfPipe_fire) begin + interconnect_read_aggregated_cmd_rValid <= 1'b0; + end + if(readLogic_adapter_ar_valid) begin + readLogic_adapter_ar_rValid <= 1'b1; + end + if(readLogic_adapter_ar_halfPipe_fire) begin + readLogic_adapter_ar_rValid <= 1'b0; + end + if(read_rvalid) begin + read_r_rValidN <= 1'b0; + end + if(read_r_s2mPipe_ready) begin + read_r_rValidN <= 1'b1; + end + if(read_r_s2mPipe_ready) begin + read_r_s2mPipe_rValid <= read_r_s2mPipe_valid; + end + if(interconnect_write_aggregated_cmd_ready) begin + interconnect_write_aggregated_cmd_rValid <= interconnect_write_aggregated_cmd_valid; + end + if(writeLogic_adapter_aw_valid) begin + writeLogic_adapter_aw_rValid <= 1'b1; + end + if(writeLogic_adapter_aw_halfPipe_fire) begin + writeLogic_adapter_aw_rValid <= 1'b0; + end + if(writeLogic_adapter_w_valid) begin + writeLogic_adapter_w_rValidN <= 1'b0; + end + if(writeLogic_adapter_w_s2mPipe_ready) begin + writeLogic_adapter_w_rValidN <= 1'b1; + end + if(writeLogic_adapter_w_s2mPipe_ready) begin + writeLogic_adapter_w_s2mPipe_rValid <= writeLogic_adapter_w_s2mPipe_valid; + end + if(write_bvalid) begin + write_b_rValid <= 1'b1; + end + if(write_b_halfPipe_fire) begin + write_b_rValid <= 1'b0; + end + if(inputsAdapter_0_crossclock_fifo_io_pop_valid) begin + io_pop_rValidN <= 1'b0; + end + if(io_pop_s2mPipe_ready) begin + io_pop_rValidN <= 1'b1; + end + if(io_pop_s2mPipe_ready) begin + io_pop_s2mPipe_rValid <= io_pop_s2mPipe_valid; + end + if(core_io_outputs_0_valid) begin + io_outputs_0_rValidN <= 1'b0; + end + if(io_outputs_0_s2mPipe_ready) begin + io_outputs_0_rValidN <= 1'b1; + end + if(io_outputs_0_s2mPipe_ready) begin + io_outputs_0_s2mPipe_rValid <= io_outputs_0_s2mPipe_valid; + end + end + end + + always @(posedge clk) begin + if(io_write_cmd_rValidN) begin + io_write_cmd_rData_last <= core_io_write_cmd_payload_last; + io_write_cmd_rData_fragment_opcode <= core_io_write_cmd_payload_fragment_opcode; + io_write_cmd_rData_fragment_address <= core_io_write_cmd_payload_fragment_address; + io_write_cmd_rData_fragment_length <= core_io_write_cmd_payload_fragment_length; + io_write_cmd_rData_fragment_data <= core_io_write_cmd_payload_fragment_data; + io_write_cmd_rData_fragment_mask <= core_io_write_cmd_payload_fragment_mask; + io_write_cmd_rData_fragment_context <= core_io_write_cmd_payload_fragment_context; + end + if(io_write_cmd_s2mPipe_ready) begin + io_write_cmd_s2mPipe_rData_last <= io_write_cmd_s2mPipe_payload_last; + io_write_cmd_s2mPipe_rData_fragment_opcode <= io_write_cmd_s2mPipe_payload_fragment_opcode; + io_write_cmd_s2mPipe_rData_fragment_address <= io_write_cmd_s2mPipe_payload_fragment_address; + io_write_cmd_s2mPipe_rData_fragment_length <= io_write_cmd_s2mPipe_payload_fragment_length; + io_write_cmd_s2mPipe_rData_fragment_data <= io_write_cmd_s2mPipe_payload_fragment_data; + io_write_cmd_s2mPipe_rData_fragment_mask <= io_write_cmd_s2mPipe_payload_fragment_mask; + io_write_cmd_s2mPipe_rData_fragment_context <= io_write_cmd_s2mPipe_payload_fragment_context; + end + if(interconnect_read_aggregated_cmd_ready) begin + interconnect_read_aggregated_cmd_rData_last <= interconnect_read_aggregated_cmd_payload_last; + interconnect_read_aggregated_cmd_rData_fragment_source <= interconnect_read_aggregated_cmd_payload_fragment_source; + interconnect_read_aggregated_cmd_rData_fragment_opcode <= interconnect_read_aggregated_cmd_payload_fragment_opcode; + interconnect_read_aggregated_cmd_rData_fragment_address <= interconnect_read_aggregated_cmd_payload_fragment_address; + interconnect_read_aggregated_cmd_rData_fragment_length <= interconnect_read_aggregated_cmd_payload_fragment_length; + interconnect_read_aggregated_cmd_rData_fragment_context <= interconnect_read_aggregated_cmd_payload_fragment_context; + end + if(readLogic_adapter_ar_ready) begin + readLogic_adapter_ar_rData_addr <= readLogic_adapter_ar_payload_addr; + readLogic_adapter_ar_rData_region <= readLogic_adapter_ar_payload_region; + readLogic_adapter_ar_rData_len <= readLogic_adapter_ar_payload_len; + readLogic_adapter_ar_rData_size <= readLogic_adapter_ar_payload_size; + readLogic_adapter_ar_rData_burst <= readLogic_adapter_ar_payload_burst; + readLogic_adapter_ar_rData_lock <= readLogic_adapter_ar_payload_lock; + readLogic_adapter_ar_rData_cache <= readLogic_adapter_ar_payload_cache; + readLogic_adapter_ar_rData_qos <= readLogic_adapter_ar_payload_qos; + readLogic_adapter_ar_rData_prot <= readLogic_adapter_ar_payload_prot; + end + if(read_rready) begin + read_r_rData_data <= read_rdata; + read_r_rData_resp <= read_rresp; + read_r_rData_last <= read_rlast; + end + if(read_r_s2mPipe_ready) begin + read_r_s2mPipe_rData_data <= read_r_s2mPipe_payload_data; + read_r_s2mPipe_rData_resp <= read_r_s2mPipe_payload_resp; + read_r_s2mPipe_rData_last <= read_r_s2mPipe_payload_last; + end + if(interconnect_write_aggregated_cmd_ready) begin + interconnect_write_aggregated_cmd_rData_last <= interconnect_write_aggregated_cmd_payload_last; + interconnect_write_aggregated_cmd_rData_fragment_source <= interconnect_write_aggregated_cmd_payload_fragment_source; + interconnect_write_aggregated_cmd_rData_fragment_opcode <= interconnect_write_aggregated_cmd_payload_fragment_opcode; + interconnect_write_aggregated_cmd_rData_fragment_address <= interconnect_write_aggregated_cmd_payload_fragment_address; + interconnect_write_aggregated_cmd_rData_fragment_length <= interconnect_write_aggregated_cmd_payload_fragment_length; + interconnect_write_aggregated_cmd_rData_fragment_data <= interconnect_write_aggregated_cmd_payload_fragment_data; + interconnect_write_aggregated_cmd_rData_fragment_mask <= interconnect_write_aggregated_cmd_payload_fragment_mask; + interconnect_write_aggregated_cmd_rData_fragment_context <= interconnect_write_aggregated_cmd_payload_fragment_context; + end + if(writeLogic_adapter_aw_ready) begin + writeLogic_adapter_aw_rData_addr <= writeLogic_adapter_aw_payload_addr; + writeLogic_adapter_aw_rData_region <= writeLogic_adapter_aw_payload_region; + writeLogic_adapter_aw_rData_len <= writeLogic_adapter_aw_payload_len; + writeLogic_adapter_aw_rData_size <= writeLogic_adapter_aw_payload_size; + writeLogic_adapter_aw_rData_burst <= writeLogic_adapter_aw_payload_burst; + writeLogic_adapter_aw_rData_lock <= writeLogic_adapter_aw_payload_lock; + writeLogic_adapter_aw_rData_cache <= writeLogic_adapter_aw_payload_cache; + writeLogic_adapter_aw_rData_qos <= writeLogic_adapter_aw_payload_qos; + writeLogic_adapter_aw_rData_prot <= writeLogic_adapter_aw_payload_prot; + end + if(writeLogic_adapter_w_ready) begin + writeLogic_adapter_w_rData_data <= writeLogic_adapter_w_payload_data; + writeLogic_adapter_w_rData_strb <= writeLogic_adapter_w_payload_strb; + writeLogic_adapter_w_rData_last <= writeLogic_adapter_w_payload_last; + end + if(writeLogic_adapter_w_s2mPipe_ready) begin + writeLogic_adapter_w_s2mPipe_rData_data <= writeLogic_adapter_w_s2mPipe_payload_data; + writeLogic_adapter_w_s2mPipe_rData_strb <= writeLogic_adapter_w_s2mPipe_payload_strb; + writeLogic_adapter_w_s2mPipe_rData_last <= writeLogic_adapter_w_s2mPipe_payload_last; + end + if(write_bready) begin + write_b_rData_resp <= write_bresp; + end + if(io_pop_rValidN) begin + io_pop_rData_data <= inputsAdapter_0_crossclock_fifo_io_pop_payload_data; + io_pop_rData_mask <= inputsAdapter_0_crossclock_fifo_io_pop_payload_mask; + io_pop_rData_sink <= inputsAdapter_0_crossclock_fifo_io_pop_payload_sink; + io_pop_rData_last <= inputsAdapter_0_crossclock_fifo_io_pop_payload_last; + end + if(io_pop_s2mPipe_ready) begin + io_pop_s2mPipe_rData_data <= io_pop_s2mPipe_payload_data; + io_pop_s2mPipe_rData_mask <= io_pop_s2mPipe_payload_mask; + io_pop_s2mPipe_rData_sink <= io_pop_s2mPipe_payload_sink; + io_pop_s2mPipe_rData_last <= io_pop_s2mPipe_payload_last; + end + if(io_outputs_0_rValidN) begin + io_outputs_0_rData_data <= core_io_outputs_0_payload_data; + io_outputs_0_rData_mask <= core_io_outputs_0_payload_mask; + io_outputs_0_rData_sink <= core_io_outputs_0_payload_sink; + io_outputs_0_rData_last <= core_io_outputs_0_payload_last; + end + if(io_outputs_0_s2mPipe_ready) begin + io_outputs_0_s2mPipe_rData_data <= io_outputs_0_s2mPipe_payload_data; + io_outputs_0_s2mPipe_rData_mask <= io_outputs_0_s2mPipe_payload_mask; + io_outputs_0_s2mPipe_rData_sink <= io_outputs_0_s2mPipe_payload_sink; + io_outputs_0_s2mPipe_rData_last <= io_outputs_0_s2mPipe_payload_last; + end + end + + +endmodule + +module EfxDMA_BmbArbiter_1 ( + input wire io_inputs_0_cmd_valid, + output wire io_inputs_0_cmd_ready, + input wire io_inputs_0_cmd_payload_last, + input wire [0:0] io_inputs_0_cmd_payload_fragment_opcode, + input wire [31:0] io_inputs_0_cmd_payload_fragment_address, + input wire [1:0] io_inputs_0_cmd_payload_fragment_length, + input wire [127:0] io_inputs_0_cmd_payload_fragment_data, + input wire [15:0] io_inputs_0_cmd_payload_fragment_mask, + input wire [0:0] io_inputs_0_cmd_payload_fragment_context, + output wire io_inputs_0_rsp_valid, + input wire io_inputs_0_rsp_ready, + output wire io_inputs_0_rsp_payload_last, + output wire [0:0] io_inputs_0_rsp_payload_fragment_opcode, + output wire [0:0] io_inputs_0_rsp_payload_fragment_context, + input wire io_inputs_1_cmd_valid, + output wire io_inputs_1_cmd_ready, + input wire io_inputs_1_cmd_payload_last, + input wire [0:0] io_inputs_1_cmd_payload_fragment_opcode, + input wire [31:0] io_inputs_1_cmd_payload_fragment_address, + input wire [11:0] io_inputs_1_cmd_payload_fragment_length, + input wire [127:0] io_inputs_1_cmd_payload_fragment_data, + input wire [15:0] io_inputs_1_cmd_payload_fragment_mask, + input wire [12:0] io_inputs_1_cmd_payload_fragment_context, + output wire io_inputs_1_rsp_valid, + input wire io_inputs_1_rsp_ready, + output wire io_inputs_1_rsp_payload_last, + output wire [0:0] io_inputs_1_rsp_payload_fragment_opcode, + output wire [12:0] io_inputs_1_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_source, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + output wire [127:0] io_output_cmd_payload_fragment_data, + output wire [15:0] io_output_cmd_payload_fragment_mask, + output wire [12:0] io_output_cmd_payload_fragment_context, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_source, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [12:0] io_output_rsp_payload_fragment_context, + input wire clk, + input wire reset +); + + wire [11:0] memory_arbiter_io_inputs_0_payload_fragment_length; + wire [12:0] memory_arbiter_io_inputs_0_payload_fragment_context; + wire memory_arbiter_io_inputs_0_ready; + wire memory_arbiter_io_inputs_1_ready; + wire memory_arbiter_io_output_valid; + wire memory_arbiter_io_output_payload_last; + wire [0:0] memory_arbiter_io_output_payload_fragment_source; + wire [0:0] memory_arbiter_io_output_payload_fragment_opcode; + wire [31:0] memory_arbiter_io_output_payload_fragment_address; + wire [11:0] memory_arbiter_io_output_payload_fragment_length; + wire [127:0] memory_arbiter_io_output_payload_fragment_data; + wire [15:0] memory_arbiter_io_output_payload_fragment_mask; + wire [12:0] memory_arbiter_io_output_payload_fragment_context; + wire [0:0] memory_arbiter_io_chosen; + wire [1:0] memory_arbiter_io_chosenOH; + wire [1:0] _zz_io_output_cmd_payload_fragment_source; + reg _zz_io_output_rsp_ready; + wire [0:0] memory_rspSel; + + assign _zz_io_output_cmd_payload_fragment_source = {memory_arbiter_io_output_payload_fragment_source,memory_arbiter_io_chosen}; + EfxDMA_StreamArbiter_1 memory_arbiter ( + .io_inputs_0_valid (io_inputs_0_cmd_valid ), //i + .io_inputs_0_ready (memory_arbiter_io_inputs_0_ready ), //o + .io_inputs_0_payload_last (io_inputs_0_cmd_payload_last ), //i + .io_inputs_0_payload_fragment_source (1'b0 ), //i + .io_inputs_0_payload_fragment_opcode (io_inputs_0_cmd_payload_fragment_opcode ), //i + .io_inputs_0_payload_fragment_address (io_inputs_0_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_0_payload_fragment_length (memory_arbiter_io_inputs_0_payload_fragment_length[11:0] ), //i + .io_inputs_0_payload_fragment_data (io_inputs_0_cmd_payload_fragment_data[127:0] ), //i + .io_inputs_0_payload_fragment_mask (io_inputs_0_cmd_payload_fragment_mask[15:0] ), //i + .io_inputs_0_payload_fragment_context (memory_arbiter_io_inputs_0_payload_fragment_context[12:0]), //i + .io_inputs_1_valid (io_inputs_1_cmd_valid ), //i + .io_inputs_1_ready (memory_arbiter_io_inputs_1_ready ), //o + .io_inputs_1_payload_last (io_inputs_1_cmd_payload_last ), //i + .io_inputs_1_payload_fragment_source (1'b0 ), //i + .io_inputs_1_payload_fragment_opcode (io_inputs_1_cmd_payload_fragment_opcode ), //i + .io_inputs_1_payload_fragment_address (io_inputs_1_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_1_payload_fragment_length (io_inputs_1_cmd_payload_fragment_length[11:0] ), //i + .io_inputs_1_payload_fragment_data (io_inputs_1_cmd_payload_fragment_data[127:0] ), //i + .io_inputs_1_payload_fragment_mask (io_inputs_1_cmd_payload_fragment_mask[15:0] ), //i + .io_inputs_1_payload_fragment_context (io_inputs_1_cmd_payload_fragment_context[12:0] ), //i + .io_output_valid (memory_arbiter_io_output_valid ), //o + .io_output_ready (io_output_cmd_ready ), //i + .io_output_payload_last (memory_arbiter_io_output_payload_last ), //o + .io_output_payload_fragment_source (memory_arbiter_io_output_payload_fragment_source ), //o + .io_output_payload_fragment_opcode (memory_arbiter_io_output_payload_fragment_opcode ), //o + .io_output_payload_fragment_address (memory_arbiter_io_output_payload_fragment_address[31:0] ), //o + .io_output_payload_fragment_length (memory_arbiter_io_output_payload_fragment_length[11:0] ), //o + .io_output_payload_fragment_data (memory_arbiter_io_output_payload_fragment_data[127:0] ), //o + .io_output_payload_fragment_mask (memory_arbiter_io_output_payload_fragment_mask[15:0] ), //o + .io_output_payload_fragment_context (memory_arbiter_io_output_payload_fragment_context[12:0] ), //o + .io_chosen (memory_arbiter_io_chosen ), //o + .io_chosenOH (memory_arbiter_io_chosenOH[1:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(memory_rspSel) + 1'b0 : _zz_io_output_rsp_ready = io_inputs_0_rsp_ready; + default : _zz_io_output_rsp_ready = io_inputs_1_rsp_ready; + endcase + end + + assign io_inputs_0_cmd_ready = memory_arbiter_io_inputs_0_ready; + assign memory_arbiter_io_inputs_0_payload_fragment_length = {10'd0, io_inputs_0_cmd_payload_fragment_length}; + assign memory_arbiter_io_inputs_0_payload_fragment_context = {12'd0, io_inputs_0_cmd_payload_fragment_context}; + assign io_inputs_1_cmd_ready = memory_arbiter_io_inputs_1_ready; + assign io_output_cmd_valid = memory_arbiter_io_output_valid; + assign io_output_cmd_payload_last = memory_arbiter_io_output_payload_last; + assign io_output_cmd_payload_fragment_opcode = memory_arbiter_io_output_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = memory_arbiter_io_output_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = memory_arbiter_io_output_payload_fragment_length; + assign io_output_cmd_payload_fragment_data = memory_arbiter_io_output_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = memory_arbiter_io_output_payload_fragment_mask; + assign io_output_cmd_payload_fragment_context = memory_arbiter_io_output_payload_fragment_context; + assign io_output_cmd_payload_fragment_source = _zz_io_output_cmd_payload_fragment_source[0:0]; + assign memory_rspSel = io_output_rsp_payload_fragment_source[0 : 0]; + assign io_inputs_0_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b0)); + assign io_inputs_0_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_0_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_0_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context[0:0]; + assign io_inputs_1_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b1)); + assign io_inputs_1_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_1_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_1_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; + assign io_output_rsp_ready = _zz_io_output_rsp_ready; + +endmodule + +module EfxDMA_BmbArbiter ( + input wire io_inputs_0_cmd_valid, + output wire io_inputs_0_cmd_ready, + input wire io_inputs_0_cmd_payload_last, + input wire [0:0] io_inputs_0_cmd_payload_fragment_opcode, + input wire [31:0] io_inputs_0_cmd_payload_fragment_address, + input wire [4:0] io_inputs_0_cmd_payload_fragment_length, + input wire [0:0] io_inputs_0_cmd_payload_fragment_context, + output wire io_inputs_0_rsp_valid, + input wire io_inputs_0_rsp_ready, + output wire io_inputs_0_rsp_payload_last, + output wire [0:0] io_inputs_0_rsp_payload_fragment_opcode, + output wire [127:0] io_inputs_0_rsp_payload_fragment_data, + output wire [0:0] io_inputs_0_rsp_payload_fragment_context, + input wire io_inputs_1_cmd_valid, + output wire io_inputs_1_cmd_ready, + input wire io_inputs_1_cmd_payload_last, + input wire [0:0] io_inputs_1_cmd_payload_fragment_opcode, + input wire [31:0] io_inputs_1_cmd_payload_fragment_address, + input wire [11:0] io_inputs_1_cmd_payload_fragment_length, + input wire [20:0] io_inputs_1_cmd_payload_fragment_context, + output wire io_inputs_1_rsp_valid, + input wire io_inputs_1_rsp_ready, + output wire io_inputs_1_rsp_payload_last, + output wire [0:0] io_inputs_1_rsp_payload_fragment_opcode, + output wire [127:0] io_inputs_1_rsp_payload_fragment_data, + output wire [20:0] io_inputs_1_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_source, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + output wire [20:0] io_output_cmd_payload_fragment_context, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_source, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [127:0] io_output_rsp_payload_fragment_data, + input wire [20:0] io_output_rsp_payload_fragment_context, + input wire clk, + input wire reset +); + + wire [11:0] memory_arbiter_io_inputs_0_payload_fragment_length; + wire [20:0] memory_arbiter_io_inputs_0_payload_fragment_context; + wire memory_arbiter_io_inputs_0_ready; + wire memory_arbiter_io_inputs_1_ready; + wire memory_arbiter_io_output_valid; + wire memory_arbiter_io_output_payload_last; + wire [0:0] memory_arbiter_io_output_payload_fragment_source; + wire [0:0] memory_arbiter_io_output_payload_fragment_opcode; + wire [31:0] memory_arbiter_io_output_payload_fragment_address; + wire [11:0] memory_arbiter_io_output_payload_fragment_length; + wire [20:0] memory_arbiter_io_output_payload_fragment_context; + wire [0:0] memory_arbiter_io_chosen; + wire [1:0] memory_arbiter_io_chosenOH; + wire [1:0] _zz_io_output_cmd_payload_fragment_source; + reg _zz_io_output_rsp_ready; + wire [0:0] memory_rspSel; + + assign _zz_io_output_cmd_payload_fragment_source = {memory_arbiter_io_output_payload_fragment_source,memory_arbiter_io_chosen}; + EfxDMA_StreamArbiter memory_arbiter ( + .io_inputs_0_valid (io_inputs_0_cmd_valid ), //i + .io_inputs_0_ready (memory_arbiter_io_inputs_0_ready ), //o + .io_inputs_0_payload_last (io_inputs_0_cmd_payload_last ), //i + .io_inputs_0_payload_fragment_source (1'b0 ), //i + .io_inputs_0_payload_fragment_opcode (io_inputs_0_cmd_payload_fragment_opcode ), //i + .io_inputs_0_payload_fragment_address (io_inputs_0_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_0_payload_fragment_length (memory_arbiter_io_inputs_0_payload_fragment_length[11:0] ), //i + .io_inputs_0_payload_fragment_context (memory_arbiter_io_inputs_0_payload_fragment_context[20:0]), //i + .io_inputs_1_valid (io_inputs_1_cmd_valid ), //i + .io_inputs_1_ready (memory_arbiter_io_inputs_1_ready ), //o + .io_inputs_1_payload_last (io_inputs_1_cmd_payload_last ), //i + .io_inputs_1_payload_fragment_source (1'b0 ), //i + .io_inputs_1_payload_fragment_opcode (io_inputs_1_cmd_payload_fragment_opcode ), //i + .io_inputs_1_payload_fragment_address (io_inputs_1_cmd_payload_fragment_address[31:0] ), //i + .io_inputs_1_payload_fragment_length (io_inputs_1_cmd_payload_fragment_length[11:0] ), //i + .io_inputs_1_payload_fragment_context (io_inputs_1_cmd_payload_fragment_context[20:0] ), //i + .io_output_valid (memory_arbiter_io_output_valid ), //o + .io_output_ready (io_output_cmd_ready ), //i + .io_output_payload_last (memory_arbiter_io_output_payload_last ), //o + .io_output_payload_fragment_source (memory_arbiter_io_output_payload_fragment_source ), //o + .io_output_payload_fragment_opcode (memory_arbiter_io_output_payload_fragment_opcode ), //o + .io_output_payload_fragment_address (memory_arbiter_io_output_payload_fragment_address[31:0] ), //o + .io_output_payload_fragment_length (memory_arbiter_io_output_payload_fragment_length[11:0] ), //o + .io_output_payload_fragment_context (memory_arbiter_io_output_payload_fragment_context[20:0] ), //o + .io_chosen (memory_arbiter_io_chosen ), //o + .io_chosenOH (memory_arbiter_io_chosenOH[1:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(memory_rspSel) + 1'b0 : _zz_io_output_rsp_ready = io_inputs_0_rsp_ready; + default : _zz_io_output_rsp_ready = io_inputs_1_rsp_ready; + endcase + end + + assign io_inputs_0_cmd_ready = memory_arbiter_io_inputs_0_ready; + assign memory_arbiter_io_inputs_0_payload_fragment_length = {7'd0, io_inputs_0_cmd_payload_fragment_length}; + assign memory_arbiter_io_inputs_0_payload_fragment_context = {20'd0, io_inputs_0_cmd_payload_fragment_context}; + assign io_inputs_1_cmd_ready = memory_arbiter_io_inputs_1_ready; + assign io_output_cmd_valid = memory_arbiter_io_output_valid; + assign io_output_cmd_payload_last = memory_arbiter_io_output_payload_last; + assign io_output_cmd_payload_fragment_opcode = memory_arbiter_io_output_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = memory_arbiter_io_output_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = memory_arbiter_io_output_payload_fragment_length; + assign io_output_cmd_payload_fragment_context = memory_arbiter_io_output_payload_fragment_context; + assign io_output_cmd_payload_fragment_source = _zz_io_output_cmd_payload_fragment_source[0:0]; + assign memory_rspSel = io_output_rsp_payload_fragment_source[0 : 0]; + assign io_inputs_0_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b0)); + assign io_inputs_0_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_0_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_0_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_inputs_0_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context[0:0]; + assign io_inputs_1_rsp_valid = (io_output_rsp_valid && (memory_rspSel == 1'b1)); + assign io_inputs_1_rsp_payload_last = io_output_rsp_payload_last; + assign io_inputs_1_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_inputs_1_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_inputs_1_rsp_payload_fragment_context = io_output_rsp_payload_fragment_context; + assign io_output_rsp_ready = _zz_io_output_rsp_ready; + +endmodule + +module EfxDMA_BsbDownSizerSparse ( + input wire io_input_valid, + output wire io_input_ready, + input wire [63:0] io_input_payload_data, + input wire [7:0] io_input_payload_mask, + input wire [3:0] io_input_payload_sink, + input wire io_input_payload_last, + output wire io_output_valid, + input wire io_output_ready, + output wire [7:0] io_output_payload_data, + output wire [0:0] io_output_payload_mask, + output wire [3:0] io_output_payload_sink, + output wire io_output_payload_last, + input wire dat1_o_clk, + input wire dat1_o_reset +); + + reg [7:0] _zz_io_output_payload_data; + reg [0:0] _zz_io_output_payload_mask; + reg [2:0] counter; + wire end_1; + wire io_output_fire; + + always @(*) begin + case(counter) + 3'b000 : begin + _zz_io_output_payload_data = io_input_payload_data[7 : 0]; + _zz_io_output_payload_mask = io_input_payload_mask[0 : 0]; + end + 3'b001 : begin + _zz_io_output_payload_data = io_input_payload_data[15 : 8]; + _zz_io_output_payload_mask = io_input_payload_mask[1 : 1]; + end + 3'b010 : begin + _zz_io_output_payload_data = io_input_payload_data[23 : 16]; + _zz_io_output_payload_mask = io_input_payload_mask[2 : 2]; + end + 3'b011 : begin + _zz_io_output_payload_data = io_input_payload_data[31 : 24]; + _zz_io_output_payload_mask = io_input_payload_mask[3 : 3]; + end + 3'b100 : begin + _zz_io_output_payload_data = io_input_payload_data[39 : 32]; + _zz_io_output_payload_mask = io_input_payload_mask[4 : 4]; + end + 3'b101 : begin + _zz_io_output_payload_data = io_input_payload_data[47 : 40]; + _zz_io_output_payload_mask = io_input_payload_mask[5 : 5]; + end + 3'b110 : begin + _zz_io_output_payload_data = io_input_payload_data[55 : 48]; + _zz_io_output_payload_mask = io_input_payload_mask[6 : 6]; + end + default : begin + _zz_io_output_payload_data = io_input_payload_data[63 : 56]; + _zz_io_output_payload_mask = io_input_payload_mask[7 : 7]; + end + endcase + end + + assign end_1 = (counter == 3'b111); + assign io_output_fire = (io_output_valid && io_output_ready); + assign io_input_ready = (io_output_ready && end_1); + assign io_output_valid = io_input_valid; + assign io_output_payload_data = _zz_io_output_payload_data; + assign io_output_payload_mask = _zz_io_output_payload_mask; + assign io_output_payload_sink = io_input_payload_sink; + assign io_output_payload_last = (io_input_payload_last && end_1); + always @(posedge dat1_o_clk) begin + if(dat1_o_reset) begin + counter <= 3'b000; + end else begin + if(io_output_fire) begin + counter <= (counter + 3'b001); + end + end + end + + +endmodule + +module EfxDMA_StreamFifoCC_1 ( + input wire io_push_valid, + output wire io_push_ready, + input wire [63:0] io_push_payload_data, + input wire [7:0] io_push_payload_mask, + input wire [3:0] io_push_payload_sink, + input wire io_push_payload_last, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [63:0] io_pop_payload_data, + output wire [7:0] io_pop_payload_mask, + output wire [3:0] io_pop_payload_sink, + output wire io_pop_payload_last, + output wire [4:0] io_pushOccupancy, + output wire [4:0] io_popOccupancy, + input wire clk, + input wire reset, + input wire dat1_o_clk, + input wire dat1_o_reset +); + + reg [76:0] ram_spinal_port1; + wire [4:0] popToPushGray_buffercc_io_dataOut; + wire [4:0] pushToPopGray_buffercc_io_dataOut; + wire [4:0] _zz_pushCC_pushPtrGray; + wire [3:0] _zz_ram_port; + wire [76:0] _zz_ram_port_1; + wire [4:0] _zz_popCC_popPtrGray; + reg _zz_1; + wire [4:0] popToPushGray; + wire [4:0] pushToPopGray; + reg [4:0] pushCC_pushPtr; + wire [4:0] pushCC_pushPtrPlus; + wire io_push_fire; + reg [4:0] pushCC_pushPtrGray; + wire [4:0] pushCC_popPtrGray; + wire pushCC_full; + wire _zz_io_pushOccupancy; + wire _zz_io_pushOccupancy_1; + wire _zz_io_pushOccupancy_2; + wire _zz_io_pushOccupancy_3; + reg [4:0] popCC_popPtr; + (* keep , syn_keep *) wire [4:0] popCC_popPtrPlus /* synthesis syn_keep = 1 */ ; + wire [4:0] popCC_popPtrGray; + wire [4:0] popCC_pushPtrGray; + wire popCC_addressGen_valid; + reg popCC_addressGen_ready; + wire [3:0] popCC_addressGen_payload; + wire popCC_empty; + wire popCC_addressGen_fire; + wire popCC_readArbitation_valid; + wire popCC_readArbitation_ready; + wire [3:0] popCC_readArbitation_payload; + reg popCC_addressGen_rValid; + reg [3:0] popCC_addressGen_rData; + wire when_Stream_l375; + wire popCC_readPort_cmd_valid; + wire [3:0] popCC_readPort_cmd_payload; + wire [63:0] popCC_readPort_rsp_data; + wire [7:0] popCC_readPort_rsp_mask; + wire [3:0] popCC_readPort_rsp_sink; + wire popCC_readPort_rsp_last; + wire [76:0] _zz_popCC_readPort_rsp_data; + wire popCC_readArbitation_translated_valid; + wire popCC_readArbitation_translated_ready; + wire [63:0] popCC_readArbitation_translated_payload_data; + wire [7:0] popCC_readArbitation_translated_payload_mask; + wire [3:0] popCC_readArbitation_translated_payload_sink; + wire popCC_readArbitation_translated_payload_last; + wire popCC_readArbitation_fire; + reg [4:0] popCC_ptrToPush; + reg [4:0] popCC_ptrToOccupancy; + wire _zz_io_popOccupancy; + wire _zz_io_popOccupancy_1; + wire _zz_io_popOccupancy_2; + wire _zz_io_popOccupancy_3; + reg [76:0] ram [0:15]; + + assign _zz_pushCC_pushPtrGray = (pushCC_pushPtrPlus >>> 1'b1); + assign _zz_ram_port = pushCC_pushPtr[3:0]; + assign _zz_popCC_popPtrGray = (popCC_popPtr >>> 1'b1); + assign _zz_ram_port_1 = {io_push_payload_last,{io_push_payload_sink,{io_push_payload_mask,io_push_payload_data}}}; + always @(posedge clk) begin + if(_zz_1) begin + ram[_zz_ram_port] <= _zz_ram_port_1; + end + end + + always @(posedge dat1_o_clk) begin + if(popCC_readPort_cmd_valid) begin + ram_spinal_port1 <= ram[popCC_readPort_cmd_payload]; + end + end + + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_3 popToPushGray_buffercc ( + .io_dataIn (popToPushGray[4:0] ), //i + .io_dataOut (popToPushGray_buffercc_io_dataOut[4:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_5 pushToPopGray_buffercc ( + .io_dataIn (pushToPopGray[4:0] ), //i + .io_dataOut (pushToPopGray_buffercc_io_dataOut[4:0]), //o + .dat1_o_clk (dat1_o_clk ), //i + .dat1_o_reset (dat1_o_reset ) //i + ); + always @(*) begin + _zz_1 = 1'b0; + if(io_push_fire) begin + _zz_1 = 1'b1; + end + end + + assign pushCC_pushPtrPlus = (pushCC_pushPtr + 5'h01); + assign io_push_fire = (io_push_valid && io_push_ready); + assign pushCC_popPtrGray = popToPushGray_buffercc_io_dataOut; + assign pushCC_full = ((pushCC_pushPtrGray[4 : 3] == (~ pushCC_popPtrGray[4 : 3])) && (pushCC_pushPtrGray[2 : 0] == pushCC_popPtrGray[2 : 0])); + assign io_push_ready = (! pushCC_full); + assign _zz_io_pushOccupancy = (pushCC_popPtrGray[1] ^ _zz_io_pushOccupancy_1); + assign _zz_io_pushOccupancy_1 = (pushCC_popPtrGray[2] ^ _zz_io_pushOccupancy_2); + assign _zz_io_pushOccupancy_2 = (pushCC_popPtrGray[3] ^ _zz_io_pushOccupancy_3); + assign _zz_io_pushOccupancy_3 = pushCC_popPtrGray[4]; + assign io_pushOccupancy = (pushCC_pushPtr - {_zz_io_pushOccupancy_3,{_zz_io_pushOccupancy_2,{_zz_io_pushOccupancy_1,{_zz_io_pushOccupancy,(pushCC_popPtrGray[0] ^ _zz_io_pushOccupancy)}}}}); + assign popCC_popPtrPlus = (popCC_popPtr + 5'h01); + assign popCC_popPtrGray = (_zz_popCC_popPtrGray ^ popCC_popPtr); + assign popCC_pushPtrGray = pushToPopGray_buffercc_io_dataOut; + assign popCC_empty = (popCC_popPtrGray == popCC_pushPtrGray); + assign popCC_addressGen_valid = (! popCC_empty); + assign popCC_addressGen_payload = popCC_popPtr[3:0]; + assign popCC_addressGen_fire = (popCC_addressGen_valid && popCC_addressGen_ready); + always @(*) begin + popCC_addressGen_ready = popCC_readArbitation_ready; + if(when_Stream_l375) begin + popCC_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! popCC_readArbitation_valid); + assign popCC_readArbitation_valid = popCC_addressGen_rValid; + assign popCC_readArbitation_payload = popCC_addressGen_rData; + assign _zz_popCC_readPort_rsp_data = ram_spinal_port1; + assign popCC_readPort_rsp_data = _zz_popCC_readPort_rsp_data[63 : 0]; + assign popCC_readPort_rsp_mask = _zz_popCC_readPort_rsp_data[71 : 64]; + assign popCC_readPort_rsp_sink = _zz_popCC_readPort_rsp_data[75 : 72]; + assign popCC_readPort_rsp_last = _zz_popCC_readPort_rsp_data[76]; + assign popCC_readPort_cmd_valid = popCC_addressGen_fire; + assign popCC_readPort_cmd_payload = popCC_addressGen_payload; + assign popCC_readArbitation_translated_valid = popCC_readArbitation_valid; + assign popCC_readArbitation_ready = popCC_readArbitation_translated_ready; + assign popCC_readArbitation_translated_payload_data = popCC_readPort_rsp_data; + assign popCC_readArbitation_translated_payload_mask = popCC_readPort_rsp_mask; + assign popCC_readArbitation_translated_payload_sink = popCC_readPort_rsp_sink; + assign popCC_readArbitation_translated_payload_last = popCC_readPort_rsp_last; + assign io_pop_valid = popCC_readArbitation_translated_valid; + assign popCC_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_data = popCC_readArbitation_translated_payload_data; + assign io_pop_payload_mask = popCC_readArbitation_translated_payload_mask; + assign io_pop_payload_sink = popCC_readArbitation_translated_payload_sink; + assign io_pop_payload_last = popCC_readArbitation_translated_payload_last; + assign popCC_readArbitation_fire = (popCC_readArbitation_valid && popCC_readArbitation_ready); + assign _zz_io_popOccupancy = (popCC_pushPtrGray[1] ^ _zz_io_popOccupancy_1); + assign _zz_io_popOccupancy_1 = (popCC_pushPtrGray[2] ^ _zz_io_popOccupancy_2); + assign _zz_io_popOccupancy_2 = (popCC_pushPtrGray[3] ^ _zz_io_popOccupancy_3); + assign _zz_io_popOccupancy_3 = popCC_pushPtrGray[4]; + assign io_popOccupancy = ({_zz_io_popOccupancy_3,{_zz_io_popOccupancy_2,{_zz_io_popOccupancy_1,{_zz_io_popOccupancy,(popCC_pushPtrGray[0] ^ _zz_io_popOccupancy)}}}} - popCC_ptrToOccupancy); + assign pushToPopGray = pushCC_pushPtrGray; + assign popToPushGray = popCC_ptrToPush; + always @(posedge clk) begin + if(reset) begin + pushCC_pushPtr <= 5'h0; + pushCC_pushPtrGray <= 5'h0; + end else begin + if(io_push_fire) begin + pushCC_pushPtrGray <= (_zz_pushCC_pushPtrGray ^ pushCC_pushPtrPlus); + end + if(io_push_fire) begin + pushCC_pushPtr <= pushCC_pushPtrPlus; + end + end + end + + always @(posedge dat1_o_clk) begin + if(dat1_o_reset) begin + popCC_popPtr <= 5'h0; + popCC_addressGen_rValid <= 1'b0; + popCC_ptrToPush <= 5'h0; + popCC_ptrToOccupancy <= 5'h0; + end else begin + if(popCC_addressGen_fire) begin + popCC_popPtr <= popCC_popPtrPlus; + end + if(popCC_addressGen_ready) begin + popCC_addressGen_rValid <= popCC_addressGen_valid; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToPush <= popCC_popPtrGray; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToOccupancy <= popCC_popPtr; + end + end + end + + always @(posedge dat1_o_clk) begin + if(popCC_addressGen_ready) begin + popCC_addressGen_rData <= popCC_addressGen_payload; + end + end + + +endmodule + +module EfxDMA_StreamFifoCC ( + input wire io_push_valid, + output wire io_push_ready, + input wire [63:0] io_push_payload_data, + input wire [7:0] io_push_payload_mask, + input wire [3:0] io_push_payload_sink, + input wire io_push_payload_last, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [63:0] io_pop_payload_data, + output wire [7:0] io_pop_payload_mask, + output wire [3:0] io_pop_payload_sink, + output wire io_pop_payload_last, + output wire [4:0] io_pushOccupancy, + output wire [4:0] io_popOccupancy, + input wire dat0_i_clk, + input wire dat0_i_reset, + input wire clk, + input wire reset +); + + reg [76:0] ram_spinal_port1; + wire [4:0] popToPushGray_buffercc_io_dataOut; + wire [4:0] pushToPopGray_buffercc_io_dataOut; + wire [4:0] _zz_pushCC_pushPtrGray; + wire [3:0] _zz_ram_port; + wire [76:0] _zz_ram_port_1; + wire [4:0] _zz_popCC_popPtrGray; + reg _zz_1; + wire [4:0] popToPushGray; + wire [4:0] pushToPopGray; + reg [4:0] pushCC_pushPtr; + wire [4:0] pushCC_pushPtrPlus; + wire io_push_fire; + reg [4:0] pushCC_pushPtrGray; + wire [4:0] pushCC_popPtrGray; + wire pushCC_full; + wire _zz_io_pushOccupancy; + wire _zz_io_pushOccupancy_1; + wire _zz_io_pushOccupancy_2; + wire _zz_io_pushOccupancy_3; + reg [4:0] popCC_popPtr; + (* keep , syn_keep *) wire [4:0] popCC_popPtrPlus /* synthesis syn_keep = 1 */ ; + wire [4:0] popCC_popPtrGray; + wire [4:0] popCC_pushPtrGray; + wire popCC_addressGen_valid; + reg popCC_addressGen_ready; + wire [3:0] popCC_addressGen_payload; + wire popCC_empty; + wire popCC_addressGen_fire; + wire popCC_readArbitation_valid; + wire popCC_readArbitation_ready; + wire [3:0] popCC_readArbitation_payload; + reg popCC_addressGen_rValid; + reg [3:0] popCC_addressGen_rData; + wire when_Stream_l375; + wire popCC_readPort_cmd_valid; + wire [3:0] popCC_readPort_cmd_payload; + wire [63:0] popCC_readPort_rsp_data; + wire [7:0] popCC_readPort_rsp_mask; + wire [3:0] popCC_readPort_rsp_sink; + wire popCC_readPort_rsp_last; + wire [76:0] _zz_popCC_readPort_rsp_data; + wire popCC_readArbitation_translated_valid; + wire popCC_readArbitation_translated_ready; + wire [63:0] popCC_readArbitation_translated_payload_data; + wire [7:0] popCC_readArbitation_translated_payload_mask; + wire [3:0] popCC_readArbitation_translated_payload_sink; + wire popCC_readArbitation_translated_payload_last; + wire popCC_readArbitation_fire; + reg [4:0] popCC_ptrToPush; + reg [4:0] popCC_ptrToOccupancy; + wire _zz_io_popOccupancy; + wire _zz_io_popOccupancy_1; + wire _zz_io_popOccupancy_2; + wire _zz_io_popOccupancy_3; + reg [76:0] ram [0:15]; + + assign _zz_pushCC_pushPtrGray = (pushCC_pushPtrPlus >>> 1'b1); + assign _zz_ram_port = pushCC_pushPtr[3:0]; + assign _zz_popCC_popPtrGray = (popCC_popPtr >>> 1'b1); + assign _zz_ram_port_1 = {io_push_payload_last,{io_push_payload_sink,{io_push_payload_mask,io_push_payload_data}}}; + always @(posedge dat0_i_clk) begin + if(_zz_1) begin + ram[_zz_ram_port] <= _zz_ram_port_1; + end + end + + always @(posedge clk) begin + if(popCC_readPort_cmd_valid) begin + ram_spinal_port1 <= ram[popCC_readPort_cmd_payload]; + end + end + + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_2 popToPushGray_buffercc ( + .io_dataIn (popToPushGray[4:0] ), //i + .io_dataOut (popToPushGray_buffercc_io_dataOut[4:0]), //o + .dat0_i_clk (dat0_i_clk ), //i + .dat0_i_reset (dat0_i_reset ) //i + ); + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_3 pushToPopGray_buffercc ( + .io_dataIn (pushToPopGray[4:0] ), //i + .io_dataOut (pushToPopGray_buffercc_io_dataOut[4:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + _zz_1 = 1'b0; + if(io_push_fire) begin + _zz_1 = 1'b1; + end + end + + assign pushCC_pushPtrPlus = (pushCC_pushPtr + 5'h01); + assign io_push_fire = (io_push_valid && io_push_ready); + assign pushCC_popPtrGray = popToPushGray_buffercc_io_dataOut; + assign pushCC_full = ((pushCC_pushPtrGray[4 : 3] == (~ pushCC_popPtrGray[4 : 3])) && (pushCC_pushPtrGray[2 : 0] == pushCC_popPtrGray[2 : 0])); + assign io_push_ready = (! pushCC_full); + assign _zz_io_pushOccupancy = (pushCC_popPtrGray[1] ^ _zz_io_pushOccupancy_1); + assign _zz_io_pushOccupancy_1 = (pushCC_popPtrGray[2] ^ _zz_io_pushOccupancy_2); + assign _zz_io_pushOccupancy_2 = (pushCC_popPtrGray[3] ^ _zz_io_pushOccupancy_3); + assign _zz_io_pushOccupancy_3 = pushCC_popPtrGray[4]; + assign io_pushOccupancy = (pushCC_pushPtr - {_zz_io_pushOccupancy_3,{_zz_io_pushOccupancy_2,{_zz_io_pushOccupancy_1,{_zz_io_pushOccupancy,(pushCC_popPtrGray[0] ^ _zz_io_pushOccupancy)}}}}); + assign popCC_popPtrPlus = (popCC_popPtr + 5'h01); + assign popCC_popPtrGray = (_zz_popCC_popPtrGray ^ popCC_popPtr); + assign popCC_pushPtrGray = pushToPopGray_buffercc_io_dataOut; + assign popCC_empty = (popCC_popPtrGray == popCC_pushPtrGray); + assign popCC_addressGen_valid = (! popCC_empty); + assign popCC_addressGen_payload = popCC_popPtr[3:0]; + assign popCC_addressGen_fire = (popCC_addressGen_valid && popCC_addressGen_ready); + always @(*) begin + popCC_addressGen_ready = popCC_readArbitation_ready; + if(when_Stream_l375) begin + popCC_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! popCC_readArbitation_valid); + assign popCC_readArbitation_valid = popCC_addressGen_rValid; + assign popCC_readArbitation_payload = popCC_addressGen_rData; + assign _zz_popCC_readPort_rsp_data = ram_spinal_port1; + assign popCC_readPort_rsp_data = _zz_popCC_readPort_rsp_data[63 : 0]; + assign popCC_readPort_rsp_mask = _zz_popCC_readPort_rsp_data[71 : 64]; + assign popCC_readPort_rsp_sink = _zz_popCC_readPort_rsp_data[75 : 72]; + assign popCC_readPort_rsp_last = _zz_popCC_readPort_rsp_data[76]; + assign popCC_readPort_cmd_valid = popCC_addressGen_fire; + assign popCC_readPort_cmd_payload = popCC_addressGen_payload; + assign popCC_readArbitation_translated_valid = popCC_readArbitation_valid; + assign popCC_readArbitation_ready = popCC_readArbitation_translated_ready; + assign popCC_readArbitation_translated_payload_data = popCC_readPort_rsp_data; + assign popCC_readArbitation_translated_payload_mask = popCC_readPort_rsp_mask; + assign popCC_readArbitation_translated_payload_sink = popCC_readPort_rsp_sink; + assign popCC_readArbitation_translated_payload_last = popCC_readPort_rsp_last; + assign io_pop_valid = popCC_readArbitation_translated_valid; + assign popCC_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_data = popCC_readArbitation_translated_payload_data; + assign io_pop_payload_mask = popCC_readArbitation_translated_payload_mask; + assign io_pop_payload_sink = popCC_readArbitation_translated_payload_sink; + assign io_pop_payload_last = popCC_readArbitation_translated_payload_last; + assign popCC_readArbitation_fire = (popCC_readArbitation_valid && popCC_readArbitation_ready); + assign _zz_io_popOccupancy = (popCC_pushPtrGray[1] ^ _zz_io_popOccupancy_1); + assign _zz_io_popOccupancy_1 = (popCC_pushPtrGray[2] ^ _zz_io_popOccupancy_2); + assign _zz_io_popOccupancy_2 = (popCC_pushPtrGray[3] ^ _zz_io_popOccupancy_3); + assign _zz_io_popOccupancy_3 = popCC_pushPtrGray[4]; + assign io_popOccupancy = ({_zz_io_popOccupancy_3,{_zz_io_popOccupancy_2,{_zz_io_popOccupancy_1,{_zz_io_popOccupancy,(popCC_pushPtrGray[0] ^ _zz_io_popOccupancy)}}}} - popCC_ptrToOccupancy); + assign pushToPopGray = pushCC_pushPtrGray; + assign popToPushGray = popCC_ptrToPush; + always @(posedge dat0_i_clk) begin + if(dat0_i_reset) begin + pushCC_pushPtr <= 5'h0; + pushCC_pushPtrGray <= 5'h0; + end else begin + if(io_push_fire) begin + pushCC_pushPtrGray <= (_zz_pushCC_pushPtrGray ^ pushCC_pushPtrPlus); + end + if(io_push_fire) begin + pushCC_pushPtr <= pushCC_pushPtrPlus; + end + end + end + + always @(posedge clk) begin + if(reset) begin + popCC_popPtr <= 5'h0; + popCC_addressGen_rValid <= 1'b0; + popCC_ptrToPush <= 5'h0; + popCC_ptrToOccupancy <= 5'h0; + end else begin + if(popCC_addressGen_fire) begin + popCC_popPtr <= popCC_popPtrPlus; + end + if(popCC_addressGen_ready) begin + popCC_addressGen_rValid <= popCC_addressGen_valid; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToPush <= popCC_popPtrGray; + end + if(popCC_readArbitation_fire) begin + popCC_ptrToOccupancy <= popCC_popPtr; + end + end + end + + always @(posedge clk) begin + if(popCC_addressGen_ready) begin + popCC_addressGen_rData <= popCC_addressGen_payload; + end + end + + +endmodule + +module EfxDMA_BsbUpSizerDense ( + input wire io_input_valid, + output wire io_input_ready, + input wire [7:0] io_input_payload_data, + input wire [0:0] io_input_payload_mask, + input wire [3:0] io_input_payload_sink, + input wire io_input_payload_last, + output wire io_output_valid, + input wire io_output_ready, + output wire [63:0] io_output_payload_data, + output wire [7:0] io_output_payload_mask, + output wire [3:0] io_output_payload_sink, + output wire io_output_payload_last, + input wire dat0_i_clk, + input wire dat0_i_reset +); + + reg valid; + reg [2:0] counter; + reg [63:0] buffer_data; + reg [7:0] buffer_mask; + reg [3:0] buffer_sink; + reg buffer_last; + wire full; + wire canAggregate; + wire onOutput; + wire [2:0] counterSample; + wire io_output_fire; + wire io_input_fire; + wire [7:0] _zz_1; + wire [7:0] _zz_2; + + assign full = ((counter == 3'b000) || buffer_last); + assign canAggregate = ((((valid && (! buffer_last)) && (! full)) && 1'b1) && (buffer_sink == io_input_payload_sink)); + assign counterSample = (canAggregate ? counter : 3'b000); + assign io_output_fire = (io_output_valid && io_output_ready); + assign io_input_fire = (io_input_valid && io_input_ready); + assign _zz_1 = ({7'd0,1'b1} <<< counterSample); + assign _zz_2 = ({7'd0,1'b1} <<< counterSample); + assign io_output_valid = (valid && ((valid && full) || (io_input_valid && (! canAggregate)))); + assign io_output_payload_data = buffer_data; + assign io_output_payload_mask = buffer_mask; + assign io_output_payload_sink = buffer_sink; + assign io_output_payload_last = buffer_last; + assign io_input_ready = (((! valid) || canAggregate) || io_output_ready); + always @(posedge dat0_i_clk) begin + if(dat0_i_reset) begin + valid <= 1'b0; + counter <= 3'b000; + buffer_last <= 1'b0; + buffer_mask <= 8'h0; + end else begin + if(io_output_fire) begin + valid <= 1'b0; + buffer_mask <= 8'h0; + end + if(io_input_fire) begin + valid <= 1'b1; + if(_zz_2[0]) begin + buffer_mask[0 : 0] <= io_input_payload_mask; + end + if(_zz_2[1]) begin + buffer_mask[1 : 1] <= io_input_payload_mask; + end + if(_zz_2[2]) begin + buffer_mask[2 : 2] <= io_input_payload_mask; + end + if(_zz_2[3]) begin + buffer_mask[3 : 3] <= io_input_payload_mask; + end + if(_zz_2[4]) begin + buffer_mask[4 : 4] <= io_input_payload_mask; + end + if(_zz_2[5]) begin + buffer_mask[5 : 5] <= io_input_payload_mask; + end + if(_zz_2[6]) begin + buffer_mask[6 : 6] <= io_input_payload_mask; + end + if(_zz_2[7]) begin + buffer_mask[7 : 7] <= io_input_payload_mask; + end + buffer_last <= io_input_payload_last; + counter <= (counterSample + 3'b001); + end + end + end + + always @(posedge dat0_i_clk) begin + if(io_input_fire) begin + buffer_sink <= io_input_payload_sink; + if(_zz_1[0]) begin + buffer_data[7 : 0] <= io_input_payload_data; + end + if(_zz_1[1]) begin + buffer_data[15 : 8] <= io_input_payload_data; + end + if(_zz_1[2]) begin + buffer_data[23 : 16] <= io_input_payload_data; + end + if(_zz_1[3]) begin + buffer_data[31 : 24] <= io_input_payload_data; + end + if(_zz_1[4]) begin + buffer_data[39 : 32] <= io_input_payload_data; + end + if(_zz_1[5]) begin + buffer_data[47 : 40] <= io_input_payload_data; + end + if(_zz_1[6]) begin + buffer_data[55 : 48] <= io_input_payload_data; + end + if(_zz_1[7]) begin + buffer_data[63 : 56] <= io_input_payload_data; + end + end + end + + +endmodule + +module EfxDMA_BmbToAxi4WriteOnlyBridge ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [127:0] io_input_cmd_payload_fragment_data, + input wire [15:0] io_input_cmd_payload_fragment_mask, + input wire [13:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [13:0] io_input_rsp_payload_fragment_context, + output wire io_output_aw_valid, + input wire io_output_aw_ready, + output wire [31:0] io_output_aw_payload_addr, + output wire [7:0] io_output_aw_payload_len, + output wire [2:0] io_output_aw_payload_size, + output wire [3:0] io_output_aw_payload_cache, + output wire [2:0] io_output_aw_payload_prot, + output wire io_output_w_valid, + input wire io_output_w_ready, + output wire [127:0] io_output_w_payload_data, + output wire [15:0] io_output_w_payload_strb, + output wire io_output_w_payload_last, + input wire io_output_b_valid, + output wire io_output_b_ready, + input wire [1:0] io_output_b_payload_resp, + input wire clk, + input wire reset +); + + reg contextRemover_io_output_cmd_ready; + reg [0:0] contextRemover_io_output_rsp_payload_fragment_opcode; + wire contextRemover_io_input_cmd_ready; + wire contextRemover_io_input_rsp_valid; + wire contextRemover_io_input_rsp_payload_last; + wire [0:0] contextRemover_io_input_rsp_payload_fragment_opcode; + wire [13:0] contextRemover_io_input_rsp_payload_fragment_context; + wire contextRemover_io_output_cmd_valid; + wire contextRemover_io_output_cmd_payload_last; + wire [0:0] contextRemover_io_output_cmd_payload_fragment_opcode; + wire [31:0] contextRemover_io_output_cmd_payload_fragment_address; + wire [11:0] contextRemover_io_output_cmd_payload_fragment_length; + wire [127:0] contextRemover_io_output_cmd_payload_fragment_data; + wire [15:0] contextRemover_io_output_cmd_payload_fragment_mask; + wire contextRemover_io_output_rsp_ready; + wire [8:0] _zz_io_output_aw_payload_len; + wire [12:0] _zz_io_output_aw_payload_len_1; + wire [12:0] _zz_io_output_aw_payload_len_2; + wire [3:0] _zz_io_output_aw_payload_len_3; + wire cmdFork_valid; + reg cmdFork_ready; + wire cmdFork_payload_last; + wire [0:0] cmdFork_payload_fragment_opcode; + wire [31:0] cmdFork_payload_fragment_address; + wire [11:0] cmdFork_payload_fragment_length; + wire [127:0] cmdFork_payload_fragment_data; + wire [15:0] cmdFork_payload_fragment_mask; + wire dataFork_valid; + wire dataFork_ready; + wire dataFork_payload_last; + wire [0:0] dataFork_payload_fragment_opcode; + wire [31:0] dataFork_payload_fragment_address; + wire [11:0] dataFork_payload_fragment_length; + wire [127:0] dataFork_payload_fragment_data; + wire [15:0] dataFork_payload_fragment_mask; + reg contextRemover_io_output_cmd_fork2_logic_linkEnable_0; + reg contextRemover_io_output_cmd_fork2_logic_linkEnable_1; + wire when_Stream_l1063; + wire when_Stream_l1063_1; + wire cmdFork_fire; + wire dataFork_fire; + wire contextRemover_io_output_cmd_fire; + reg contextRemover_io_output_cmd_payload_first; + wire when_Stream_l445; + reg cmdStage_valid; + wire cmdStage_ready; + wire cmdStage_payload_last; + wire [0:0] cmdStage_payload_fragment_opcode; + wire [31:0] cmdStage_payload_fragment_address; + wire [11:0] cmdStage_payload_fragment_length; + wire [127:0] cmdStage_payload_fragment_data; + wire [15:0] cmdStage_payload_fragment_mask; + wire when_BmbToAxi4Bridge_l297; + + assign _zz_io_output_aw_payload_len = _zz_io_output_aw_payload_len_1[12 : 4]; + assign _zz_io_output_aw_payload_len_1 = ({1'b0,cmdStage_payload_fragment_length} + _zz_io_output_aw_payload_len_2); + assign _zz_io_output_aw_payload_len_3 = cmdStage_payload_fragment_address[3 : 0]; + assign _zz_io_output_aw_payload_len_2 = {9'd0, _zz_io_output_aw_payload_len_3}; + EfxDMA_BmbContextRemover_1 contextRemover ( + .io_input_cmd_valid (io_input_cmd_valid ), //i + .io_input_cmd_ready (contextRemover_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (io_input_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (io_input_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (io_input_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (io_input_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_data (io_input_cmd_payload_fragment_data[127:0] ), //i + .io_input_cmd_payload_fragment_mask (io_input_cmd_payload_fragment_mask[15:0] ), //i + .io_input_cmd_payload_fragment_context (io_input_cmd_payload_fragment_context[13:0] ), //i + .io_input_rsp_valid (contextRemover_io_input_rsp_valid ), //o + .io_input_rsp_ready (io_input_rsp_ready ), //i + .io_input_rsp_payload_last (contextRemover_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (contextRemover_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_context (contextRemover_io_input_rsp_payload_fragment_context[13:0] ), //o + .io_output_cmd_valid (contextRemover_io_output_cmd_valid ), //o + .io_output_cmd_ready (contextRemover_io_output_cmd_ready ), //i + .io_output_cmd_payload_last (contextRemover_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (contextRemover_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (contextRemover_io_output_cmd_payload_fragment_address[31:0]), //o + .io_output_cmd_payload_fragment_length (contextRemover_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_cmd_payload_fragment_data (contextRemover_io_output_cmd_payload_fragment_data[127:0] ), //o + .io_output_cmd_payload_fragment_mask (contextRemover_io_output_cmd_payload_fragment_mask[15:0] ), //o + .io_output_rsp_valid (io_output_b_valid ), //i + .io_output_rsp_ready (contextRemover_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (1'b1 ), //i + .io_output_rsp_payload_fragment_opcode (contextRemover_io_output_rsp_payload_fragment_opcode ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign io_input_cmd_ready = contextRemover_io_input_cmd_ready; + assign io_input_rsp_valid = contextRemover_io_input_rsp_valid; + assign io_input_rsp_payload_last = contextRemover_io_input_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = contextRemover_io_input_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_context = contextRemover_io_input_rsp_payload_fragment_context; + always @(*) begin + contextRemover_io_output_cmd_ready = 1'b1; + if(when_Stream_l1063) begin + contextRemover_io_output_cmd_ready = 1'b0; + end + if(when_Stream_l1063_1) begin + contextRemover_io_output_cmd_ready = 1'b0; + end + end + + assign when_Stream_l1063 = ((! cmdFork_ready) && contextRemover_io_output_cmd_fork2_logic_linkEnable_0); + assign when_Stream_l1063_1 = ((! dataFork_ready) && contextRemover_io_output_cmd_fork2_logic_linkEnable_1); + assign cmdFork_valid = (contextRemover_io_output_cmd_valid && contextRemover_io_output_cmd_fork2_logic_linkEnable_0); + assign cmdFork_payload_last = contextRemover_io_output_cmd_payload_last; + assign cmdFork_payload_fragment_opcode = contextRemover_io_output_cmd_payload_fragment_opcode; + assign cmdFork_payload_fragment_address = contextRemover_io_output_cmd_payload_fragment_address; + assign cmdFork_payload_fragment_length = contextRemover_io_output_cmd_payload_fragment_length; + assign cmdFork_payload_fragment_data = contextRemover_io_output_cmd_payload_fragment_data; + assign cmdFork_payload_fragment_mask = contextRemover_io_output_cmd_payload_fragment_mask; + assign cmdFork_fire = (cmdFork_valid && cmdFork_ready); + assign dataFork_valid = (contextRemover_io_output_cmd_valid && contextRemover_io_output_cmd_fork2_logic_linkEnable_1); + assign dataFork_payload_last = contextRemover_io_output_cmd_payload_last; + assign dataFork_payload_fragment_opcode = contextRemover_io_output_cmd_payload_fragment_opcode; + assign dataFork_payload_fragment_address = contextRemover_io_output_cmd_payload_fragment_address; + assign dataFork_payload_fragment_length = contextRemover_io_output_cmd_payload_fragment_length; + assign dataFork_payload_fragment_data = contextRemover_io_output_cmd_payload_fragment_data; + assign dataFork_payload_fragment_mask = contextRemover_io_output_cmd_payload_fragment_mask; + assign dataFork_fire = (dataFork_valid && dataFork_ready); + assign contextRemover_io_output_cmd_fire = (contextRemover_io_output_cmd_valid && contextRemover_io_output_cmd_ready); + assign when_Stream_l445 = (! contextRemover_io_output_cmd_payload_first); + always @(*) begin + cmdStage_valid = cmdFork_valid; + if(when_Stream_l445) begin + cmdStage_valid = 1'b0; + end + end + + always @(*) begin + cmdFork_ready = cmdStage_ready; + if(when_Stream_l445) begin + cmdFork_ready = 1'b1; + end + end + + assign cmdStage_payload_last = cmdFork_payload_last; + assign cmdStage_payload_fragment_opcode = cmdFork_payload_fragment_opcode; + assign cmdStage_payload_fragment_address = cmdFork_payload_fragment_address; + assign cmdStage_payload_fragment_length = cmdFork_payload_fragment_length; + assign cmdStage_payload_fragment_data = cmdFork_payload_fragment_data; + assign cmdStage_payload_fragment_mask = cmdFork_payload_fragment_mask; + assign io_output_aw_valid = cmdStage_valid; + assign cmdStage_ready = io_output_aw_ready; + assign io_output_aw_payload_addr = cmdStage_payload_fragment_address; + assign io_output_aw_payload_len = _zz_io_output_aw_payload_len[7:0]; + assign io_output_aw_payload_size = 3'b100; + assign io_output_aw_payload_prot = 3'b010; + assign io_output_aw_payload_cache = 4'b1111; + assign io_output_w_valid = dataFork_valid; + assign dataFork_ready = io_output_w_ready; + assign io_output_w_payload_data = dataFork_payload_fragment_data; + assign io_output_w_payload_strb = dataFork_payload_fragment_mask; + assign io_output_w_payload_last = dataFork_payload_last; + assign io_output_b_ready = contextRemover_io_output_rsp_ready; + assign when_BmbToAxi4Bridge_l297 = (io_output_b_payload_resp == 2'b00); + always @(*) begin + if(when_BmbToAxi4Bridge_l297) begin + contextRemover_io_output_rsp_payload_fragment_opcode = 1'b0; + end else begin + contextRemover_io_output_rsp_payload_fragment_opcode = 1'b1; + end + end + + always @(posedge clk) begin + if(reset) begin + contextRemover_io_output_cmd_fork2_logic_linkEnable_0 <= 1'b1; + contextRemover_io_output_cmd_fork2_logic_linkEnable_1 <= 1'b1; + contextRemover_io_output_cmd_payload_first <= 1'b1; + end else begin + if(cmdFork_fire) begin + contextRemover_io_output_cmd_fork2_logic_linkEnable_0 <= 1'b0; + end + if(dataFork_fire) begin + contextRemover_io_output_cmd_fork2_logic_linkEnable_1 <= 1'b0; + end + if(contextRemover_io_output_cmd_ready) begin + contextRemover_io_output_cmd_fork2_logic_linkEnable_0 <= 1'b1; + contextRemover_io_output_cmd_fork2_logic_linkEnable_1 <= 1'b1; + end + if(contextRemover_io_output_cmd_fire) begin + contextRemover_io_output_cmd_payload_first <= contextRemover_io_output_cmd_payload_last; + end + end + end + + +endmodule + +module EfxDMA_BmbSourceRemover_1 ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_source, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [127:0] io_input_cmd_payload_fragment_data, + input wire [15:0] io_input_cmd_payload_fragment_mask, + input wire [12:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_source, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [12:0] io_input_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + output wire [127:0] io_output_cmd_payload_fragment_data, + output wire [15:0] io_output_cmd_payload_fragment_mask, + output wire [13:0] io_output_cmd_payload_fragment_context, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [13:0] io_output_rsp_payload_fragment_context +); + + wire [0:0] cmdContext_source; + wire [12:0] cmdContext_context; + wire [0:0] rspContext_source; + wire [12:0] rspContext_context; + wire [13:0] _zz_rspContext_source; + + assign cmdContext_source = io_input_cmd_payload_fragment_source; + assign cmdContext_context = io_input_cmd_payload_fragment_context; + assign io_output_cmd_valid = io_input_cmd_valid; + assign io_input_cmd_ready = io_output_cmd_ready; + assign io_output_cmd_payload_last = io_input_cmd_payload_last; + assign io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign io_output_cmd_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign io_output_cmd_payload_fragment_context = {cmdContext_context,cmdContext_source}; + assign _zz_rspContext_source = io_output_rsp_payload_fragment_context; + assign rspContext_source = _zz_rspContext_source[0 : 0]; + assign rspContext_context = _zz_rspContext_source[13 : 1]; + assign io_input_rsp_valid = io_output_rsp_valid; + assign io_output_rsp_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = io_output_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_source = rspContext_source; + assign io_input_rsp_payload_fragment_context = rspContext_context; + +endmodule + +module EfxDMA_BmbToAxi4ReadOnlyBridge ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [21:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [127:0] io_input_rsp_payload_fragment_data, + output wire [21:0] io_input_rsp_payload_fragment_context, + output wire io_output_ar_valid, + input wire io_output_ar_ready, + output wire [31:0] io_output_ar_payload_addr, + output wire [7:0] io_output_ar_payload_len, + output wire [2:0] io_output_ar_payload_size, + output wire [3:0] io_output_ar_payload_cache, + output wire [2:0] io_output_ar_payload_prot, + input wire io_output_r_valid, + output wire io_output_r_ready, + input wire [127:0] io_output_r_payload_data, + input wire [1:0] io_output_r_payload_resp, + input wire io_output_r_payload_last, + input wire clk, + input wire reset +); + + reg [0:0] contextRemover_io_output_rsp_payload_fragment_opcode; + wire contextRemover_io_input_cmd_ready; + wire contextRemover_io_input_rsp_valid; + wire contextRemover_io_input_rsp_payload_last; + wire [0:0] contextRemover_io_input_rsp_payload_fragment_opcode; + wire [127:0] contextRemover_io_input_rsp_payload_fragment_data; + wire [21:0] contextRemover_io_input_rsp_payload_fragment_context; + wire contextRemover_io_output_cmd_valid; + wire contextRemover_io_output_cmd_payload_last; + wire [0:0] contextRemover_io_output_cmd_payload_fragment_opcode; + wire [31:0] contextRemover_io_output_cmd_payload_fragment_address; + wire [11:0] contextRemover_io_output_cmd_payload_fragment_length; + wire contextRemover_io_output_rsp_ready; + wire [8:0] _zz_io_output_ar_payload_len; + wire [12:0] _zz_io_output_ar_payload_len_1; + wire [12:0] _zz_io_output_ar_payload_len_2; + wire [3:0] _zz_io_output_ar_payload_len_3; + wire when_BmbToAxi4Bridge_l243; + + assign _zz_io_output_ar_payload_len = _zz_io_output_ar_payload_len_1[12 : 4]; + assign _zz_io_output_ar_payload_len_1 = ({1'b0,contextRemover_io_output_cmd_payload_fragment_length} + _zz_io_output_ar_payload_len_2); + assign _zz_io_output_ar_payload_len_3 = contextRemover_io_output_cmd_payload_fragment_address[3 : 0]; + assign _zz_io_output_ar_payload_len_2 = {9'd0, _zz_io_output_ar_payload_len_3}; + EfxDMA_BmbContextRemover contextRemover ( + .io_input_cmd_valid (io_input_cmd_valid ), //i + .io_input_cmd_ready (contextRemover_io_input_cmd_ready ), //o + .io_input_cmd_payload_last (io_input_cmd_payload_last ), //i + .io_input_cmd_payload_fragment_opcode (io_input_cmd_payload_fragment_opcode ), //i + .io_input_cmd_payload_fragment_address (io_input_cmd_payload_fragment_address[31:0] ), //i + .io_input_cmd_payload_fragment_length (io_input_cmd_payload_fragment_length[11:0] ), //i + .io_input_cmd_payload_fragment_context (io_input_cmd_payload_fragment_context[21:0] ), //i + .io_input_rsp_valid (contextRemover_io_input_rsp_valid ), //o + .io_input_rsp_ready (io_input_rsp_ready ), //i + .io_input_rsp_payload_last (contextRemover_io_input_rsp_payload_last ), //o + .io_input_rsp_payload_fragment_opcode (contextRemover_io_input_rsp_payload_fragment_opcode ), //o + .io_input_rsp_payload_fragment_data (contextRemover_io_input_rsp_payload_fragment_data[127:0] ), //o + .io_input_rsp_payload_fragment_context (contextRemover_io_input_rsp_payload_fragment_context[21:0] ), //o + .io_output_cmd_valid (contextRemover_io_output_cmd_valid ), //o + .io_output_cmd_ready (io_output_ar_ready ), //i + .io_output_cmd_payload_last (contextRemover_io_output_cmd_payload_last ), //o + .io_output_cmd_payload_fragment_opcode (contextRemover_io_output_cmd_payload_fragment_opcode ), //o + .io_output_cmd_payload_fragment_address (contextRemover_io_output_cmd_payload_fragment_address[31:0]), //o + .io_output_cmd_payload_fragment_length (contextRemover_io_output_cmd_payload_fragment_length[11:0] ), //o + .io_output_rsp_valid (io_output_r_valid ), //i + .io_output_rsp_ready (contextRemover_io_output_rsp_ready ), //o + .io_output_rsp_payload_last (io_output_r_payload_last ), //i + .io_output_rsp_payload_fragment_opcode (contextRemover_io_output_rsp_payload_fragment_opcode ), //i + .io_output_rsp_payload_fragment_data (io_output_r_payload_data[127:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign io_input_cmd_ready = contextRemover_io_input_cmd_ready; + assign io_input_rsp_valid = contextRemover_io_input_rsp_valid; + assign io_input_rsp_payload_last = contextRemover_io_input_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = contextRemover_io_input_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = contextRemover_io_input_rsp_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = contextRemover_io_input_rsp_payload_fragment_context; + assign io_output_ar_valid = contextRemover_io_output_cmd_valid; + assign io_output_ar_payload_addr = contextRemover_io_output_cmd_payload_fragment_address; + assign io_output_ar_payload_len = _zz_io_output_ar_payload_len[7:0]; + assign io_output_ar_payload_size = 3'b100; + assign io_output_ar_payload_prot = 3'b010; + assign io_output_ar_payload_cache = 4'b1111; + assign io_output_r_ready = contextRemover_io_output_rsp_ready; + assign when_BmbToAxi4Bridge_l243 = (io_output_r_payload_resp == 2'b00); + always @(*) begin + if(when_BmbToAxi4Bridge_l243) begin + contextRemover_io_output_rsp_payload_fragment_opcode = 1'b0; + end else begin + contextRemover_io_output_rsp_payload_fragment_opcode = 1'b1; + end + end + + +endmodule + +module EfxDMA_BmbSourceRemover ( + input wire io_input_cmd_valid, + output wire io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_source, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [20:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_source, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [127:0] io_input_rsp_payload_fragment_data, + output wire [20:0] io_input_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + output wire [21:0] io_output_cmd_payload_fragment_context, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [127:0] io_output_rsp_payload_fragment_data, + input wire [21:0] io_output_rsp_payload_fragment_context +); + + wire [0:0] cmdContext_source; + wire [20:0] cmdContext_context; + wire [0:0] rspContext_source; + wire [20:0] rspContext_context; + wire [21:0] _zz_rspContext_source; + + assign cmdContext_source = io_input_cmd_payload_fragment_source; + assign cmdContext_context = io_input_cmd_payload_fragment_context; + assign io_output_cmd_valid = io_input_cmd_valid; + assign io_input_cmd_ready = io_output_cmd_ready; + assign io_output_cmd_payload_last = io_input_cmd_payload_last; + assign io_output_cmd_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign io_output_cmd_payload_fragment_context = {cmdContext_context,cmdContext_source}; + assign _zz_rspContext_source = io_output_rsp_payload_fragment_context; + assign rspContext_source = _zz_rspContext_source[0 : 0]; + assign rspContext_context = _zz_rspContext_source[21 : 1]; + assign io_input_rsp_valid = io_output_rsp_valid; + assign io_output_rsp_ready = io_input_rsp_ready; + assign io_input_rsp_payload_last = io_output_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_input_rsp_payload_fragment_source = rspContext_source; + assign io_input_rsp_payload_fragment_context = rspContext_context; + +endmodule + +module EfxDMA_BufferCC_6 ( + input wire [1:0] io_dataIn, + output wire [1:0] io_dataOut, + input wire ctrl_clk, + input wire ctrl_reset +); + + (* async_reg = "true" *) reg [1:0] buffers_0; + (* async_reg = "true" *) reg [1:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge ctrl_clk) begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + + +endmodule + +module EfxDMA_Apb3CC ( + input wire [13:0] io_input_PADDR, + input wire [0:0] io_input_PSEL, + input wire io_input_PENABLE, + output wire io_input_PREADY, + input wire io_input_PWRITE, + input wire [31:0] io_input_PWDATA, + output wire [31:0] io_input_PRDATA, + output wire io_input_PSLVERROR, + output wire [13:0] io_output_PADDR, + output reg [0:0] io_output_PSEL, + output reg io_output_PENABLE, + input wire io_output_PREADY, + output wire io_output_PWRITE, + output wire [31:0] io_output_PWDATA, + input wire [31:0] io_output_PRDATA, + input wire io_output_PSLVERROR, + input wire ctrl_clk, + input wire ctrl_reset, + input wire clk, + input wire reset +); + + wire flowCCUnsafeByToggle_io_output_valid; + wire [13:0] flowCCUnsafeByToggle_io_output_payload_PADDR; + wire flowCCUnsafeByToggle_io_output_payload_PWRITE; + wire [31:0] flowCCUnsafeByToggle_io_output_payload_PWDATA; + wire flowCCUnsafeByToggle_1_io_output_valid; + wire [31:0] flowCCUnsafeByToggle_1_io_output_payload_PRDATA; + wire flowCCUnsafeByToggle_1_io_output_payload_PSLVERROR; + wire inputLogic_inputCmd_valid; + wire [13:0] inputLogic_inputCmd_payload_PADDR; + wire inputLogic_inputCmd_payload_PWRITE; + wire [31:0] inputLogic_inputCmd_payload_PWDATA; + wire inputLogic_inputRsp_valid; + wire [31:0] inputLogic_inputRsp_payload_PRDATA; + wire inputLogic_inputRsp_payload_PSLVERROR; + reg inputLogic_state; + wire flowCCUnsafeByToggle_io_output_toStream_valid; + reg flowCCUnsafeByToggle_io_output_toStream_ready; + wire [13:0] flowCCUnsafeByToggle_io_output_toStream_payload_PADDR; + wire flowCCUnsafeByToggle_io_output_toStream_payload_PWRITE; + wire [31:0] flowCCUnsafeByToggle_io_output_toStream_payload_PWDATA; + wire outputLogic_outputCmd_valid; + reg outputLogic_outputCmd_ready; + wire [13:0] outputLogic_outputCmd_payload_PADDR; + wire outputLogic_outputCmd_payload_PWRITE; + wire [31:0] outputLogic_outputCmd_payload_PWDATA; + reg flowCCUnsafeByToggle_io_output_toStream_rValid; + wire flowCCUnsafeByToggle_io_output_toStream_fire; + (* async_reg = "true" *) reg [13:0] flowCCUnsafeByToggle_io_output_toStream_rData_PADDR; + (* async_reg = "true" *) reg flowCCUnsafeByToggle_io_output_toStream_rData_PWRITE; + (* async_reg = "true" *) reg [31:0] flowCCUnsafeByToggle_io_output_toStream_rData_PWDATA; + wire when_Stream_l375; + reg outputLogic_state; + wire when_Apb3CCToggle_l81; + wire outputLogic_outputRsp_valid; + wire [31:0] outputLogic_outputRsp_payload_PRDATA; + wire outputLogic_outputRsp_payload_PSLVERROR; + wire outputLogic_outputCmd_fire; + + EfxDMA_FlowCCUnsafeByToggle flowCCUnsafeByToggle ( + .io_input_valid (inputLogic_inputCmd_valid ), //i + .io_input_payload_PADDR (inputLogic_inputCmd_payload_PADDR[13:0] ), //i + .io_input_payload_PWRITE (inputLogic_inputCmd_payload_PWRITE ), //i + .io_input_payload_PWDATA (inputLogic_inputCmd_payload_PWDATA[31:0] ), //i + .io_output_valid (flowCCUnsafeByToggle_io_output_valid ), //o + .io_output_payload_PADDR (flowCCUnsafeByToggle_io_output_payload_PADDR[13:0] ), //o + .io_output_payload_PWRITE (flowCCUnsafeByToggle_io_output_payload_PWRITE ), //o + .io_output_payload_PWDATA (flowCCUnsafeByToggle_io_output_payload_PWDATA[31:0]), //o + .ctrl_clk (ctrl_clk ), //i + .ctrl_reset (ctrl_reset ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_FlowCCUnsafeByToggle_1 flowCCUnsafeByToggle_1 ( + .io_input_valid (outputLogic_outputRsp_valid ), //i + .io_input_payload_PRDATA (outputLogic_outputRsp_payload_PRDATA[31:0] ), //i + .io_input_payload_PSLVERROR (outputLogic_outputRsp_payload_PSLVERROR ), //i + .io_output_valid (flowCCUnsafeByToggle_1_io_output_valid ), //o + .io_output_payload_PRDATA (flowCCUnsafeByToggle_1_io_output_payload_PRDATA[31:0]), //o + .io_output_payload_PSLVERROR (flowCCUnsafeByToggle_1_io_output_payload_PSLVERROR ), //o + .clk (clk ), //i + .reset (reset ), //i + .ctrl_clk (ctrl_clk ), //i + .ctrl_reset (ctrl_reset ) //i + ); + assign inputLogic_inputCmd_valid = ((io_input_PSEL[0] && io_input_PENABLE) && (! inputLogic_state)); + assign inputLogic_inputCmd_payload_PADDR = io_input_PADDR; + assign inputLogic_inputCmd_payload_PWRITE = io_input_PWRITE; + assign inputLogic_inputCmd_payload_PWDATA = io_input_PWDATA; + assign io_input_PREADY = inputLogic_inputRsp_valid; + assign io_input_PRDATA = inputLogic_inputRsp_payload_PRDATA; + assign io_input_PSLVERROR = inputLogic_inputRsp_payload_PSLVERROR; + assign flowCCUnsafeByToggle_io_output_toStream_valid = flowCCUnsafeByToggle_io_output_valid; + assign flowCCUnsafeByToggle_io_output_toStream_payload_PADDR = flowCCUnsafeByToggle_io_output_payload_PADDR; + assign flowCCUnsafeByToggle_io_output_toStream_payload_PWRITE = flowCCUnsafeByToggle_io_output_payload_PWRITE; + assign flowCCUnsafeByToggle_io_output_toStream_payload_PWDATA = flowCCUnsafeByToggle_io_output_payload_PWDATA; + assign flowCCUnsafeByToggle_io_output_toStream_fire = (flowCCUnsafeByToggle_io_output_toStream_valid && flowCCUnsafeByToggle_io_output_toStream_ready); + always @(*) begin + flowCCUnsafeByToggle_io_output_toStream_ready = outputLogic_outputCmd_ready; + if(when_Stream_l375) begin + flowCCUnsafeByToggle_io_output_toStream_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! outputLogic_outputCmd_valid); + assign outputLogic_outputCmd_valid = flowCCUnsafeByToggle_io_output_toStream_rValid; + assign outputLogic_outputCmd_payload_PADDR = flowCCUnsafeByToggle_io_output_toStream_rData_PADDR; + assign outputLogic_outputCmd_payload_PWRITE = flowCCUnsafeByToggle_io_output_toStream_rData_PWRITE; + assign outputLogic_outputCmd_payload_PWDATA = flowCCUnsafeByToggle_io_output_toStream_rData_PWDATA; + always @(*) begin + io_output_PENABLE = 1'b0; + if(outputLogic_outputCmd_valid) begin + if(when_Apb3CCToggle_l81) begin + io_output_PENABLE = 1'b0; + end else begin + io_output_PENABLE = 1'b1; + end + end + end + + always @(*) begin + io_output_PSEL = 1'b0; + if(outputLogic_outputCmd_valid) begin + io_output_PSEL = 1'b1; + end + end + + assign io_output_PADDR = outputLogic_outputCmd_payload_PADDR; + assign io_output_PWDATA = outputLogic_outputCmd_payload_PWDATA; + assign io_output_PWRITE = outputLogic_outputCmd_payload_PWRITE; + always @(*) begin + outputLogic_outputCmd_ready = 1'b0; + if(outputLogic_outputCmd_valid) begin + if(!when_Apb3CCToggle_l81) begin + if(io_output_PREADY) begin + outputLogic_outputCmd_ready = 1'b1; + end + end + end + end + + assign when_Apb3CCToggle_l81 = (! outputLogic_state); + assign outputLogic_outputCmd_fire = (outputLogic_outputCmd_valid && outputLogic_outputCmd_ready); + assign outputLogic_outputRsp_valid = outputLogic_outputCmd_fire; + assign outputLogic_outputRsp_payload_PRDATA = io_output_PRDATA; + assign outputLogic_outputRsp_payload_PSLVERROR = io_output_PSLVERROR; + assign inputLogic_inputRsp_valid = flowCCUnsafeByToggle_1_io_output_valid; + assign inputLogic_inputRsp_payload_PRDATA = flowCCUnsafeByToggle_1_io_output_payload_PRDATA; + assign inputLogic_inputRsp_payload_PSLVERROR = flowCCUnsafeByToggle_1_io_output_payload_PSLVERROR; + always @(posedge ctrl_clk) begin + if(ctrl_reset) begin + inputLogic_state <= 1'b0; + end else begin + if(inputLogic_inputCmd_valid) begin + inputLogic_state <= 1'b1; + end + if(inputLogic_inputRsp_valid) begin + inputLogic_state <= 1'b0; + end + end + end + + always @(posedge clk) begin + if(reset) begin + flowCCUnsafeByToggle_io_output_toStream_rValid <= 1'b0; + outputLogic_state <= 1'b0; + end else begin + if(flowCCUnsafeByToggle_io_output_toStream_ready) begin + flowCCUnsafeByToggle_io_output_toStream_rValid <= flowCCUnsafeByToggle_io_output_toStream_valid; + end + if(outputLogic_outputCmd_valid) begin + if(when_Apb3CCToggle_l81) begin + outputLogic_state <= 1'b1; + end else begin + if(io_output_PREADY) begin + outputLogic_state <= 1'b0; + end + end + end + end + end + + always @(posedge clk) begin + if(flowCCUnsafeByToggle_io_output_toStream_fire) begin + flowCCUnsafeByToggle_io_output_toStream_rData_PADDR <= flowCCUnsafeByToggle_io_output_toStream_payload_PADDR; + flowCCUnsafeByToggle_io_output_toStream_rData_PWRITE <= flowCCUnsafeByToggle_io_output_toStream_payload_PWRITE; + flowCCUnsafeByToggle_io_output_toStream_rData_PWDATA <= flowCCUnsafeByToggle_io_output_toStream_payload_PWDATA; + end + end + + +endmodule + +module EfxDMA_Core ( + output wire io_sgRead_cmd_valid, + input wire io_sgRead_cmd_ready, + output wire io_sgRead_cmd_payload_last, + output wire [0:0] io_sgRead_cmd_payload_fragment_opcode, + output wire [31:0] io_sgRead_cmd_payload_fragment_address, + output wire [4:0] io_sgRead_cmd_payload_fragment_length, + output wire [0:0] io_sgRead_cmd_payload_fragment_context, + input wire io_sgRead_rsp_valid, + output wire io_sgRead_rsp_ready, + input wire io_sgRead_rsp_payload_last, + input wire [0:0] io_sgRead_rsp_payload_fragment_opcode, + input wire [127:0] io_sgRead_rsp_payload_fragment_data, + input wire [0:0] io_sgRead_rsp_payload_fragment_context, + output wire io_sgWrite_cmd_valid, + input wire io_sgWrite_cmd_ready, + output wire io_sgWrite_cmd_payload_last, + output wire [0:0] io_sgWrite_cmd_payload_fragment_opcode, + output wire [31:0] io_sgWrite_cmd_payload_fragment_address, + output wire [1:0] io_sgWrite_cmd_payload_fragment_length, + output reg [127:0] io_sgWrite_cmd_payload_fragment_data, + output reg [15:0] io_sgWrite_cmd_payload_fragment_mask, + output wire [0:0] io_sgWrite_cmd_payload_fragment_context, + input wire io_sgWrite_rsp_valid, + output wire io_sgWrite_rsp_ready, + input wire io_sgWrite_rsp_payload_last, + input wire [0:0] io_sgWrite_rsp_payload_fragment_opcode, + input wire [0:0] io_sgWrite_rsp_payload_fragment_context, + output reg io_read_cmd_valid, + input wire io_read_cmd_ready, + output wire io_read_cmd_payload_last, + output wire [0:0] io_read_cmd_payload_fragment_opcode, + output wire [31:0] io_read_cmd_payload_fragment_address, + output wire [11:0] io_read_cmd_payload_fragment_length, + output wire [20:0] io_read_cmd_payload_fragment_context, + input wire io_read_rsp_valid, + output wire io_read_rsp_ready, + input wire io_read_rsp_payload_last, + input wire [0:0] io_read_rsp_payload_fragment_opcode, + input wire [127:0] io_read_rsp_payload_fragment_data, + input wire [20:0] io_read_rsp_payload_fragment_context, + output wire io_write_cmd_valid, + input wire io_write_cmd_ready, + output wire io_write_cmd_payload_last, + output wire [0:0] io_write_cmd_payload_fragment_opcode, + output wire [31:0] io_write_cmd_payload_fragment_address, + output wire [11:0] io_write_cmd_payload_fragment_length, + output wire [127:0] io_write_cmd_payload_fragment_data, + output wire [15:0] io_write_cmd_payload_fragment_mask, + output wire [12:0] io_write_cmd_payload_fragment_context, + input wire io_write_rsp_valid, + output wire io_write_rsp_ready, + input wire io_write_rsp_payload_last, + input wire [0:0] io_write_rsp_payload_fragment_opcode, + input wire [12:0] io_write_rsp_payload_fragment_context, + output wire io_outputs_0_valid, + input wire io_outputs_0_ready, + output wire [63:0] io_outputs_0_payload_data, + output wire [7:0] io_outputs_0_payload_mask, + output wire [3:0] io_outputs_0_payload_sink, + output wire io_outputs_0_payload_last, + input wire io_inputs_0_valid, + output reg io_inputs_0_ready, + input wire [63:0] io_inputs_0_payload_data, + input wire [7:0] io_inputs_0_payload_mask, + input wire [3:0] io_inputs_0_payload_sink, + input wire io_inputs_0_payload_last, + output reg [1:0] io_interrupts, + input wire [13:0] io_ctrl_PADDR, + input wire [0:0] io_ctrl_PSEL, + input wire io_ctrl_PENABLE, + output wire io_ctrl_PREADY, + input wire io_ctrl_PWRITE, + input wire [31:0] io_ctrl_PWDATA, + output reg [31:0] io_ctrl_PRDATA, + output wire io_ctrl_PSLVERROR, + output wire ll_0_descriptorUpdate, + output wire ll_1_descriptorUpdate, + input wire clk, + input wire reset +); + + wire [9:0] memory_core_io_writes_0_cmd_payload_address; + wire [6:0] memory_core_io_writes_0_cmd_payload_context; + wire [9:0] memory_core_io_writes_1_cmd_payload_address; + reg [15:0] memory_core_io_writes_1_cmd_payload_mask; + wire [6:0] memory_core_io_writes_1_cmd_payload_context; + wire memory_core_io_reads_0_cmd_valid; + wire [9:0] memory_core_io_reads_0_cmd_payload_address; + wire [2:0] memory_core_io_reads_0_cmd_payload_context; + wire [9:0] memory_core_io_reads_1_cmd_payload_address; + wire [11:0] memory_core_io_reads_1_cmd_payload_context; + wire [15:0] b2m_fsm_aggregate_engine_io_input_payload_mask; + wire b2m_fsm_aggregate_engine_io_flush; + wire [3:0] b2m_fsm_aggregate_engine_io_offset; + wire memory_core_io_writes_0_cmd_ready; + wire memory_core_io_writes_0_rsp_valid; + wire [6:0] memory_core_io_writes_0_rsp_payload_context; + wire memory_core_io_writes_1_cmd_ready; + wire memory_core_io_writes_1_rsp_valid; + wire [6:0] memory_core_io_writes_1_rsp_payload_context; + wire memory_core_io_reads_0_cmd_ready; + wire memory_core_io_reads_0_rsp_valid; + wire [63:0] memory_core_io_reads_0_rsp_payload_data; + wire [7:0] memory_core_io_reads_0_rsp_payload_mask; + wire [2:0] memory_core_io_reads_0_rsp_payload_context; + wire memory_core_io_reads_1_cmd_ready; + wire memory_core_io_reads_1_rsp_valid; + wire [127:0] memory_core_io_reads_1_rsp_payload_data; + wire [15:0] memory_core_io_reads_1_rsp_payload_mask; + wire [11:0] memory_core_io_reads_1_rsp_payload_context; + wire b2m_fsm_aggregate_engine_io_input_ready; + wire [127:0] b2m_fsm_aggregate_engine_io_output_data; + wire [15:0] b2m_fsm_aggregate_engine_io_output_mask; + wire b2m_fsm_aggregate_engine_io_output_consumed; + wire [3:0] b2m_fsm_aggregate_engine_io_output_usedUntil; + wire [26:0] _zz_channels_0_bytesProbe_value; + wire [26:0] _zz_channels_0_bytesProbe_value_1; + wire [13:0] _zz_channels_0_fifo_pop_withOverride_backupNext; + wire [13:0] _zz_channels_0_fifo_pop_withOverride_exposed; + wire [26:0] _zz_channels_0_pop_b2m_selfFlush; + wire [13:0] _zz_channels_0_pop_b2m_request; + wire [10:0] _zz_channels_0_pop_b2m_request_1; + wire [9:0] _zz_channels_0_pop_b2m_request_2; + wire [3:0] _zz_channels_0_pop_b2m_memPending; + wire [3:0] _zz_channels_0_pop_b2m_memPending_1; + wire [0:0] _zz_channels_0_pop_b2m_memPending_2; + wire [3:0] _zz_channels_0_pop_b2m_memPending_3; + wire [0:0] _zz_channels_0_pop_b2m_memPending_4; + wire [10:0] _zz_channels_0_fifo_push_available; + wire [26:0] _zz_channels_1_bytesProbe_value; + wire [26:0] _zz_channels_1_bytesProbe_value_1; + wire [13:0] _zz_channels_1_fifo_pop_withoutOverride_exposed; + wire [3:0] _zz_channels_1_push_m2b_memPending; + wire [3:0] _zz_channels_1_push_m2b_memPending_1; + wire [0:0] _zz_channels_1_push_m2b_memPending_2; + wire [3:0] _zz_channels_1_push_m2b_memPending_3; + wire [0:0] _zz_channels_1_push_m2b_memPending_4; + wire [10:0] _zz_channels_1_push_m2b_loadRequest; + wire [8:0] _zz_channels_1_push_m2b_loadRequest_1; + wire [25:0] _zz_when_DmaSg_l486; + wire [10:0] _zz_channels_1_fifo_push_available; + wire [0:0] _zz_s2b_0_cmd_firsts; + wire [4:0] _zz_s2b_0_cmd_firsts_1; + wire [3:0] _zz_s2b_0_cmd_byteCount_8; + reg [3:0] _zz_s2b_0_cmd_byteCount_9; + wire [2:0] _zz_s2b_0_cmd_byteCount_10; + reg [3:0] _zz_s2b_0_cmd_byteCount_11; + wire [2:0] _zz_s2b_0_cmd_byteCount_12; + reg [3:0] _zz_s2b_0_cmd_byteCount_13; + wire [2:0] _zz_s2b_0_cmd_byteCount_14; + wire [1:0] _zz_s2b_0_cmd_byteCount_15; + wire [1:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2; + wire [1:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2_1; + wire [0:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2_2; + reg [0:0] _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3; + wire [25:0] _zz_m2b_cmd_s0_length; + wire [25:0] _zz_m2b_cmd_s0_length_1; + wire [25:0] _zz_m2b_cmd_s0_length_2; + wire [25:0] _zz_m2b_cmd_s0_lastBurst; + wire [31:0] _zz_m2b_cmd_s1_context_stop; + wire [31:0] _zz_m2b_cmd_s1_context_stop_1; + wire [31:0] _zz_m2b_cmd_s1_addressNext; + wire [31:0] _zz_m2b_cmd_s1_addressNext_1; + wire [25:0] _zz_m2b_cmd_s1_byteLeftNext; + wire [25:0] _zz_m2b_cmd_s1_byteLeftNext_1; + wire [12:0] _zz_m2b_cmd_s1_fifoPushDecr; + wire [11:0] _zz_m2b_cmd_s1_fifoPushDecr_1; + wire [11:0] _zz_m2b_cmd_s1_fifoPushDecr_2; + wire [3:0] _zz_m2b_cmd_s1_fifoPushDecr_3; + wire [12:0] _zz_m2b_cmd_s1_fifoPushDecr_4; + wire [1:0] _zz_m2b_cmd_s1_fifoPushDecr_5; + wire [1:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2; + wire [1:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_1; + wire [0:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_2; + reg [0:0] _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3; + wire [0:0] _zz_when; + wire [12:0] _zz_b2m_fsm_bytesInBurstP1; + wire [1:0] _zz_b2m_fsm_bytesInBurstP1_1; + wire [31:0] _zz_b2m_fsm_addressNext; + wire [26:0] _zz_b2m_fsm_bytesLeftNext; + wire [13:0] _zz_b2m_fsm_bytesLeftNext_1; + wire [25:0] _zz__zz_b2m_fsm_sel_bytesInBurst_1; + wire [25:0] _zz__zz_b2m_fsm_sel_bytesInBurst_1_1; + wire [11:0] _zz__zz_b2m_fsm_sel_bytesInBurst_2; + wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_3; + wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_4; + wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_5; + wire [13:0] _zz_b2m_fsm_fifoCompletion; + wire [13:0] _zz_b2m_fsm_fifoCompletion_1; + wire [11:0] _zz_b2m_fsm_beatCounter; + wire [11:0] _zz_b2m_fsm_beatCounter_1; + wire [3:0] _zz_b2m_fsm_beatCounter_2; + wire [10:0] _zz_b2m_fsm_sel_ptr; + wire [3:0] _zz_b2m_fsm_aggregate_bytesToSkipMask; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_1; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_2; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_3; + wire [0:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_4; + wire [9:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_5; + wire [3:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_6; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_7; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_8; + wire _zz_b2m_fsm_aggregate_bytesToSkipMask_9; + wire [0:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_10; + wire [3:0] _zz_b2m_fsm_aggregate_bytesToSkipMask_11; + wire [3:0] _zz_b2m_fsm_cmd_maskLastTriggerComb; + wire [3:0] _zz_b2m_fsm_cmd_maskLast; + wire _zz_b2m_fsm_cmd_maskLast_1; + wire [0:0] _zz_b2m_fsm_cmd_maskLast_2; + wire [7:0] _zz_b2m_fsm_cmd_maskLast_3; + wire [3:0] _zz_b2m_fsm_cmd_maskLast_4; + wire [3:0] _zz_b2m_fsm_cmd_maskLast_5; + wire [3:0] _zz_b2m_fsm_cmd_maskFirst; + wire _zz_b2m_fsm_cmd_maskFirst_1; + wire [0:0] _zz_b2m_fsm_cmd_maskFirst_2; + wire [7:0] _zz_b2m_fsm_cmd_maskFirst_3; + wire [3:0] _zz_b2m_fsm_cmd_maskFirst_4; + wire [3:0] _zz_b2m_fsm_cmd_maskFirst_5; + wire [0:0] _zz_when_1; + wire [0:0] _zz_when_2; + wire [1:0] _zz__zz_ll_arbiter_head_1; + wire [1:0] _zz__zz_ll_arbiter_head_1_1; + wire [1:0] _zz_ll_arbiter_head_2; + wire [1:0] _zz_ll_arbiter_isJustASink; + wire [1:0] _zz_ll_arbiter_doDescriptorStall; + wire [1:0] _zz_ll_arbiter_onSgStream; + wire [1:0] _zz_ll_cmd_ptr; + wire [1:0] _zz_ll_cmd_ptrNext; + wire [1:0] _zz_ll_cmd_endOfPacket; + wire [0:0] _zz_channels_0_channelStart; + wire [0:0] _zz_channels_0_ctrl_kick; + wire [0:0] _zz_channels_0_channelStart_1; + wire [0:0] _zz_channels_0_ll_sgStart; + wire [0:0] _zz_channels_0_interrupts_completion_valid; + wire [0:0] _zz_channels_0_interrupts_onChannelCompletion_valid; + wire [0:0] _zz_channels_0_interrupts_onLinkedListUpdate_valid; + wire [0:0] _zz_channels_0_interrupts_s2mPacket_valid; + wire [0:0] _zz_channels_1_channelStart; + wire [0:0] _zz_channels_1_ctrl_kick; + wire [0:0] _zz_channels_1_channelStart_1; + wire [0:0] _zz_channels_1_ll_sgStart; + wire [0:0] _zz_channels_1_interrupts_completion_valid; + wire [0:0] _zz_channels_1_interrupts_onChannelCompletion_valid; + wire [0:0] _zz_channels_1_interrupts_onLinkedListUpdate_valid; + wire [31:0] _zz_io_ctrl_PRDATA; + wire [31:0] _zz_io_ctrl_PRDATA_1; + wire [10:0] _zz_channels_0_fifo_push_ptrIncr_value; + wire [0:0] _zz_channels_0_fifo_push_ptrIncr_value_1; + wire [13:0] _zz_channels_0_fifo_pop_bytesIncr_value_1; + wire [3:0] _zz_channels_0_fifo_pop_bytesIncr_value_2; + wire [10:0] _zz_channels_0_fifo_pop_ptrIncr_value; + wire [1:0] _zz_channels_0_fifo_pop_ptrIncr_value_1; + wire [10:0] _zz_channels_1_fifo_push_ptrIncr_value_1; + wire [1:0] _zz_channels_1_fifo_push_ptrIncr_value_2; + wire [13:0] _zz_channels_1_fifo_pop_bytesIncr_value_1; + wire [4:0] _zz_channels_1_fifo_pop_bytesIncr_value_2; + wire [4:0] _zz_channels_1_fifo_pop_bytesIncr_value_3; + wire [10:0] _zz_channels_1_fifo_pop_ptrIncr_value; + wire [0:0] _zz_channels_1_fifo_pop_ptrIncr_value_1; + wire ctrl_readErrorFlag; + wire ctrl_writeErrorFlag; + wire ctrl_askWrite; + wire ctrl_askRead; + wire ctrl_doWrite; + wire ctrl_doRead; + reg channels_0_channelStart; + reg channels_0_channelStop; + reg channels_0_channelCompletion; + reg channels_0_channelValid; + reg channels_0_descriptorStart; + reg channels_0_descriptorCompletion; + reg channels_0_descriptorValid; + reg [25:0] channels_0_bytes; + reg [1:0] channels_0_priority; + reg [1:0] channels_0_weight; + reg channels_0_readyToStop; + reg [26:0] channels_0_bytesProbe_value; + reg channels_0_bytesProbe_incr_valid; + reg [11:0] channels_0_bytesProbe_incr_payload; + reg channels_0_ctrl_kick; + reg channels_0_ll_sgStart; + reg channels_0_ll_valid; + reg channels_0_ll_onSgStream; + reg channels_0_ll_head; + reg channels_0_ll_justASync; + reg channels_0_ll_waitDone; + reg channels_0_ll_readDone; + reg channels_0_ll_writeDone; + reg channels_0_ll_gotDescriptorStall; + reg channels_0_ll_controlNoCompletion; + reg channels_0_ll_packet; + reg channels_0_ll_requireSync; + reg [31:0] channels_0_ll_ptr; + reg [31:0] channels_0_ll_ptrNext; + wire channels_0_ll_requestLl; + reg channels_0_ll_descriptorUpdated; + wire when_DmaSg_l318; + wire when_DmaSg_l320; + wire when_DmaSg_l322; + wire when_DmaSg_l328; + wire [10:0] channels_0_fifo_base; + wire [10:0] channels_0_fifo_words; + reg [10:0] channels_0_fifo_push_available; + wire [10:0] channels_0_fifo_push_availableDecr; + reg [10:0] channels_0_fifo_push_ptr; + wire [10:0] channels_0_fifo_push_ptrWithBase; + wire [10:0] channels_0_fifo_push_ptrIncr_value; + reg [10:0] channels_0_fifo_pop_ptr; + wire [13:0] channels_0_fifo_pop_bytes; + wire [10:0] channels_0_fifo_pop_ptrWithBase; + wire [13:0] channels_0_fifo_pop_bytesIncr_value; + wire [13:0] channels_0_fifo_pop_bytesDecr_value; + wire channels_0_fifo_pop_empty; + wire [10:0] channels_0_fifo_pop_ptrIncr_value; + reg [13:0] channels_0_fifo_pop_withOverride_backup; + wire [13:0] channels_0_fifo_pop_withOverride_backupNext; + reg channels_0_fifo_pop_withOverride_load; + reg channels_0_fifo_pop_withOverride_unload; + reg [13:0] channels_0_fifo_pop_withOverride_exposed; + reg channels_0_fifo_pop_withOverride_valid; + wire when_DmaSg_l409; + wire channels_0_fifo_empty; + reg channels_0_push_memory; + reg channels_0_push_s2b_completionOnLast; + reg channels_0_push_s2b_packetEvent; + reg channels_0_push_s2b_packetLock; + reg channels_0_push_s2b_waitFirst; + wire when_DmaSg_l457; + reg channels_0_pop_memory; + wire [11:0] channels_0_pop_b2m_bytePerBurst; + reg channels_0_pop_b2m_fire; + reg channels_0_pop_b2m_waitFinalRsp; + reg channels_0_pop_b2m_flush; + reg channels_0_pop_b2m_packetSync; + reg channels_0_pop_b2m_packet; + wire when_DmaSg_l505; + reg channels_0_pop_b2m_memRsp; + reg [3:0] channels_0_pop_b2m_memPending; + reg [31:0] channels_0_pop_b2m_address; + reg [26:0] channels_0_pop_b2m_bytesLeft; + wire channels_0_pop_b2m_selfFlush; + wire channels_0_pop_b2m_request; + reg [3:0] channels_0_pop_b2m_bytesToSkip; + reg [13:0] channels_0_pop_b2m_decrBytes; + reg channels_0_pop_b2m_memPendingInc; + wire when_DmaSg_l523; + wire when_DmaSg_l532; + wire when_DmaSg_l536; + wire when_DmaSg_l547; + wire when_DmaSg_l563; + wire channels_0_readyForChannelCompletion; + wire when_DmaSg_l575; + reg _zz_when_DmaSg_l593; + wire when_DmaSg_l593; + wire channels_0_s2b_full; + reg [10:0] channels_0_fifo_pop_ptrIncr_value_regNext; + wire when_DmaSg_l255; + reg channels_0_interrupts_completion_enable; + reg channels_0_interrupts_completion_valid; + wire when_DmaSg_l255_1; + wire when_DmaSg_l255_2; + reg channels_0_interrupts_onChannelCompletion_enable; + reg channels_0_interrupts_onChannelCompletion_valid; + wire when_DmaSg_l255_3; + reg channels_0_interrupts_onLinkedListUpdate_enable; + reg channels_0_interrupts_onLinkedListUpdate_valid; + wire when_DmaSg_l255_4; + reg channels_0_interrupts_s2mPacket_enable; + reg channels_0_interrupts_s2mPacket_valid; + wire when_DmaSg_l255_5; + wire when_DmaSg_l625; + reg channels_1_channelStart; + reg channels_1_channelStop; + reg channels_1_channelCompletion; + reg channels_1_channelValid; + reg channels_1_descriptorStart; + reg channels_1_descriptorCompletion; + reg channels_1_descriptorValid; + reg [25:0] channels_1_bytes; + reg [1:0] channels_1_priority; + reg [1:0] channels_1_weight; + reg channels_1_readyToStop; + reg [26:0] channels_1_bytesProbe_value; + reg channels_1_bytesProbe_incr_valid; + reg [11:0] channels_1_bytesProbe_incr_payload; + reg channels_1_ctrl_kick; + reg channels_1_ll_sgStart; + reg channels_1_ll_valid; + reg channels_1_ll_onSgStream; + reg channels_1_ll_head; + reg channels_1_ll_justASync; + reg channels_1_ll_waitDone; + reg channels_1_ll_readDone; + reg channels_1_ll_writeDone; + reg channels_1_ll_gotDescriptorStall; + reg channels_1_ll_controlNoCompletion; + reg channels_1_ll_packet; + reg channels_1_ll_requireSync; + reg [31:0] channels_1_ll_ptr; + reg [31:0] channels_1_ll_ptrNext; + wire channels_1_ll_requestLl; + reg channels_1_ll_descriptorUpdated; + wire when_DmaSg_l318_1; + wire when_DmaSg_l320_1; + wire when_DmaSg_l322_1; + wire when_DmaSg_l328_1; + wire [10:0] channels_1_fifo_base; + wire [10:0] channels_1_fifo_words; + reg [10:0] channels_1_fifo_push_available; + reg [10:0] channels_1_fifo_push_availableDecr; + reg [10:0] channels_1_fifo_push_ptr; + wire [10:0] channels_1_fifo_push_ptrWithBase; + wire [10:0] channels_1_fifo_push_ptrIncr_value; + reg [10:0] channels_1_fifo_pop_ptr; + wire [13:0] channels_1_fifo_pop_bytes; + wire [10:0] channels_1_fifo_pop_ptrWithBase; + wire [13:0] channels_1_fifo_pop_bytesIncr_value; + wire [13:0] channels_1_fifo_pop_bytesDecr_value; + wire channels_1_fifo_pop_empty; + wire [10:0] channels_1_fifo_pop_ptrIncr_value; + reg [13:0] channels_1_fifo_pop_withoutOverride_exposed; + wire channels_1_fifo_empty; + reg channels_1_push_memory; + reg [31:0] channels_1_push_m2b_address; + wire [11:0] channels_1_push_m2b_bytePerBurst; + reg channels_1_push_m2b_loadDone; + reg [25:0] channels_1_push_m2b_bytesLeft; + reg [3:0] channels_1_push_m2b_memPending; + reg channels_1_push_m2b_memPendingIncr; + reg channels_1_push_m2b_memPendingDecr; + reg channels_1_push_m2b_loadRequest; + reg channels_1_pop_memory; + reg channels_1_pop_b2s_last; + reg [3:0] channels_1_pop_b2s_sinkId; + reg channels_1_pop_b2s_veryLastTrigger; + reg channels_1_pop_b2s_veryLastValid; + wire when_DmaSg_l474; + reg [10:0] channels_1_pop_b2s_veryLastPtr; + reg channels_1_pop_b2s_veryLastEndPacket; + wire when_DmaSg_l483; + wire when_DmaSg_l486; + wire when_DmaSg_l562; + reg channels_1_readyForChannelCompletion; + wire when_DmaSg_l566; + wire when_DmaSg_l575_1; + reg _zz_when_DmaSg_l593_1; + wire when_DmaSg_l593_1; + wire channels_1_s2b_full; + reg [10:0] channels_1_fifo_pop_ptrIncr_value_regNext; + wire when_DmaSg_l255_6; + reg channels_1_interrupts_completion_enable; + reg channels_1_interrupts_completion_valid; + wire when_DmaSg_l255_7; + wire when_DmaSg_l255_8; + reg channels_1_interrupts_onChannelCompletion_enable; + reg channels_1_interrupts_onChannelCompletion_valid; + wire when_DmaSg_l255_9; + reg channels_1_interrupts_onLinkedListUpdate_enable; + reg channels_1_interrupts_onLinkedListUpdate_valid; + wire when_DmaSg_l255_10; + wire when_DmaSg_l625_1; + wire io_inputs_0_fire; + wire when_package_l12; + reg io_inputs_0_payload_last_regNextWhen; + wire when_package_l12_1; + reg io_inputs_0_payload_last_regNextWhen_1; + wire when_package_l12_2; + reg io_inputs_0_payload_last_regNextWhen_2; + wire when_package_l12_3; + reg io_inputs_0_payload_last_regNextWhen_3; + wire when_package_l12_4; + reg io_inputs_0_payload_last_regNextWhen_4; + wire when_package_l12_5; + reg io_inputs_0_payload_last_regNextWhen_5; + wire when_package_l12_6; + reg io_inputs_0_payload_last_regNextWhen_6; + wire when_package_l12_7; + reg io_inputs_0_payload_last_regNextWhen_7; + wire when_package_l12_8; + reg io_inputs_0_payload_last_regNextWhen_8; + wire when_package_l12_9; + reg io_inputs_0_payload_last_regNextWhen_9; + wire when_package_l12_10; + reg io_inputs_0_payload_last_regNextWhen_10; + wire when_package_l12_11; + reg io_inputs_0_payload_last_regNextWhen_11; + wire when_package_l12_12; + reg io_inputs_0_payload_last_regNextWhen_12; + wire when_package_l12_13; + reg io_inputs_0_payload_last_regNextWhen_13; + wire when_package_l12_14; + reg io_inputs_0_payload_last_regNextWhen_14; + wire when_package_l12_15; + reg io_inputs_0_payload_last_regNextWhen_15; + wire [15:0] s2b_0_cmd_firsts; + wire s2b_0_cmd_first; + wire [0:0] s2b_0_cmd_channelsOh; + wire s2b_0_cmd_noHit; + wire [0:0] s2b_0_cmd_channelsFull; + reg io_inputs_0_thrown_valid; + wire io_inputs_0_thrown_ready; + wire [63:0] io_inputs_0_thrown_payload_data; + wire [7:0] io_inputs_0_thrown_payload_mask; + wire [3:0] io_inputs_0_thrown_payload_sink; + wire io_inputs_0_thrown_payload_last; + wire _zz_io_inputs_0_thrown_ready; + wire s2b_0_cmd_sinkHalted_valid; + wire s2b_0_cmd_sinkHalted_ready; + wire [63:0] s2b_0_cmd_sinkHalted_payload_data; + wire [7:0] s2b_0_cmd_sinkHalted_payload_mask; + wire [3:0] s2b_0_cmd_sinkHalted_payload_sink; + wire s2b_0_cmd_sinkHalted_payload_last; + wire [3:0] _zz_s2b_0_cmd_byteCount; + wire [3:0] _zz_s2b_0_cmd_byteCount_1; + wire [3:0] _zz_s2b_0_cmd_byteCount_2; + wire [3:0] _zz_s2b_0_cmd_byteCount_3; + wire [3:0] _zz_s2b_0_cmd_byteCount_4; + wire [3:0] _zz_s2b_0_cmd_byteCount_5; + wire [3:0] _zz_s2b_0_cmd_byteCount_6; + wire [3:0] _zz_s2b_0_cmd_byteCount_7; + wire [3:0] s2b_0_cmd_byteCount; + wire [0:0] s2b_0_cmd_context_channel; + wire [3:0] s2b_0_cmd_context_bytes; + wire s2b_0_cmd_context_flush; + wire s2b_0_cmd_context_packet; + wire memory_core_io_writes_0_cmd_fire; + wire when_DmaSg_l665; + wire [0:0] s2b_0_rsp_context_channel; + wire [3:0] s2b_0_rsp_context_bytes; + wire s2b_0_rsp_context_flush; + wire s2b_0_rsp_context_packet; + wire [6:0] _zz_s2b_0_rsp_context_channel; + wire _zz_channels_0_fifo_pop_bytesIncr_value; + wire when_DmaSg_l679; + wire when_DmaSg_l681; + wire when_DmaSg_l682; + wire [0:0] b2s_0_cmd_channelsOh; + wire [0:0] b2s_0_cmd_context_channel; + wire b2s_0_cmd_context_veryLast; + wire b2s_0_cmd_context_endPacket; + wire [10:0] b2s_0_cmd_veryLastPtr; + wire [10:0] b2s_0_cmd_address; + wire [0:0] b2s_0_rsp_context_channel; + wire b2s_0_rsp_context_veryLast; + wire b2s_0_rsp_context_endPacket; + wire [2:0] _zz_b2s_0_rsp_context_channel; + wire io_outputs_0_fire; + wire when_DmaSg_l725; + wire when_DmaSg_l726; + reg m2b_cmd_s0_valid; + wire [1:0] _zz_m2b_cmd_s0_priority_masked; + wire [0:0] m2b_cmd_s0_priority_masked; + reg [0:0] m2b_cmd_s0_priority_roundRobins_0; + reg [0:0] m2b_cmd_s0_priority_roundRobins_1; + reg [0:0] m2b_cmd_s0_priority_roundRobins_2; + reg [0:0] m2b_cmd_s0_priority_roundRobins_3; + reg [1:0] m2b_cmd_s0_priority_counter; + wire [0:0] _zz_m2b_cmd_s0_priority_chosenOh; + wire [1:0] _zz_m2b_cmd_s0_priority_chosenOh_1; + wire [1:0] _zz_m2b_cmd_s0_priority_chosenOh_2; + wire [0:0] m2b_cmd_s0_priority_chosenOh; + wire m2b_cmd_s0_priority_weightLast; + wire [0:0] m2b_cmd_s0_priority_contextNext; + wire when_DmaSg_l758; + wire when_DmaSg_l760; + wire when_DmaSg_l763; + wire when_DmaSg_l763_1; + wire when_DmaSg_l763_2; + wire when_DmaSg_l763_3; + wire when_DmaSg_l773; + wire [31:0] m2b_cmd_s0_address; + wire [25:0] m2b_cmd_s0_bytesLeft; + wire [11:0] m2b_cmd_s0_readAddressBurstRange; + wire [11:0] m2b_cmd_s0_lengthHead; + wire [11:0] m2b_cmd_s0_length; + wire m2b_cmd_s0_lastBurst; + reg m2b_cmd_s1_valid; + reg [31:0] m2b_cmd_s1_address; + reg [11:0] m2b_cmd_s1_length; + reg m2b_cmd_s1_lastBurst; + reg [25:0] m2b_cmd_s1_bytesLeft; + wire [3:0] m2b_cmd_s1_context_start; + wire [3:0] m2b_cmd_s1_context_stop; + wire [11:0] m2b_cmd_s1_context_length; + wire m2b_cmd_s1_context_last; + wire [31:0] m2b_cmd_s1_addressNext; + wire [25:0] m2b_cmd_s1_byteLeftNext; + wire [9:0] m2b_cmd_s1_fifoPushDecr; + wire when_DmaSg_l828; + wire [3:0] m2b_rsp_context_start; + wire [3:0] m2b_rsp_context_stop; + wire [11:0] m2b_rsp_context_length; + wire m2b_rsp_context_last; + wire [20:0] _zz_m2b_rsp_context_start; + wire m2b_rsp_veryLast; + wire io_read_rsp_fire; + wire when_DmaSg_l847; + wire when_DmaSg_l848; + reg m2b_rsp_first; + wire m2b_rsp_writeContext_last; + wire m2b_rsp_writeContext_lastOfBurst; + wire [4:0] m2b_rsp_writeContext_loadByteInNextBeat; + wire memory_core_io_writes_1_cmd_fire; + wire _zz_channels_1_fifo_push_ptrIncr_value; + wire when_DmaSg_l874; + wire m2b_writeRsp_context_last; + wire m2b_writeRsp_context_lastOfBurst; + wire [4:0] m2b_writeRsp_context_loadByteInNextBeat; + wire [6:0] _zz_m2b_writeRsp_context_last; + wire _zz_channels_1_fifo_pop_bytesIncr_value; + wire when_DmaSg_l893; + reg b2m_fsm_sel_valid; + reg b2m_fsm_sel_ready; + reg [11:0] b2m_fsm_sel_bytePerBurst; + reg [11:0] b2m_fsm_sel_bytesInBurst; + reg [13:0] b2m_fsm_sel_bytesInFifo; + reg [31:0] b2m_fsm_sel_address; + reg [10:0] b2m_fsm_sel_ptr; + reg [10:0] b2m_fsm_sel_ptrMask; + reg b2m_fsm_sel_flush; + reg b2m_fsm_sel_packet; + reg [25:0] b2m_fsm_sel_bytesLeft; + reg b2m_fsm_arbiter_logic_valid; + wire [1:0] _zz_b2m_fsm_arbiter_logic_priority_masked; + wire [0:0] b2m_fsm_arbiter_logic_priority_masked; + reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_0; + reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_1; + reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_2; + reg [0:0] b2m_fsm_arbiter_logic_priority_roundRobins_3; + reg [1:0] b2m_fsm_arbiter_logic_priority_counter; + wire [0:0] _zz_b2m_fsm_arbiter_logic_priority_chosenOh; + wire [1:0] _zz_b2m_fsm_arbiter_logic_priority_chosenOh_1; + wire [1:0] _zz_b2m_fsm_arbiter_logic_priority_chosenOh_2; + wire [0:0] b2m_fsm_arbiter_logic_priority_chosenOh; + wire b2m_fsm_arbiter_logic_priority_weightLast; + wire [0:0] b2m_fsm_arbiter_logic_priority_contextNext; + wire when_DmaSg_l758_1; + wire when_DmaSg_l760_1; + wire when_DmaSg_l763_4; + wire when_DmaSg_l763_5; + wire when_DmaSg_l763_6; + wire when_DmaSg_l763_7; + wire when_DmaSg_l773_1; + wire when_DmaSg_l935; + wire [12:0] b2m_fsm_bytesInBurstP1; + wire [31:0] b2m_fsm_addressNext; + wire [26:0] b2m_fsm_bytesLeftNext; + wire b2m_fsm_isFinalCmd; + reg [7:0] b2m_fsm_beatCounter; + reg b2m_fsm_sel_valid_regNext; + wire b2m_fsm_s0; + reg b2m_fsm_s1; + reg b2m_fsm_s2; + wire when_DmaSg_l986; + wire [13:0] _zz_b2m_fsm_sel_bytesInBurst; + wire [25:0] _zz_b2m_fsm_sel_bytesInBurst_1; + wire [11:0] _zz_b2m_fsm_sel_bytesInBurst_2; + wire b2m_fsm_fifoCompletion; + wire when_DmaSg_l996; + wire when_DmaSg_l1001; + reg b2m_fsm_toggle; + wire when_DmaSg_l1013; + wire [10:0] b2m_fsm_fetch_context_ptr; + wire b2m_fsm_fetch_context_toggle; + wire when_DmaSg_l1033; + wire [10:0] b2m_fsm_aggregate_context_ptr; + wire b2m_fsm_aggregate_context_toggle; + wire [11:0] _zz_b2m_fsm_aggregate_context_ptr; + wire memory_core_io_reads_1_rsp_s2mPipe_valid; + reg memory_core_io_reads_1_rsp_s2mPipe_ready; + wire [127:0] memory_core_io_reads_1_rsp_s2mPipe_payload_data; + wire [15:0] memory_core_io_reads_1_rsp_s2mPipe_payload_mask; + wire [11:0] memory_core_io_reads_1_rsp_s2mPipe_payload_context; + reg memory_core_io_reads_1_rsp_rValidN; + reg [127:0] memory_core_io_reads_1_rsp_rData_data; + reg [15:0] memory_core_io_reads_1_rsp_rData_mask; + reg [11:0] memory_core_io_reads_1_rsp_rData_context; + wire when_Stream_l445; + reg b2m_fsm_aggregate_memoryPort_valid; + wire b2m_fsm_aggregate_memoryPort_ready; + wire [127:0] b2m_fsm_aggregate_memoryPort_payload_data; + wire [15:0] b2m_fsm_aggregate_memoryPort_payload_mask; + wire [11:0] b2m_fsm_aggregate_memoryPort_payload_context; + reg b2m_fsm_aggregate_first; + wire b2m_fsm_aggregate_memoryPort_fire; + wire when_DmaSg_l1050; + wire [3:0] b2m_fsm_aggregate_bytesToSkip; + wire [15:0] b2m_fsm_aggregate_bytesToSkipMask; + reg _zz_io_flush; + wire [3:0] b2m_fsm_cmd_maskFirstTrigger; + wire [3:0] b2m_fsm_cmd_maskLastTriggerComb; + reg [3:0] b2m_fsm_cmd_maskLastTriggerReg; + reg [15:0] b2m_fsm_cmd_maskLast; + wire [15:0] b2m_fsm_cmd_maskFirst; + wire b2m_fsm_cmd_enoughAggregation; + wire io_write_cmd_fire; + reg io_write_cmd_payload_first; + wire b2m_fsm_cmd_doPtrIncr; + wire [11:0] b2m_fsm_cmd_context_length; + wire b2m_fsm_cmd_context_doPacketSync; + wire when_DmaSg_l1102; + wire [11:0] b2m_rsp_context_length; + wire b2m_rsp_context_doPacketSync; + wire [12:0] _zz_b2m_rsp_context_length; + wire io_write_rsp_fire; + wire when_DmaSg_l1116; + wire [1:0] _zz_ll_arbiter_head; + wire _zz_ll_arbiter_head_1; + wire ll_arbiter_head; + wire ll_arbiter_isJustASink; + wire ll_arbiter_doDescriptorStall; + wire ll_arbiter_onSgStream; + reg ll_cmd_valid; + wire when_DmaSg_l1149; + reg ll_cmd_oh_0; + reg ll_cmd_oh_1; + wire when_DmaSg_l1148; + reg [31:0] ll_cmd_ptr; + wire when_DmaSg_l1148_1; + reg [31:0] ll_cmd_ptrNext; + wire when_DmaSg_l1148_2; + reg [26:0] ll_cmd_bytesDone; + wire when_DmaSg_l1148_3; + reg ll_cmd_endOfPacket; + wire when_DmaSg_l1154; + reg ll_cmd_isJustASink; + wire when_DmaSg_l1155; + reg ll_cmd_doDescriptorStall; + wire when_DmaSg_l1156; + reg ll_cmd_onSgStream; + reg ll_cmd_readFired; + reg ll_cmd_writeFired; + wire when_DmaSg_l1160; + wire when_DmaSg_l1161; + wire when_DmaSg_l1169; + wire when_DmaSg_l1169_1; + wire when_DmaSg_l1177; + wire [0:0] ll_cmd_context_channel; + wire [3:0] ll_cmd_writeMaskSplit_0; + wire [3:0] ll_cmd_writeMaskSplit_1; + wire [3:0] ll_cmd_writeMaskSplit_2; + wire [3:0] ll_cmd_writeMaskSplit_3; + wire [31:0] ll_cmd_writeDataSplit_0; + wire [31:0] ll_cmd_writeDataSplit_1; + wire [31:0] ll_cmd_writeDataSplit_2; + wire [31:0] ll_cmd_writeDataSplit_3; + wire io_sgRead_cmd_fire; + wire io_sgWrite_cmd_fire; + wire [0:0] ll_readRsp_context_channel; + wire [1:0] _zz_ll_readRsp_oh_0; + wire ll_readRsp_oh_0; + wire ll_readRsp_oh_1; + reg [0:0] ll_readRsp_beatCounter; + reg ll_readRsp_completed; + wire io_sgRead_rsp_fire; + wire when_DmaSg_l1248; + wire when_DmaSg_l1248_1; + wire when_DmaSg_l1248_2; + wire when_DmaSg_l1248_3; + wire when_DmaSg_l1248_4; + wire when_DmaSg_l1248_5; + wire when_DmaSg_l1248_6; + wire when_DmaSg_l1271; + wire [0:0] ll_writeRsp_context_channel; + wire [1:0] _zz_ll_writeRsp_oh_0; + wire ll_writeRsp_oh_0; + wire ll_writeRsp_oh_1; + wire io_sgWrite_rsp_fire; + reg when_BusSlaveFactory_l377; + wire when_BusSlaveFactory_l379; + reg when_BusSlaveFactory_l377_1; + wire when_BusSlaveFactory_l379_1; + reg when_BusSlaveFactory_l377_2; + wire when_BusSlaveFactory_l379_2; + reg when_BusSlaveFactory_l377_3; + wire when_BusSlaveFactory_l379_3; + reg when_BusSlaveFactory_l341; + wire when_BusSlaveFactory_l347; + reg when_BusSlaveFactory_l341_1; + wire when_BusSlaveFactory_l347_1; + reg when_BusSlaveFactory_l341_2; + wire when_BusSlaveFactory_l347_2; + reg when_BusSlaveFactory_l341_3; + wire when_BusSlaveFactory_l347_3; + reg when_BusSlaveFactory_l377_4; + wire when_BusSlaveFactory_l379_4; + reg when_BusSlaveFactory_l377_5; + wire when_BusSlaveFactory_l379_5; + reg when_BusSlaveFactory_l377_6; + wire when_BusSlaveFactory_l379_6; + reg when_BusSlaveFactory_l377_7; + wire when_BusSlaveFactory_l379_7; + reg when_BusSlaveFactory_l341_4; + wire when_BusSlaveFactory_l347_4; + reg when_BusSlaveFactory_l341_5; + wire when_BusSlaveFactory_l347_5; + reg when_BusSlaveFactory_l341_6; + wire when_BusSlaveFactory_l347_6; + wire when_Apb3SlaveFactory_l81; + wire when_Apb3SlaveFactory_l81_1; + wire when_Apb3SlaveFactory_l81_2; + wire when_Apb3SlaveFactory_l81_3; + function [15:0] zz_io_sgWrite_cmd_payload_fragment_mask(input dummy); + begin + zz_io_sgWrite_cmd_payload_fragment_mask[7 : 4] = 4'b0000; + zz_io_sgWrite_cmd_payload_fragment_mask[11 : 8] = 4'b0000; + zz_io_sgWrite_cmd_payload_fragment_mask[15 : 12] = 4'b0000; + zz_io_sgWrite_cmd_payload_fragment_mask[3 : 0] = 4'b1111; + end + endfunction + wire [15:0] _zz_1; + + assign _zz_channels_0_bytesProbe_value = (channels_0_bytesProbe_value + _zz_channels_0_bytesProbe_value_1); + assign _zz_channels_0_bytesProbe_value_1 = {15'd0, channels_0_bytesProbe_incr_payload}; + assign _zz_channels_0_fifo_pop_withOverride_backupNext = (channels_0_fifo_pop_withOverride_backup + channels_0_fifo_pop_bytesIncr_value); + assign _zz_channels_0_fifo_pop_withOverride_exposed = (channels_0_fifo_pop_withOverride_exposed - channels_0_fifo_pop_bytesDecr_value); + assign _zz_channels_0_pop_b2m_selfFlush = {13'd0, channels_0_fifo_pop_bytes}; + assign _zz_channels_0_pop_b2m_request = {2'd0, channels_0_pop_b2m_bytePerBurst}; + assign _zz_channels_0_pop_b2m_request_2 = (channels_0_fifo_words >>> 1'd1); + assign _zz_channels_0_pop_b2m_request_1 = {1'd0, _zz_channels_0_pop_b2m_request_2}; + assign _zz_channels_0_pop_b2m_memPending = (channels_0_pop_b2m_memPending + _zz_channels_0_pop_b2m_memPending_1); + assign _zz_channels_0_pop_b2m_memPending_2 = channels_0_pop_b2m_memPendingInc; + assign _zz_channels_0_pop_b2m_memPending_1 = {3'd0, _zz_channels_0_pop_b2m_memPending_2}; + assign _zz_channels_0_pop_b2m_memPending_4 = channels_0_pop_b2m_memRsp; + assign _zz_channels_0_pop_b2m_memPending_3 = {3'd0, _zz_channels_0_pop_b2m_memPending_4}; + assign _zz_channels_0_fifo_push_available = (channels_0_fifo_push_available + channels_0_fifo_pop_ptrIncr_value_regNext); + assign _zz_channels_1_bytesProbe_value = (channels_1_bytesProbe_value + _zz_channels_1_bytesProbe_value_1); + assign _zz_channels_1_bytesProbe_value_1 = {15'd0, channels_1_bytesProbe_incr_payload}; + assign _zz_channels_1_fifo_pop_withoutOverride_exposed = (channels_1_fifo_pop_withoutOverride_exposed + channels_1_fifo_pop_bytesIncr_value); + assign _zz_channels_1_push_m2b_memPending = (channels_1_push_m2b_memPending + _zz_channels_1_push_m2b_memPending_1); + assign _zz_channels_1_push_m2b_memPending_2 = channels_1_push_m2b_memPendingIncr; + assign _zz_channels_1_push_m2b_memPending_1 = {3'd0, _zz_channels_1_push_m2b_memPending_2}; + assign _zz_channels_1_push_m2b_memPending_4 = channels_1_push_m2b_memPendingDecr; + assign _zz_channels_1_push_m2b_memPending_3 = {3'd0, _zz_channels_1_push_m2b_memPending_4}; + assign _zz_channels_1_push_m2b_loadRequest_1 = (channels_1_push_m2b_bytePerBurst >>> 2'd3); + assign _zz_channels_1_push_m2b_loadRequest = {2'd0, _zz_channels_1_push_m2b_loadRequest_1}; + assign _zz_when_DmaSg_l486 = {14'd0, channels_1_push_m2b_bytePerBurst}; + assign _zz_channels_1_fifo_push_available = (channels_1_fifo_push_available + channels_1_fifo_pop_ptrIncr_value_regNext); + assign _zz_s2b_0_cmd_byteCount_8 = (_zz_s2b_0_cmd_byteCount_9 + _zz_s2b_0_cmd_byteCount_11); + assign _zz_s2b_0_cmd_byteCount_15 = {s2b_0_cmd_sinkHalted_payload_mask[7],s2b_0_cmd_sinkHalted_payload_mask[6]}; + assign _zz_s2b_0_cmd_byteCount_14 = {1'd0, _zz_s2b_0_cmd_byteCount_15}; + assign _zz__zz_m2b_cmd_s0_priority_chosenOh_2 = (_zz_m2b_cmd_s0_priority_chosenOh_1 - _zz__zz_m2b_cmd_s0_priority_chosenOh_2_1); + assign _zz__zz_m2b_cmd_s0_priority_chosenOh_2_2 = _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3; + assign _zz__zz_m2b_cmd_s0_priority_chosenOh_2_1 = {1'd0, _zz__zz_m2b_cmd_s0_priority_chosenOh_2_2}; + assign _zz_m2b_cmd_s0_length = ((_zz_m2b_cmd_s0_length_1 < m2b_cmd_s0_bytesLeft) ? _zz_m2b_cmd_s0_length_2 : m2b_cmd_s0_bytesLeft); + assign _zz_m2b_cmd_s0_length_1 = {14'd0, m2b_cmd_s0_lengthHead}; + assign _zz_m2b_cmd_s0_length_2 = {14'd0, m2b_cmd_s0_lengthHead}; + assign _zz_m2b_cmd_s0_lastBurst = {14'd0, m2b_cmd_s0_length}; + assign _zz_m2b_cmd_s1_context_stop = (m2b_cmd_s1_address + _zz_m2b_cmd_s1_context_stop_1); + assign _zz_m2b_cmd_s1_context_stop_1 = {20'd0, m2b_cmd_s1_length}; + assign _zz_m2b_cmd_s1_addressNext = (m2b_cmd_s1_address + _zz_m2b_cmd_s1_addressNext_1); + assign _zz_m2b_cmd_s1_addressNext_1 = {20'd0, m2b_cmd_s1_length}; + assign _zz_m2b_cmd_s1_byteLeftNext = (m2b_cmd_s1_bytesLeft - _zz_m2b_cmd_s1_byteLeftNext_1); + assign _zz_m2b_cmd_s1_byteLeftNext_1 = {14'd0, m2b_cmd_s1_length}; + assign _zz_m2b_cmd_s1_fifoPushDecr = ({1'b0,(_zz_m2b_cmd_s1_fifoPushDecr_1 | 12'h00f)} + _zz_m2b_cmd_s1_fifoPushDecr_4); + assign _zz_m2b_cmd_s1_fifoPushDecr_1 = (_zz_m2b_cmd_s1_fifoPushDecr_2 + io_read_cmd_payload_fragment_length); + assign _zz_m2b_cmd_s1_fifoPushDecr_3 = m2b_cmd_s1_address[3 : 0]; + assign _zz_m2b_cmd_s1_fifoPushDecr_2 = {8'd0, _zz_m2b_cmd_s1_fifoPushDecr_3}; + assign _zz_m2b_cmd_s1_fifoPushDecr_5 = {1'b0,1'b1}; + assign _zz_m2b_cmd_s1_fifoPushDecr_4 = {11'd0, _zz_m2b_cmd_s1_fifoPushDecr_5}; + assign _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2 = (_zz_b2m_fsm_arbiter_logic_priority_chosenOh_1 - _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_1); + assign _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_2 = _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3; + assign _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_1 = {1'd0, _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_2}; + assign _zz_when = 1'b1; + assign _zz_b2m_fsm_bytesInBurstP1_1 = {1'b0,1'b1}; + assign _zz_b2m_fsm_bytesInBurstP1 = {11'd0, _zz_b2m_fsm_bytesInBurstP1_1}; + assign _zz_b2m_fsm_addressNext = {19'd0, b2m_fsm_bytesInBurstP1}; + assign _zz_b2m_fsm_bytesLeftNext_1 = {1'b0,b2m_fsm_bytesInBurstP1}; + assign _zz_b2m_fsm_bytesLeftNext = {13'd0, _zz_b2m_fsm_bytesLeftNext_1}; + assign _zz__zz_b2m_fsm_sel_bytesInBurst_1 = {12'd0, _zz_b2m_fsm_sel_bytesInBurst}; + assign _zz__zz_b2m_fsm_sel_bytesInBurst_1_1 = {12'd0, _zz_b2m_fsm_sel_bytesInBurst}; + assign _zz__zz_b2m_fsm_sel_bytesInBurst_2 = b2m_fsm_sel_address[11:0]; + assign _zz_b2m_fsm_sel_bytesInBurst_3 = ((_zz_b2m_fsm_sel_bytesInBurst_1 < _zz_b2m_fsm_sel_bytesInBurst_4) ? _zz_b2m_fsm_sel_bytesInBurst_1 : _zz_b2m_fsm_sel_bytesInBurst_5); + assign _zz_b2m_fsm_sel_bytesInBurst_4 = {14'd0, _zz_b2m_fsm_sel_bytesInBurst_2}; + assign _zz_b2m_fsm_sel_bytesInBurst_5 = {14'd0, _zz_b2m_fsm_sel_bytesInBurst_2}; + assign _zz_b2m_fsm_fifoCompletion = {2'd0, b2m_fsm_sel_bytesInBurst}; + assign _zz_b2m_fsm_fifoCompletion_1 = (b2m_fsm_sel_bytesInFifo - 14'h0001); + assign _zz_b2m_fsm_beatCounter = (_zz_b2m_fsm_beatCounter_1 + b2m_fsm_sel_bytesInBurst); + assign _zz_b2m_fsm_beatCounter_2 = b2m_fsm_sel_address[3 : 0]; + assign _zz_b2m_fsm_beatCounter_1 = {8'd0, _zz_b2m_fsm_beatCounter_2}; + assign _zz_b2m_fsm_sel_ptr = (b2m_fsm_sel_ptr + 11'h002); + assign _zz_b2m_fsm_cmd_maskLastTriggerComb = b2m_fsm_sel_bytesInBurst[3:0]; + assign _zz_when_1 = 1'b1; + assign _zz_when_2 = 1'b1; + assign _zz__zz_ll_arbiter_head_1 = (_zz_ll_arbiter_head & (~ _zz__zz_ll_arbiter_head_1_1)); + assign _zz__zz_ll_arbiter_head_1_1 = (_zz_ll_arbiter_head - 2'b01); + assign _zz_ll_arbiter_head_2 = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_arbiter_isJustASink = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_arbiter_doDescriptorStall = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_arbiter_onSgStream = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_cmd_ptr = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_cmd_ptrNext = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_ll_cmd_endOfPacket = {_zz_ll_arbiter_head_1,channels_0_ll_requestLl}; + assign _zz_channels_0_channelStart = 1'b1; + assign _zz_channels_0_ctrl_kick = 1'b1; + assign _zz_channels_0_channelStart_1 = 1'b1; + assign _zz_channels_0_ll_sgStart = 1'b1; + assign _zz_channels_0_interrupts_completion_valid = 1'b0; + assign _zz_channels_0_interrupts_onChannelCompletion_valid = 1'b0; + assign _zz_channels_0_interrupts_onLinkedListUpdate_valid = 1'b0; + assign _zz_channels_0_interrupts_s2mPacket_valid = 1'b0; + assign _zz_channels_1_channelStart = 1'b1; + assign _zz_channels_1_ctrl_kick = 1'b1; + assign _zz_channels_1_channelStart_1 = 1'b1; + assign _zz_channels_1_ll_sgStart = 1'b1; + assign _zz_channels_1_interrupts_completion_valid = 1'b0; + assign _zz_channels_1_interrupts_onChannelCompletion_valid = 1'b0; + assign _zz_channels_1_interrupts_onLinkedListUpdate_valid = 1'b0; + assign _zz_io_ctrl_PRDATA = channels_0_ll_ptr; + assign _zz_io_ctrl_PRDATA_1 = channels_1_ll_ptr; + assign _zz_channels_0_fifo_push_ptrIncr_value_1 = ((when_DmaSg_l665 && (|s2b_0_cmd_sinkHalted_payload_mask)) ? 1'b1 : 1'b0); + assign _zz_channels_0_fifo_push_ptrIncr_value = {10'd0, _zz_channels_0_fifo_push_ptrIncr_value_1}; + assign _zz_channels_0_fifo_pop_bytesIncr_value_2 = (_zz_channels_0_fifo_pop_bytesIncr_value ? s2b_0_rsp_context_bytes : 4'b0000); + assign _zz_channels_0_fifo_pop_bytesIncr_value_1 = {10'd0, _zz_channels_0_fifo_pop_bytesIncr_value_2}; + assign _zz_channels_0_fifo_pop_ptrIncr_value_1 = ((b2m_fsm_cmd_doPtrIncr && 1'b1) ? 2'b10 : 2'b00); + assign _zz_channels_0_fifo_pop_ptrIncr_value = {9'd0, _zz_channels_0_fifo_pop_ptrIncr_value_1}; + assign _zz_channels_1_fifo_push_ptrIncr_value_2 = (_zz_channels_1_fifo_push_ptrIncr_value ? 2'b10 : 2'b00); + assign _zz_channels_1_fifo_push_ptrIncr_value_1 = {9'd0, _zz_channels_1_fifo_push_ptrIncr_value_2}; + assign _zz_channels_1_fifo_pop_bytesIncr_value_2 = (_zz_channels_1_fifo_pop_bytesIncr_value ? _zz_channels_1_fifo_pop_bytesIncr_value_3 : 5'h0); + assign _zz_channels_1_fifo_pop_bytesIncr_value_1 = {9'd0, _zz_channels_1_fifo_pop_bytesIncr_value_2}; + assign _zz_channels_1_fifo_pop_bytesIncr_value_3 = (m2b_writeRsp_context_loadByteInNextBeat + 5'h01); + assign _zz_channels_1_fifo_pop_ptrIncr_value_1 = ((b2s_0_cmd_channelsOh[0] && memory_core_io_reads_0_cmd_ready) ? 1'b1 : 1'b0); + assign _zz_channels_1_fifo_pop_ptrIncr_value = {10'd0, _zz_channels_1_fifo_pop_ptrIncr_value_1}; + assign _zz_s2b_0_cmd_byteCount_10 = {s2b_0_cmd_sinkHalted_payload_mask[2],{s2b_0_cmd_sinkHalted_payload_mask[1],s2b_0_cmd_sinkHalted_payload_mask[0]}}; + assign _zz_s2b_0_cmd_byteCount_12 = {s2b_0_cmd_sinkHalted_payload_mask[5],{s2b_0_cmd_sinkHalted_payload_mask[4],s2b_0_cmd_sinkHalted_payload_mask[3]}}; + assign _zz_s2b_0_cmd_firsts = io_inputs_0_payload_last_regNextWhen_5; + assign _zz_s2b_0_cmd_firsts_1 = {io_inputs_0_payload_last_regNextWhen_4,{io_inputs_0_payload_last_regNextWhen_3,{io_inputs_0_payload_last_regNextWhen_2,{io_inputs_0_payload_last_regNextWhen_1,io_inputs_0_payload_last_regNextWhen}}}}; + assign _zz_b2m_fsm_aggregate_bytesToSkipMask = 4'b1101; + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_1 = (! b2m_fsm_aggregate_first); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_2 = (b2m_fsm_aggregate_bytesToSkip <= 4'b1100); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_3 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1011)); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_4 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1010)); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_5 = {((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1001)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1000)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= _zz_b2m_fsm_aggregate_bytesToSkipMask_6)),{(_zz_b2m_fsm_aggregate_bytesToSkipMask_7 || _zz_b2m_fsm_aggregate_bytesToSkipMask_8),{_zz_b2m_fsm_aggregate_bytesToSkipMask_9,{_zz_b2m_fsm_aggregate_bytesToSkipMask_10,_zz_b2m_fsm_aggregate_bytesToSkipMask_11}}}}}}; + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_6 = 4'b0111; + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_7 = (! b2m_fsm_aggregate_first); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_8 = (b2m_fsm_aggregate_bytesToSkip <= 4'b0110); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_9 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0101)); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_10 = ((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0100)); + assign _zz_b2m_fsm_aggregate_bytesToSkipMask_11 = {((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0011)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0010)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0001)),((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b0000))}}}; + assign _zz_b2m_fsm_cmd_maskLast = 4'b1010; + assign _zz_b2m_fsm_cmd_maskLast_1 = (4'b1001 <= b2m_fsm_cmd_maskLastTriggerComb); + assign _zz_b2m_fsm_cmd_maskLast_2 = (4'b1000 <= b2m_fsm_cmd_maskLastTriggerComb); + assign _zz_b2m_fsm_cmd_maskLast_3 = {(4'b0111 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0110 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0101 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0100 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0011 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b0010 <= b2m_fsm_cmd_maskLastTriggerComb),{(_zz_b2m_fsm_cmd_maskLast_4 <= b2m_fsm_cmd_maskLastTriggerComb),(_zz_b2m_fsm_cmd_maskLast_5 <= b2m_fsm_cmd_maskLastTriggerComb)}}}}}}}; + assign _zz_b2m_fsm_cmd_maskLast_4 = 4'b0001; + assign _zz_b2m_fsm_cmd_maskLast_5 = 4'b0000; + assign _zz_b2m_fsm_cmd_maskFirst = 4'b1010; + assign _zz_b2m_fsm_cmd_maskFirst_1 = (b2m_fsm_cmd_maskFirstTrigger <= 4'b1001); + assign _zz_b2m_fsm_cmd_maskFirst_2 = (b2m_fsm_cmd_maskFirstTrigger <= 4'b1000); + assign _zz_b2m_fsm_cmd_maskFirst_3 = {(b2m_fsm_cmd_maskFirstTrigger <= 4'b0111),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0110),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0101),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0100),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0011),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b0010),{(b2m_fsm_cmd_maskFirstTrigger <= _zz_b2m_fsm_cmd_maskFirst_4),(b2m_fsm_cmd_maskFirstTrigger <= _zz_b2m_fsm_cmd_maskFirst_5)}}}}}}}; + assign _zz_b2m_fsm_cmd_maskFirst_4 = 4'b0001; + assign _zz_b2m_fsm_cmd_maskFirst_5 = 4'b0000; + EfxDMA_DmaMemoryCore memory_core ( + .io_writes_0_cmd_valid (s2b_0_cmd_sinkHalted_valid ), //i + .io_writes_0_cmd_ready (memory_core_io_writes_0_cmd_ready ), //o + .io_writes_0_cmd_payload_address (memory_core_io_writes_0_cmd_payload_address[9:0]), //i + .io_writes_0_cmd_payload_data (s2b_0_cmd_sinkHalted_payload_data[63:0] ), //i + .io_writes_0_cmd_payload_mask (s2b_0_cmd_sinkHalted_payload_mask[7:0] ), //i + .io_writes_0_cmd_payload_priority (channels_0_priority[1:0] ), //i + .io_writes_0_cmd_payload_context (memory_core_io_writes_0_cmd_payload_context[6:0]), //i + .io_writes_0_rsp_valid (memory_core_io_writes_0_rsp_valid ), //o + .io_writes_0_rsp_payload_context (memory_core_io_writes_0_rsp_payload_context[6:0]), //o + .io_writes_1_cmd_valid (io_read_rsp_valid ), //i + .io_writes_1_cmd_ready (memory_core_io_writes_1_cmd_ready ), //o + .io_writes_1_cmd_payload_address (memory_core_io_writes_1_cmd_payload_address[9:0]), //i + .io_writes_1_cmd_payload_data (io_read_rsp_payload_fragment_data[127:0] ), //i + .io_writes_1_cmd_payload_mask (memory_core_io_writes_1_cmd_payload_mask[15:0] ), //i + .io_writes_1_cmd_payload_context (memory_core_io_writes_1_cmd_payload_context[6:0]), //i + .io_writes_1_rsp_valid (memory_core_io_writes_1_rsp_valid ), //o + .io_writes_1_rsp_payload_context (memory_core_io_writes_1_rsp_payload_context[6:0]), //o + .io_reads_0_cmd_valid (memory_core_io_reads_0_cmd_valid ), //i + .io_reads_0_cmd_ready (memory_core_io_reads_0_cmd_ready ), //o + .io_reads_0_cmd_payload_address (memory_core_io_reads_0_cmd_payload_address[9:0] ), //i + .io_reads_0_cmd_payload_priority (channels_1_priority[1:0] ), //i + .io_reads_0_cmd_payload_context (memory_core_io_reads_0_cmd_payload_context[2:0] ), //i + .io_reads_0_rsp_valid (memory_core_io_reads_0_rsp_valid ), //o + .io_reads_0_rsp_ready (io_outputs_0_ready ), //i + .io_reads_0_rsp_payload_data (memory_core_io_reads_0_rsp_payload_data[63:0] ), //o + .io_reads_0_rsp_payload_mask (memory_core_io_reads_0_rsp_payload_mask[7:0] ), //o + .io_reads_0_rsp_payload_context (memory_core_io_reads_0_rsp_payload_context[2:0] ), //o + .io_reads_1_cmd_valid (b2m_fsm_sel_valid ), //i + .io_reads_1_cmd_ready (memory_core_io_reads_1_cmd_ready ), //o + .io_reads_1_cmd_payload_address (memory_core_io_reads_1_cmd_payload_address[9:0] ), //i + .io_reads_1_cmd_payload_context (memory_core_io_reads_1_cmd_payload_context[11:0]), //i + .io_reads_1_rsp_valid (memory_core_io_reads_1_rsp_valid ), //o + .io_reads_1_rsp_ready (memory_core_io_reads_1_rsp_rValidN ), //i + .io_reads_1_rsp_payload_data (memory_core_io_reads_1_rsp_payload_data[127:0] ), //o + .io_reads_1_rsp_payload_mask (memory_core_io_reads_1_rsp_payload_mask[15:0] ), //o + .io_reads_1_rsp_payload_context (memory_core_io_reads_1_rsp_payload_context[11:0]), //o + .clk (clk ), //i + .reset (reset ) //i + ); + EfxDMA_Aggregator b2m_fsm_aggregate_engine ( + .io_input_valid (b2m_fsm_aggregate_memoryPort_valid ), //i + .io_input_ready (b2m_fsm_aggregate_engine_io_input_ready ), //o + .io_input_payload_data (b2m_fsm_aggregate_memoryPort_payload_data[127:0] ), //i + .io_input_payload_mask (b2m_fsm_aggregate_engine_io_input_payload_mask[15:0]), //i + .io_output_data (b2m_fsm_aggregate_engine_io_output_data[127:0] ), //o + .io_output_mask (b2m_fsm_aggregate_engine_io_output_mask[15:0] ), //o + .io_output_enough (b2m_fsm_cmd_enoughAggregation ), //i + .io_output_consume (io_write_cmd_fire ), //i + .io_output_consumed (b2m_fsm_aggregate_engine_io_output_consumed ), //o + .io_output_lastByteUsed (b2m_fsm_cmd_maskLastTriggerReg[3:0] ), //i + .io_output_usedUntil (b2m_fsm_aggregate_engine_io_output_usedUntil[3:0] ), //o + .io_flush (b2m_fsm_aggregate_engine_io_flush ), //i + .io_offset (b2m_fsm_aggregate_engine_io_offset[3:0] ), //i + .io_burstLength (b2m_fsm_sel_bytesInBurst[11:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_s2b_0_cmd_byteCount_10) + 3'b000 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount; + 3'b001 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_1; + 3'b010 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_2; + 3'b011 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_3; + 3'b100 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_4; + 3'b101 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_5; + 3'b110 : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_6; + default : _zz_s2b_0_cmd_byteCount_9 = _zz_s2b_0_cmd_byteCount_7; + endcase + end + + always @(*) begin + case(_zz_s2b_0_cmd_byteCount_12) + 3'b000 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount; + 3'b001 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_1; + 3'b010 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_2; + 3'b011 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_3; + 3'b100 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_4; + 3'b101 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_5; + 3'b110 : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_6; + default : _zz_s2b_0_cmd_byteCount_11 = _zz_s2b_0_cmd_byteCount_7; + endcase + end + + always @(*) begin + case(_zz_s2b_0_cmd_byteCount_14) + 3'b000 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount; + 3'b001 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_1; + 3'b010 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_2; + 3'b011 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_3; + 3'b100 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_4; + 3'b101 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_5; + 3'b110 : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_6; + default : _zz_s2b_0_cmd_byteCount_13 = _zz_s2b_0_cmd_byteCount_7; + endcase + end + + always @(*) begin + case(_zz_m2b_cmd_s0_priority_masked) + 2'b00 : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_0; + 2'b01 : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_1; + 2'b10 : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_2; + default : _zz__zz_m2b_cmd_s0_priority_chosenOh_2_3 = m2b_cmd_s0_priority_roundRobins_3; + endcase + end + + always @(*) begin + case(_zz_b2m_fsm_arbiter_logic_priority_masked) + 2'b00 : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_0; + 2'b01 : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_1; + 2'b10 : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_2; + default : _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2_3 = b2m_fsm_arbiter_logic_priority_roundRobins_3; + endcase + end + + assign ctrl_readErrorFlag = 1'b0; + assign ctrl_writeErrorFlag = 1'b0; + assign io_ctrl_PREADY = 1'b1; + always @(*) begin + io_ctrl_PRDATA = 32'h0; + case(io_ctrl_PADDR) + 14'h002c : begin + io_ctrl_PRDATA[0 : 0] = channels_0_channelValid; + end + 14'h0054 : begin + io_ctrl_PRDATA[0 : 0] = channels_0_interrupts_completion_valid; + io_ctrl_PRDATA[2 : 2] = channels_0_interrupts_onChannelCompletion_valid; + io_ctrl_PRDATA[3 : 3] = channels_0_interrupts_onLinkedListUpdate_valid; + io_ctrl_PRDATA[4 : 4] = channels_0_interrupts_s2mPacket_valid; + end + 14'h0060 : begin + io_ctrl_PRDATA[26 : 0] = channels_0_bytesProbe_value; + end + 14'h00ac : begin + io_ctrl_PRDATA[0 : 0] = channels_1_channelValid; + end + 14'h00d4 : begin + io_ctrl_PRDATA[0 : 0] = channels_1_interrupts_completion_valid; + io_ctrl_PRDATA[2 : 2] = channels_1_interrupts_onChannelCompletion_valid; + io_ctrl_PRDATA[3 : 3] = channels_1_interrupts_onLinkedListUpdate_valid; + end + 14'h00e0 : begin + io_ctrl_PRDATA[26 : 0] = channels_1_bytesProbe_value; + end + default : begin + end + endcase + if(when_Apb3SlaveFactory_l81_1) begin + io_ctrl_PRDATA[31 : 0] = _zz_io_ctrl_PRDATA[31 : 0]; + end + if(when_Apb3SlaveFactory_l81_3) begin + io_ctrl_PRDATA[31 : 0] = _zz_io_ctrl_PRDATA_1[31 : 0]; + end + end + + assign ctrl_askWrite = ((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && io_ctrl_PWRITE); + assign ctrl_askRead = ((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && (! io_ctrl_PWRITE)); + assign ctrl_doWrite = (((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && io_ctrl_PREADY) && io_ctrl_PWRITE); + assign ctrl_doRead = (((io_ctrl_PSEL[0] && io_ctrl_PENABLE) && io_ctrl_PREADY) && (! io_ctrl_PWRITE)); + assign io_ctrl_PSLVERROR = ((ctrl_doWrite && ctrl_writeErrorFlag) || (ctrl_doRead && ctrl_readErrorFlag)); + always @(*) begin + channels_0_channelStart = 1'b0; + if(when_BusSlaveFactory_l377) begin + if(when_BusSlaveFactory_l379) begin + channels_0_channelStart = _zz_channels_0_channelStart[0]; + end + end + if(when_BusSlaveFactory_l377_2) begin + if(when_BusSlaveFactory_l379_2) begin + channels_0_channelStart = _zz_channels_0_channelStart_1[0]; + end + end + end + + always @(*) begin + channels_0_channelCompletion = 1'b0; + if(channels_0_channelValid) begin + if(channels_0_channelStop) begin + if(channels_0_readyToStop) begin + channels_0_channelCompletion = 1'b1; + end + end + end + end + + always @(*) begin + channels_0_descriptorStart = 1'b0; + if(channels_0_ctrl_kick) begin + channels_0_descriptorStart = 1'b1; + end + if(when_DmaSg_l318) begin + if(when_DmaSg_l320) begin + if(when_DmaSg_l322) begin + channels_0_descriptorStart = 1'b1; + end + end + end + end + + always @(*) begin + channels_0_descriptorCompletion = 1'b0; + if(channels_0_pop_b2m_packetSync) begin + if(when_DmaSg_l532) begin + if(channels_0_push_s2b_completionOnLast) begin + channels_0_descriptorCompletion = 1'b1; + end + end + end + if(when_DmaSg_l547) begin + channels_0_descriptorCompletion = 1'b1; + end + if(channels_0_channelValid) begin + if(channels_0_channelStop) begin + if(channels_0_readyToStop) begin + channels_0_descriptorCompletion = 1'b1; + end + end + end + end + + always @(*) begin + channels_0_readyToStop = 1'b1; + if(channels_0_ll_waitDone) begin + channels_0_readyToStop = 1'b0; + end + if(when_DmaSg_l563) begin + channels_0_readyToStop = 1'b0; + end + end + + always @(*) begin + channels_0_bytesProbe_incr_valid = 1'b0; + if(io_write_rsp_fire) begin + if(when_DmaSg_l1116) begin + channels_0_bytesProbe_incr_valid = 1'b1; + end + end + end + + always @(*) begin + channels_0_bytesProbe_incr_payload = 12'bxxxxxxxxxxxx; + if(io_write_rsp_fire) begin + if(when_DmaSg_l1116) begin + channels_0_bytesProbe_incr_payload = b2m_rsp_context_length; + end + end + end + + always @(*) begin + channels_0_ll_sgStart = 1'b0; + if(when_BusSlaveFactory_l377_3) begin + if(when_BusSlaveFactory_l379_3) begin + channels_0_ll_sgStart = _zz_channels_0_ll_sgStart[0]; + end + end + end + + assign channels_0_ll_requestLl = ((((channels_0_channelValid && channels_0_ll_valid) && (! channels_0_channelStop)) && (! channels_0_ll_waitDone)) && ((! channels_0_descriptorValid) || channels_0_ll_requireSync)); + always @(*) begin + channels_0_ll_descriptorUpdated = 1'b0; + if(when_DmaSg_l318) begin + if(when_DmaSg_l328) begin + channels_0_ll_descriptorUpdated = 1'b1; + end + end + end + + assign when_DmaSg_l318 = (((channels_0_ll_valid && channels_0_ll_waitDone) && channels_0_ll_writeDone) && channels_0_ll_readDone); + assign when_DmaSg_l320 = (! channels_0_ll_justASync); + assign when_DmaSg_l322 = (! channels_0_ll_gotDescriptorStall); + assign when_DmaSg_l328 = (! channels_0_ll_head); + assign channels_0_fifo_base = 11'h0; + assign channels_0_fifo_words = 11'h1ff; + assign channels_0_fifo_push_availableDecr = 11'h0; + assign channels_0_fifo_push_ptrWithBase = ((channels_0_fifo_base & (~ channels_0_fifo_words)) | (channels_0_fifo_push_ptr & channels_0_fifo_words)); + assign channels_0_fifo_pop_ptrWithBase = ((channels_0_fifo_base & (~ channels_0_fifo_words)) | (channels_0_fifo_pop_ptr & channels_0_fifo_words)); + assign channels_0_fifo_pop_empty = (channels_0_fifo_pop_ptr == channels_0_fifo_push_ptr); + assign channels_0_fifo_pop_withOverride_backupNext = (_zz_channels_0_fifo_pop_withOverride_backupNext - channels_0_fifo_pop_bytesDecr_value); + always @(*) begin + channels_0_fifo_pop_withOverride_load = 1'b0; + if(when_DmaSg_l457) begin + channels_0_fifo_pop_withOverride_load = 1'b1; + end + end + + always @(*) begin + channels_0_fifo_pop_withOverride_unload = 1'b0; + if(channels_0_pop_b2m_packetSync) begin + channels_0_fifo_pop_withOverride_unload = 1'b1; + end + end + + assign when_DmaSg_l409 = (channels_0_channelStart || channels_0_fifo_pop_withOverride_unload); + assign channels_0_fifo_pop_bytes = channels_0_fifo_pop_withOverride_exposed; + assign channels_0_fifo_empty = (channels_0_fifo_push_ptr == channels_0_fifo_pop_ptr); + always @(*) begin + channels_0_push_s2b_packetEvent = 1'b0; + if(when_DmaSg_l679) begin + channels_0_push_s2b_packetEvent = 1'b1; + end + end + + assign when_DmaSg_l457 = (channels_0_push_s2b_packetEvent && channels_0_push_s2b_completionOnLast); + assign channels_0_pop_b2m_bytePerBurst = 12'h3ff; + always @(*) begin + channels_0_pop_b2m_fire = 1'b0; + if(when_DmaSg_l935) begin + if(_zz_when[0]) begin + channels_0_pop_b2m_fire = 1'b1; + end + end + end + + always @(*) begin + channels_0_pop_b2m_packetSync = 1'b0; + if(when_DmaSg_l523) begin + if(channels_0_pop_b2m_packet) begin + channels_0_pop_b2m_packetSync = 1'b1; + end + end + if(io_write_rsp_fire) begin + if(when_DmaSg_l1116) begin + if(b2m_rsp_context_doPacketSync) begin + channels_0_pop_b2m_packetSync = 1'b1; + end + end + end + end + + assign when_DmaSg_l505 = (channels_0_channelStart || channels_0_pop_b2m_fire); + always @(*) begin + channels_0_pop_b2m_memRsp = 1'b0; + if(io_write_rsp_fire) begin + if(_zz_when_2[0]) begin + channels_0_pop_b2m_memRsp = 1'b1; + end + end + end + + assign channels_0_pop_b2m_selfFlush = (channels_0_pop_b2m_bytesLeft < _zz_channels_0_pop_b2m_selfFlush); + assign channels_0_pop_b2m_request = ((((((channels_0_descriptorValid && (! channels_0_channelStop)) && (! channels_0_pop_b2m_waitFinalRsp)) && channels_0_pop_memory) && ((_zz_channels_0_pop_b2m_request < channels_0_fifo_pop_bytes) || (((channels_0_fifo_push_available < _zz_channels_0_pop_b2m_request_1) || channels_0_pop_b2m_flush) || channels_0_pop_b2m_selfFlush))) && (channels_0_fifo_pop_bytes != 14'h0)) && (channels_0_pop_b2m_memPending != 4'b1111)); + always @(*) begin + channels_0_pop_b2m_memPendingInc = 1'b0; + if(when_DmaSg_l758_1) begin + if(when_DmaSg_l773_1) begin + channels_0_pop_b2m_memPendingInc = 1'b1; + end + end + end + + always @(*) begin + channels_0_pop_b2m_decrBytes = 14'h0; + if(b2m_fsm_s1) begin + if(when_DmaSg_l996) begin + channels_0_pop_b2m_decrBytes = {1'd0, b2m_fsm_bytesInBurstP1}; + end + end + end + + assign when_DmaSg_l523 = ((channels_0_pop_b2m_memPending == 4'b0000) && (channels_0_fifo_pop_bytes == 14'h0)); + assign when_DmaSg_l532 = (channels_0_descriptorValid && (! channels_0_push_memory)); + assign when_DmaSg_l536 = (! channels_0_pop_b2m_waitFinalRsp); + assign when_DmaSg_l547 = ((channels_0_descriptorValid && (channels_0_pop_b2m_memPending == 4'b0000)) && channels_0_pop_b2m_waitFinalRsp); + assign when_DmaSg_l563 = (channels_0_pop_b2m_memPending != 4'b0000); + assign channels_0_readyForChannelCompletion = 1'b1; + assign when_DmaSg_l575 = (! channels_0_descriptorValid); + always @(*) begin + _zz_when_DmaSg_l593 = 1'b1; + if(channels_0_ctrl_kick) begin + _zz_when_DmaSg_l593 = 1'b0; + end + if(channels_0_ll_valid) begin + _zz_when_DmaSg_l593 = 1'b0; + end + end + + assign when_DmaSg_l593 = (_zz_when_DmaSg_l593 && channels_0_readyForChannelCompletion); + assign channels_0_s2b_full = (channels_0_fifo_push_available < 11'h002); + assign when_DmaSg_l255 = (channels_0_descriptorValid && channels_0_descriptorCompletion); + assign when_DmaSg_l255_1 = (! channels_0_interrupts_completion_enable); + assign when_DmaSg_l255_2 = (channels_0_channelValid && channels_0_channelCompletion); + assign when_DmaSg_l255_3 = (! channels_0_interrupts_onChannelCompletion_enable); + assign when_DmaSg_l255_4 = (! channels_0_interrupts_onLinkedListUpdate_enable); + assign when_DmaSg_l255_5 = (! channels_0_interrupts_s2mPacket_enable); + assign when_DmaSg_l625 = (channels_0_channelStart || channels_0_descriptorStart); + always @(*) begin + channels_1_channelStart = 1'b0; + if(when_BusSlaveFactory_l377_4) begin + if(when_BusSlaveFactory_l379_4) begin + channels_1_channelStart = _zz_channels_1_channelStart[0]; + end + end + if(when_BusSlaveFactory_l377_6) begin + if(when_BusSlaveFactory_l379_6) begin + channels_1_channelStart = _zz_channels_1_channelStart_1[0]; + end + end + end + + always @(*) begin + channels_1_channelCompletion = 1'b0; + if(channels_1_channelValid) begin + if(channels_1_channelStop) begin + if(channels_1_readyToStop) begin + channels_1_channelCompletion = 1'b1; + end + end + end + end + + always @(*) begin + channels_1_descriptorStart = 1'b0; + if(channels_1_ctrl_kick) begin + channels_1_descriptorStart = 1'b1; + end + if(when_DmaSg_l318_1) begin + if(when_DmaSg_l320_1) begin + if(when_DmaSg_l322_1) begin + channels_1_descriptorStart = 1'b1; + end + end + end + end + + always @(*) begin + channels_1_descriptorCompletion = 1'b0; + if(when_DmaSg_l483) begin + channels_1_descriptorCompletion = 1'b1; + end + if(channels_1_channelValid) begin + if(channels_1_channelStop) begin + if(channels_1_readyToStop) begin + channels_1_descriptorCompletion = 1'b1; + end + end + end + end + + always @(*) begin + channels_1_readyToStop = 1'b1; + if(channels_1_ll_waitDone) begin + channels_1_readyToStop = 1'b0; + end + if(when_DmaSg_l562) begin + channels_1_readyToStop = 1'b0; + end + end + + always @(*) begin + channels_1_bytesProbe_incr_valid = 1'b0; + if(when_DmaSg_l874) begin + channels_1_bytesProbe_incr_valid = 1'b1; + end + end + + always @(*) begin + channels_1_bytesProbe_incr_payload = 12'bxxxxxxxxxxxx; + if(when_DmaSg_l874) begin + channels_1_bytesProbe_incr_payload = m2b_rsp_context_length; + end + end + + always @(*) begin + channels_1_ll_sgStart = 1'b0; + if(when_BusSlaveFactory_l377_7) begin + if(when_BusSlaveFactory_l379_7) begin + channels_1_ll_sgStart = _zz_channels_1_ll_sgStart[0]; + end + end + end + + assign channels_1_ll_requestLl = ((((channels_1_channelValid && channels_1_ll_valid) && (! channels_1_channelStop)) && (! channels_1_ll_waitDone)) && ((! channels_1_descriptorValid) || channels_1_ll_requireSync)); + always @(*) begin + channels_1_ll_descriptorUpdated = 1'b0; + if(when_DmaSg_l318_1) begin + if(when_DmaSg_l328_1) begin + channels_1_ll_descriptorUpdated = 1'b1; + end + end + end + + assign when_DmaSg_l318_1 = (((channels_1_ll_valid && channels_1_ll_waitDone) && channels_1_ll_writeDone) && channels_1_ll_readDone); + assign when_DmaSg_l320_1 = (! channels_1_ll_justASync); + assign when_DmaSg_l322_1 = (! channels_1_ll_gotDescriptorStall); + assign when_DmaSg_l328_1 = (! channels_1_ll_head); + assign channels_1_fifo_base = 11'h200; + assign channels_1_fifo_words = 11'h1ff; + always @(*) begin + channels_1_fifo_push_availableDecr = 11'h0; + if(m2b_cmd_s1_valid) begin + if(io_read_cmd_ready) begin + if(when_DmaSg_l828) begin + channels_1_fifo_push_availableDecr = {1'd0, m2b_cmd_s1_fifoPushDecr}; + end + end + end + end + + assign channels_1_fifo_push_ptrWithBase = ((channels_1_fifo_base & (~ channels_1_fifo_words)) | (channels_1_fifo_push_ptr & channels_1_fifo_words)); + assign channels_1_fifo_pop_ptrWithBase = ((channels_1_fifo_base & (~ channels_1_fifo_words)) | (channels_1_fifo_pop_ptr & channels_1_fifo_words)); + assign channels_1_fifo_pop_empty = (channels_1_fifo_pop_ptr == channels_1_fifo_push_ptr); + assign channels_1_fifo_pop_bytes = channels_1_fifo_pop_withoutOverride_exposed; + assign channels_1_fifo_empty = (channels_1_fifo_push_ptr == channels_1_fifo_pop_ptr); + assign channels_1_push_m2b_bytePerBurst = 12'h3ff; + always @(*) begin + channels_1_push_m2b_memPendingIncr = 1'b0; + if(when_DmaSg_l758) begin + if(when_DmaSg_l773) begin + channels_1_push_m2b_memPendingIncr = 1'b1; + end + end + end + + always @(*) begin + channels_1_push_m2b_memPendingDecr = 1'b0; + if(when_DmaSg_l893) begin + channels_1_push_m2b_memPendingDecr = 1'b1; + end + end + + always @(*) begin + channels_1_push_m2b_loadRequest = (((((channels_1_descriptorValid && (! channels_1_channelStop)) && (! channels_1_push_m2b_loadDone)) && channels_1_push_memory) && (_zz_channels_1_push_m2b_loadRequest < channels_1_fifo_push_available)) && (channels_1_push_m2b_memPending != 4'b1111)); + if(when_DmaSg_l486) begin + channels_1_push_m2b_loadRequest = 1'b0; + end + end + + always @(*) begin + channels_1_pop_b2s_veryLastTrigger = 1'b0; + if(when_DmaSg_l847) begin + if(when_DmaSg_l848) begin + channels_1_pop_b2s_veryLastTrigger = 1'b1; + end + end + end + + assign when_DmaSg_l474 = (channels_1_pop_b2s_veryLastTrigger && channels_1_pop_b2s_last); + assign when_DmaSg_l483 = ((((channels_1_descriptorValid && (! channels_1_pop_memory)) && channels_1_push_memory) && channels_1_push_m2b_loadDone) && (channels_1_push_m2b_memPending == 4'b0000)); + assign when_DmaSg_l486 = (((! channels_1_pop_memory) && channels_1_pop_b2s_veryLastValid) && (channels_1_push_m2b_bytesLeft <= _zz_when_DmaSg_l486)); + assign when_DmaSg_l562 = (channels_1_push_m2b_memPending != 4'b0000); + always @(*) begin + channels_1_readyForChannelCompletion = 1'b1; + if(when_DmaSg_l566) begin + channels_1_readyForChannelCompletion = 1'b0; + end + end + + assign when_DmaSg_l566 = ((! channels_1_pop_memory) && (! channels_1_fifo_pop_empty)); + assign when_DmaSg_l575_1 = (! channels_1_descriptorValid); + always @(*) begin + _zz_when_DmaSg_l593_1 = 1'b1; + if(channels_1_ctrl_kick) begin + _zz_when_DmaSg_l593_1 = 1'b0; + end + if(channels_1_ll_valid) begin + _zz_when_DmaSg_l593_1 = 1'b0; + end + end + + assign when_DmaSg_l593_1 = (_zz_when_DmaSg_l593_1 && channels_1_readyForChannelCompletion); + assign channels_1_s2b_full = (channels_1_fifo_push_available < 11'h002); + assign when_DmaSg_l255_6 = (channels_1_descriptorValid && channels_1_descriptorCompletion); + assign when_DmaSg_l255_7 = (! channels_1_interrupts_completion_enable); + assign when_DmaSg_l255_8 = (channels_1_channelValid && channels_1_channelCompletion); + assign when_DmaSg_l255_9 = (! channels_1_interrupts_onChannelCompletion_enable); + assign when_DmaSg_l255_10 = (! channels_1_interrupts_onLinkedListUpdate_enable); + assign when_DmaSg_l625_1 = (channels_1_channelStart || channels_1_descriptorStart); + assign io_inputs_0_fire = (io_inputs_0_valid && io_inputs_0_ready); + assign when_package_l12 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0000)); + assign when_package_l12_1 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0001)); + assign when_package_l12_2 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0010)); + assign when_package_l12_3 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0011)); + assign when_package_l12_4 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0100)); + assign when_package_l12_5 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0101)); + assign when_package_l12_6 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0110)); + assign when_package_l12_7 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b0111)); + assign when_package_l12_8 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1000)); + assign when_package_l12_9 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1001)); + assign when_package_l12_10 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1010)); + assign when_package_l12_11 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1011)); + assign when_package_l12_12 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1100)); + assign when_package_l12_13 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1101)); + assign when_package_l12_14 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1110)); + assign when_package_l12_15 = (io_inputs_0_fire && (io_inputs_0_payload_sink == 4'b1111)); + assign s2b_0_cmd_firsts = {io_inputs_0_payload_last_regNextWhen_15,{io_inputs_0_payload_last_regNextWhen_14,{io_inputs_0_payload_last_regNextWhen_13,{io_inputs_0_payload_last_regNextWhen_12,{io_inputs_0_payload_last_regNextWhen_11,{io_inputs_0_payload_last_regNextWhen_10,{io_inputs_0_payload_last_regNextWhen_9,{io_inputs_0_payload_last_regNextWhen_8,{io_inputs_0_payload_last_regNextWhen_7,{io_inputs_0_payload_last_regNextWhen_6,{_zz_s2b_0_cmd_firsts,_zz_s2b_0_cmd_firsts_1}}}}}}}}}}}; + assign s2b_0_cmd_first = s2b_0_cmd_firsts[io_inputs_0_payload_sink]; + assign s2b_0_cmd_channelsOh = ((((channels_0_channelValid && (s2b_0_cmd_first || (! channels_0_push_s2b_waitFirst))) && (! channels_0_push_memory)) && 1'b1) && (io_inputs_0_payload_sink == 4'b0000)); + assign s2b_0_cmd_noHit = (! (|s2b_0_cmd_channelsOh)); + assign s2b_0_cmd_channelsFull = (channels_0_s2b_full || (channels_0_push_s2b_packetLock && io_inputs_0_payload_last)); + always @(*) begin + io_inputs_0_thrown_valid = io_inputs_0_valid; + if(s2b_0_cmd_noHit) begin + io_inputs_0_thrown_valid = 1'b0; + end + end + + always @(*) begin + io_inputs_0_ready = io_inputs_0_thrown_ready; + if(s2b_0_cmd_noHit) begin + io_inputs_0_ready = 1'b1; + end + end + + assign io_inputs_0_thrown_payload_data = io_inputs_0_payload_data; + assign io_inputs_0_thrown_payload_mask = io_inputs_0_payload_mask; + assign io_inputs_0_thrown_payload_sink = io_inputs_0_payload_sink; + assign io_inputs_0_thrown_payload_last = io_inputs_0_payload_last; + assign _zz_io_inputs_0_thrown_ready = (! (|(s2b_0_cmd_channelsOh & s2b_0_cmd_channelsFull))); + assign s2b_0_cmd_sinkHalted_valid = (io_inputs_0_thrown_valid && _zz_io_inputs_0_thrown_ready); + assign io_inputs_0_thrown_ready = (s2b_0_cmd_sinkHalted_ready && _zz_io_inputs_0_thrown_ready); + assign s2b_0_cmd_sinkHalted_payload_data = io_inputs_0_thrown_payload_data; + assign s2b_0_cmd_sinkHalted_payload_mask = io_inputs_0_thrown_payload_mask; + assign s2b_0_cmd_sinkHalted_payload_sink = io_inputs_0_thrown_payload_sink; + assign s2b_0_cmd_sinkHalted_payload_last = io_inputs_0_thrown_payload_last; + assign _zz_s2b_0_cmd_byteCount = 4'b0000; + assign _zz_s2b_0_cmd_byteCount_1 = 4'b0001; + assign _zz_s2b_0_cmd_byteCount_2 = 4'b0001; + assign _zz_s2b_0_cmd_byteCount_3 = 4'b0010; + assign _zz_s2b_0_cmd_byteCount_4 = 4'b0001; + assign _zz_s2b_0_cmd_byteCount_5 = 4'b0010; + assign _zz_s2b_0_cmd_byteCount_6 = 4'b0010; + assign _zz_s2b_0_cmd_byteCount_7 = 4'b0011; + assign s2b_0_cmd_byteCount = (_zz_s2b_0_cmd_byteCount_8 + _zz_s2b_0_cmd_byteCount_13); + assign s2b_0_cmd_context_channel = s2b_0_cmd_channelsOh; + assign s2b_0_cmd_context_bytes = s2b_0_cmd_byteCount; + assign s2b_0_cmd_context_flush = io_inputs_0_payload_last; + assign s2b_0_cmd_context_packet = io_inputs_0_payload_last; + assign s2b_0_cmd_sinkHalted_ready = memory_core_io_writes_0_cmd_ready; + assign memory_core_io_writes_0_cmd_payload_address = channels_0_fifo_push_ptrWithBase[9:0]; + assign memory_core_io_writes_0_cmd_payload_context = {s2b_0_cmd_context_packet,{s2b_0_cmd_context_flush,{s2b_0_cmd_context_bytes,s2b_0_cmd_context_channel}}}; + assign memory_core_io_writes_0_cmd_fire = (s2b_0_cmd_sinkHalted_valid && memory_core_io_writes_0_cmd_ready); + assign when_DmaSg_l665 = (s2b_0_cmd_channelsOh[0] && memory_core_io_writes_0_cmd_fire); + assign _zz_s2b_0_rsp_context_channel = memory_core_io_writes_0_rsp_payload_context; + assign s2b_0_rsp_context_channel = _zz_s2b_0_rsp_context_channel[0 : 0]; + assign s2b_0_rsp_context_bytes = _zz_s2b_0_rsp_context_channel[4 : 1]; + assign s2b_0_rsp_context_flush = _zz_s2b_0_rsp_context_channel[5]; + assign s2b_0_rsp_context_packet = _zz_s2b_0_rsp_context_channel[6]; + assign _zz_channels_0_fifo_pop_bytesIncr_value = (memory_core_io_writes_0_rsp_valid && s2b_0_rsp_context_channel[0]); + assign when_DmaSg_l679 = (_zz_channels_0_fifo_pop_bytesIncr_value && s2b_0_rsp_context_packet); + assign when_DmaSg_l681 = (_zz_channels_0_fifo_pop_bytesIncr_value && s2b_0_rsp_context_flush); + assign when_DmaSg_l682 = (_zz_channels_0_fifo_pop_bytesIncr_value && s2b_0_rsp_context_packet); + assign b2s_0_cmd_channelsOh = (((channels_1_channelValid && (! channels_1_pop_memory)) && 1'b1) && (! channels_1_fifo_pop_empty)); + assign b2s_0_cmd_veryLastPtr = channels_1_pop_b2s_veryLastPtr; + assign b2s_0_cmd_address = channels_1_fifo_pop_ptrWithBase; + assign b2s_0_cmd_context_channel = b2s_0_cmd_channelsOh; + assign b2s_0_cmd_context_veryLast = ((channels_1_pop_b2s_veryLastValid && (b2s_0_cmd_address[10 : 1] == b2s_0_cmd_veryLastPtr[10 : 1])) && (b2s_0_cmd_address[0 : 0] == 1'b1)); + assign b2s_0_cmd_context_endPacket = channels_1_pop_b2s_veryLastEndPacket; + assign memory_core_io_reads_0_cmd_valid = (|b2s_0_cmd_channelsOh); + assign memory_core_io_reads_0_cmd_payload_address = b2s_0_cmd_address[9:0]; + assign memory_core_io_reads_0_cmd_payload_context = {b2s_0_cmd_context_endPacket,{b2s_0_cmd_context_veryLast,b2s_0_cmd_context_channel}}; + assign _zz_b2s_0_rsp_context_channel = memory_core_io_reads_0_rsp_payload_context; + assign b2s_0_rsp_context_channel = _zz_b2s_0_rsp_context_channel[0 : 0]; + assign b2s_0_rsp_context_veryLast = _zz_b2s_0_rsp_context_channel[1]; + assign b2s_0_rsp_context_endPacket = _zz_b2s_0_rsp_context_channel[2]; + assign io_outputs_0_valid = memory_core_io_reads_0_rsp_valid; + assign io_outputs_0_payload_data = memory_core_io_reads_0_rsp_payload_data; + assign io_outputs_0_payload_mask = memory_core_io_reads_0_rsp_payload_mask; + assign io_outputs_0_payload_sink = channels_1_pop_b2s_sinkId; + assign io_outputs_0_payload_last = (b2s_0_rsp_context_veryLast && b2s_0_rsp_context_endPacket); + assign io_outputs_0_fire = (io_outputs_0_valid && io_outputs_0_ready); + assign when_DmaSg_l725 = (io_outputs_0_fire && b2s_0_rsp_context_veryLast); + assign when_DmaSg_l726 = b2s_0_rsp_context_channel[0]; + assign _zz_m2b_cmd_s0_priority_masked = channels_1_priority; + assign m2b_cmd_s0_priority_masked = (channels_1_push_m2b_loadRequest && (channels_1_priority == _zz_m2b_cmd_s0_priority_masked)); + assign _zz_m2b_cmd_s0_priority_chosenOh = m2b_cmd_s0_priority_masked; + assign _zz_m2b_cmd_s0_priority_chosenOh_1 = {_zz_m2b_cmd_s0_priority_chosenOh,_zz_m2b_cmd_s0_priority_chosenOh}; + assign _zz_m2b_cmd_s0_priority_chosenOh_2 = (_zz_m2b_cmd_s0_priority_chosenOh_1 & (~ _zz__zz_m2b_cmd_s0_priority_chosenOh_2)); + assign m2b_cmd_s0_priority_chosenOh = (_zz_m2b_cmd_s0_priority_chosenOh_2[1 : 1] | _zz_m2b_cmd_s0_priority_chosenOh_2[0 : 0]); + assign m2b_cmd_s0_priority_weightLast = (channels_1_weight == m2b_cmd_s0_priority_counter); + assign m2b_cmd_s0_priority_contextNext = (m2b_cmd_s0_priority_weightLast ? m2b_cmd_s0_priority_chosenOh[0 : 0] : m2b_cmd_s0_priority_chosenOh); + assign when_DmaSg_l758 = (! m2b_cmd_s0_valid); + assign when_DmaSg_l760 = (|channels_1_push_m2b_loadRequest); + assign when_DmaSg_l763 = (2'b00 == _zz_m2b_cmd_s0_priority_masked); + assign when_DmaSg_l763_1 = (2'b01 == _zz_m2b_cmd_s0_priority_masked); + assign when_DmaSg_l763_2 = (2'b10 == _zz_m2b_cmd_s0_priority_masked); + assign when_DmaSg_l763_3 = (2'b11 == _zz_m2b_cmd_s0_priority_masked); + assign when_DmaSg_l773 = (channels_1_push_m2b_loadRequest && m2b_cmd_s0_priority_chosenOh[0]); + assign m2b_cmd_s0_address = channels_1_push_m2b_address; + assign m2b_cmd_s0_bytesLeft = channels_1_push_m2b_bytesLeft; + assign m2b_cmd_s0_readAddressBurstRange = m2b_cmd_s0_address[11 : 0]; + assign m2b_cmd_s0_lengthHead = ((~ m2b_cmd_s0_readAddressBurstRange) & channels_1_push_m2b_bytePerBurst); + assign m2b_cmd_s0_length = _zz_m2b_cmd_s0_length[11:0]; + assign m2b_cmd_s0_lastBurst = (m2b_cmd_s0_bytesLeft == _zz_m2b_cmd_s0_lastBurst); + assign m2b_cmd_s1_context_start = m2b_cmd_s1_address[3:0]; + assign m2b_cmd_s1_context_stop = _zz_m2b_cmd_s1_context_stop[3:0]; + assign m2b_cmd_s1_context_last = m2b_cmd_s1_lastBurst; + assign m2b_cmd_s1_context_length = m2b_cmd_s1_length; + always @(*) begin + io_read_cmd_valid = 1'b0; + if(m2b_cmd_s1_valid) begin + io_read_cmd_valid = 1'b1; + end + end + + assign io_read_cmd_payload_last = 1'b1; + assign io_read_cmd_payload_fragment_opcode = 1'b0; + assign io_read_cmd_payload_fragment_address = m2b_cmd_s1_address; + assign io_read_cmd_payload_fragment_length = m2b_cmd_s1_length; + assign io_read_cmd_payload_fragment_context = {m2b_cmd_s1_context_last,{m2b_cmd_s1_context_length,{m2b_cmd_s1_context_stop,m2b_cmd_s1_context_start}}}; + assign m2b_cmd_s1_addressNext = (_zz_m2b_cmd_s1_addressNext + 32'h00000001); + assign m2b_cmd_s1_byteLeftNext = (_zz_m2b_cmd_s1_byteLeftNext - 26'h0000001); + assign m2b_cmd_s1_fifoPushDecr = (_zz_m2b_cmd_s1_fifoPushDecr >>> 2'd3); + assign when_DmaSg_l828 = 1'b1; + assign _zz_m2b_rsp_context_start = io_read_rsp_payload_fragment_context; + assign m2b_rsp_context_start = _zz_m2b_rsp_context_start[3 : 0]; + assign m2b_rsp_context_stop = _zz_m2b_rsp_context_start[7 : 4]; + assign m2b_rsp_context_length = _zz_m2b_rsp_context_start[19 : 8]; + assign m2b_rsp_context_last = _zz_m2b_rsp_context_start[20]; + assign m2b_rsp_veryLast = (m2b_rsp_context_last && io_read_rsp_payload_last); + assign io_read_rsp_fire = (io_read_rsp_valid && io_read_rsp_ready); + assign when_DmaSg_l847 = (io_read_rsp_fire && m2b_rsp_veryLast); + assign when_DmaSg_l848 = 1'b1; + always @(*) begin + memory_core_io_writes_1_cmd_payload_mask[0] = ((! (m2b_rsp_first && (4'b0000 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0000)))); + memory_core_io_writes_1_cmd_payload_mask[1] = ((! (m2b_rsp_first && (4'b0001 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0001)))); + memory_core_io_writes_1_cmd_payload_mask[2] = ((! (m2b_rsp_first && (4'b0010 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0010)))); + memory_core_io_writes_1_cmd_payload_mask[3] = ((! (m2b_rsp_first && (4'b0011 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0011)))); + memory_core_io_writes_1_cmd_payload_mask[4] = ((! (m2b_rsp_first && (4'b0100 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0100)))); + memory_core_io_writes_1_cmd_payload_mask[5] = ((! (m2b_rsp_first && (4'b0101 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0101)))); + memory_core_io_writes_1_cmd_payload_mask[6] = ((! (m2b_rsp_first && (4'b0110 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0110)))); + memory_core_io_writes_1_cmd_payload_mask[7] = ((! (m2b_rsp_first && (4'b0111 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b0111)))); + memory_core_io_writes_1_cmd_payload_mask[8] = ((! (m2b_rsp_first && (4'b1000 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1000)))); + memory_core_io_writes_1_cmd_payload_mask[9] = ((! (m2b_rsp_first && (4'b1001 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1001)))); + memory_core_io_writes_1_cmd_payload_mask[10] = ((! (m2b_rsp_first && (4'b1010 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1010)))); + memory_core_io_writes_1_cmd_payload_mask[11] = ((! (m2b_rsp_first && (4'b1011 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1011)))); + memory_core_io_writes_1_cmd_payload_mask[12] = ((! (m2b_rsp_first && (4'b1100 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1100)))); + memory_core_io_writes_1_cmd_payload_mask[13] = ((! (m2b_rsp_first && (4'b1101 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1101)))); + memory_core_io_writes_1_cmd_payload_mask[14] = ((! (m2b_rsp_first && (4'b1110 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1110)))); + memory_core_io_writes_1_cmd_payload_mask[15] = ((! (m2b_rsp_first && (4'b1111 < m2b_rsp_context_start))) && (! (io_read_rsp_payload_last && (m2b_rsp_context_stop < 4'b1111)))); + end + + assign m2b_rsp_writeContext_last = m2b_rsp_veryLast; + assign m2b_rsp_writeContext_lastOfBurst = io_read_rsp_payload_last; + assign m2b_rsp_writeContext_loadByteInNextBeat = ({1'b0,(io_read_rsp_payload_last ? m2b_rsp_context_stop : 4'b1111)} - {1'b0,(m2b_rsp_first ? m2b_rsp_context_start : 4'b0000)}); + assign memory_core_io_writes_1_cmd_payload_address = channels_1_fifo_push_ptrWithBase[9:0]; + assign io_read_rsp_ready = memory_core_io_writes_1_cmd_ready; + assign memory_core_io_writes_1_cmd_payload_context = {m2b_rsp_writeContext_loadByteInNextBeat,{m2b_rsp_writeContext_lastOfBurst,m2b_rsp_writeContext_last}}; + assign memory_core_io_writes_1_cmd_fire = (io_read_rsp_valid && memory_core_io_writes_1_cmd_ready); + assign _zz_channels_1_fifo_push_ptrIncr_value = (memory_core_io_writes_1_cmd_fire && 1'b1); + assign when_DmaSg_l874 = (_zz_channels_1_fifo_push_ptrIncr_value && io_read_rsp_payload_last); + assign _zz_m2b_writeRsp_context_last = memory_core_io_writes_1_rsp_payload_context; + assign m2b_writeRsp_context_last = _zz_m2b_writeRsp_context_last[0]; + assign m2b_writeRsp_context_lastOfBurst = _zz_m2b_writeRsp_context_last[1]; + assign m2b_writeRsp_context_loadByteInNextBeat = _zz_m2b_writeRsp_context_last[6 : 2]; + assign _zz_channels_1_fifo_pop_bytesIncr_value = (memory_core_io_writes_1_rsp_valid && 1'b1); + assign when_DmaSg_l893 = (_zz_channels_1_fifo_pop_bytesIncr_value && m2b_writeRsp_context_lastOfBurst); + assign _zz_b2m_fsm_arbiter_logic_priority_masked = channels_0_priority; + assign b2m_fsm_arbiter_logic_priority_masked = (channels_0_pop_b2m_request && (channels_0_priority == _zz_b2m_fsm_arbiter_logic_priority_masked)); + assign _zz_b2m_fsm_arbiter_logic_priority_chosenOh = b2m_fsm_arbiter_logic_priority_masked; + assign _zz_b2m_fsm_arbiter_logic_priority_chosenOh_1 = {_zz_b2m_fsm_arbiter_logic_priority_chosenOh,_zz_b2m_fsm_arbiter_logic_priority_chosenOh}; + assign _zz_b2m_fsm_arbiter_logic_priority_chosenOh_2 = (_zz_b2m_fsm_arbiter_logic_priority_chosenOh_1 & (~ _zz__zz_b2m_fsm_arbiter_logic_priority_chosenOh_2)); + assign b2m_fsm_arbiter_logic_priority_chosenOh = (_zz_b2m_fsm_arbiter_logic_priority_chosenOh_2[1 : 1] | _zz_b2m_fsm_arbiter_logic_priority_chosenOh_2[0 : 0]); + assign b2m_fsm_arbiter_logic_priority_weightLast = (channels_0_weight == b2m_fsm_arbiter_logic_priority_counter); + assign b2m_fsm_arbiter_logic_priority_contextNext = (b2m_fsm_arbiter_logic_priority_weightLast ? b2m_fsm_arbiter_logic_priority_chosenOh[0 : 0] : b2m_fsm_arbiter_logic_priority_chosenOh); + assign when_DmaSg_l758_1 = (! b2m_fsm_arbiter_logic_valid); + assign when_DmaSg_l760_1 = (|channels_0_pop_b2m_request); + assign when_DmaSg_l763_4 = (2'b00 == _zz_b2m_fsm_arbiter_logic_priority_masked); + assign when_DmaSg_l763_5 = (2'b01 == _zz_b2m_fsm_arbiter_logic_priority_masked); + assign when_DmaSg_l763_6 = (2'b10 == _zz_b2m_fsm_arbiter_logic_priority_masked); + assign when_DmaSg_l763_7 = (2'b11 == _zz_b2m_fsm_arbiter_logic_priority_masked); + assign when_DmaSg_l773_1 = (channels_0_pop_b2m_request && b2m_fsm_arbiter_logic_priority_chosenOh[0]); + assign when_DmaSg_l935 = ((! b2m_fsm_sel_valid) && b2m_fsm_arbiter_logic_valid); + assign b2m_fsm_bytesInBurstP1 = ({1'b0,b2m_fsm_sel_bytesInBurst} + _zz_b2m_fsm_bytesInBurstP1); + assign b2m_fsm_addressNext = (b2m_fsm_sel_address + _zz_b2m_fsm_addressNext); + assign b2m_fsm_bytesLeftNext = ({1'b0,b2m_fsm_sel_bytesLeft} - _zz_b2m_fsm_bytesLeftNext); + assign b2m_fsm_isFinalCmd = b2m_fsm_bytesLeftNext[26]; + assign b2m_fsm_s0 = (b2m_fsm_sel_valid && (! b2m_fsm_sel_valid_regNext)); + assign when_DmaSg_l986 = (! b2m_fsm_sel_valid); + assign _zz_b2m_fsm_sel_bytesInBurst = (b2m_fsm_sel_bytesInFifo - 14'h0001); + assign _zz_b2m_fsm_sel_bytesInBurst_1 = ((_zz__zz_b2m_fsm_sel_bytesInBurst_1 < b2m_fsm_sel_bytesLeft) ? _zz__zz_b2m_fsm_sel_bytesInBurst_1_1 : b2m_fsm_sel_bytesLeft); + assign _zz_b2m_fsm_sel_bytesInBurst_2 = (b2m_fsm_sel_bytePerBurst - (_zz__zz_b2m_fsm_sel_bytesInBurst_2 & b2m_fsm_sel_bytePerBurst)); + assign b2m_fsm_fifoCompletion = (_zz_b2m_fsm_fifoCompletion == _zz_b2m_fsm_fifoCompletion_1); + assign when_DmaSg_l996 = 1'b1; + assign when_DmaSg_l1001 = (! b2m_fsm_fifoCompletion); + assign when_DmaSg_l1013 = (b2m_fsm_sel_valid && b2m_fsm_sel_ready); + always @(*) begin + b2m_fsm_sel_ready = 1'b0; + if(when_DmaSg_l1102) begin + b2m_fsm_sel_ready = 1'b1; + end + end + + assign b2m_fsm_fetch_context_ptr = channels_0_fifo_pop_ptr; + assign b2m_fsm_fetch_context_toggle = b2m_fsm_toggle; + assign memory_core_io_reads_1_cmd_payload_address = b2m_fsm_sel_ptr[9:0]; + assign memory_core_io_reads_1_cmd_payload_context = {b2m_fsm_fetch_context_toggle,b2m_fsm_fetch_context_ptr}; + assign when_DmaSg_l1033 = (b2m_fsm_sel_valid && memory_core_io_reads_1_cmd_ready); + assign _zz_b2m_fsm_aggregate_context_ptr = memory_core_io_reads_1_rsp_payload_context; + assign b2m_fsm_aggregate_context_ptr = _zz_b2m_fsm_aggregate_context_ptr[10 : 0]; + assign b2m_fsm_aggregate_context_toggle = _zz_b2m_fsm_aggregate_context_ptr[11]; + assign memory_core_io_reads_1_rsp_s2mPipe_valid = (memory_core_io_reads_1_rsp_valid || (! memory_core_io_reads_1_rsp_rValidN)); + assign memory_core_io_reads_1_rsp_s2mPipe_payload_data = (memory_core_io_reads_1_rsp_rValidN ? memory_core_io_reads_1_rsp_payload_data : memory_core_io_reads_1_rsp_rData_data); + assign memory_core_io_reads_1_rsp_s2mPipe_payload_mask = (memory_core_io_reads_1_rsp_rValidN ? memory_core_io_reads_1_rsp_payload_mask : memory_core_io_reads_1_rsp_rData_mask); + assign memory_core_io_reads_1_rsp_s2mPipe_payload_context = (memory_core_io_reads_1_rsp_rValidN ? memory_core_io_reads_1_rsp_payload_context : memory_core_io_reads_1_rsp_rData_context); + assign when_Stream_l445 = (b2m_fsm_aggregate_context_toggle != b2m_fsm_toggle); + always @(*) begin + b2m_fsm_aggregate_memoryPort_valid = memory_core_io_reads_1_rsp_s2mPipe_valid; + if(when_Stream_l445) begin + b2m_fsm_aggregate_memoryPort_valid = 1'b0; + end + end + + always @(*) begin + memory_core_io_reads_1_rsp_s2mPipe_ready = b2m_fsm_aggregate_memoryPort_ready; + if(when_Stream_l445) begin + memory_core_io_reads_1_rsp_s2mPipe_ready = 1'b1; + end + end + + assign b2m_fsm_aggregate_memoryPort_payload_data = memory_core_io_reads_1_rsp_s2mPipe_payload_data; + assign b2m_fsm_aggregate_memoryPort_payload_mask = memory_core_io_reads_1_rsp_s2mPipe_payload_mask; + assign b2m_fsm_aggregate_memoryPort_payload_context = memory_core_io_reads_1_rsp_s2mPipe_payload_context; + assign b2m_fsm_aggregate_memoryPort_fire = (b2m_fsm_aggregate_memoryPort_valid && b2m_fsm_aggregate_memoryPort_ready); + assign when_DmaSg_l1050 = (! (b2m_fsm_sel_valid && (! b2m_fsm_sel_ready))); + assign b2m_fsm_aggregate_bytesToSkip = channels_0_pop_b2m_bytesToSkip; + assign b2m_fsm_aggregate_bytesToSkipMask = {((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1111)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= 4'b1110)),{((! b2m_fsm_aggregate_first) || (b2m_fsm_aggregate_bytesToSkip <= _zz_b2m_fsm_aggregate_bytesToSkipMask)),{(_zz_b2m_fsm_aggregate_bytesToSkipMask_1 || _zz_b2m_fsm_aggregate_bytesToSkipMask_2),{_zz_b2m_fsm_aggregate_bytesToSkipMask_3,{_zz_b2m_fsm_aggregate_bytesToSkipMask_4,_zz_b2m_fsm_aggregate_bytesToSkipMask_5}}}}}}; + assign b2m_fsm_aggregate_memoryPort_ready = b2m_fsm_aggregate_engine_io_input_ready; + assign b2m_fsm_aggregate_engine_io_input_payload_mask = (b2m_fsm_aggregate_memoryPort_payload_mask & b2m_fsm_aggregate_bytesToSkipMask); + assign b2m_fsm_aggregate_engine_io_offset = b2m_fsm_sel_address[3:0]; + assign b2m_fsm_aggregate_engine_io_flush = (! _zz_io_flush); + assign b2m_fsm_cmd_maskFirstTrigger = b2m_fsm_sel_address[3:0]; + assign b2m_fsm_cmd_maskLastTriggerComb = (b2m_fsm_cmd_maskFirstTrigger + _zz_b2m_fsm_cmd_maskLastTriggerComb); + assign b2m_fsm_cmd_maskFirst = {(b2m_fsm_cmd_maskFirstTrigger <= 4'b1111),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1110),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1101),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1100),{(b2m_fsm_cmd_maskFirstTrigger <= 4'b1011),{(b2m_fsm_cmd_maskFirstTrigger <= _zz_b2m_fsm_cmd_maskFirst),{_zz_b2m_fsm_cmd_maskFirst_1,{_zz_b2m_fsm_cmd_maskFirst_2,_zz_b2m_fsm_cmd_maskFirst_3}}}}}}}}; + assign b2m_fsm_cmd_enoughAggregation = (((b2m_fsm_s2 && b2m_fsm_sel_valid) && (! b2m_fsm_aggregate_engine_io_flush)) && (io_write_cmd_payload_last ? ((b2m_fsm_aggregate_engine_io_output_mask & b2m_fsm_cmd_maskLast) == b2m_fsm_cmd_maskLast) : (&b2m_fsm_aggregate_engine_io_output_mask))); + assign io_write_cmd_fire = (io_write_cmd_valid && io_write_cmd_ready); + assign io_write_cmd_valid = b2m_fsm_cmd_enoughAggregation; + assign io_write_cmd_payload_last = (b2m_fsm_beatCounter == 8'h0); + assign io_write_cmd_payload_fragment_address = b2m_fsm_sel_address; + assign io_write_cmd_payload_fragment_opcode = 1'b1; + assign io_write_cmd_payload_fragment_data = b2m_fsm_aggregate_engine_io_output_data; + assign io_write_cmd_payload_fragment_mask = (~ ((io_write_cmd_payload_first ? (~ b2m_fsm_cmd_maskFirst) : 16'h0) | (io_write_cmd_payload_last ? (~ b2m_fsm_cmd_maskLast) : 16'h0))); + assign io_write_cmd_payload_fragment_length = b2m_fsm_sel_bytesInBurst; + assign b2m_fsm_cmd_doPtrIncr = (b2m_fsm_sel_valid && (b2m_fsm_aggregate_engine_io_output_consumed || ((io_write_cmd_fire && io_write_cmd_payload_last) && (b2m_fsm_aggregate_engine_io_output_usedUntil == 4'b1111)))); + assign b2m_fsm_cmd_context_length = b2m_fsm_sel_bytesInBurst; + assign b2m_fsm_cmd_context_doPacketSync = (b2m_fsm_sel_packet && b2m_fsm_fifoCompletion); + assign io_write_cmd_payload_fragment_context = {b2m_fsm_cmd_context_doPacketSync,b2m_fsm_cmd_context_length}; + assign when_DmaSg_l1102 = (io_write_cmd_fire && io_write_cmd_payload_last); + assign io_write_rsp_ready = 1'b1; + assign _zz_b2m_rsp_context_length = io_write_rsp_payload_fragment_context; + assign b2m_rsp_context_length = _zz_b2m_rsp_context_length[11 : 0]; + assign b2m_rsp_context_doPacketSync = _zz_b2m_rsp_context_length[12]; + assign io_write_rsp_fire = (io_write_rsp_valid && io_write_rsp_ready); + assign when_DmaSg_l1116 = 1'b1; + assign _zz_ll_arbiter_head = {channels_1_ll_requestLl,channels_0_ll_requestLl}; + assign _zz_ll_arbiter_head_1 = _zz__zz_ll_arbiter_head_1[1]; + assign ll_arbiter_head = (_zz_ll_arbiter_head_2[0] ? channels_0_ll_head : channels_1_ll_head); + assign ll_arbiter_isJustASink = (_zz_ll_arbiter_isJustASink[0] ? channels_0_descriptorValid : channels_1_descriptorValid); + assign ll_arbiter_doDescriptorStall = (_zz_ll_arbiter_doDescriptorStall[0] ? ((! channels_0_ll_controlNoCompletion) || channels_0_ll_gotDescriptorStall) : ((! channels_1_ll_controlNoCompletion) || channels_1_ll_gotDescriptorStall)); + assign ll_arbiter_onSgStream = (_zz_ll_arbiter_onSgStream[0] ? channels_0_ll_onSgStream : channels_1_ll_onSgStream); + assign when_DmaSg_l1149 = (! ll_cmd_valid); + assign when_DmaSg_l1148 = (! ll_cmd_valid); + assign when_DmaSg_l1148_1 = (! ll_cmd_valid); + assign when_DmaSg_l1148_2 = (! ll_cmd_valid); + assign when_DmaSg_l1148_3 = (! ll_cmd_valid); + assign when_DmaSg_l1154 = (! ll_cmd_valid); + assign when_DmaSg_l1155 = (! ll_cmd_valid); + assign when_DmaSg_l1156 = (! ll_cmd_valid); + assign when_DmaSg_l1160 = (! ll_cmd_valid); + assign when_DmaSg_l1161 = (|{_zz_ll_arbiter_head_1,channels_0_ll_requestLl}); + assign when_DmaSg_l1169 = (! ll_arbiter_isJustASink); + assign when_DmaSg_l1169_1 = (! ll_arbiter_isJustASink); + assign when_DmaSg_l1177 = (ll_cmd_writeFired && ll_cmd_readFired); + assign ll_cmd_context_channel = ll_cmd_oh_1; + assign io_sgRead_cmd_valid = ((ll_cmd_valid && (! ll_cmd_readFired)) && (! ll_cmd_onSgStream)); + assign io_sgRead_cmd_payload_last = 1'b1; + assign io_sgRead_cmd_payload_fragment_address = {ll_cmd_ptrNext[31 : 5],5'h0}; + assign io_sgRead_cmd_payload_fragment_length = 5'h1f; + assign io_sgRead_cmd_payload_fragment_opcode = 1'b0; + assign io_sgRead_cmd_payload_fragment_context = ll_cmd_context_channel; + assign io_sgWrite_cmd_valid = ((ll_cmd_valid && (! ll_cmd_writeFired)) && (! ll_cmd_onSgStream)); + assign io_sgWrite_cmd_payload_last = 1'b1; + assign io_sgWrite_cmd_payload_fragment_address = {ll_cmd_ptr[31 : 5],5'h0}; + assign io_sgWrite_cmd_payload_fragment_length = 2'b11; + assign io_sgWrite_cmd_payload_fragment_opcode = 1'b1; + assign io_sgWrite_cmd_payload_fragment_context = ll_cmd_context_channel; + assign ll_cmd_writeMaskSplit_0 = io_sgWrite_cmd_payload_fragment_mask[3 : 0]; + assign ll_cmd_writeMaskSplit_1 = io_sgWrite_cmd_payload_fragment_mask[7 : 4]; + assign ll_cmd_writeMaskSplit_2 = io_sgWrite_cmd_payload_fragment_mask[11 : 8]; + assign ll_cmd_writeMaskSplit_3 = io_sgWrite_cmd_payload_fragment_mask[15 : 12]; + assign ll_cmd_writeDataSplit_0 = io_sgWrite_cmd_payload_fragment_data[31 : 0]; + assign ll_cmd_writeDataSplit_1 = io_sgWrite_cmd_payload_fragment_data[63 : 32]; + assign ll_cmd_writeDataSplit_2 = io_sgWrite_cmd_payload_fragment_data[95 : 64]; + assign ll_cmd_writeDataSplit_3 = io_sgWrite_cmd_payload_fragment_data[127 : 96]; + assign _zz_1 = zz_io_sgWrite_cmd_payload_fragment_mask(1'b0); + always @(*) io_sgWrite_cmd_payload_fragment_mask = _zz_1; + always @(*) begin + io_sgWrite_cmd_payload_fragment_data[63 : 32] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + io_sgWrite_cmd_payload_fragment_data[95 : 64] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + io_sgWrite_cmd_payload_fragment_data[127 : 96] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + io_sgWrite_cmd_payload_fragment_data[31 : 0] = 32'h0; + io_sgWrite_cmd_payload_fragment_data[26 : 0] = ll_cmd_bytesDone; + io_sgWrite_cmd_payload_fragment_data[30] = ll_cmd_endOfPacket; + io_sgWrite_cmd_payload_fragment_data[31] = ((! ll_cmd_isJustASink) && ll_cmd_doDescriptorStall); + end + + assign io_sgRead_cmd_fire = (io_sgRead_cmd_valid && io_sgRead_cmd_ready); + assign io_sgWrite_cmd_fire = (io_sgWrite_cmd_valid && io_sgWrite_cmd_ready); + assign ll_readRsp_context_channel = io_sgRead_rsp_payload_fragment_context[0 : 0]; + assign _zz_ll_readRsp_oh_0 = (2'b01 <<< ll_readRsp_context_channel); + assign ll_readRsp_oh_0 = _zz_ll_readRsp_oh_0[0]; + assign ll_readRsp_oh_1 = _zz_ll_readRsp_oh_0[1]; + assign io_sgRead_rsp_ready = 1'b1; + assign io_sgRead_rsp_fire = (io_sgRead_rsp_valid && io_sgRead_rsp_ready); + assign when_DmaSg_l1248 = (1'b0 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_1 = (1'b1 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_2 = (1'b1 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_3 = (1'b0 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_4 = (1'b0 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_5 = (1'b0 == ll_readRsp_beatCounter); + assign when_DmaSg_l1248_6 = (1'b0 == ll_readRsp_beatCounter); + assign when_DmaSg_l1271 = (io_sgRead_rsp_fire && io_sgRead_rsp_payload_last); + assign ll_writeRsp_context_channel = io_sgWrite_rsp_payload_fragment_context[0 : 0]; + assign _zz_ll_writeRsp_oh_0 = (2'b01 <<< ll_writeRsp_context_channel); + assign ll_writeRsp_oh_0 = _zz_ll_writeRsp_oh_0[0]; + assign ll_writeRsp_oh_1 = _zz_ll_writeRsp_oh_0[1]; + assign io_sgWrite_rsp_ready = 1'b1; + assign io_sgWrite_rsp_fire = (io_sgWrite_rsp_valid && io_sgWrite_rsp_ready); + always @(*) begin + io_interrupts = 2'b00; + if(channels_0_interrupts_completion_valid) begin + io_interrupts[0] = 1'b1; + end + if(channels_0_interrupts_onChannelCompletion_valid) begin + io_interrupts[0] = 1'b1; + end + if(channels_0_interrupts_onLinkedListUpdate_valid) begin + io_interrupts[0] = 1'b1; + end + if(channels_0_interrupts_s2mPacket_valid) begin + io_interrupts[0] = 1'b1; + end + if(channels_1_interrupts_completion_valid) begin + io_interrupts[1] = 1'b1; + end + if(channels_1_interrupts_onChannelCompletion_valid) begin + io_interrupts[1] = 1'b1; + end + if(channels_1_interrupts_onLinkedListUpdate_valid) begin + io_interrupts[1] = 1'b1; + end + end + + always @(*) begin + when_BusSlaveFactory_l377 = 1'b0; + case(io_ctrl_PADDR) + 14'h002c : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l377_1 = 1'b0; + case(io_ctrl_PADDR) + 14'h002c : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_1 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l377_2 = 1'b0; + case(io_ctrl_PADDR) + 14'h002c : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_2 = io_ctrl_PWDATA[4]; + always @(*) begin + when_BusSlaveFactory_l377_3 = 1'b0; + case(io_ctrl_PADDR) + 14'h002c : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_3 = io_ctrl_PWDATA[4]; + always @(*) begin + when_BusSlaveFactory_l341 = 1'b0; + case(io_ctrl_PADDR) + 14'h0054 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l341_1 = 1'b0; + case(io_ctrl_PADDR) + 14'h0054 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_1 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_1 = io_ctrl_PWDATA[2]; + always @(*) begin + when_BusSlaveFactory_l341_2 = 1'b0; + case(io_ctrl_PADDR) + 14'h0054 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_2 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_2 = io_ctrl_PWDATA[3]; + always @(*) begin + when_BusSlaveFactory_l341_3 = 1'b0; + case(io_ctrl_PADDR) + 14'h0054 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_3 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_3 = io_ctrl_PWDATA[4]; + always @(*) begin + when_BusSlaveFactory_l377_4 = 1'b0; + case(io_ctrl_PADDR) + 14'h00ac : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_4 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_4 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l377_5 = 1'b0; + case(io_ctrl_PADDR) + 14'h00ac : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_5 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_5 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l377_6 = 1'b0; + case(io_ctrl_PADDR) + 14'h00ac : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_6 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_6 = io_ctrl_PWDATA[4]; + always @(*) begin + when_BusSlaveFactory_l377_7 = 1'b0; + case(io_ctrl_PADDR) + 14'h00ac : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l377_7 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l379_7 = io_ctrl_PWDATA[4]; + always @(*) begin + when_BusSlaveFactory_l341_4 = 1'b0; + case(io_ctrl_PADDR) + 14'h00d4 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_4 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_4 = io_ctrl_PWDATA[0]; + always @(*) begin + when_BusSlaveFactory_l341_5 = 1'b0; + case(io_ctrl_PADDR) + 14'h00d4 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_5 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_5 = io_ctrl_PWDATA[2]; + always @(*) begin + when_BusSlaveFactory_l341_6 = 1'b0; + case(io_ctrl_PADDR) + 14'h00d4 : begin + if(ctrl_doWrite) begin + when_BusSlaveFactory_l341_6 = 1'b1; + end + end + default : begin + end + endcase + end + + assign when_BusSlaveFactory_l347_6 = io_ctrl_PWDATA[3]; + assign when_Apb3SlaveFactory_l81 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h0010); + assign when_Apb3SlaveFactory_l81_1 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h0070); + assign when_Apb3SlaveFactory_l81_2 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h0080); + assign when_Apb3SlaveFactory_l81_3 = ((io_ctrl_PADDR & (~ 14'h0003)) == 14'h00f0); + assign channels_0_fifo_push_ptrIncr_value = _zz_channels_0_fifo_push_ptrIncr_value; + assign channels_0_fifo_pop_bytesIncr_value = _zz_channels_0_fifo_pop_bytesIncr_value_1; + assign channels_0_fifo_pop_bytesDecr_value = channels_0_pop_b2m_decrBytes; + assign channels_0_fifo_pop_ptrIncr_value = _zz_channels_0_fifo_pop_ptrIncr_value; + assign channels_1_fifo_push_ptrIncr_value = _zz_channels_1_fifo_push_ptrIncr_value_1; + assign channels_1_fifo_pop_bytesIncr_value = _zz_channels_1_fifo_pop_bytesIncr_value_1; + assign channels_1_fifo_pop_bytesDecr_value = 14'h0; + assign channels_1_fifo_pop_ptrIncr_value = _zz_channels_1_fifo_pop_ptrIncr_value; + assign ll_0_descriptorUpdate = (channels_0_ll_descriptorUpdated && (! channels_0_ll_gotDescriptorStall)); + assign ll_1_descriptorUpdate = (channels_1_ll_descriptorUpdated && (! channels_1_ll_gotDescriptorStall)); + always @(posedge clk) begin + if(reset) begin + channels_0_channelValid <= 1'b0; + channels_0_descriptorValid <= 1'b0; + channels_0_priority <= 2'b00; + channels_0_weight <= 2'b00; + channels_0_ctrl_kick <= 1'b0; + channels_0_ll_valid <= 1'b0; + channels_0_ll_onSgStream <= 1'b0; + channels_0_pop_b2m_memPending <= 4'b0000; + channels_0_interrupts_completion_enable <= 1'b0; + channels_0_interrupts_completion_valid <= 1'b0; + channels_0_interrupts_onChannelCompletion_enable <= 1'b0; + channels_0_interrupts_onChannelCompletion_valid <= 1'b0; + channels_0_interrupts_onLinkedListUpdate_enable <= 1'b0; + channels_0_interrupts_onLinkedListUpdate_valid <= 1'b0; + channels_0_interrupts_s2mPacket_enable <= 1'b0; + channels_0_interrupts_s2mPacket_valid <= 1'b0; + channels_1_channelValid <= 1'b0; + channels_1_descriptorValid <= 1'b0; + channels_1_priority <= 2'b00; + channels_1_weight <= 2'b00; + channels_1_ctrl_kick <= 1'b0; + channels_1_ll_valid <= 1'b0; + channels_1_ll_onSgStream <= 1'b0; + channels_1_push_m2b_loadDone <= 1'b1; + channels_1_push_m2b_memPending <= 4'b0000; + channels_1_interrupts_completion_enable <= 1'b0; + channels_1_interrupts_completion_valid <= 1'b0; + channels_1_interrupts_onChannelCompletion_enable <= 1'b0; + channels_1_interrupts_onChannelCompletion_valid <= 1'b0; + channels_1_interrupts_onLinkedListUpdate_enable <= 1'b0; + channels_1_interrupts_onLinkedListUpdate_valid <= 1'b0; + io_inputs_0_payload_last_regNextWhen <= 1'b1; + io_inputs_0_payload_last_regNextWhen_1 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_2 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_3 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_4 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_5 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_6 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_7 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_8 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_9 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_10 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_11 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_12 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_13 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_14 <= 1'b1; + io_inputs_0_payload_last_regNextWhen_15 <= 1'b1; + m2b_cmd_s0_valid <= 1'b0; + m2b_cmd_s0_priority_roundRobins_0 <= 1'b1; + m2b_cmd_s0_priority_roundRobins_1 <= 1'b1; + m2b_cmd_s0_priority_roundRobins_2 <= 1'b1; + m2b_cmd_s0_priority_roundRobins_3 <= 1'b1; + m2b_cmd_s0_priority_counter <= 2'b00; + m2b_cmd_s1_valid <= 1'b0; + m2b_rsp_first <= 1'b1; + b2m_fsm_sel_valid <= 1'b0; + b2m_fsm_arbiter_logic_valid <= 1'b0; + b2m_fsm_arbiter_logic_priority_roundRobins_0 <= 1'b1; + b2m_fsm_arbiter_logic_priority_roundRobins_1 <= 1'b1; + b2m_fsm_arbiter_logic_priority_roundRobins_2 <= 1'b1; + b2m_fsm_arbiter_logic_priority_roundRobins_3 <= 1'b1; + b2m_fsm_arbiter_logic_priority_counter <= 2'b00; + b2m_fsm_sel_valid_regNext <= 1'b0; + b2m_fsm_s1 <= 1'b0; + b2m_fsm_s2 <= 1'b0; + b2m_fsm_toggle <= 1'b0; + memory_core_io_reads_1_rsp_rValidN <= 1'b1; + _zz_io_flush <= 1'b0; + io_write_cmd_payload_first <= 1'b1; + ll_cmd_valid <= 1'b0; + ll_readRsp_beatCounter <= 1'b0; + end else begin + if(channels_0_channelStart) begin + channels_0_channelValid <= 1'b1; + end + if(channels_0_channelCompletion) begin + channels_0_channelValid <= 1'b0; + end + if(channels_0_descriptorStart) begin + channels_0_descriptorValid <= 1'b1; + end + if(channels_0_descriptorCompletion) begin + channels_0_descriptorValid <= 1'b0; + end + channels_0_ctrl_kick <= 1'b0; + if(channels_0_channelCompletion) begin + channels_0_ctrl_kick <= 1'b0; + end + if(when_DmaSg_l318) begin + if(when_DmaSg_l320) begin + if(!when_DmaSg_l322) begin + channels_0_ll_valid <= 1'b0; + end + end + end + if(channels_0_ll_sgStart) begin + channels_0_ll_valid <= 1'b1; + end + if(channels_0_channelCompletion) begin + channels_0_ll_valid <= 1'b0; + end + channels_0_pop_b2m_memPending <= (_zz_channels_0_pop_b2m_memPending - _zz_channels_0_pop_b2m_memPending_3); + if(when_DmaSg_l255) begin + channels_0_interrupts_completion_valid <= 1'b1; + end + if(when_DmaSg_l255_1) begin + channels_0_interrupts_completion_valid <= 1'b0; + end + if(when_DmaSg_l255_2) begin + channels_0_interrupts_onChannelCompletion_valid <= 1'b1; + end + if(when_DmaSg_l255_3) begin + channels_0_interrupts_onChannelCompletion_valid <= 1'b0; + end + if(channels_0_ll_descriptorUpdated) begin + channels_0_interrupts_onLinkedListUpdate_valid <= 1'b1; + end + if(when_DmaSg_l255_4) begin + channels_0_interrupts_onLinkedListUpdate_valid <= 1'b0; + end + if(channels_0_pop_b2m_packetSync) begin + channels_0_interrupts_s2mPacket_valid <= 1'b1; + end + if(when_DmaSg_l255_5) begin + channels_0_interrupts_s2mPacket_valid <= 1'b0; + end + if(channels_1_channelStart) begin + channels_1_channelValid <= 1'b1; + end + if(channels_1_channelCompletion) begin + channels_1_channelValid <= 1'b0; + end + if(channels_1_descriptorStart) begin + channels_1_descriptorValid <= 1'b1; + end + if(channels_1_descriptorCompletion) begin + channels_1_descriptorValid <= 1'b0; + end + channels_1_ctrl_kick <= 1'b0; + if(channels_1_channelCompletion) begin + channels_1_ctrl_kick <= 1'b0; + end + if(when_DmaSg_l318_1) begin + if(when_DmaSg_l320_1) begin + if(!when_DmaSg_l322_1) begin + channels_1_ll_valid <= 1'b0; + end + end + end + if(channels_1_ll_sgStart) begin + channels_1_ll_valid <= 1'b1; + end + if(channels_1_channelCompletion) begin + channels_1_ll_valid <= 1'b0; + end + channels_1_push_m2b_memPending <= (_zz_channels_1_push_m2b_memPending - _zz_channels_1_push_m2b_memPending_3); + if(channels_1_descriptorStart) begin + channels_1_push_m2b_loadDone <= 1'b0; + end + if(when_DmaSg_l255_6) begin + channels_1_interrupts_completion_valid <= 1'b1; + end + if(when_DmaSg_l255_7) begin + channels_1_interrupts_completion_valid <= 1'b0; + end + if(when_DmaSg_l255_8) begin + channels_1_interrupts_onChannelCompletion_valid <= 1'b1; + end + if(when_DmaSg_l255_9) begin + channels_1_interrupts_onChannelCompletion_valid <= 1'b0; + end + if(channels_1_ll_descriptorUpdated) begin + channels_1_interrupts_onLinkedListUpdate_valid <= 1'b1; + end + if(when_DmaSg_l255_10) begin + channels_1_interrupts_onLinkedListUpdate_valid <= 1'b0; + end + if(when_package_l12) begin + io_inputs_0_payload_last_regNextWhen <= io_inputs_0_payload_last; + end + if(when_package_l12_1) begin + io_inputs_0_payload_last_regNextWhen_1 <= io_inputs_0_payload_last; + end + if(when_package_l12_2) begin + io_inputs_0_payload_last_regNextWhen_2 <= io_inputs_0_payload_last; + end + if(when_package_l12_3) begin + io_inputs_0_payload_last_regNextWhen_3 <= io_inputs_0_payload_last; + end + if(when_package_l12_4) begin + io_inputs_0_payload_last_regNextWhen_4 <= io_inputs_0_payload_last; + end + if(when_package_l12_5) begin + io_inputs_0_payload_last_regNextWhen_5 <= io_inputs_0_payload_last; + end + if(when_package_l12_6) begin + io_inputs_0_payload_last_regNextWhen_6 <= io_inputs_0_payload_last; + end + if(when_package_l12_7) begin + io_inputs_0_payload_last_regNextWhen_7 <= io_inputs_0_payload_last; + end + if(when_package_l12_8) begin + io_inputs_0_payload_last_regNextWhen_8 <= io_inputs_0_payload_last; + end + if(when_package_l12_9) begin + io_inputs_0_payload_last_regNextWhen_9 <= io_inputs_0_payload_last; + end + if(when_package_l12_10) begin + io_inputs_0_payload_last_regNextWhen_10 <= io_inputs_0_payload_last; + end + if(when_package_l12_11) begin + io_inputs_0_payload_last_regNextWhen_11 <= io_inputs_0_payload_last; + end + if(when_package_l12_12) begin + io_inputs_0_payload_last_regNextWhen_12 <= io_inputs_0_payload_last; + end + if(when_package_l12_13) begin + io_inputs_0_payload_last_regNextWhen_13 <= io_inputs_0_payload_last; + end + if(when_package_l12_14) begin + io_inputs_0_payload_last_regNextWhen_14 <= io_inputs_0_payload_last; + end + if(when_package_l12_15) begin + io_inputs_0_payload_last_regNextWhen_15 <= io_inputs_0_payload_last; + end + if(when_DmaSg_l758) begin + if(when_DmaSg_l760) begin + m2b_cmd_s0_valid <= 1'b1; + if(when_DmaSg_l763) begin + m2b_cmd_s0_priority_roundRobins_0 <= m2b_cmd_s0_priority_contextNext; + end + if(when_DmaSg_l763_1) begin + m2b_cmd_s0_priority_roundRobins_1 <= m2b_cmd_s0_priority_contextNext; + end + if(when_DmaSg_l763_2) begin + m2b_cmd_s0_priority_roundRobins_2 <= m2b_cmd_s0_priority_contextNext; + end + if(when_DmaSg_l763_3) begin + m2b_cmd_s0_priority_roundRobins_3 <= m2b_cmd_s0_priority_contextNext; + end + m2b_cmd_s0_priority_counter <= (m2b_cmd_s0_priority_counter + 2'b01); + if(m2b_cmd_s0_priority_weightLast) begin + m2b_cmd_s0_priority_counter <= 2'b00; + end + end + end + if(m2b_cmd_s0_valid) begin + m2b_cmd_s1_valid <= 1'b1; + end + if(m2b_cmd_s1_valid) begin + if(io_read_cmd_ready) begin + m2b_cmd_s0_valid <= 1'b0; + m2b_cmd_s1_valid <= 1'b0; + if(when_DmaSg_l828) begin + if(m2b_cmd_s1_lastBurst) begin + channels_1_push_m2b_loadDone <= 1'b1; + end + end + end + end + if(io_read_rsp_fire) begin + m2b_rsp_first <= io_read_rsp_payload_last; + end + if(when_DmaSg_l758_1) begin + if(when_DmaSg_l760_1) begin + b2m_fsm_arbiter_logic_valid <= 1'b1; + if(when_DmaSg_l763_4) begin + b2m_fsm_arbiter_logic_priority_roundRobins_0 <= b2m_fsm_arbiter_logic_priority_contextNext; + end + if(when_DmaSg_l763_5) begin + b2m_fsm_arbiter_logic_priority_roundRobins_1 <= b2m_fsm_arbiter_logic_priority_contextNext; + end + if(when_DmaSg_l763_6) begin + b2m_fsm_arbiter_logic_priority_roundRobins_2 <= b2m_fsm_arbiter_logic_priority_contextNext; + end + if(when_DmaSg_l763_7) begin + b2m_fsm_arbiter_logic_priority_roundRobins_3 <= b2m_fsm_arbiter_logic_priority_contextNext; + end + b2m_fsm_arbiter_logic_priority_counter <= (b2m_fsm_arbiter_logic_priority_counter + 2'b01); + if(b2m_fsm_arbiter_logic_priority_weightLast) begin + b2m_fsm_arbiter_logic_priority_counter <= 2'b00; + end + end + end + if(b2m_fsm_sel_ready) begin + b2m_fsm_sel_valid <= 1'b0; + if(b2m_fsm_sel_valid) begin + b2m_fsm_arbiter_logic_valid <= 1'b0; + end + end + if(when_DmaSg_l935) begin + b2m_fsm_sel_valid <= 1'b1; + end + b2m_fsm_sel_valid_regNext <= b2m_fsm_sel_valid; + b2m_fsm_s1 <= b2m_fsm_s0; + if(b2m_fsm_s1) begin + b2m_fsm_s2 <= 1'b1; + end + if(when_DmaSg_l986) begin + b2m_fsm_s2 <= 1'b0; + end + if(when_DmaSg_l1013) begin + b2m_fsm_toggle <= (! b2m_fsm_toggle); + end + if(memory_core_io_reads_1_rsp_valid) begin + memory_core_io_reads_1_rsp_rValidN <= 1'b0; + end + if(memory_core_io_reads_1_rsp_s2mPipe_ready) begin + memory_core_io_reads_1_rsp_rValidN <= 1'b1; + end + _zz_io_flush <= (b2m_fsm_sel_valid && (! b2m_fsm_sel_ready)); + if(io_write_cmd_fire) begin + io_write_cmd_payload_first <= io_write_cmd_payload_last; + end + if(when_DmaSg_l1160) begin + if(when_DmaSg_l1161) begin + ll_cmd_valid <= 1'b1; + end + end else begin + if(when_DmaSg_l1177) begin + ll_cmd_valid <= 1'b0; + end + end + if(io_sgRead_rsp_fire) begin + ll_readRsp_beatCounter <= (ll_readRsp_beatCounter + 1'b1); + end + if(when_BusSlaveFactory_l377_1) begin + if(when_BusSlaveFactory_l379_1) begin + channels_0_ctrl_kick <= _zz_channels_0_ctrl_kick[0]; + end + end + if(when_BusSlaveFactory_l341) begin + if(when_BusSlaveFactory_l347) begin + channels_0_interrupts_completion_valid <= _zz_channels_0_interrupts_completion_valid[0]; + end + end + if(when_BusSlaveFactory_l341_1) begin + if(when_BusSlaveFactory_l347_1) begin + channels_0_interrupts_onChannelCompletion_valid <= _zz_channels_0_interrupts_onChannelCompletion_valid[0]; + end + end + if(when_BusSlaveFactory_l341_2) begin + if(when_BusSlaveFactory_l347_2) begin + channels_0_interrupts_onLinkedListUpdate_valid <= _zz_channels_0_interrupts_onLinkedListUpdate_valid[0]; + end + end + if(when_BusSlaveFactory_l341_3) begin + if(when_BusSlaveFactory_l347_3) begin + channels_0_interrupts_s2mPacket_valid <= _zz_channels_0_interrupts_s2mPacket_valid[0]; + end + end + if(when_BusSlaveFactory_l377_5) begin + if(when_BusSlaveFactory_l379_5) begin + channels_1_ctrl_kick <= _zz_channels_1_ctrl_kick[0]; + end + end + if(when_BusSlaveFactory_l341_4) begin + if(when_BusSlaveFactory_l347_4) begin + channels_1_interrupts_completion_valid <= _zz_channels_1_interrupts_completion_valid[0]; + end + end + if(when_BusSlaveFactory_l341_5) begin + if(when_BusSlaveFactory_l347_5) begin + channels_1_interrupts_onChannelCompletion_valid <= _zz_channels_1_interrupts_onChannelCompletion_valid[0]; + end + end + if(when_BusSlaveFactory_l341_6) begin + if(when_BusSlaveFactory_l347_6) begin + channels_1_interrupts_onLinkedListUpdate_valid <= _zz_channels_1_interrupts_onLinkedListUpdate_valid[0]; + end + end + case(io_ctrl_PADDR) + 14'h0078 : begin + if(ctrl_doWrite) begin + channels_0_ll_onSgStream <= io_ctrl_PWDATA[0]; + end + end + 14'h0044 : begin + if(ctrl_doWrite) begin + channels_0_priority <= io_ctrl_PWDATA[1 : 0]; + channels_0_weight <= io_ctrl_PWDATA[9 : 8]; + end + end + 14'h0050 : begin + if(ctrl_doWrite) begin + channels_0_interrupts_completion_enable <= io_ctrl_PWDATA[0]; + channels_0_interrupts_onChannelCompletion_enable <= io_ctrl_PWDATA[2]; + channels_0_interrupts_onLinkedListUpdate_enable <= io_ctrl_PWDATA[3]; + channels_0_interrupts_s2mPacket_enable <= io_ctrl_PWDATA[4]; + end + end + 14'h00f8 : begin + if(ctrl_doWrite) begin + channels_1_ll_onSgStream <= io_ctrl_PWDATA[0]; + end + end + 14'h00c4 : begin + if(ctrl_doWrite) begin + channels_1_priority <= io_ctrl_PWDATA[1 : 0]; + channels_1_weight <= io_ctrl_PWDATA[9 : 8]; + end + end + 14'h00d0 : begin + if(ctrl_doWrite) begin + channels_1_interrupts_completion_enable <= io_ctrl_PWDATA[0]; + channels_1_interrupts_onChannelCompletion_enable <= io_ctrl_PWDATA[2]; + channels_1_interrupts_onLinkedListUpdate_enable <= io_ctrl_PWDATA[3]; + end + end + default : begin + end + endcase + end + end + + always @(posedge clk) begin + if(channels_0_bytesProbe_incr_valid) begin + channels_0_bytesProbe_value <= (_zz_channels_0_bytesProbe_value + 27'h0000001); + end + if(channels_0_descriptorStart) begin + channels_0_ll_packet <= 1'b0; + end + if(channels_0_descriptorStart) begin + channels_0_ll_requireSync <= 1'b0; + end + if(when_DmaSg_l318) begin + channels_0_ll_waitDone <= 1'b0; + if(when_DmaSg_l320) begin + channels_0_ll_head <= 1'b0; + end + end + if(channels_0_channelStart) begin + channels_0_ll_waitDone <= 1'b0; + channels_0_ll_head <= 1'b1; + end + channels_0_fifo_push_ptr <= (channels_0_fifo_push_ptr + channels_0_fifo_push_ptrIncr_value); + if(channels_0_channelStart) begin + channels_0_fifo_push_ptr <= 11'h0; + end + channels_0_fifo_pop_ptr <= (channels_0_fifo_pop_ptr + channels_0_fifo_pop_ptrIncr_value); + channels_0_fifo_pop_withOverride_backup <= channels_0_fifo_pop_withOverride_backupNext; + if(when_DmaSg_l409) begin + channels_0_fifo_pop_withOverride_valid <= 1'b0; + end + if(channels_0_fifo_pop_withOverride_load) begin + channels_0_fifo_pop_withOverride_valid <= 1'b1; + end + channels_0_fifo_pop_withOverride_exposed <= ((! channels_0_fifo_pop_withOverride_valid) ? channels_0_fifo_pop_withOverride_backupNext : _zz_channels_0_fifo_pop_withOverride_exposed); + if(channels_0_channelStart) begin + channels_0_fifo_pop_withOverride_backup <= 14'h0; + channels_0_fifo_pop_withOverride_valid <= 1'b0; + end + if(channels_0_channelStart) begin + channels_0_push_s2b_packetLock <= 1'b0; + end + if(channels_0_pop_b2m_fire) begin + channels_0_pop_b2m_flush <= 1'b0; + end + if(when_DmaSg_l505) begin + channels_0_pop_b2m_packet <= 1'b0; + end + if(when_DmaSg_l523) begin + channels_0_pop_b2m_flush <= 1'b0; + channels_0_pop_b2m_packet <= 1'b0; + end + if(channels_0_pop_b2m_packetSync) begin + channels_0_push_s2b_packetLock <= 1'b0; + if(when_DmaSg_l532) begin + if(!channels_0_push_s2b_completionOnLast) begin + if(when_DmaSg_l536) begin + channels_0_ll_requireSync <= 1'b1; + end + end + channels_0_ll_packet <= 1'b1; + end + end + if(channels_0_channelStart) begin + channels_0_pop_b2m_bytesToSkip <= 4'b0000; + channels_0_pop_b2m_flush <= 1'b0; + end + if(channels_0_descriptorStart) begin + channels_0_pop_b2m_bytesLeft <= {1'd0, channels_0_bytes}; + channels_0_pop_b2m_waitFinalRsp <= 1'b0; + end + if(channels_0_channelValid) begin + if(!channels_0_channelStop) begin + if(when_DmaSg_l575) begin + if(when_DmaSg_l593) begin + channels_0_channelStop <= 1'b1; + end + end + end + end + channels_0_fifo_pop_ptrIncr_value_regNext <= channels_0_fifo_pop_ptrIncr_value; + channels_0_fifo_push_available <= (_zz_channels_0_fifo_push_available - (channels_0_push_memory ? channels_0_fifo_push_availableDecr : channels_0_fifo_push_ptrIncr_value)); + if(channels_0_channelStart) begin + channels_0_fifo_push_ptr <= 11'h0; + channels_0_fifo_push_available <= (channels_0_fifo_words + 11'h001); + channels_0_fifo_pop_ptr <= 11'h0; + end + if(when_DmaSg_l625) begin + channels_0_bytesProbe_value <= 27'h0; + end + if(channels_1_bytesProbe_incr_valid) begin + channels_1_bytesProbe_value <= (_zz_channels_1_bytesProbe_value + 27'h0000001); + end + if(channels_1_descriptorStart) begin + channels_1_ll_packet <= 1'b0; + end + if(channels_1_descriptorStart) begin + channels_1_ll_requireSync <= 1'b0; + end + if(when_DmaSg_l318_1) begin + channels_1_ll_waitDone <= 1'b0; + if(when_DmaSg_l320_1) begin + channels_1_ll_head <= 1'b0; + end + end + if(channels_1_channelStart) begin + channels_1_ll_waitDone <= 1'b0; + channels_1_ll_head <= 1'b1; + end + channels_1_fifo_push_ptr <= (channels_1_fifo_push_ptr + channels_1_fifo_push_ptrIncr_value); + if(channels_1_channelStart) begin + channels_1_fifo_push_ptr <= 11'h0; + end + channels_1_fifo_pop_ptr <= (channels_1_fifo_pop_ptr + channels_1_fifo_pop_ptrIncr_value); + channels_1_fifo_pop_withoutOverride_exposed <= (_zz_channels_1_fifo_pop_withoutOverride_exposed - channels_1_fifo_pop_bytesDecr_value); + if(channels_1_channelStart) begin + channels_1_fifo_pop_withoutOverride_exposed <= 14'h0; + end + if(channels_1_descriptorStart) begin + channels_1_push_m2b_bytesLeft <= channels_1_bytes; + end + if(when_DmaSg_l474) begin + channels_1_pop_b2s_veryLastValid <= 1'b1; + end + if(channels_1_pop_b2s_veryLastTrigger) begin + channels_1_pop_b2s_veryLastPtr <= channels_1_fifo_push_ptrWithBase; + channels_1_pop_b2s_veryLastEndPacket <= channels_1_pop_b2s_last; + end + if(channels_1_channelStart) begin + channels_1_pop_b2s_veryLastValid <= 1'b0; + end + if(channels_1_channelValid) begin + if(!channels_1_channelStop) begin + if(when_DmaSg_l575_1) begin + if(when_DmaSg_l593_1) begin + channels_1_channelStop <= 1'b1; + end + end + end + end + channels_1_fifo_pop_ptrIncr_value_regNext <= channels_1_fifo_pop_ptrIncr_value; + channels_1_fifo_push_available <= (_zz_channels_1_fifo_push_available - (channels_1_push_memory ? channels_1_fifo_push_availableDecr : channels_1_fifo_push_ptrIncr_value)); + if(channels_1_channelStart) begin + channels_1_fifo_push_ptr <= 11'h0; + channels_1_fifo_push_available <= (channels_1_fifo_words + 11'h001); + channels_1_fifo_pop_ptr <= 11'h0; + end + if(when_DmaSg_l625_1) begin + channels_1_bytesProbe_value <= 27'h0; + end + if(when_DmaSg_l665) begin + channels_0_push_s2b_waitFirst <= 1'b0; + if(io_inputs_0_payload_last) begin + channels_0_push_s2b_packetLock <= 1'b1; + end + end + if(when_DmaSg_l681) begin + channels_0_pop_b2m_flush <= 1'b1; + end + if(when_DmaSg_l682) begin + channels_0_pop_b2m_packet <= 1'b1; + end + if(when_DmaSg_l725) begin + if(when_DmaSg_l726) begin + channels_1_pop_b2s_veryLastValid <= 1'b0; + end + end + m2b_cmd_s1_address <= m2b_cmd_s0_address; + m2b_cmd_s1_length <= m2b_cmd_s0_length; + m2b_cmd_s1_lastBurst <= m2b_cmd_s0_lastBurst; + m2b_cmd_s1_bytesLeft <= m2b_cmd_s0_bytesLeft; + if(m2b_cmd_s1_valid) begin + if(io_read_cmd_ready) begin + if(when_DmaSg_l828) begin + channels_1_push_m2b_address <= m2b_cmd_s1_addressNext; + channels_1_push_m2b_bytesLeft <= m2b_cmd_s1_byteLeftNext; + end + end + end + if(when_DmaSg_l935) begin + b2m_fsm_sel_address <= channels_0_pop_b2m_address; + b2m_fsm_sel_ptr <= channels_0_fifo_pop_ptrWithBase; + b2m_fsm_sel_ptrMask <= channels_0_fifo_words; + b2m_fsm_sel_bytePerBurst <= channels_0_pop_b2m_bytePerBurst; + b2m_fsm_sel_bytesInFifo <= channels_0_fifo_pop_bytes; + b2m_fsm_sel_flush <= channels_0_pop_b2m_flush; + b2m_fsm_sel_packet <= channels_0_pop_b2m_packet; + b2m_fsm_sel_bytesLeft <= channels_0_pop_b2m_bytesLeft[25:0]; + end + if(b2m_fsm_s0) begin + b2m_fsm_sel_bytesInBurst <= _zz_b2m_fsm_sel_bytesInBurst_3[11:0]; + end + if(b2m_fsm_s1) begin + b2m_fsm_beatCounter <= (_zz_b2m_fsm_beatCounter >>> 3'd4); + if(when_DmaSg_l996) begin + channels_0_pop_b2m_address <= b2m_fsm_addressNext; + channels_0_pop_b2m_bytesLeft <= b2m_fsm_bytesLeftNext; + if(b2m_fsm_isFinalCmd) begin + channels_0_pop_b2m_waitFinalRsp <= 1'b1; + end + if(when_DmaSg_l1001) begin + if(b2m_fsm_sel_flush) begin + channels_0_pop_b2m_flush <= 1'b1; + end + if(b2m_fsm_sel_packet) begin + channels_0_pop_b2m_packet <= 1'b1; + end + end + end + end + if(when_DmaSg_l1033) begin + b2m_fsm_sel_ptr <= ((b2m_fsm_sel_ptr & (~ b2m_fsm_sel_ptrMask)) | (_zz_b2m_fsm_sel_ptr & b2m_fsm_sel_ptrMask)); + end + if(memory_core_io_reads_1_rsp_rValidN) begin + memory_core_io_reads_1_rsp_rData_data <= memory_core_io_reads_1_rsp_payload_data; + memory_core_io_reads_1_rsp_rData_mask <= memory_core_io_reads_1_rsp_payload_mask; + memory_core_io_reads_1_rsp_rData_context <= memory_core_io_reads_1_rsp_payload_context; + end + if(b2m_fsm_aggregate_memoryPort_fire) begin + b2m_fsm_aggregate_first <= 1'b0; + end + if(when_DmaSg_l1050) begin + b2m_fsm_aggregate_first <= 1'b1; + end + b2m_fsm_cmd_maskLastTriggerReg <= b2m_fsm_cmd_maskLastTriggerComb; + b2m_fsm_cmd_maskLast <= {(4'b1111 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1110 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1101 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1100 <= b2m_fsm_cmd_maskLastTriggerComb),{(4'b1011 <= b2m_fsm_cmd_maskLastTriggerComb),{(_zz_b2m_fsm_cmd_maskLast <= b2m_fsm_cmd_maskLastTriggerComb),{_zz_b2m_fsm_cmd_maskLast_1,{_zz_b2m_fsm_cmd_maskLast_2,_zz_b2m_fsm_cmd_maskLast_3}}}}}}}}; + if(io_write_cmd_fire) begin + b2m_fsm_beatCounter <= (b2m_fsm_beatCounter - 8'h01); + end + if(when_DmaSg_l1102) begin + if(_zz_when_1[0]) begin + channels_0_pop_b2m_bytesToSkip <= (b2m_fsm_aggregate_engine_io_output_usedUntil + 4'b0001); + end + end + if(when_DmaSg_l1149) begin + ll_cmd_oh_0 <= channels_0_ll_requestLl; + ll_cmd_oh_1 <= _zz_ll_arbiter_head_1; + end + if(when_DmaSg_l1148) begin + ll_cmd_ptr <= (_zz_ll_cmd_ptr[0] ? channels_0_ll_ptr : channels_1_ll_ptr); + end + if(when_DmaSg_l1148_1) begin + ll_cmd_ptrNext <= (_zz_ll_cmd_ptrNext[0] ? channels_0_ll_ptrNext : channels_1_ll_ptrNext); + end + if(when_DmaSg_l1148_2) begin + ll_cmd_bytesDone <= channels_0_bytesProbe_value; + end + if(when_DmaSg_l1148_3) begin + ll_cmd_endOfPacket <= (_zz_ll_cmd_endOfPacket[0] ? channels_0_ll_packet : channels_1_ll_packet); + end + if(when_DmaSg_l1154) begin + ll_cmd_isJustASink <= ll_arbiter_isJustASink; + end + if(when_DmaSg_l1155) begin + ll_cmd_doDescriptorStall <= ll_arbiter_doDescriptorStall; + end + if(when_DmaSg_l1156) begin + ll_cmd_onSgStream <= ll_arbiter_onSgStream; + end + if(when_DmaSg_l1160) begin + ll_cmd_oh_0 <= channels_0_ll_requestLl; + ll_cmd_oh_1 <= _zz_ll_arbiter_head_1; + if(channels_0_ll_requestLl) begin + channels_0_ll_waitDone <= 1'b1; + channels_0_ll_writeDone <= ll_arbiter_head; + channels_0_ll_justASync <= ll_arbiter_isJustASink; + channels_0_ll_packet <= 1'b0; + channels_0_ll_requireSync <= 1'b0; + if(when_DmaSg_l1169) begin + channels_0_ll_ptr <= channels_0_ll_ptrNext; + end + channels_0_ll_readDone <= ll_arbiter_isJustASink; + end + if(_zz_ll_arbiter_head_1) begin + channels_1_ll_waitDone <= 1'b1; + channels_1_ll_writeDone <= ll_arbiter_head; + channels_1_ll_justASync <= ll_arbiter_isJustASink; + channels_1_ll_packet <= 1'b0; + channels_1_ll_requireSync <= 1'b0; + if(when_DmaSg_l1169_1) begin + channels_1_ll_ptr <= channels_1_ll_ptrNext; + end + channels_1_ll_readDone <= ll_arbiter_isJustASink; + end + ll_cmd_readFired <= ll_arbiter_isJustASink; + ll_cmd_writeFired <= ll_arbiter_head; + end + if(io_sgRead_cmd_fire) begin + ll_cmd_readFired <= 1'b1; + end + if(io_sgWrite_cmd_fire) begin + ll_cmd_writeFired <= 1'b1; + end + if(io_sgRead_rsp_fire) begin + if(when_DmaSg_l1248) begin + if(ll_readRsp_oh_1) begin + channels_1_push_m2b_address <= io_sgRead_rsp_payload_fragment_data[95 : 64]; + end + end + if(when_DmaSg_l1248_1) begin + if(ll_readRsp_oh_0) begin + channels_0_pop_b2m_address <= io_sgRead_rsp_payload_fragment_data[31 : 0]; + end + end + if(when_DmaSg_l1248_2) begin + if(ll_readRsp_oh_0) begin + channels_0_ll_ptrNext <= io_sgRead_rsp_payload_fragment_data[95 : 64]; + end + if(ll_readRsp_oh_1) begin + channels_1_ll_ptrNext <= io_sgRead_rsp_payload_fragment_data[95 : 64]; + end + end + if(when_DmaSg_l1248_3) begin + if(ll_readRsp_oh_0) begin + channels_0_bytes <= io_sgRead_rsp_payload_fragment_data[57 : 32]; + end + if(ll_readRsp_oh_1) begin + channels_1_bytes <= io_sgRead_rsp_payload_fragment_data[57 : 32]; + end + end + if(when_DmaSg_l1248_4) begin + if(ll_readRsp_oh_0) begin + channels_0_ll_controlNoCompletion <= io_sgRead_rsp_payload_fragment_data[63]; + end + if(ll_readRsp_oh_1) begin + channels_1_ll_controlNoCompletion <= io_sgRead_rsp_payload_fragment_data[63]; + end + end + if(when_DmaSg_l1248_5) begin + if(ll_readRsp_oh_1) begin + channels_1_pop_b2s_last <= io_sgRead_rsp_payload_fragment_data[62]; + end + end + if(when_DmaSg_l1248_6) begin + if(ll_readRsp_oh_0) begin + channels_0_ll_gotDescriptorStall <= io_sgRead_rsp_payload_fragment_data[31]; + end + if(ll_readRsp_oh_1) begin + channels_1_ll_gotDescriptorStall <= io_sgRead_rsp_payload_fragment_data[31]; + end + end + if(when_DmaSg_l1271) begin + if(ll_readRsp_oh_0) begin + channels_0_ll_readDone <= 1'b1; + end + if(ll_readRsp_oh_1) begin + channels_1_ll_readDone <= 1'b1; + end + end + end + if(io_sgWrite_rsp_fire) begin + if(ll_writeRsp_oh_0) begin + channels_0_ll_writeDone <= 1'b1; + end + if(ll_writeRsp_oh_1) begin + channels_1_ll_writeDone <= 1'b1; + end + end + case(io_ctrl_PADDR) + 14'h000c : begin + if(ctrl_doWrite) begin + channels_0_push_memory <= io_ctrl_PWDATA[12]; + channels_0_push_s2b_completionOnLast <= io_ctrl_PWDATA[13]; + channels_0_push_s2b_waitFirst <= io_ctrl_PWDATA[14]; + end + end + 14'h001c : begin + if(ctrl_doWrite) begin + channels_0_pop_memory <= io_ctrl_PWDATA[12]; + end + end + 14'h002c : begin + if(ctrl_doWrite) begin + channels_0_channelStop <= io_ctrl_PWDATA[2]; + end + end + 14'h0020 : begin + if(ctrl_doWrite) begin + channels_0_bytes <= io_ctrl_PWDATA[25 : 0]; + end + end + 14'h008c : begin + if(ctrl_doWrite) begin + channels_1_push_memory <= io_ctrl_PWDATA[12]; + end + end + 14'h0098 : begin + if(ctrl_doWrite) begin + channels_1_pop_b2s_sinkId <= io_ctrl_PWDATA[19 : 16]; + end + end + 14'h009c : begin + if(ctrl_doWrite) begin + channels_1_pop_memory <= io_ctrl_PWDATA[12]; + channels_1_pop_b2s_last <= io_ctrl_PWDATA[13]; + end + end + 14'h00ac : begin + if(ctrl_doWrite) begin + channels_1_channelStop <= io_ctrl_PWDATA[2]; + end + end + 14'h00a0 : begin + if(ctrl_doWrite) begin + channels_1_bytes <= io_ctrl_PWDATA[25 : 0]; + end + end + default : begin + end + endcase + if(when_Apb3SlaveFactory_l81) begin + if(ctrl_doWrite) begin + channels_0_pop_b2m_address[31 : 0] <= io_ctrl_PWDATA[31 : 0]; + end + end + if(when_Apb3SlaveFactory_l81_1) begin + if(ctrl_doWrite) begin + channels_0_ll_ptrNext[31 : 0] <= io_ctrl_PWDATA[31 : 0]; + end + end + if(when_Apb3SlaveFactory_l81_2) begin + if(ctrl_doWrite) begin + channels_1_push_m2b_address[31 : 0] <= io_ctrl_PWDATA[31 : 0]; + end + end + if(when_Apb3SlaveFactory_l81_3) begin + if(ctrl_doWrite) begin + channels_1_ll_ptrNext[31 : 0] <= io_ctrl_PWDATA[31 : 0]; + end + end + end + + +endmodule + +module EfxDMA_StreamArbiter_1 ( + input wire io_inputs_0_valid, + output wire io_inputs_0_ready, + input wire io_inputs_0_payload_last, + input wire [0:0] io_inputs_0_payload_fragment_source, + input wire [0:0] io_inputs_0_payload_fragment_opcode, + input wire [31:0] io_inputs_0_payload_fragment_address, + input wire [11:0] io_inputs_0_payload_fragment_length, + input wire [127:0] io_inputs_0_payload_fragment_data, + input wire [15:0] io_inputs_0_payload_fragment_mask, + input wire [12:0] io_inputs_0_payload_fragment_context, + input wire io_inputs_1_valid, + output wire io_inputs_1_ready, + input wire io_inputs_1_payload_last, + input wire [0:0] io_inputs_1_payload_fragment_source, + input wire [0:0] io_inputs_1_payload_fragment_opcode, + input wire [31:0] io_inputs_1_payload_fragment_address, + input wire [11:0] io_inputs_1_payload_fragment_length, + input wire [127:0] io_inputs_1_payload_fragment_data, + input wire [15:0] io_inputs_1_payload_fragment_mask, + input wire [12:0] io_inputs_1_payload_fragment_context, + output wire io_output_valid, + input wire io_output_ready, + output wire io_output_payload_last, + output wire [0:0] io_output_payload_fragment_source, + output wire [0:0] io_output_payload_fragment_opcode, + output wire [31:0] io_output_payload_fragment_address, + output wire [11:0] io_output_payload_fragment_length, + output wire [127:0] io_output_payload_fragment_data, + output wire [15:0] io_output_payload_fragment_mask, + output wire [12:0] io_output_payload_fragment_context, + output wire [0:0] io_chosen, + output wire [1:0] io_chosenOH, + input wire clk, + input wire reset +); + + wire [3:0] _zz__zz_maskProposal_0_2; + wire [3:0] _zz__zz_maskProposal_0_2_1; + wire [1:0] _zz__zz_maskProposal_0_2_2; + reg locked; + wire maskProposal_0; + wire maskProposal_1; + reg maskLocked_0; + reg maskLocked_1; + wire maskRouted_0; + wire maskRouted_1; + wire [1:0] _zz_maskProposal_0; + wire [3:0] _zz_maskProposal_0_1; + wire [3:0] _zz_maskProposal_0_2; + wire [1:0] _zz_maskProposal_0_3; + wire io_output_fire; + wire when_Stream_l683; + wire _zz_io_chosen; + + assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); + assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; + assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; + assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); + assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); + assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; + assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; + assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); + assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); + assign maskProposal_0 = _zz_maskProposal_0_3[0]; + assign maskProposal_1 = _zz_maskProposal_0_3[1]; + assign io_output_fire = (io_output_valid && io_output_ready); + assign when_Stream_l683 = (io_output_fire && io_output_payload_last); + assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); + assign io_output_payload_last = (maskRouted_0 ? io_inputs_0_payload_last : io_inputs_1_payload_last); + assign io_output_payload_fragment_source = (maskRouted_0 ? io_inputs_0_payload_fragment_source : io_inputs_1_payload_fragment_source); + assign io_output_payload_fragment_opcode = (maskRouted_0 ? io_inputs_0_payload_fragment_opcode : io_inputs_1_payload_fragment_opcode); + assign io_output_payload_fragment_address = (maskRouted_0 ? io_inputs_0_payload_fragment_address : io_inputs_1_payload_fragment_address); + assign io_output_payload_fragment_length = (maskRouted_0 ? io_inputs_0_payload_fragment_length : io_inputs_1_payload_fragment_length); + assign io_output_payload_fragment_data = (maskRouted_0 ? io_inputs_0_payload_fragment_data : io_inputs_1_payload_fragment_data); + assign io_output_payload_fragment_mask = (maskRouted_0 ? io_inputs_0_payload_fragment_mask : io_inputs_1_payload_fragment_mask); + assign io_output_payload_fragment_context = (maskRouted_0 ? io_inputs_0_payload_fragment_context : io_inputs_1_payload_fragment_context); + assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); + assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); + assign io_chosenOH = {maskRouted_1,maskRouted_0}; + assign _zz_io_chosen = io_chosenOH[1]; + assign io_chosen = _zz_io_chosen; + always @(posedge clk) begin + if(reset) begin + locked <= 1'b0; + maskLocked_0 <= 1'b0; + maskLocked_1 <= 1'b1; + end else begin + if(io_output_valid) begin + maskLocked_0 <= maskRouted_0; + maskLocked_1 <= maskRouted_1; + end + if(io_output_valid) begin + locked <= 1'b1; + end + if(when_Stream_l683) begin + locked <= 1'b0; + end + end + end + + +endmodule + +module EfxDMA_StreamArbiter ( + input wire io_inputs_0_valid, + output wire io_inputs_0_ready, + input wire io_inputs_0_payload_last, + input wire [0:0] io_inputs_0_payload_fragment_source, + input wire [0:0] io_inputs_0_payload_fragment_opcode, + input wire [31:0] io_inputs_0_payload_fragment_address, + input wire [11:0] io_inputs_0_payload_fragment_length, + input wire [20:0] io_inputs_0_payload_fragment_context, + input wire io_inputs_1_valid, + output wire io_inputs_1_ready, + input wire io_inputs_1_payload_last, + input wire [0:0] io_inputs_1_payload_fragment_source, + input wire [0:0] io_inputs_1_payload_fragment_opcode, + input wire [31:0] io_inputs_1_payload_fragment_address, + input wire [11:0] io_inputs_1_payload_fragment_length, + input wire [20:0] io_inputs_1_payload_fragment_context, + output wire io_output_valid, + input wire io_output_ready, + output wire io_output_payload_last, + output wire [0:0] io_output_payload_fragment_source, + output wire [0:0] io_output_payload_fragment_opcode, + output wire [31:0] io_output_payload_fragment_address, + output wire [11:0] io_output_payload_fragment_length, + output wire [20:0] io_output_payload_fragment_context, + output wire [0:0] io_chosen, + output wire [1:0] io_chosenOH, + input wire clk, + input wire reset +); + + wire [3:0] _zz__zz_maskProposal_0_2; + wire [3:0] _zz__zz_maskProposal_0_2_1; + wire [1:0] _zz__zz_maskProposal_0_2_2; + reg locked; + wire maskProposal_0; + wire maskProposal_1; + reg maskLocked_0; + reg maskLocked_1; + wire maskRouted_0; + wire maskRouted_1; + wire [1:0] _zz_maskProposal_0; + wire [3:0] _zz_maskProposal_0_1; + wire [3:0] _zz_maskProposal_0_2; + wire [1:0] _zz_maskProposal_0_3; + wire io_output_fire; + wire when_Stream_l683; + wire _zz_io_chosen; + + assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1); + assign _zz__zz_maskProposal_0_2_2 = {maskLocked_0,maskLocked_1}; + assign _zz__zz_maskProposal_0_2_1 = {2'd0, _zz__zz_maskProposal_0_2_2}; + assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0); + assign maskRouted_1 = (locked ? maskLocked_1 : maskProposal_1); + assign _zz_maskProposal_0 = {io_inputs_1_valid,io_inputs_0_valid}; + assign _zz_maskProposal_0_1 = {_zz_maskProposal_0,_zz_maskProposal_0}; + assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~ _zz__zz_maskProposal_0_2)); + assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[3 : 2] | _zz_maskProposal_0_2[1 : 0]); + assign maskProposal_0 = _zz_maskProposal_0_3[0]; + assign maskProposal_1 = _zz_maskProposal_0_3[1]; + assign io_output_fire = (io_output_valid && io_output_ready); + assign when_Stream_l683 = (io_output_fire && io_output_payload_last); + assign io_output_valid = ((io_inputs_0_valid && maskRouted_0) || (io_inputs_1_valid && maskRouted_1)); + assign io_output_payload_last = (maskRouted_0 ? io_inputs_0_payload_last : io_inputs_1_payload_last); + assign io_output_payload_fragment_source = (maskRouted_0 ? io_inputs_0_payload_fragment_source : io_inputs_1_payload_fragment_source); + assign io_output_payload_fragment_opcode = (maskRouted_0 ? io_inputs_0_payload_fragment_opcode : io_inputs_1_payload_fragment_opcode); + assign io_output_payload_fragment_address = (maskRouted_0 ? io_inputs_0_payload_fragment_address : io_inputs_1_payload_fragment_address); + assign io_output_payload_fragment_length = (maskRouted_0 ? io_inputs_0_payload_fragment_length : io_inputs_1_payload_fragment_length); + assign io_output_payload_fragment_context = (maskRouted_0 ? io_inputs_0_payload_fragment_context : io_inputs_1_payload_fragment_context); + assign io_inputs_0_ready = (maskRouted_0 && io_output_ready); + assign io_inputs_1_ready = (maskRouted_1 && io_output_ready); + assign io_chosenOH = {maskRouted_1,maskRouted_0}; + assign _zz_io_chosen = io_chosenOH[1]; + assign io_chosen = _zz_io_chosen; + always @(posedge clk) begin + if(reset) begin + locked <= 1'b0; + maskLocked_0 <= 1'b0; + maskLocked_1 <= 1'b1; + end else begin + if(io_output_valid) begin + maskLocked_0 <= maskRouted_0; + maskLocked_1 <= maskRouted_1; + end + if(io_output_valid) begin + locked <= 1'b1; + end + if(when_Stream_l683) begin + locked <= 1'b0; + end + end + end + + +endmodule + +module EfxDMA_BufferCC_5 ( + input wire [4:0] io_dataIn, + output wire [4:0] io_dataOut, + input wire dat1_o_clk, + input wire dat1_o_reset +); + + (* async_reg = "true" *) reg [4:0] buffers_0; + (* async_reg = "true" *) reg [4:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge dat1_o_clk) begin + if(dat1_o_reset) begin + buffers_0 <= 5'h0; + buffers_1 <= 5'h0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +//EfxDMA_BufferCC_4 replaced by EfxDMA_BufferCC_3 + +module EfxDMA_BufferCC_3 ( + input wire [4:0] io_dataIn, + output wire [4:0] io_dataOut, + input wire clk, + input wire reset +); + + (* async_reg = "true" *) reg [4:0] buffers_0; + (* async_reg = "true" *) reg [4:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge clk) begin + if(reset) begin + buffers_0 <= 5'h0; + buffers_1 <= 5'h0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module EfxDMA_BufferCC_2 ( + input wire [4:0] io_dataIn, + output wire [4:0] io_dataOut, + input wire dat0_i_clk, + input wire dat0_i_reset +); + + (* async_reg = "true" *) reg [4:0] buffers_0; + (* async_reg = "true" *) reg [4:0] buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge dat0_i_clk) begin + if(dat0_i_reset) begin + buffers_0 <= 5'h0; + buffers_1 <= 5'h0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module EfxDMA_BmbContextRemover_1 ( + input wire io_input_cmd_valid, + output reg io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [127:0] io_input_cmd_payload_fragment_data, + input wire [15:0] io_input_cmd_payload_fragment_mask, + input wire [13:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [13:0] io_input_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + output wire [127:0] io_output_cmd_payload_fragment_data, + output wire [15:0] io_output_cmd_payload_fragment_mask, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire clk, + input wire reset +); + + reg fifoFork_thrown_translated_fifo_io_pop_ready; + wire fifoFork_thrown_translated_fifo_io_push_ready; + wire fifoFork_thrown_translated_fifo_io_pop_valid; + wire [13:0] fifoFork_thrown_translated_fifo_io_pop_payload_context; + wire [2:0] fifoFork_thrown_translated_fifo_io_occupancy; + wire [2:0] fifoFork_thrown_translated_fifo_io_availability; + wire fifoFork_valid; + reg fifoFork_ready; + wire fifoFork_payload_last; + wire [0:0] fifoFork_payload_fragment_opcode; + wire [31:0] fifoFork_payload_fragment_address; + wire [11:0] fifoFork_payload_fragment_length; + wire [127:0] fifoFork_payload_fragment_data; + wire [15:0] fifoFork_payload_fragment_mask; + wire [13:0] fifoFork_payload_fragment_context; + wire cmdFork_valid; + wire cmdFork_ready; + wire cmdFork_payload_last; + wire [0:0] cmdFork_payload_fragment_opcode; + wire [31:0] cmdFork_payload_fragment_address; + wire [11:0] cmdFork_payload_fragment_length; + wire [127:0] cmdFork_payload_fragment_data; + wire [15:0] cmdFork_payload_fragment_mask; + wire [13:0] cmdFork_payload_fragment_context; + reg io_input_cmd_fork2_logic_linkEnable_0; + reg io_input_cmd_fork2_logic_linkEnable_1; + wire when_Stream_l1063; + wire when_Stream_l1063_1; + wire fifoFork_fire; + wire cmdFork_fire; + wire [13:0] pushCtx_context; + reg fifoFork_payload_first; + wire when_Stream_l445; + reg fifoFork_thrown_valid; + wire fifoFork_thrown_ready; + wire fifoFork_thrown_payload_last; + wire [0:0] fifoFork_thrown_payload_fragment_opcode; + wire [31:0] fifoFork_thrown_payload_fragment_address; + wire [11:0] fifoFork_thrown_payload_fragment_length; + wire [127:0] fifoFork_thrown_payload_fragment_data; + wire [15:0] fifoFork_thrown_payload_fragment_mask; + wire [13:0] fifoFork_thrown_payload_fragment_context; + wire fifoFork_thrown_translated_valid; + wire fifoFork_thrown_translated_ready; + wire [13:0] fifoFork_thrown_translated_payload_context; + wire popCtx_valid; + wire popCtx_ready; + wire [13:0] popCtx_payload_context; + reg fifoFork_thrown_translated_fifo_io_pop_rValid; + reg [13:0] fifoFork_thrown_translated_fifo_io_pop_rData_context; + wire when_Stream_l375; + wire _zz_io_input_rsp_valid; + + EfxDMA_StreamFifo_1 fifoFork_thrown_translated_fifo ( + .io_push_valid (fifoFork_thrown_translated_valid ), //i + .io_push_ready (fifoFork_thrown_translated_fifo_io_push_ready ), //o + .io_push_payload_context (fifoFork_thrown_translated_payload_context[13:0] ), //i + .io_pop_valid (fifoFork_thrown_translated_fifo_io_pop_valid ), //o + .io_pop_ready (fifoFork_thrown_translated_fifo_io_pop_ready ), //i + .io_pop_payload_context (fifoFork_thrown_translated_fifo_io_pop_payload_context[13:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (fifoFork_thrown_translated_fifo_io_occupancy[2:0] ), //o + .io_availability (fifoFork_thrown_translated_fifo_io_availability[2:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + io_input_cmd_ready = 1'b1; + if(when_Stream_l1063) begin + io_input_cmd_ready = 1'b0; + end + if(when_Stream_l1063_1) begin + io_input_cmd_ready = 1'b0; + end + end + + assign when_Stream_l1063 = ((! fifoFork_ready) && io_input_cmd_fork2_logic_linkEnable_0); + assign when_Stream_l1063_1 = ((! cmdFork_ready) && io_input_cmd_fork2_logic_linkEnable_1); + assign fifoFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_0); + assign fifoFork_payload_last = io_input_cmd_payload_last; + assign fifoFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign fifoFork_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign fifoFork_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign fifoFork_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign fifoFork_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign fifoFork_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign fifoFork_fire = (fifoFork_valid && fifoFork_ready); + assign cmdFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_1); + assign cmdFork_payload_last = io_input_cmd_payload_last; + assign cmdFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign cmdFork_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign cmdFork_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign cmdFork_payload_fragment_data = io_input_cmd_payload_fragment_data; + assign cmdFork_payload_fragment_mask = io_input_cmd_payload_fragment_mask; + assign cmdFork_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign cmdFork_fire = (cmdFork_valid && cmdFork_ready); + assign io_output_cmd_valid = cmdFork_valid; + assign cmdFork_ready = io_output_cmd_ready; + assign io_output_cmd_payload_last = cmdFork_payload_last; + assign io_output_cmd_payload_fragment_opcode = cmdFork_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = cmdFork_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = cmdFork_payload_fragment_length; + assign io_output_cmd_payload_fragment_data = cmdFork_payload_fragment_data; + assign io_output_cmd_payload_fragment_mask = cmdFork_payload_fragment_mask; + assign pushCtx_context = fifoFork_payload_fragment_context; + assign when_Stream_l445 = (! fifoFork_payload_first); + always @(*) begin + fifoFork_thrown_valid = fifoFork_valid; + if(when_Stream_l445) begin + fifoFork_thrown_valid = 1'b0; + end + end + + always @(*) begin + fifoFork_ready = fifoFork_thrown_ready; + if(when_Stream_l445) begin + fifoFork_ready = 1'b1; + end + end + + assign fifoFork_thrown_payload_last = fifoFork_payload_last; + assign fifoFork_thrown_payload_fragment_opcode = fifoFork_payload_fragment_opcode; + assign fifoFork_thrown_payload_fragment_address = fifoFork_payload_fragment_address; + assign fifoFork_thrown_payload_fragment_length = fifoFork_payload_fragment_length; + assign fifoFork_thrown_payload_fragment_data = fifoFork_payload_fragment_data; + assign fifoFork_thrown_payload_fragment_mask = fifoFork_payload_fragment_mask; + assign fifoFork_thrown_payload_fragment_context = fifoFork_payload_fragment_context; + assign fifoFork_thrown_translated_valid = fifoFork_thrown_valid; + assign fifoFork_thrown_ready = fifoFork_thrown_translated_ready; + assign fifoFork_thrown_translated_payload_context = pushCtx_context; + assign fifoFork_thrown_translated_ready = fifoFork_thrown_translated_fifo_io_push_ready; + always @(*) begin + fifoFork_thrown_translated_fifo_io_pop_ready = popCtx_ready; + if(when_Stream_l375) begin + fifoFork_thrown_translated_fifo_io_pop_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! popCtx_valid); + assign popCtx_valid = fifoFork_thrown_translated_fifo_io_pop_rValid; + assign popCtx_payload_context = fifoFork_thrown_translated_fifo_io_pop_rData_context; + assign popCtx_ready = ((io_output_rsp_valid && io_output_rsp_payload_last) && io_input_rsp_ready); + assign _zz_io_input_rsp_valid = (! (! popCtx_valid)); + assign io_output_rsp_ready = (io_input_rsp_ready && _zz_io_input_rsp_valid); + assign io_input_rsp_valid = (io_output_rsp_valid && _zz_io_input_rsp_valid); + assign io_input_rsp_payload_last = io_output_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_context = popCtx_payload_context; + always @(posedge clk) begin + if(reset) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; + fifoFork_payload_first <= 1'b1; + fifoFork_thrown_translated_fifo_io_pop_rValid <= 1'b0; + end else begin + if(fifoFork_fire) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdFork_fire) begin + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_cmd_ready) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; + end + if(fifoFork_fire) begin + fifoFork_payload_first <= fifoFork_payload_last; + end + if(fifoFork_thrown_translated_fifo_io_pop_ready) begin + fifoFork_thrown_translated_fifo_io_pop_rValid <= fifoFork_thrown_translated_fifo_io_pop_valid; + end + end + end + + always @(posedge clk) begin + if(fifoFork_thrown_translated_fifo_io_pop_ready) begin + fifoFork_thrown_translated_fifo_io_pop_rData_context <= fifoFork_thrown_translated_fifo_io_pop_payload_context; + end + end + + +endmodule + +module EfxDMA_BmbContextRemover ( + input wire io_input_cmd_valid, + output reg io_input_cmd_ready, + input wire io_input_cmd_payload_last, + input wire [0:0] io_input_cmd_payload_fragment_opcode, + input wire [31:0] io_input_cmd_payload_fragment_address, + input wire [11:0] io_input_cmd_payload_fragment_length, + input wire [21:0] io_input_cmd_payload_fragment_context, + output wire io_input_rsp_valid, + input wire io_input_rsp_ready, + output wire io_input_rsp_payload_last, + output wire [0:0] io_input_rsp_payload_fragment_opcode, + output wire [127:0] io_input_rsp_payload_fragment_data, + output wire [21:0] io_input_rsp_payload_fragment_context, + output wire io_output_cmd_valid, + input wire io_output_cmd_ready, + output wire io_output_cmd_payload_last, + output wire [0:0] io_output_cmd_payload_fragment_opcode, + output wire [31:0] io_output_cmd_payload_fragment_address, + output wire [11:0] io_output_cmd_payload_fragment_length, + input wire io_output_rsp_valid, + output wire io_output_rsp_ready, + input wire io_output_rsp_payload_last, + input wire [0:0] io_output_rsp_payload_fragment_opcode, + input wire [127:0] io_output_rsp_payload_fragment_data, + input wire clk, + input wire reset +); + + reg fifoFork_thrown_translated_fifo_io_pop_ready; + wire fifoFork_thrown_translated_fifo_io_push_ready; + wire fifoFork_thrown_translated_fifo_io_pop_valid; + wire [21:0] fifoFork_thrown_translated_fifo_io_pop_payload_context; + wire [2:0] fifoFork_thrown_translated_fifo_io_occupancy; + wire [2:0] fifoFork_thrown_translated_fifo_io_availability; + wire fifoFork_valid; + reg fifoFork_ready; + wire fifoFork_payload_last; + wire [0:0] fifoFork_payload_fragment_opcode; + wire [31:0] fifoFork_payload_fragment_address; + wire [11:0] fifoFork_payload_fragment_length; + wire [21:0] fifoFork_payload_fragment_context; + wire cmdFork_valid; + wire cmdFork_ready; + wire cmdFork_payload_last; + wire [0:0] cmdFork_payload_fragment_opcode; + wire [31:0] cmdFork_payload_fragment_address; + wire [11:0] cmdFork_payload_fragment_length; + wire [21:0] cmdFork_payload_fragment_context; + reg io_input_cmd_fork2_logic_linkEnable_0; + reg io_input_cmd_fork2_logic_linkEnable_1; + wire when_Stream_l1063; + wire when_Stream_l1063_1; + wire fifoFork_fire; + wire cmdFork_fire; + wire [21:0] pushCtx_context; + reg fifoFork_payload_first; + wire when_Stream_l445; + reg fifoFork_thrown_valid; + wire fifoFork_thrown_ready; + wire fifoFork_thrown_payload_last; + wire [0:0] fifoFork_thrown_payload_fragment_opcode; + wire [31:0] fifoFork_thrown_payload_fragment_address; + wire [11:0] fifoFork_thrown_payload_fragment_length; + wire [21:0] fifoFork_thrown_payload_fragment_context; + wire fifoFork_thrown_translated_valid; + wire fifoFork_thrown_translated_ready; + wire [21:0] fifoFork_thrown_translated_payload_context; + wire popCtx_valid; + wire popCtx_ready; + wire [21:0] popCtx_payload_context; + reg fifoFork_thrown_translated_fifo_io_pop_rValid; + reg [21:0] fifoFork_thrown_translated_fifo_io_pop_rData_context; + wire when_Stream_l375; + wire _zz_io_input_rsp_valid; + + EfxDMA_StreamFifo fifoFork_thrown_translated_fifo ( + .io_push_valid (fifoFork_thrown_translated_valid ), //i + .io_push_ready (fifoFork_thrown_translated_fifo_io_push_ready ), //o + .io_push_payload_context (fifoFork_thrown_translated_payload_context[21:0] ), //i + .io_pop_valid (fifoFork_thrown_translated_fifo_io_pop_valid ), //o + .io_pop_ready (fifoFork_thrown_translated_fifo_io_pop_ready ), //i + .io_pop_payload_context (fifoFork_thrown_translated_fifo_io_pop_payload_context[21:0]), //o + .io_flush (1'b0 ), //i + .io_occupancy (fifoFork_thrown_translated_fifo_io_occupancy[2:0] ), //o + .io_availability (fifoFork_thrown_translated_fifo_io_availability[2:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + io_input_cmd_ready = 1'b1; + if(when_Stream_l1063) begin + io_input_cmd_ready = 1'b0; + end + if(when_Stream_l1063_1) begin + io_input_cmd_ready = 1'b0; + end + end + + assign when_Stream_l1063 = ((! fifoFork_ready) && io_input_cmd_fork2_logic_linkEnable_0); + assign when_Stream_l1063_1 = ((! cmdFork_ready) && io_input_cmd_fork2_logic_linkEnable_1); + assign fifoFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_0); + assign fifoFork_payload_last = io_input_cmd_payload_last; + assign fifoFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign fifoFork_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign fifoFork_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign fifoFork_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign fifoFork_fire = (fifoFork_valid && fifoFork_ready); + assign cmdFork_valid = (io_input_cmd_valid && io_input_cmd_fork2_logic_linkEnable_1); + assign cmdFork_payload_last = io_input_cmd_payload_last; + assign cmdFork_payload_fragment_opcode = io_input_cmd_payload_fragment_opcode; + assign cmdFork_payload_fragment_address = io_input_cmd_payload_fragment_address; + assign cmdFork_payload_fragment_length = io_input_cmd_payload_fragment_length; + assign cmdFork_payload_fragment_context = io_input_cmd_payload_fragment_context; + assign cmdFork_fire = (cmdFork_valid && cmdFork_ready); + assign io_output_cmd_valid = cmdFork_valid; + assign cmdFork_ready = io_output_cmd_ready; + assign io_output_cmd_payload_last = cmdFork_payload_last; + assign io_output_cmd_payload_fragment_opcode = cmdFork_payload_fragment_opcode; + assign io_output_cmd_payload_fragment_address = cmdFork_payload_fragment_address; + assign io_output_cmd_payload_fragment_length = cmdFork_payload_fragment_length; + assign pushCtx_context = fifoFork_payload_fragment_context; + assign when_Stream_l445 = (! fifoFork_payload_first); + always @(*) begin + fifoFork_thrown_valid = fifoFork_valid; + if(when_Stream_l445) begin + fifoFork_thrown_valid = 1'b0; + end + end + + always @(*) begin + fifoFork_ready = fifoFork_thrown_ready; + if(when_Stream_l445) begin + fifoFork_ready = 1'b1; + end + end + + assign fifoFork_thrown_payload_last = fifoFork_payload_last; + assign fifoFork_thrown_payload_fragment_opcode = fifoFork_payload_fragment_opcode; + assign fifoFork_thrown_payload_fragment_address = fifoFork_payload_fragment_address; + assign fifoFork_thrown_payload_fragment_length = fifoFork_payload_fragment_length; + assign fifoFork_thrown_payload_fragment_context = fifoFork_payload_fragment_context; + assign fifoFork_thrown_translated_valid = fifoFork_thrown_valid; + assign fifoFork_thrown_ready = fifoFork_thrown_translated_ready; + assign fifoFork_thrown_translated_payload_context = pushCtx_context; + assign fifoFork_thrown_translated_ready = fifoFork_thrown_translated_fifo_io_push_ready; + always @(*) begin + fifoFork_thrown_translated_fifo_io_pop_ready = popCtx_ready; + if(when_Stream_l375) begin + fifoFork_thrown_translated_fifo_io_pop_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! popCtx_valid); + assign popCtx_valid = fifoFork_thrown_translated_fifo_io_pop_rValid; + assign popCtx_payload_context = fifoFork_thrown_translated_fifo_io_pop_rData_context; + assign popCtx_ready = ((io_output_rsp_valid && io_output_rsp_payload_last) && io_input_rsp_ready); + assign _zz_io_input_rsp_valid = (! (! popCtx_valid)); + assign io_output_rsp_ready = (io_input_rsp_ready && _zz_io_input_rsp_valid); + assign io_input_rsp_valid = (io_output_rsp_valid && _zz_io_input_rsp_valid); + assign io_input_rsp_payload_last = io_output_rsp_payload_last; + assign io_input_rsp_payload_fragment_opcode = io_output_rsp_payload_fragment_opcode; + assign io_input_rsp_payload_fragment_data = io_output_rsp_payload_fragment_data; + assign io_input_rsp_payload_fragment_context = popCtx_payload_context; + always @(posedge clk) begin + if(reset) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; + fifoFork_payload_first <= 1'b1; + fifoFork_thrown_translated_fifo_io_pop_rValid <= 1'b0; + end else begin + if(fifoFork_fire) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdFork_fire) begin + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_cmd_ready) begin + io_input_cmd_fork2_logic_linkEnable_0 <= 1'b1; + io_input_cmd_fork2_logic_linkEnable_1 <= 1'b1; + end + if(fifoFork_fire) begin + fifoFork_payload_first <= fifoFork_payload_last; + end + if(fifoFork_thrown_translated_fifo_io_pop_ready) begin + fifoFork_thrown_translated_fifo_io_pop_rValid <= fifoFork_thrown_translated_fifo_io_pop_valid; + end + end + end + + always @(posedge clk) begin + if(fifoFork_thrown_translated_fifo_io_pop_ready) begin + fifoFork_thrown_translated_fifo_io_pop_rData_context <= fifoFork_thrown_translated_fifo_io_pop_payload_context; + end + end + + +endmodule + +module EfxDMA_FlowCCUnsafeByToggle_1 ( + input wire io_input_valid, + input wire [31:0] io_input_payload_PRDATA, + input wire io_input_payload_PSLVERROR, + output wire io_output_valid, + output wire [31:0] io_output_payload_PRDATA, + output wire io_output_payload_PSLVERROR, + input wire clk, + input wire reset, + input wire ctrl_clk, + input wire ctrl_reset +); + + wire inputArea_target_buffercc_io_dataOut; + reg inputArea_target; + reg [31:0] inputArea_data_PRDATA; + reg inputArea_data_PSLVERROR; + wire outputArea_target; + reg outputArea_hit; + wire outputArea_flow_valid; + wire [31:0] outputArea_flow_payload_PRDATA; + wire outputArea_flow_payload_PSLVERROR; + reg outputArea_flow_m2sPipe_valid; + (* async_reg = "true" *) reg [31:0] outputArea_flow_m2sPipe_payload_PRDATA; + (* async_reg = "true" *) reg outputArea_flow_m2sPipe_payload_PSLVERROR; + + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC_1 inputArea_target_buffercc ( + .io_dataIn (inputArea_target ), //i + .io_dataOut (inputArea_target_buffercc_io_dataOut), //o + .ctrl_clk (ctrl_clk ), //i + .ctrl_reset (ctrl_reset ) //i + ); + assign outputArea_target = inputArea_target_buffercc_io_dataOut; + assign outputArea_flow_valid = (outputArea_target != outputArea_hit); + assign outputArea_flow_payload_PRDATA = inputArea_data_PRDATA; + assign outputArea_flow_payload_PSLVERROR = inputArea_data_PSLVERROR; + assign io_output_valid = outputArea_flow_m2sPipe_valid; + assign io_output_payload_PRDATA = outputArea_flow_m2sPipe_payload_PRDATA; + assign io_output_payload_PSLVERROR = outputArea_flow_m2sPipe_payload_PSLVERROR; + always @(posedge clk) begin + if(reset) begin + inputArea_target <= 1'b0; + end else begin + if(io_input_valid) begin + inputArea_target <= (! inputArea_target); + end + end + end + + always @(posedge clk) begin + if(io_input_valid) begin + inputArea_data_PRDATA <= io_input_payload_PRDATA; + inputArea_data_PSLVERROR <= io_input_payload_PSLVERROR; + end + end + + always @(posedge ctrl_clk) begin + if(ctrl_reset) begin + outputArea_flow_m2sPipe_valid <= 1'b0; + outputArea_hit <= 1'b0; + end else begin + outputArea_hit <= outputArea_target; + outputArea_flow_m2sPipe_valid <= outputArea_flow_valid; + end + end + + always @(posedge ctrl_clk) begin + if(outputArea_flow_valid) begin + outputArea_flow_m2sPipe_payload_PRDATA <= outputArea_flow_payload_PRDATA; + outputArea_flow_m2sPipe_payload_PSLVERROR <= outputArea_flow_payload_PSLVERROR; + end + end + + +endmodule + +module EfxDMA_FlowCCUnsafeByToggle ( + input wire io_input_valid, + input wire [13:0] io_input_payload_PADDR, + input wire io_input_payload_PWRITE, + input wire [31:0] io_input_payload_PWDATA, + output wire io_output_valid, + output wire [13:0] io_output_payload_PADDR, + output wire io_output_payload_PWRITE, + output wire [31:0] io_output_payload_PWDATA, + input wire ctrl_clk, + input wire ctrl_reset, + input wire clk, + input wire reset +); + + wire inputArea_target_buffercc_io_dataOut; + reg inputArea_target; + reg [13:0] inputArea_data_PADDR; + reg inputArea_data_PWRITE; + reg [31:0] inputArea_data_PWDATA; + wire outputArea_target; + reg outputArea_hit; + wire outputArea_flow_valid; + wire [13:0] outputArea_flow_payload_PADDR; + wire outputArea_flow_payload_PWRITE; + wire [31:0] outputArea_flow_payload_PWDATA; + + (* keep_hierarchy = "TRUE" *) EfxDMA_BufferCC inputArea_target_buffercc ( + .io_dataIn (inputArea_target ), //i + .io_dataOut (inputArea_target_buffercc_io_dataOut), //o + .clk (clk ), //i + .reset (reset ) //i + ); + assign outputArea_target = inputArea_target_buffercc_io_dataOut; + assign outputArea_flow_valid = (outputArea_target != outputArea_hit); + assign outputArea_flow_payload_PADDR = inputArea_data_PADDR; + assign outputArea_flow_payload_PWRITE = inputArea_data_PWRITE; + assign outputArea_flow_payload_PWDATA = inputArea_data_PWDATA; + assign io_output_valid = outputArea_flow_valid; + assign io_output_payload_PADDR = outputArea_flow_payload_PADDR; + assign io_output_payload_PWRITE = outputArea_flow_payload_PWRITE; + assign io_output_payload_PWDATA = outputArea_flow_payload_PWDATA; + always @(posedge ctrl_clk) begin + if(ctrl_reset) begin + inputArea_target <= 1'b0; + end else begin + if(io_input_valid) begin + inputArea_target <= (! inputArea_target); + end + end + end + + always @(posedge ctrl_clk) begin + if(io_input_valid) begin + inputArea_data_PADDR <= io_input_payload_PADDR; + inputArea_data_PWRITE <= io_input_payload_PWRITE; + inputArea_data_PWDATA <= io_input_payload_PWDATA; + end + end + + always @(posedge clk) begin + if(reset) begin + outputArea_hit <= 1'b0; + end else begin + outputArea_hit <= outputArea_target; + end + end + + +endmodule + +module EfxDMA_Aggregator ( + input wire io_input_valid, + output reg io_input_ready, + input wire [127:0] io_input_payload_data, + input wire [15:0] io_input_payload_mask, + output reg [127:0] io_output_data, + output reg [15:0] io_output_mask, + input wire io_output_enough, + input wire io_output_consume, + output wire io_output_consumed, + input wire [3:0] io_output_lastByteUsed, + output wire [3:0] io_output_usedUntil, + input wire io_flush, + input wire [3:0] io_offset, + input wire [11:0] io_burstLength, + input wire clk, + input wire reset +); + + reg [0:0] _zz_s0_countOnesLogic_0_1; + wire [0:0] _zz_s0_countOnesLogic_0_2; + reg [1:0] _zz_s0_countOnesLogic_1_1; + wire [1:0] _zz_s0_countOnesLogic_1_2; + reg [1:0] _zz_s0_countOnesLogic_2_1; + wire [2:0] _zz_s0_countOnesLogic_2_2; + reg [2:0] _zz_s0_countOnesLogic_3_9; + wire [2:0] _zz_s0_countOnesLogic_3_10; + reg [2:0] _zz_s0_countOnesLogic_3_11; + wire [2:0] _zz_s0_countOnesLogic_3_12; + wire [0:0] _zz_s0_countOnesLogic_3_13; + reg [2:0] _zz_s0_countOnesLogic_4_9; + wire [2:0] _zz_s0_countOnesLogic_4_10; + reg [2:0] _zz_s0_countOnesLogic_4_11; + wire [2:0] _zz_s0_countOnesLogic_4_12; + wire [1:0] _zz_s0_countOnesLogic_4_13; + reg [2:0] _zz_s0_countOnesLogic_5_9; + wire [2:0] _zz_s0_countOnesLogic_5_10; + reg [2:0] _zz_s0_countOnesLogic_5_11; + wire [2:0] _zz_s0_countOnesLogic_5_12; + wire [2:0] _zz_s0_countOnesLogic_6_9; + reg [2:0] _zz_s0_countOnesLogic_6_10; + wire [2:0] _zz_s0_countOnesLogic_6_11; + reg [2:0] _zz_s0_countOnesLogic_6_12; + wire [2:0] _zz_s0_countOnesLogic_6_13; + reg [2:0] _zz_s0_countOnesLogic_6_14; + wire [2:0] _zz_s0_countOnesLogic_6_15; + wire [0:0] _zz_s0_countOnesLogic_6_16; + wire [3:0] _zz_s0_countOnesLogic_7_9; + reg [3:0] _zz_s0_countOnesLogic_7_10; + wire [2:0] _zz_s0_countOnesLogic_7_11; + reg [3:0] _zz_s0_countOnesLogic_7_12; + wire [2:0] _zz_s0_countOnesLogic_7_13; + reg [3:0] _zz_s0_countOnesLogic_7_14; + wire [2:0] _zz_s0_countOnesLogic_7_15; + wire [1:0] _zz_s0_countOnesLogic_7_16; + wire [3:0] _zz_s0_countOnesLogic_8_9; + reg [3:0] _zz_s0_countOnesLogic_8_10; + wire [2:0] _zz_s0_countOnesLogic_8_11; + reg [3:0] _zz_s0_countOnesLogic_8_12; + wire [2:0] _zz_s0_countOnesLogic_8_13; + reg [3:0] _zz_s0_countOnesLogic_8_14; + wire [2:0] _zz_s0_countOnesLogic_8_15; + wire [3:0] _zz_s0_countOnesLogic_9_9; + reg [3:0] _zz_s0_countOnesLogic_9_10; + wire [2:0] _zz_s0_countOnesLogic_9_11; + reg [3:0] _zz_s0_countOnesLogic_9_12; + wire [2:0] _zz_s0_countOnesLogic_9_13; + wire [3:0] _zz_s0_countOnesLogic_9_14; + reg [3:0] _zz_s0_countOnesLogic_9_15; + wire [2:0] _zz_s0_countOnesLogic_9_16; + reg [3:0] _zz_s0_countOnesLogic_9_17; + wire [2:0] _zz_s0_countOnesLogic_9_18; + wire [0:0] _zz_s0_countOnesLogic_9_19; + wire [3:0] _zz_s0_countOnesLogic_10_9; + reg [3:0] _zz_s0_countOnesLogic_10_10; + wire [2:0] _zz_s0_countOnesLogic_10_11; + reg [3:0] _zz_s0_countOnesLogic_10_12; + wire [2:0] _zz_s0_countOnesLogic_10_13; + wire [3:0] _zz_s0_countOnesLogic_10_14; + reg [3:0] _zz_s0_countOnesLogic_10_15; + wire [2:0] _zz_s0_countOnesLogic_10_16; + reg [3:0] _zz_s0_countOnesLogic_10_17; + wire [2:0] _zz_s0_countOnesLogic_10_18; + wire [1:0] _zz_s0_countOnesLogic_10_19; + wire [3:0] _zz_s0_countOnesLogic_11_9; + reg [3:0] _zz_s0_countOnesLogic_11_10; + wire [2:0] _zz_s0_countOnesLogic_11_11; + reg [3:0] _zz_s0_countOnesLogic_11_12; + wire [2:0] _zz_s0_countOnesLogic_11_13; + wire [3:0] _zz_s0_countOnesLogic_11_14; + reg [3:0] _zz_s0_countOnesLogic_11_15; + wire [2:0] _zz_s0_countOnesLogic_11_16; + reg [3:0] _zz_s0_countOnesLogic_11_17; + wire [2:0] _zz_s0_countOnesLogic_11_18; + wire [3:0] _zz_s0_countOnesLogic_12_9; + wire [3:0] _zz_s0_countOnesLogic_12_10; + reg [3:0] _zz_s0_countOnesLogic_12_11; + wire [2:0] _zz_s0_countOnesLogic_12_12; + reg [3:0] _zz_s0_countOnesLogic_12_13; + wire [2:0] _zz_s0_countOnesLogic_12_14; + wire [3:0] _zz_s0_countOnesLogic_12_15; + reg [3:0] _zz_s0_countOnesLogic_12_16; + wire [2:0] _zz_s0_countOnesLogic_12_17; + reg [3:0] _zz_s0_countOnesLogic_12_18; + wire [2:0] _zz_s0_countOnesLogic_12_19; + reg [3:0] _zz_s0_countOnesLogic_12_20; + wire [2:0] _zz_s0_countOnesLogic_12_21; + wire [0:0] _zz_s0_countOnesLogic_12_22; + wire [3:0] _zz_s0_countOnesLogic_13_9; + wire [3:0] _zz_s0_countOnesLogic_13_10; + reg [3:0] _zz_s0_countOnesLogic_13_11; + wire [2:0] _zz_s0_countOnesLogic_13_12; + reg [3:0] _zz_s0_countOnesLogic_13_13; + wire [2:0] _zz_s0_countOnesLogic_13_14; + wire [3:0] _zz_s0_countOnesLogic_13_15; + reg [3:0] _zz_s0_countOnesLogic_13_16; + wire [2:0] _zz_s0_countOnesLogic_13_17; + reg [3:0] _zz_s0_countOnesLogic_13_18; + wire [2:0] _zz_s0_countOnesLogic_13_19; + reg [3:0] _zz_s0_countOnesLogic_13_20; + wire [2:0] _zz_s0_countOnesLogic_13_21; + wire [1:0] _zz_s0_countOnesLogic_13_22; + wire [3:0] _zz_s0_countOnesLogic_14_9; + wire [3:0] _zz_s0_countOnesLogic_14_10; + reg [3:0] _zz_s0_countOnesLogic_14_11; + wire [2:0] _zz_s0_countOnesLogic_14_12; + reg [3:0] _zz_s0_countOnesLogic_14_13; + wire [2:0] _zz_s0_countOnesLogic_14_14; + wire [3:0] _zz_s0_countOnesLogic_14_15; + reg [3:0] _zz_s0_countOnesLogic_14_16; + wire [2:0] _zz_s0_countOnesLogic_14_17; + reg [3:0] _zz_s0_countOnesLogic_14_18; + wire [2:0] _zz_s0_countOnesLogic_14_19; + reg [3:0] _zz_s0_countOnesLogic_14_20; + wire [2:0] _zz_s0_countOnesLogic_14_21; + wire [4:0] _zz_s0_countOnesLogic_15_8; + wire [4:0] _zz_s0_countOnesLogic_15_9; + reg [4:0] _zz_s0_countOnesLogic_15_10; + wire [2:0] _zz_s0_countOnesLogic_15_11; + reg [4:0] _zz_s0_countOnesLogic_15_12; + wire [2:0] _zz_s0_countOnesLogic_15_13; + wire [4:0] _zz_s0_countOnesLogic_15_14; + reg [4:0] _zz_s0_countOnesLogic_15_15; + wire [2:0] _zz_s0_countOnesLogic_15_16; + reg [4:0] _zz_s0_countOnesLogic_15_17; + wire [2:0] _zz_s0_countOnesLogic_15_18; + wire [4:0] _zz_s0_countOnesLogic_15_19; + reg [4:0] _zz_s0_countOnesLogic_15_20; + wire [2:0] _zz_s0_countOnesLogic_15_21; + reg [4:0] _zz_s0_countOnesLogic_15_22; + wire [2:0] _zz_s0_countOnesLogic_15_23; + wire [0:0] _zz_s0_countOnesLogic_15_24; + wire [4:0] _zz_s1_offsetNext; + wire [12:0] _zz_s1_byteCounter; + wire [3:0] _zz_s1_inputIndexes_1; + wire [3:0] _zz_s1_inputIndexes_2; + wire [3:0] _zz_s1_inputIndexes_3; + wire [3:0] _zz_s1_inputIndexes_4; + wire [3:0] _zz_s1_inputIndexes_5; + wire [3:0] _zz_s1_inputIndexes_6; + wire [3:0] _zz_s1_inputIndexes_7; + wire [0:0] _zz_s1_outputPayload_selValid_240; + wire [6:0] _zz_s1_outputPayload_selValid_241; + wire [0:0] _zz_s1_outputPayload_selValid_242; + wire [6:0] _zz_s1_outputPayload_selValid_243; + wire [0:0] _zz_s1_outputPayload_selValid_244; + wire [6:0] _zz_s1_outputPayload_selValid_245; + wire [0:0] _zz_s1_outputPayload_selValid_246; + wire [6:0] _zz_s1_outputPayload_selValid_247; + wire [0:0] _zz_s1_outputPayload_selValid_248; + wire [6:0] _zz_s1_outputPayload_selValid_249; + wire [0:0] _zz_s1_outputPayload_selValid_250; + wire [6:0] _zz_s1_outputPayload_selValid_251; + wire [0:0] _zz_s1_outputPayload_selValid_252; + wire [6:0] _zz_s1_outputPayload_selValid_253; + wire [0:0] _zz_s1_outputPayload_selValid_254; + wire [6:0] _zz_s1_outputPayload_selValid_255; + wire [0:0] _zz_s1_outputPayload_selValid_256; + wire [6:0] _zz_s1_outputPayload_selValid_257; + wire [0:0] _zz_s1_outputPayload_selValid_258; + wire [6:0] _zz_s1_outputPayload_selValid_259; + wire [0:0] _zz_s1_outputPayload_selValid_260; + wire [6:0] _zz_s1_outputPayload_selValid_261; + wire [0:0] _zz_s1_outputPayload_selValid_262; + wire [6:0] _zz_s1_outputPayload_selValid_263; + wire [0:0] _zz_s1_outputPayload_selValid_264; + wire [6:0] _zz_s1_outputPayload_selValid_265; + wire [0:0] _zz_s1_outputPayload_selValid_266; + wire [6:0] _zz_s1_outputPayload_selValid_267; + wire [0:0] _zz_s1_outputPayload_selValid_268; + wire [6:0] _zz_s1_outputPayload_selValid_269; + wire [0:0] _zz_s1_outputPayload_selValid_270; + wire [6:0] _zz_s1_outputPayload_selValid_271; + wire [12:0] _zz_when_DmaSg_l1464; + reg [7:0] _zz_s2_byteLogic_0_inputData; + reg [7:0] _zz_s2_byteLogic_1_inputData; + reg [7:0] _zz_s2_byteLogic_2_inputData; + reg [7:0] _zz_s2_byteLogic_3_inputData; + reg [7:0] _zz_s2_byteLogic_4_inputData; + reg [7:0] _zz_s2_byteLogic_5_inputData; + reg [7:0] _zz_s2_byteLogic_6_inputData; + reg [7:0] _zz_s2_byteLogic_7_inputData; + reg [7:0] _zz_s2_byteLogic_8_inputData; + reg [7:0] _zz_s2_byteLogic_9_inputData; + reg [7:0] _zz_s2_byteLogic_10_inputData; + reg [7:0] _zz_s2_byteLogic_11_inputData; + reg [7:0] _zz_s2_byteLogic_12_inputData; + reg [7:0] _zz_s2_byteLogic_13_inputData; + reg [7:0] _zz_s2_byteLogic_14_inputData; + reg [7:0] _zz_s2_byteLogic_15_inputData; + reg [3:0] _zz_io_output_usedUntil_4; + wire [3:0] _zz_io_output_usedUntil_5; + wire s0_input_valid; + wire s0_input_ready; + wire [127:0] s0_input_payload_data; + wire [15:0] s0_input_payload_mask; + reg io_input_rValid; + reg [127:0] io_input_rData_data; + reg [15:0] io_input_rData_mask; + wire when_Stream_l375; + wire _zz_s0_countOnesLogic_0; + wire _zz_s0_countOnesLogic_1; + wire _zz_s0_countOnesLogic_2; + wire _zz_s0_countOnesLogic_3; + wire _zz_s0_countOnesLogic_4; + wire _zz_s0_countOnesLogic_5; + wire _zz_s0_countOnesLogic_6; + wire _zz_s0_countOnesLogic_7; + wire _zz_s0_countOnesLogic_8; + wire _zz_s0_countOnesLogic_9; + wire _zz_s0_countOnesLogic_10; + wire _zz_s0_countOnesLogic_11; + wire _zz_s0_countOnesLogic_12; + wire _zz_s0_countOnesLogic_13; + wire _zz_s0_countOnesLogic_14; + wire [0:0] s0_countOnesLogic_0; + wire [1:0] s0_countOnesLogic_1; + wire [1:0] s0_countOnesLogic_2; + wire [2:0] _zz_s0_countOnesLogic_3_1; + wire [2:0] _zz_s0_countOnesLogic_3_2; + wire [2:0] _zz_s0_countOnesLogic_3_3; + wire [2:0] _zz_s0_countOnesLogic_3_4; + wire [2:0] _zz_s0_countOnesLogic_3_5; + wire [2:0] _zz_s0_countOnesLogic_3_6; + wire [2:0] _zz_s0_countOnesLogic_3_7; + wire [2:0] _zz_s0_countOnesLogic_3_8; + wire [2:0] s0_countOnesLogic_3; + wire [2:0] _zz_s0_countOnesLogic_4_1; + wire [2:0] _zz_s0_countOnesLogic_4_2; + wire [2:0] _zz_s0_countOnesLogic_4_3; + wire [2:0] _zz_s0_countOnesLogic_4_4; + wire [2:0] _zz_s0_countOnesLogic_4_5; + wire [2:0] _zz_s0_countOnesLogic_4_6; + wire [2:0] _zz_s0_countOnesLogic_4_7; + wire [2:0] _zz_s0_countOnesLogic_4_8; + wire [2:0] s0_countOnesLogic_4; + wire [2:0] _zz_s0_countOnesLogic_5_1; + wire [2:0] _zz_s0_countOnesLogic_5_2; + wire [2:0] _zz_s0_countOnesLogic_5_3; + wire [2:0] _zz_s0_countOnesLogic_5_4; + wire [2:0] _zz_s0_countOnesLogic_5_5; + wire [2:0] _zz_s0_countOnesLogic_5_6; + wire [2:0] _zz_s0_countOnesLogic_5_7; + wire [2:0] _zz_s0_countOnesLogic_5_8; + wire [2:0] s0_countOnesLogic_5; + wire [2:0] _zz_s0_countOnesLogic_6_1; + wire [2:0] _zz_s0_countOnesLogic_6_2; + wire [2:0] _zz_s0_countOnesLogic_6_3; + wire [2:0] _zz_s0_countOnesLogic_6_4; + wire [2:0] _zz_s0_countOnesLogic_6_5; + wire [2:0] _zz_s0_countOnesLogic_6_6; + wire [2:0] _zz_s0_countOnesLogic_6_7; + wire [2:0] _zz_s0_countOnesLogic_6_8; + wire [2:0] s0_countOnesLogic_6; + wire [3:0] _zz_s0_countOnesLogic_7_1; + wire [3:0] _zz_s0_countOnesLogic_7_2; + wire [3:0] _zz_s0_countOnesLogic_7_3; + wire [3:0] _zz_s0_countOnesLogic_7_4; + wire [3:0] _zz_s0_countOnesLogic_7_5; + wire [3:0] _zz_s0_countOnesLogic_7_6; + wire [3:0] _zz_s0_countOnesLogic_7_7; + wire [3:0] _zz_s0_countOnesLogic_7_8; + wire [3:0] s0_countOnesLogic_7; + wire [3:0] _zz_s0_countOnesLogic_8_1; + wire [3:0] _zz_s0_countOnesLogic_8_2; + wire [3:0] _zz_s0_countOnesLogic_8_3; + wire [3:0] _zz_s0_countOnesLogic_8_4; + wire [3:0] _zz_s0_countOnesLogic_8_5; + wire [3:0] _zz_s0_countOnesLogic_8_6; + wire [3:0] _zz_s0_countOnesLogic_8_7; + wire [3:0] _zz_s0_countOnesLogic_8_8; + wire [3:0] s0_countOnesLogic_8; + wire [3:0] _zz_s0_countOnesLogic_9_1; + wire [3:0] _zz_s0_countOnesLogic_9_2; + wire [3:0] _zz_s0_countOnesLogic_9_3; + wire [3:0] _zz_s0_countOnesLogic_9_4; + wire [3:0] _zz_s0_countOnesLogic_9_5; + wire [3:0] _zz_s0_countOnesLogic_9_6; + wire [3:0] _zz_s0_countOnesLogic_9_7; + wire [3:0] _zz_s0_countOnesLogic_9_8; + wire [3:0] s0_countOnesLogic_9; + wire [3:0] _zz_s0_countOnesLogic_10_1; + wire [3:0] _zz_s0_countOnesLogic_10_2; + wire [3:0] _zz_s0_countOnesLogic_10_3; + wire [3:0] _zz_s0_countOnesLogic_10_4; + wire [3:0] _zz_s0_countOnesLogic_10_5; + wire [3:0] _zz_s0_countOnesLogic_10_6; + wire [3:0] _zz_s0_countOnesLogic_10_7; + wire [3:0] _zz_s0_countOnesLogic_10_8; + wire [3:0] s0_countOnesLogic_10; + wire [3:0] _zz_s0_countOnesLogic_11_1; + wire [3:0] _zz_s0_countOnesLogic_11_2; + wire [3:0] _zz_s0_countOnesLogic_11_3; + wire [3:0] _zz_s0_countOnesLogic_11_4; + wire [3:0] _zz_s0_countOnesLogic_11_5; + wire [3:0] _zz_s0_countOnesLogic_11_6; + wire [3:0] _zz_s0_countOnesLogic_11_7; + wire [3:0] _zz_s0_countOnesLogic_11_8; + wire [3:0] s0_countOnesLogic_11; + wire [3:0] _zz_s0_countOnesLogic_12_1; + wire [3:0] _zz_s0_countOnesLogic_12_2; + wire [3:0] _zz_s0_countOnesLogic_12_3; + wire [3:0] _zz_s0_countOnesLogic_12_4; + wire [3:0] _zz_s0_countOnesLogic_12_5; + wire [3:0] _zz_s0_countOnesLogic_12_6; + wire [3:0] _zz_s0_countOnesLogic_12_7; + wire [3:0] _zz_s0_countOnesLogic_12_8; + wire [3:0] s0_countOnesLogic_12; + wire [3:0] _zz_s0_countOnesLogic_13_1; + wire [3:0] _zz_s0_countOnesLogic_13_2; + wire [3:0] _zz_s0_countOnesLogic_13_3; + wire [3:0] _zz_s0_countOnesLogic_13_4; + wire [3:0] _zz_s0_countOnesLogic_13_5; + wire [3:0] _zz_s0_countOnesLogic_13_6; + wire [3:0] _zz_s0_countOnesLogic_13_7; + wire [3:0] _zz_s0_countOnesLogic_13_8; + wire [3:0] s0_countOnesLogic_13; + wire [3:0] _zz_s0_countOnesLogic_14_1; + wire [3:0] _zz_s0_countOnesLogic_14_2; + wire [3:0] _zz_s0_countOnesLogic_14_3; + wire [3:0] _zz_s0_countOnesLogic_14_4; + wire [3:0] _zz_s0_countOnesLogic_14_5; + wire [3:0] _zz_s0_countOnesLogic_14_6; + wire [3:0] _zz_s0_countOnesLogic_14_7; + wire [3:0] _zz_s0_countOnesLogic_14_8; + wire [3:0] s0_countOnesLogic_14; + wire [4:0] _zz_s0_countOnesLogic_15; + wire [4:0] _zz_s0_countOnesLogic_15_1; + wire [4:0] _zz_s0_countOnesLogic_15_2; + wire [4:0] _zz_s0_countOnesLogic_15_3; + wire [4:0] _zz_s0_countOnesLogic_15_4; + wire [4:0] _zz_s0_countOnesLogic_15_5; + wire [4:0] _zz_s0_countOnesLogic_15_6; + wire [4:0] _zz_s0_countOnesLogic_15_7; + wire [4:0] s0_countOnesLogic_15; + wire [127:0] s0_outputPayload_cmd_data; + wire [15:0] s0_outputPayload_cmd_mask; + wire [0:0] s0_outputPayload_countOnes_0; + wire [1:0] s0_outputPayload_countOnes_1; + wire [1:0] s0_outputPayload_countOnes_2; + wire [2:0] s0_outputPayload_countOnes_3; + wire [2:0] s0_outputPayload_countOnes_4; + wire [2:0] s0_outputPayload_countOnes_5; + wire [2:0] s0_outputPayload_countOnes_6; + wire [3:0] s0_outputPayload_countOnes_7; + wire [3:0] s0_outputPayload_countOnes_8; + wire [3:0] s0_outputPayload_countOnes_9; + wire [3:0] s0_outputPayload_countOnes_10; + wire [3:0] s0_outputPayload_countOnes_11; + wire [3:0] s0_outputPayload_countOnes_12; + wire [3:0] s0_outputPayload_countOnes_13; + wire [3:0] s0_outputPayload_countOnes_14; + wire [4:0] s0_outputPayload_countOnes_15; + wire s0_output_valid; + reg s0_output_ready; + wire [127:0] s0_output_payload_cmd_data; + wire [15:0] s0_output_payload_cmd_mask; + wire [0:0] s0_output_payload_countOnes_0; + wire [1:0] s0_output_payload_countOnes_1; + wire [1:0] s0_output_payload_countOnes_2; + wire [2:0] s0_output_payload_countOnes_3; + wire [2:0] s0_output_payload_countOnes_4; + wire [2:0] s0_output_payload_countOnes_5; + wire [2:0] s0_output_payload_countOnes_6; + wire [3:0] s0_output_payload_countOnes_7; + wire [3:0] s0_output_payload_countOnes_8; + wire [3:0] s0_output_payload_countOnes_9; + wire [3:0] s0_output_payload_countOnes_10; + wire [3:0] s0_output_payload_countOnes_11; + wire [3:0] s0_output_payload_countOnes_12; + wire [3:0] s0_output_payload_countOnes_13; + wire [3:0] s0_output_payload_countOnes_14; + wire [4:0] s0_output_payload_countOnes_15; + wire s1_input_valid; + wire s1_input_ready; + wire [127:0] s1_input_payload_cmd_data; + wire [15:0] s1_input_payload_cmd_mask; + wire [0:0] s1_input_payload_countOnes_0; + wire [1:0] s1_input_payload_countOnes_1; + wire [1:0] s1_input_payload_countOnes_2; + wire [2:0] s1_input_payload_countOnes_3; + wire [2:0] s1_input_payload_countOnes_4; + wire [2:0] s1_input_payload_countOnes_5; + wire [2:0] s1_input_payload_countOnes_6; + wire [3:0] s1_input_payload_countOnes_7; + wire [3:0] s1_input_payload_countOnes_8; + wire [3:0] s1_input_payload_countOnes_9; + wire [3:0] s1_input_payload_countOnes_10; + wire [3:0] s1_input_payload_countOnes_11; + wire [3:0] s1_input_payload_countOnes_12; + wire [3:0] s1_input_payload_countOnes_13; + wire [3:0] s1_input_payload_countOnes_14; + wire [4:0] s1_input_payload_countOnes_15; + reg s0_output_rValid; + reg [127:0] s0_output_rData_cmd_data; + reg [15:0] s0_output_rData_cmd_mask; + reg [0:0] s0_output_rData_countOnes_0; + reg [1:0] s0_output_rData_countOnes_1; + reg [1:0] s0_output_rData_countOnes_2; + reg [2:0] s0_output_rData_countOnes_3; + reg [2:0] s0_output_rData_countOnes_4; + reg [2:0] s0_output_rData_countOnes_5; + reg [2:0] s0_output_rData_countOnes_6; + reg [3:0] s0_output_rData_countOnes_7; + reg [3:0] s0_output_rData_countOnes_8; + reg [3:0] s0_output_rData_countOnes_9; + reg [3:0] s0_output_rData_countOnes_10; + reg [3:0] s0_output_rData_countOnes_11; + reg [3:0] s0_output_rData_countOnes_12; + reg [3:0] s0_output_rData_countOnes_13; + reg [3:0] s0_output_rData_countOnes_14; + reg [4:0] s0_output_rData_countOnes_15; + wire when_Stream_l375_1; + reg [3:0] s1_offset; + wire [4:0] s1_offsetNext; + wire s1_input_fire; + reg [12:0] s1_byteCounter; + wire [3:0] s1_inputIndexes_0; + wire [3:0] s1_inputIndexes_1; + wire [3:0] s1_inputIndexes_2; + wire [3:0] s1_inputIndexes_3; + wire [3:0] s1_inputIndexes_4; + wire [3:0] s1_inputIndexes_5; + wire [3:0] s1_inputIndexes_6; + wire [3:0] s1_inputIndexes_7; + wire [3:0] s1_inputIndexes_8; + wire [3:0] s1_inputIndexes_9; + wire [3:0] s1_inputIndexes_10; + wire [3:0] s1_inputIndexes_11; + wire [3:0] s1_inputIndexes_12; + wire [3:0] s1_inputIndexes_13; + wire [3:0] s1_inputIndexes_14; + wire [3:0] s1_inputIndexes_15; + wire [127:0] s1_outputPayload_cmd_data; + wire [15:0] s1_outputPayload_cmd_mask; + wire [3:0] s1_outputPayload_index_0; + wire [3:0] s1_outputPayload_index_1; + wire [3:0] s1_outputPayload_index_2; + wire [3:0] s1_outputPayload_index_3; + wire [3:0] s1_outputPayload_index_4; + wire [3:0] s1_outputPayload_index_5; + wire [3:0] s1_outputPayload_index_6; + wire [3:0] s1_outputPayload_index_7; + wire [3:0] s1_outputPayload_index_8; + wire [3:0] s1_outputPayload_index_9; + wire [3:0] s1_outputPayload_index_10; + wire [3:0] s1_outputPayload_index_11; + wire [3:0] s1_outputPayload_index_12; + wire [3:0] s1_outputPayload_index_13; + wire [3:0] s1_outputPayload_index_14; + wire [3:0] s1_outputPayload_index_15; + wire s1_outputPayload_last; + wire [3:0] s1_outputPayload_sel_0; + wire [3:0] s1_outputPayload_sel_1; + wire [3:0] s1_outputPayload_sel_2; + wire [3:0] s1_outputPayload_sel_3; + wire [3:0] s1_outputPayload_sel_4; + wire [3:0] s1_outputPayload_sel_5; + wire [3:0] s1_outputPayload_sel_6; + wire [3:0] s1_outputPayload_sel_7; + wire [3:0] s1_outputPayload_sel_8; + wire [3:0] s1_outputPayload_sel_9; + wire [3:0] s1_outputPayload_sel_10; + wire [3:0] s1_outputPayload_sel_11; + wire [3:0] s1_outputPayload_sel_12; + wire [3:0] s1_outputPayload_sel_13; + wire [3:0] s1_outputPayload_sel_14; + wire [3:0] s1_outputPayload_sel_15; + reg [15:0] s1_outputPayload_selValid; + wire _zz_s1_outputPayload_selValid; + wire _zz_s1_outputPayload_selValid_1; + wire _zz_s1_outputPayload_selValid_2; + wire _zz_s1_outputPayload_selValid_3; + wire _zz_s1_outputPayload_selValid_4; + wire _zz_s1_outputPayload_selValid_5; + wire _zz_s1_outputPayload_selValid_6; + wire _zz_s1_outputPayload_selValid_7; + wire _zz_s1_outputPayload_selValid_8; + wire _zz_s1_outputPayload_selValid_9; + wire _zz_s1_outputPayload_selValid_10; + wire _zz_s1_outputPayload_selValid_11; + wire _zz_s1_outputPayload_selValid_12; + wire _zz_s1_outputPayload_selValid_13; + wire _zz_s1_outputPayload_selValid_14; + wire _zz_s1_outputPayload_sel_0; + wire _zz_s1_outputPayload_sel_0_1; + wire _zz_s1_outputPayload_sel_0_2; + wire _zz_s1_outputPayload_sel_0_3; + wire _zz_s1_outputPayload_selValid_15; + wire _zz_s1_outputPayload_selValid_16; + wire _zz_s1_outputPayload_selValid_17; + wire _zz_s1_outputPayload_selValid_18; + wire _zz_s1_outputPayload_selValid_19; + wire _zz_s1_outputPayload_selValid_20; + wire _zz_s1_outputPayload_selValid_21; + wire _zz_s1_outputPayload_selValid_22; + wire _zz_s1_outputPayload_selValid_23; + wire _zz_s1_outputPayload_selValid_24; + wire _zz_s1_outputPayload_selValid_25; + wire _zz_s1_outputPayload_selValid_26; + wire _zz_s1_outputPayload_selValid_27; + wire _zz_s1_outputPayload_selValid_28; + wire _zz_s1_outputPayload_selValid_29; + wire _zz_s1_outputPayload_sel_1; + wire _zz_s1_outputPayload_sel_1_1; + wire _zz_s1_outputPayload_sel_1_2; + wire _zz_s1_outputPayload_sel_1_3; + wire _zz_s1_outputPayload_selValid_30; + wire _zz_s1_outputPayload_selValid_31; + wire _zz_s1_outputPayload_selValid_32; + wire _zz_s1_outputPayload_selValid_33; + wire _zz_s1_outputPayload_selValid_34; + wire _zz_s1_outputPayload_selValid_35; + wire _zz_s1_outputPayload_selValid_36; + wire _zz_s1_outputPayload_selValid_37; + wire _zz_s1_outputPayload_selValid_38; + wire _zz_s1_outputPayload_selValid_39; + wire _zz_s1_outputPayload_selValid_40; + wire _zz_s1_outputPayload_selValid_41; + wire _zz_s1_outputPayload_selValid_42; + wire _zz_s1_outputPayload_selValid_43; + wire _zz_s1_outputPayload_selValid_44; + wire _zz_s1_outputPayload_sel_2; + wire _zz_s1_outputPayload_sel_2_1; + wire _zz_s1_outputPayload_sel_2_2; + wire _zz_s1_outputPayload_sel_2_3; + wire _zz_s1_outputPayload_selValid_45; + wire _zz_s1_outputPayload_selValid_46; + wire _zz_s1_outputPayload_selValid_47; + wire _zz_s1_outputPayload_selValid_48; + wire _zz_s1_outputPayload_selValid_49; + wire _zz_s1_outputPayload_selValid_50; + wire _zz_s1_outputPayload_selValid_51; + wire _zz_s1_outputPayload_selValid_52; + wire _zz_s1_outputPayload_selValid_53; + wire _zz_s1_outputPayload_selValid_54; + wire _zz_s1_outputPayload_selValid_55; + wire _zz_s1_outputPayload_selValid_56; + wire _zz_s1_outputPayload_selValid_57; + wire _zz_s1_outputPayload_selValid_58; + wire _zz_s1_outputPayload_selValid_59; + wire _zz_s1_outputPayload_sel_3; + wire _zz_s1_outputPayload_sel_3_1; + wire _zz_s1_outputPayload_sel_3_2; + wire _zz_s1_outputPayload_sel_3_3; + wire _zz_s1_outputPayload_selValid_60; + wire _zz_s1_outputPayload_selValid_61; + wire _zz_s1_outputPayload_selValid_62; + wire _zz_s1_outputPayload_selValid_63; + wire _zz_s1_outputPayload_selValid_64; + wire _zz_s1_outputPayload_selValid_65; + wire _zz_s1_outputPayload_selValid_66; + wire _zz_s1_outputPayload_selValid_67; + wire _zz_s1_outputPayload_selValid_68; + wire _zz_s1_outputPayload_selValid_69; + wire _zz_s1_outputPayload_selValid_70; + wire _zz_s1_outputPayload_selValid_71; + wire _zz_s1_outputPayload_selValid_72; + wire _zz_s1_outputPayload_selValid_73; + wire _zz_s1_outputPayload_selValid_74; + wire _zz_s1_outputPayload_sel_4; + wire _zz_s1_outputPayload_sel_4_1; + wire _zz_s1_outputPayload_sel_4_2; + wire _zz_s1_outputPayload_sel_4_3; + wire _zz_s1_outputPayload_selValid_75; + wire _zz_s1_outputPayload_selValid_76; + wire _zz_s1_outputPayload_selValid_77; + wire _zz_s1_outputPayload_selValid_78; + wire _zz_s1_outputPayload_selValid_79; + wire _zz_s1_outputPayload_selValid_80; + wire _zz_s1_outputPayload_selValid_81; + wire _zz_s1_outputPayload_selValid_82; + wire _zz_s1_outputPayload_selValid_83; + wire _zz_s1_outputPayload_selValid_84; + wire _zz_s1_outputPayload_selValid_85; + wire _zz_s1_outputPayload_selValid_86; + wire _zz_s1_outputPayload_selValid_87; + wire _zz_s1_outputPayload_selValid_88; + wire _zz_s1_outputPayload_selValid_89; + wire _zz_s1_outputPayload_sel_5; + wire _zz_s1_outputPayload_sel_5_1; + wire _zz_s1_outputPayload_sel_5_2; + wire _zz_s1_outputPayload_sel_5_3; + wire _zz_s1_outputPayload_selValid_90; + wire _zz_s1_outputPayload_selValid_91; + wire _zz_s1_outputPayload_selValid_92; + wire _zz_s1_outputPayload_selValid_93; + wire _zz_s1_outputPayload_selValid_94; + wire _zz_s1_outputPayload_selValid_95; + wire _zz_s1_outputPayload_selValid_96; + wire _zz_s1_outputPayload_selValid_97; + wire _zz_s1_outputPayload_selValid_98; + wire _zz_s1_outputPayload_selValid_99; + wire _zz_s1_outputPayload_selValid_100; + wire _zz_s1_outputPayload_selValid_101; + wire _zz_s1_outputPayload_selValid_102; + wire _zz_s1_outputPayload_selValid_103; + wire _zz_s1_outputPayload_selValid_104; + wire _zz_s1_outputPayload_sel_6; + wire _zz_s1_outputPayload_sel_6_1; + wire _zz_s1_outputPayload_sel_6_2; + wire _zz_s1_outputPayload_sel_6_3; + wire _zz_s1_outputPayload_selValid_105; + wire _zz_s1_outputPayload_selValid_106; + wire _zz_s1_outputPayload_selValid_107; + wire _zz_s1_outputPayload_selValid_108; + wire _zz_s1_outputPayload_selValid_109; + wire _zz_s1_outputPayload_selValid_110; + wire _zz_s1_outputPayload_selValid_111; + wire _zz_s1_outputPayload_selValid_112; + wire _zz_s1_outputPayload_selValid_113; + wire _zz_s1_outputPayload_selValid_114; + wire _zz_s1_outputPayload_selValid_115; + wire _zz_s1_outputPayload_selValid_116; + wire _zz_s1_outputPayload_selValid_117; + wire _zz_s1_outputPayload_selValid_118; + wire _zz_s1_outputPayload_selValid_119; + wire _zz_s1_outputPayload_sel_7; + wire _zz_s1_outputPayload_sel_7_1; + wire _zz_s1_outputPayload_sel_7_2; + wire _zz_s1_outputPayload_sel_7_3; + wire _zz_s1_outputPayload_selValid_120; + wire _zz_s1_outputPayload_selValid_121; + wire _zz_s1_outputPayload_selValid_122; + wire _zz_s1_outputPayload_selValid_123; + wire _zz_s1_outputPayload_selValid_124; + wire _zz_s1_outputPayload_selValid_125; + wire _zz_s1_outputPayload_selValid_126; + wire _zz_s1_outputPayload_selValid_127; + wire _zz_s1_outputPayload_selValid_128; + wire _zz_s1_outputPayload_selValid_129; + wire _zz_s1_outputPayload_selValid_130; + wire _zz_s1_outputPayload_selValid_131; + wire _zz_s1_outputPayload_selValid_132; + wire _zz_s1_outputPayload_selValid_133; + wire _zz_s1_outputPayload_selValid_134; + wire _zz_s1_outputPayload_sel_8; + wire _zz_s1_outputPayload_sel_8_1; + wire _zz_s1_outputPayload_sel_8_2; + wire _zz_s1_outputPayload_sel_8_3; + wire _zz_s1_outputPayload_selValid_135; + wire _zz_s1_outputPayload_selValid_136; + wire _zz_s1_outputPayload_selValid_137; + wire _zz_s1_outputPayload_selValid_138; + wire _zz_s1_outputPayload_selValid_139; + wire _zz_s1_outputPayload_selValid_140; + wire _zz_s1_outputPayload_selValid_141; + wire _zz_s1_outputPayload_selValid_142; + wire _zz_s1_outputPayload_selValid_143; + wire _zz_s1_outputPayload_selValid_144; + wire _zz_s1_outputPayload_selValid_145; + wire _zz_s1_outputPayload_selValid_146; + wire _zz_s1_outputPayload_selValid_147; + wire _zz_s1_outputPayload_selValid_148; + wire _zz_s1_outputPayload_selValid_149; + wire _zz_s1_outputPayload_sel_9; + wire _zz_s1_outputPayload_sel_9_1; + wire _zz_s1_outputPayload_sel_9_2; + wire _zz_s1_outputPayload_sel_9_3; + wire _zz_s1_outputPayload_selValid_150; + wire _zz_s1_outputPayload_selValid_151; + wire _zz_s1_outputPayload_selValid_152; + wire _zz_s1_outputPayload_selValid_153; + wire _zz_s1_outputPayload_selValid_154; + wire _zz_s1_outputPayload_selValid_155; + wire _zz_s1_outputPayload_selValid_156; + wire _zz_s1_outputPayload_selValid_157; + wire _zz_s1_outputPayload_selValid_158; + wire _zz_s1_outputPayload_selValid_159; + wire _zz_s1_outputPayload_selValid_160; + wire _zz_s1_outputPayload_selValid_161; + wire _zz_s1_outputPayload_selValid_162; + wire _zz_s1_outputPayload_selValid_163; + wire _zz_s1_outputPayload_selValid_164; + wire _zz_s1_outputPayload_sel_10; + wire _zz_s1_outputPayload_sel_10_1; + wire _zz_s1_outputPayload_sel_10_2; + wire _zz_s1_outputPayload_sel_10_3; + wire _zz_s1_outputPayload_selValid_165; + wire _zz_s1_outputPayload_selValid_166; + wire _zz_s1_outputPayload_selValid_167; + wire _zz_s1_outputPayload_selValid_168; + wire _zz_s1_outputPayload_selValid_169; + wire _zz_s1_outputPayload_selValid_170; + wire _zz_s1_outputPayload_selValid_171; + wire _zz_s1_outputPayload_selValid_172; + wire _zz_s1_outputPayload_selValid_173; + wire _zz_s1_outputPayload_selValid_174; + wire _zz_s1_outputPayload_selValid_175; + wire _zz_s1_outputPayload_selValid_176; + wire _zz_s1_outputPayload_selValid_177; + wire _zz_s1_outputPayload_selValid_178; + wire _zz_s1_outputPayload_selValid_179; + wire _zz_s1_outputPayload_sel_11; + wire _zz_s1_outputPayload_sel_11_1; + wire _zz_s1_outputPayload_sel_11_2; + wire _zz_s1_outputPayload_sel_11_3; + wire _zz_s1_outputPayload_selValid_180; + wire _zz_s1_outputPayload_selValid_181; + wire _zz_s1_outputPayload_selValid_182; + wire _zz_s1_outputPayload_selValid_183; + wire _zz_s1_outputPayload_selValid_184; + wire _zz_s1_outputPayload_selValid_185; + wire _zz_s1_outputPayload_selValid_186; + wire _zz_s1_outputPayload_selValid_187; + wire _zz_s1_outputPayload_selValid_188; + wire _zz_s1_outputPayload_selValid_189; + wire _zz_s1_outputPayload_selValid_190; + wire _zz_s1_outputPayload_selValid_191; + wire _zz_s1_outputPayload_selValid_192; + wire _zz_s1_outputPayload_selValid_193; + wire _zz_s1_outputPayload_selValid_194; + wire _zz_s1_outputPayload_sel_12; + wire _zz_s1_outputPayload_sel_12_1; + wire _zz_s1_outputPayload_sel_12_2; + wire _zz_s1_outputPayload_sel_12_3; + wire _zz_s1_outputPayload_selValid_195; + wire _zz_s1_outputPayload_selValid_196; + wire _zz_s1_outputPayload_selValid_197; + wire _zz_s1_outputPayload_selValid_198; + wire _zz_s1_outputPayload_selValid_199; + wire _zz_s1_outputPayload_selValid_200; + wire _zz_s1_outputPayload_selValid_201; + wire _zz_s1_outputPayload_selValid_202; + wire _zz_s1_outputPayload_selValid_203; + wire _zz_s1_outputPayload_selValid_204; + wire _zz_s1_outputPayload_selValid_205; + wire _zz_s1_outputPayload_selValid_206; + wire _zz_s1_outputPayload_selValid_207; + wire _zz_s1_outputPayload_selValid_208; + wire _zz_s1_outputPayload_selValid_209; + wire _zz_s1_outputPayload_sel_13; + wire _zz_s1_outputPayload_sel_13_1; + wire _zz_s1_outputPayload_sel_13_2; + wire _zz_s1_outputPayload_sel_13_3; + wire _zz_s1_outputPayload_selValid_210; + wire _zz_s1_outputPayload_selValid_211; + wire _zz_s1_outputPayload_selValid_212; + wire _zz_s1_outputPayload_selValid_213; + wire _zz_s1_outputPayload_selValid_214; + wire _zz_s1_outputPayload_selValid_215; + wire _zz_s1_outputPayload_selValid_216; + wire _zz_s1_outputPayload_selValid_217; + wire _zz_s1_outputPayload_selValid_218; + wire _zz_s1_outputPayload_selValid_219; + wire _zz_s1_outputPayload_selValid_220; + wire _zz_s1_outputPayload_selValid_221; + wire _zz_s1_outputPayload_selValid_222; + wire _zz_s1_outputPayload_selValid_223; + wire _zz_s1_outputPayload_selValid_224; + wire _zz_s1_outputPayload_sel_14; + wire _zz_s1_outputPayload_sel_14_1; + wire _zz_s1_outputPayload_sel_14_2; + wire _zz_s1_outputPayload_sel_14_3; + wire _zz_s1_outputPayload_selValid_225; + wire _zz_s1_outputPayload_selValid_226; + wire _zz_s1_outputPayload_selValid_227; + wire _zz_s1_outputPayload_selValid_228; + wire _zz_s1_outputPayload_selValid_229; + wire _zz_s1_outputPayload_selValid_230; + wire _zz_s1_outputPayload_selValid_231; + wire _zz_s1_outputPayload_selValid_232; + wire _zz_s1_outputPayload_selValid_233; + wire _zz_s1_outputPayload_selValid_234; + wire _zz_s1_outputPayload_selValid_235; + wire _zz_s1_outputPayload_selValid_236; + wire _zz_s1_outputPayload_selValid_237; + wire _zz_s1_outputPayload_selValid_238; + wire _zz_s1_outputPayload_selValid_239; + wire _zz_s1_outputPayload_sel_15; + wire _zz_s1_outputPayload_sel_15_1; + wire _zz_s1_outputPayload_sel_15_2; + wire _zz_s1_outputPayload_sel_15_3; + wire s1_output_valid; + reg s1_output_ready; + wire [127:0] s1_output_payload_cmd_data; + wire [15:0] s1_output_payload_cmd_mask; + wire [3:0] s1_output_payload_index_0; + wire [3:0] s1_output_payload_index_1; + wire [3:0] s1_output_payload_index_2; + wire [3:0] s1_output_payload_index_3; + wire [3:0] s1_output_payload_index_4; + wire [3:0] s1_output_payload_index_5; + wire [3:0] s1_output_payload_index_6; + wire [3:0] s1_output_payload_index_7; + wire [3:0] s1_output_payload_index_8; + wire [3:0] s1_output_payload_index_9; + wire [3:0] s1_output_payload_index_10; + wire [3:0] s1_output_payload_index_11; + wire [3:0] s1_output_payload_index_12; + wire [3:0] s1_output_payload_index_13; + wire [3:0] s1_output_payload_index_14; + wire [3:0] s1_output_payload_index_15; + wire s1_output_payload_last; + wire [3:0] s1_output_payload_sel_0; + wire [3:0] s1_output_payload_sel_1; + wire [3:0] s1_output_payload_sel_2; + wire [3:0] s1_output_payload_sel_3; + wire [3:0] s1_output_payload_sel_4; + wire [3:0] s1_output_payload_sel_5; + wire [3:0] s1_output_payload_sel_6; + wire [3:0] s1_output_payload_sel_7; + wire [3:0] s1_output_payload_sel_8; + wire [3:0] s1_output_payload_sel_9; + wire [3:0] s1_output_payload_sel_10; + wire [3:0] s1_output_payload_sel_11; + wire [3:0] s1_output_payload_sel_12; + wire [3:0] s1_output_payload_sel_13; + wire [3:0] s1_output_payload_sel_14; + wire [3:0] s1_output_payload_sel_15; + wire [15:0] s1_output_payload_selValid; + wire s2_input_valid; + reg s2_input_ready; + wire [127:0] s2_input_payload_cmd_data; + wire [15:0] s2_input_payload_cmd_mask; + wire [3:0] s2_input_payload_index_0; + wire [3:0] s2_input_payload_index_1; + wire [3:0] s2_input_payload_index_2; + wire [3:0] s2_input_payload_index_3; + wire [3:0] s2_input_payload_index_4; + wire [3:0] s2_input_payload_index_5; + wire [3:0] s2_input_payload_index_6; + wire [3:0] s2_input_payload_index_7; + wire [3:0] s2_input_payload_index_8; + wire [3:0] s2_input_payload_index_9; + wire [3:0] s2_input_payload_index_10; + wire [3:0] s2_input_payload_index_11; + wire [3:0] s2_input_payload_index_12; + wire [3:0] s2_input_payload_index_13; + wire [3:0] s2_input_payload_index_14; + wire [3:0] s2_input_payload_index_15; + wire s2_input_payload_last; + wire [3:0] s2_input_payload_sel_0; + wire [3:0] s2_input_payload_sel_1; + wire [3:0] s2_input_payload_sel_2; + wire [3:0] s2_input_payload_sel_3; + wire [3:0] s2_input_payload_sel_4; + wire [3:0] s2_input_payload_sel_5; + wire [3:0] s2_input_payload_sel_6; + wire [3:0] s2_input_payload_sel_7; + wire [3:0] s2_input_payload_sel_8; + wire [3:0] s2_input_payload_sel_9; + wire [3:0] s2_input_payload_sel_10; + wire [3:0] s2_input_payload_sel_11; + wire [3:0] s2_input_payload_sel_12; + wire [3:0] s2_input_payload_sel_13; + wire [3:0] s2_input_payload_sel_14; + wire [3:0] s2_input_payload_sel_15; + wire [15:0] s2_input_payload_selValid; + reg s1_output_rValid; + reg [127:0] s1_output_rData_cmd_data; + reg [15:0] s1_output_rData_cmd_mask; + reg [3:0] s1_output_rData_index_0; + reg [3:0] s1_output_rData_index_1; + reg [3:0] s1_output_rData_index_2; + reg [3:0] s1_output_rData_index_3; + reg [3:0] s1_output_rData_index_4; + reg [3:0] s1_output_rData_index_5; + reg [3:0] s1_output_rData_index_6; + reg [3:0] s1_output_rData_index_7; + reg [3:0] s1_output_rData_index_8; + reg [3:0] s1_output_rData_index_9; + reg [3:0] s1_output_rData_index_10; + reg [3:0] s1_output_rData_index_11; + reg [3:0] s1_output_rData_index_12; + reg [3:0] s1_output_rData_index_13; + reg [3:0] s1_output_rData_index_14; + reg [3:0] s1_output_rData_index_15; + reg s1_output_rData_last; + reg [3:0] s1_output_rData_sel_0; + reg [3:0] s1_output_rData_sel_1; + reg [3:0] s1_output_rData_sel_2; + reg [3:0] s1_output_rData_sel_3; + reg [3:0] s1_output_rData_sel_4; + reg [3:0] s1_output_rData_sel_5; + reg [3:0] s1_output_rData_sel_6; + reg [3:0] s1_output_rData_sel_7; + reg [3:0] s1_output_rData_sel_8; + reg [3:0] s1_output_rData_sel_9; + reg [3:0] s1_output_rData_sel_10; + reg [3:0] s1_output_rData_sel_11; + reg [3:0] s1_output_rData_sel_12; + reg [3:0] s1_output_rData_sel_13; + reg [3:0] s1_output_rData_sel_14; + reg [3:0] s1_output_rData_sel_15; + reg [15:0] s1_output_rData_selValid; + wire when_Stream_l375_2; + wire when_DmaSg_l1464; + wire s2_input_fire; + wire [7:0] s2_inputDataBytes_0; + wire [7:0] s2_inputDataBytes_1; + wire [7:0] s2_inputDataBytes_2; + wire [7:0] s2_inputDataBytes_3; + wire [7:0] s2_inputDataBytes_4; + wire [7:0] s2_inputDataBytes_5; + wire [7:0] s2_inputDataBytes_6; + wire [7:0] s2_inputDataBytes_7; + wire [7:0] s2_inputDataBytes_8; + wire [7:0] s2_inputDataBytes_9; + wire [7:0] s2_inputDataBytes_10; + wire [7:0] s2_inputDataBytes_11; + wire [7:0] s2_inputDataBytes_12; + wire [7:0] s2_inputDataBytes_13; + wire [7:0] s2_inputDataBytes_14; + wire [7:0] s2_inputDataBytes_15; + reg s2_byteLogic_0_buffer_valid; + reg [7:0] s2_byteLogic_0_buffer_data; + wire s2_byteLogic_0_lastUsed; + wire s2_byteLogic_0_inputMask; + wire [7:0] s2_byteLogic_0_inputData; + wire s2_byteLogic_0_outputMask; + wire [7:0] s2_byteLogic_0_outputData; + wire when_DmaSg_l1493; + reg s2_byteLogic_1_buffer_valid; + reg [7:0] s2_byteLogic_1_buffer_data; + wire s2_byteLogic_1_lastUsed; + wire s2_byteLogic_1_inputMask; + wire [7:0] s2_byteLogic_1_inputData; + wire s2_byteLogic_1_outputMask; + wire [7:0] s2_byteLogic_1_outputData; + wire when_DmaSg_l1493_1; + reg s2_byteLogic_2_buffer_valid; + reg [7:0] s2_byteLogic_2_buffer_data; + wire s2_byteLogic_2_lastUsed; + wire s2_byteLogic_2_inputMask; + wire [7:0] s2_byteLogic_2_inputData; + wire s2_byteLogic_2_outputMask; + wire [7:0] s2_byteLogic_2_outputData; + wire when_DmaSg_l1493_2; + reg s2_byteLogic_3_buffer_valid; + reg [7:0] s2_byteLogic_3_buffer_data; + wire s2_byteLogic_3_lastUsed; + wire s2_byteLogic_3_inputMask; + wire [7:0] s2_byteLogic_3_inputData; + wire s2_byteLogic_3_outputMask; + wire [7:0] s2_byteLogic_3_outputData; + wire when_DmaSg_l1493_3; + reg s2_byteLogic_4_buffer_valid; + reg [7:0] s2_byteLogic_4_buffer_data; + wire s2_byteLogic_4_lastUsed; + wire s2_byteLogic_4_inputMask; + wire [7:0] s2_byteLogic_4_inputData; + wire s2_byteLogic_4_outputMask; + wire [7:0] s2_byteLogic_4_outputData; + wire when_DmaSg_l1493_4; + reg s2_byteLogic_5_buffer_valid; + reg [7:0] s2_byteLogic_5_buffer_data; + wire s2_byteLogic_5_lastUsed; + wire s2_byteLogic_5_inputMask; + wire [7:0] s2_byteLogic_5_inputData; + wire s2_byteLogic_5_outputMask; + wire [7:0] s2_byteLogic_5_outputData; + wire when_DmaSg_l1493_5; + reg s2_byteLogic_6_buffer_valid; + reg [7:0] s2_byteLogic_6_buffer_data; + wire s2_byteLogic_6_lastUsed; + wire s2_byteLogic_6_inputMask; + wire [7:0] s2_byteLogic_6_inputData; + wire s2_byteLogic_6_outputMask; + wire [7:0] s2_byteLogic_6_outputData; + wire when_DmaSg_l1493_6; + reg s2_byteLogic_7_buffer_valid; + reg [7:0] s2_byteLogic_7_buffer_data; + wire s2_byteLogic_7_lastUsed; + wire s2_byteLogic_7_inputMask; + wire [7:0] s2_byteLogic_7_inputData; + wire s2_byteLogic_7_outputMask; + wire [7:0] s2_byteLogic_7_outputData; + wire when_DmaSg_l1493_7; + reg s2_byteLogic_8_buffer_valid; + reg [7:0] s2_byteLogic_8_buffer_data; + wire s2_byteLogic_8_lastUsed; + wire s2_byteLogic_8_inputMask; + wire [7:0] s2_byteLogic_8_inputData; + wire s2_byteLogic_8_outputMask; + wire [7:0] s2_byteLogic_8_outputData; + wire when_DmaSg_l1493_8; + reg s2_byteLogic_9_buffer_valid; + reg [7:0] s2_byteLogic_9_buffer_data; + wire s2_byteLogic_9_lastUsed; + wire s2_byteLogic_9_inputMask; + wire [7:0] s2_byteLogic_9_inputData; + wire s2_byteLogic_9_outputMask; + wire [7:0] s2_byteLogic_9_outputData; + wire when_DmaSg_l1493_9; + reg s2_byteLogic_10_buffer_valid; + reg [7:0] s2_byteLogic_10_buffer_data; + wire s2_byteLogic_10_lastUsed; + wire s2_byteLogic_10_inputMask; + wire [7:0] s2_byteLogic_10_inputData; + wire s2_byteLogic_10_outputMask; + wire [7:0] s2_byteLogic_10_outputData; + wire when_DmaSg_l1493_10; + reg s2_byteLogic_11_buffer_valid; + reg [7:0] s2_byteLogic_11_buffer_data; + wire s2_byteLogic_11_lastUsed; + wire s2_byteLogic_11_inputMask; + wire [7:0] s2_byteLogic_11_inputData; + wire s2_byteLogic_11_outputMask; + wire [7:0] s2_byteLogic_11_outputData; + wire when_DmaSg_l1493_11; + reg s2_byteLogic_12_buffer_valid; + reg [7:0] s2_byteLogic_12_buffer_data; + wire s2_byteLogic_12_lastUsed; + wire s2_byteLogic_12_inputMask; + wire [7:0] s2_byteLogic_12_inputData; + wire s2_byteLogic_12_outputMask; + wire [7:0] s2_byteLogic_12_outputData; + wire when_DmaSg_l1493_12; + reg s2_byteLogic_13_buffer_valid; + reg [7:0] s2_byteLogic_13_buffer_data; + wire s2_byteLogic_13_lastUsed; + wire s2_byteLogic_13_inputMask; + wire [7:0] s2_byteLogic_13_inputData; + wire s2_byteLogic_13_outputMask; + wire [7:0] s2_byteLogic_13_outputData; + wire when_DmaSg_l1493_13; + reg s2_byteLogic_14_buffer_valid; + reg [7:0] s2_byteLogic_14_buffer_data; + wire s2_byteLogic_14_lastUsed; + wire s2_byteLogic_14_inputMask; + wire [7:0] s2_byteLogic_14_inputData; + wire s2_byteLogic_14_outputMask; + wire [7:0] s2_byteLogic_14_outputData; + wire when_DmaSg_l1493_14; + reg s2_byteLogic_15_buffer_valid; + reg [7:0] s2_byteLogic_15_buffer_data; + wire s2_byteLogic_15_lastUsed; + wire s2_byteLogic_15_inputMask; + wire [7:0] s2_byteLogic_15_inputData; + wire s2_byteLogic_15_outputMask; + wire [7:0] s2_byteLogic_15_outputData; + wire when_DmaSg_l1493_15; + wire _zz_io_output_usedUntil; + wire _zz_io_output_usedUntil_1; + wire _zz_io_output_usedUntil_2; + wire _zz_io_output_usedUntil_3; + + assign _zz_s0_countOnesLogic_3_13 = _zz_s0_countOnesLogic_3; + assign _zz_s0_countOnesLogic_3_12 = {2'd0, _zz_s0_countOnesLogic_3_13}; + assign _zz_s0_countOnesLogic_4_13 = {_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}; + assign _zz_s0_countOnesLogic_4_12 = {1'd0, _zz_s0_countOnesLogic_4_13}; + assign _zz_s0_countOnesLogic_6_9 = (_zz_s0_countOnesLogic_6_10 + _zz_s0_countOnesLogic_6_12); + assign _zz_s0_countOnesLogic_6_16 = _zz_s0_countOnesLogic_6; + assign _zz_s0_countOnesLogic_6_15 = {2'd0, _zz_s0_countOnesLogic_6_16}; + assign _zz_s0_countOnesLogic_7_9 = (_zz_s0_countOnesLogic_7_10 + _zz_s0_countOnesLogic_7_12); + assign _zz_s0_countOnesLogic_7_16 = {_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}; + assign _zz_s0_countOnesLogic_7_15 = {1'd0, _zz_s0_countOnesLogic_7_16}; + assign _zz_s0_countOnesLogic_8_9 = (_zz_s0_countOnesLogic_8_10 + _zz_s0_countOnesLogic_8_12); + assign _zz_s0_countOnesLogic_9_9 = (_zz_s0_countOnesLogic_9_10 + _zz_s0_countOnesLogic_9_12); + assign _zz_s0_countOnesLogic_9_14 = (_zz_s0_countOnesLogic_9_15 + _zz_s0_countOnesLogic_9_17); + assign _zz_s0_countOnesLogic_9_19 = _zz_s0_countOnesLogic_9; + assign _zz_s0_countOnesLogic_9_18 = {2'd0, _zz_s0_countOnesLogic_9_19}; + assign _zz_s0_countOnesLogic_10_9 = (_zz_s0_countOnesLogic_10_10 + _zz_s0_countOnesLogic_10_12); + assign _zz_s0_countOnesLogic_10_14 = (_zz_s0_countOnesLogic_10_15 + _zz_s0_countOnesLogic_10_17); + assign _zz_s0_countOnesLogic_10_19 = {_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}; + assign _zz_s0_countOnesLogic_10_18 = {1'd0, _zz_s0_countOnesLogic_10_19}; + assign _zz_s0_countOnesLogic_11_9 = (_zz_s0_countOnesLogic_11_10 + _zz_s0_countOnesLogic_11_12); + assign _zz_s0_countOnesLogic_11_14 = (_zz_s0_countOnesLogic_11_15 + _zz_s0_countOnesLogic_11_17); + assign _zz_s0_countOnesLogic_12_9 = (_zz_s0_countOnesLogic_12_10 + _zz_s0_countOnesLogic_12_15); + assign _zz_s0_countOnesLogic_12_10 = (_zz_s0_countOnesLogic_12_11 + _zz_s0_countOnesLogic_12_13); + assign _zz_s0_countOnesLogic_12_15 = (_zz_s0_countOnesLogic_12_16 + _zz_s0_countOnesLogic_12_18); + assign _zz_s0_countOnesLogic_12_22 = _zz_s0_countOnesLogic_12; + assign _zz_s0_countOnesLogic_12_21 = {2'd0, _zz_s0_countOnesLogic_12_22}; + assign _zz_s0_countOnesLogic_13_9 = (_zz_s0_countOnesLogic_13_10 + _zz_s0_countOnesLogic_13_15); + assign _zz_s0_countOnesLogic_13_10 = (_zz_s0_countOnesLogic_13_11 + _zz_s0_countOnesLogic_13_13); + assign _zz_s0_countOnesLogic_13_15 = (_zz_s0_countOnesLogic_13_16 + _zz_s0_countOnesLogic_13_18); + assign _zz_s0_countOnesLogic_13_22 = {_zz_s0_countOnesLogic_13,_zz_s0_countOnesLogic_12}; + assign _zz_s0_countOnesLogic_13_21 = {1'd0, _zz_s0_countOnesLogic_13_22}; + assign _zz_s0_countOnesLogic_14_9 = (_zz_s0_countOnesLogic_14_10 + _zz_s0_countOnesLogic_14_15); + assign _zz_s0_countOnesLogic_14_10 = (_zz_s0_countOnesLogic_14_11 + _zz_s0_countOnesLogic_14_13); + assign _zz_s0_countOnesLogic_14_15 = (_zz_s0_countOnesLogic_14_16 + _zz_s0_countOnesLogic_14_18); + assign _zz_s0_countOnesLogic_15_8 = (_zz_s0_countOnesLogic_15_9 + _zz_s0_countOnesLogic_15_14); + assign _zz_s0_countOnesLogic_15_9 = (_zz_s0_countOnesLogic_15_10 + _zz_s0_countOnesLogic_15_12); + assign _zz_s0_countOnesLogic_15_14 = (_zz_s0_countOnesLogic_15_15 + _zz_s0_countOnesLogic_15_17); + assign _zz_s0_countOnesLogic_15_19 = (_zz_s0_countOnesLogic_15_20 + _zz_s0_countOnesLogic_15_22); + assign _zz_s0_countOnesLogic_15_24 = s0_input_payload_mask[15]; + assign _zz_s0_countOnesLogic_15_23 = {2'd0, _zz_s0_countOnesLogic_15_24}; + assign _zz_s1_offsetNext = {1'd0, s1_offset}; + assign _zz_s1_byteCounter = {8'd0, s1_input_payload_countOnes_15}; + assign _zz_s1_inputIndexes_1 = {3'd0, s1_input_payload_countOnes_0}; + assign _zz_s1_inputIndexes_2 = {2'd0, s1_input_payload_countOnes_1}; + assign _zz_s1_inputIndexes_3 = {2'd0, s1_input_payload_countOnes_2}; + assign _zz_s1_inputIndexes_4 = {1'd0, s1_input_payload_countOnes_3}; + assign _zz_s1_inputIndexes_5 = {1'd0, s1_input_payload_countOnes_4}; + assign _zz_s1_inputIndexes_6 = {1'd0, s1_input_payload_countOnes_5}; + assign _zz_s1_inputIndexes_7 = {1'd0, s1_input_payload_countOnes_6}; + assign _zz_when_DmaSg_l1464 = {1'd0, io_burstLength}; + assign _zz_s0_countOnesLogic_0_2 = _zz_s0_countOnesLogic_0; + assign _zz_s0_countOnesLogic_1_2 = {_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}; + assign _zz_s0_countOnesLogic_2_2 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_3_10 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_4_10 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_5_10 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_5_12 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_6_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_6_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_7_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_7_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_8_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_8_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_8_15 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_9_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_9_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_9_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_10_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_10_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_10_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_11_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_11_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_11_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_11_18 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; + assign _zz_s0_countOnesLogic_12_12 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_12_14 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_12_17 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_12_19 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; + assign _zz_s0_countOnesLogic_13_12 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_13_14 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_13_17 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_13_19 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; + assign _zz_s0_countOnesLogic_14_12 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_14_14 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_14_17 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_14_19 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; + assign _zz_s0_countOnesLogic_14_21 = {_zz_s0_countOnesLogic_14,{_zz_s0_countOnesLogic_13,_zz_s0_countOnesLogic_12}}; + assign _zz_s0_countOnesLogic_15_11 = {_zz_s0_countOnesLogic_2,{_zz_s0_countOnesLogic_1,_zz_s0_countOnesLogic_0}}; + assign _zz_s0_countOnesLogic_15_13 = {_zz_s0_countOnesLogic_5,{_zz_s0_countOnesLogic_4,_zz_s0_countOnesLogic_3}}; + assign _zz_s0_countOnesLogic_15_16 = {_zz_s0_countOnesLogic_8,{_zz_s0_countOnesLogic_7,_zz_s0_countOnesLogic_6}}; + assign _zz_s0_countOnesLogic_15_18 = {_zz_s0_countOnesLogic_11,{_zz_s0_countOnesLogic_10,_zz_s0_countOnesLogic_9}}; + assign _zz_s0_countOnesLogic_15_21 = {_zz_s0_countOnesLogic_14,{_zz_s0_countOnesLogic_13,_zz_s0_countOnesLogic_12}}; + assign _zz_io_output_usedUntil_5 = {_zz_io_output_usedUntil_3,{_zz_io_output_usedUntil_2,{_zz_io_output_usedUntil_1,_zz_io_output_usedUntil}}}; + assign _zz_s1_outputPayload_selValid_240 = _zz_s1_outputPayload_selValid_6; + assign _zz_s1_outputPayload_selValid_241 = {_zz_s1_outputPayload_selValid_5,{_zz_s1_outputPayload_selValid_4,{_zz_s1_outputPayload_selValid_3,{_zz_s1_outputPayload_selValid_2,{_zz_s1_outputPayload_selValid_1,{_zz_s1_outputPayload_selValid,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0000))}}}}}}; + assign _zz_s1_outputPayload_selValid_242 = _zz_s1_outputPayload_selValid_21; + assign _zz_s1_outputPayload_selValid_243 = {_zz_s1_outputPayload_selValid_20,{_zz_s1_outputPayload_selValid_19,{_zz_s1_outputPayload_selValid_18,{_zz_s1_outputPayload_selValid_17,{_zz_s1_outputPayload_selValid_16,{_zz_s1_outputPayload_selValid_15,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0001))}}}}}}; + assign _zz_s1_outputPayload_selValid_244 = _zz_s1_outputPayload_selValid_36; + assign _zz_s1_outputPayload_selValid_245 = {_zz_s1_outputPayload_selValid_35,{_zz_s1_outputPayload_selValid_34,{_zz_s1_outputPayload_selValid_33,{_zz_s1_outputPayload_selValid_32,{_zz_s1_outputPayload_selValid_31,{_zz_s1_outputPayload_selValid_30,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0010))}}}}}}; + assign _zz_s1_outputPayload_selValid_246 = _zz_s1_outputPayload_selValid_51; + assign _zz_s1_outputPayload_selValid_247 = {_zz_s1_outputPayload_selValid_50,{_zz_s1_outputPayload_selValid_49,{_zz_s1_outputPayload_selValid_48,{_zz_s1_outputPayload_selValid_47,{_zz_s1_outputPayload_selValid_46,{_zz_s1_outputPayload_selValid_45,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0011))}}}}}}; + assign _zz_s1_outputPayload_selValid_248 = _zz_s1_outputPayload_selValid_66; + assign _zz_s1_outputPayload_selValid_249 = {_zz_s1_outputPayload_selValid_65,{_zz_s1_outputPayload_selValid_64,{_zz_s1_outputPayload_selValid_63,{_zz_s1_outputPayload_selValid_62,{_zz_s1_outputPayload_selValid_61,{_zz_s1_outputPayload_selValid_60,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0100))}}}}}}; + assign _zz_s1_outputPayload_selValid_250 = _zz_s1_outputPayload_selValid_81; + assign _zz_s1_outputPayload_selValid_251 = {_zz_s1_outputPayload_selValid_80,{_zz_s1_outputPayload_selValid_79,{_zz_s1_outputPayload_selValid_78,{_zz_s1_outputPayload_selValid_77,{_zz_s1_outputPayload_selValid_76,{_zz_s1_outputPayload_selValid_75,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0101))}}}}}}; + assign _zz_s1_outputPayload_selValid_252 = _zz_s1_outputPayload_selValid_96; + assign _zz_s1_outputPayload_selValid_253 = {_zz_s1_outputPayload_selValid_95,{_zz_s1_outputPayload_selValid_94,{_zz_s1_outputPayload_selValid_93,{_zz_s1_outputPayload_selValid_92,{_zz_s1_outputPayload_selValid_91,{_zz_s1_outputPayload_selValid_90,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0110))}}}}}}; + assign _zz_s1_outputPayload_selValid_254 = _zz_s1_outputPayload_selValid_111; + assign _zz_s1_outputPayload_selValid_255 = {_zz_s1_outputPayload_selValid_110,{_zz_s1_outputPayload_selValid_109,{_zz_s1_outputPayload_selValid_108,{_zz_s1_outputPayload_selValid_107,{_zz_s1_outputPayload_selValid_106,{_zz_s1_outputPayload_selValid_105,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b0111))}}}}}}; + assign _zz_s1_outputPayload_selValid_256 = _zz_s1_outputPayload_selValid_126; + assign _zz_s1_outputPayload_selValid_257 = {_zz_s1_outputPayload_selValid_125,{_zz_s1_outputPayload_selValid_124,{_zz_s1_outputPayload_selValid_123,{_zz_s1_outputPayload_selValid_122,{_zz_s1_outputPayload_selValid_121,{_zz_s1_outputPayload_selValid_120,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1000))}}}}}}; + assign _zz_s1_outputPayload_selValid_258 = _zz_s1_outputPayload_selValid_141; + assign _zz_s1_outputPayload_selValid_259 = {_zz_s1_outputPayload_selValid_140,{_zz_s1_outputPayload_selValid_139,{_zz_s1_outputPayload_selValid_138,{_zz_s1_outputPayload_selValid_137,{_zz_s1_outputPayload_selValid_136,{_zz_s1_outputPayload_selValid_135,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1001))}}}}}}; + assign _zz_s1_outputPayload_selValid_260 = _zz_s1_outputPayload_selValid_156; + assign _zz_s1_outputPayload_selValid_261 = {_zz_s1_outputPayload_selValid_155,{_zz_s1_outputPayload_selValid_154,{_zz_s1_outputPayload_selValid_153,{_zz_s1_outputPayload_selValid_152,{_zz_s1_outputPayload_selValid_151,{_zz_s1_outputPayload_selValid_150,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1010))}}}}}}; + assign _zz_s1_outputPayload_selValid_262 = _zz_s1_outputPayload_selValid_171; + assign _zz_s1_outputPayload_selValid_263 = {_zz_s1_outputPayload_selValid_170,{_zz_s1_outputPayload_selValid_169,{_zz_s1_outputPayload_selValid_168,{_zz_s1_outputPayload_selValid_167,{_zz_s1_outputPayload_selValid_166,{_zz_s1_outputPayload_selValid_165,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1011))}}}}}}; + assign _zz_s1_outputPayload_selValid_264 = _zz_s1_outputPayload_selValid_186; + assign _zz_s1_outputPayload_selValid_265 = {_zz_s1_outputPayload_selValid_185,{_zz_s1_outputPayload_selValid_184,{_zz_s1_outputPayload_selValid_183,{_zz_s1_outputPayload_selValid_182,{_zz_s1_outputPayload_selValid_181,{_zz_s1_outputPayload_selValid_180,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1100))}}}}}}; + assign _zz_s1_outputPayload_selValid_266 = _zz_s1_outputPayload_selValid_201; + assign _zz_s1_outputPayload_selValid_267 = {_zz_s1_outputPayload_selValid_200,{_zz_s1_outputPayload_selValid_199,{_zz_s1_outputPayload_selValid_198,{_zz_s1_outputPayload_selValid_197,{_zz_s1_outputPayload_selValid_196,{_zz_s1_outputPayload_selValid_195,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1101))}}}}}}; + assign _zz_s1_outputPayload_selValid_268 = _zz_s1_outputPayload_selValid_216; + assign _zz_s1_outputPayload_selValid_269 = {_zz_s1_outputPayload_selValid_215,{_zz_s1_outputPayload_selValid_214,{_zz_s1_outputPayload_selValid_213,{_zz_s1_outputPayload_selValid_212,{_zz_s1_outputPayload_selValid_211,{_zz_s1_outputPayload_selValid_210,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1110))}}}}}}; + assign _zz_s1_outputPayload_selValid_270 = _zz_s1_outputPayload_selValid_231; + assign _zz_s1_outputPayload_selValid_271 = {_zz_s1_outputPayload_selValid_230,{_zz_s1_outputPayload_selValid_229,{_zz_s1_outputPayload_selValid_228,{_zz_s1_outputPayload_selValid_227,{_zz_s1_outputPayload_selValid_226,{_zz_s1_outputPayload_selValid_225,(s1_input_payload_cmd_mask[0] && (s1_inputIndexes_0 == 4'b1111))}}}}}}; + always @(*) begin + case(_zz_s0_countOnesLogic_0_2) + 1'b0 : _zz_s0_countOnesLogic_0_1 = 1'b0; + default : _zz_s0_countOnesLogic_0_1 = 1'b1; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_1_2) + 2'b00 : _zz_s0_countOnesLogic_1_1 = 2'b00; + 2'b01 : _zz_s0_countOnesLogic_1_1 = 2'b01; + 2'b10 : _zz_s0_countOnesLogic_1_1 = 2'b01; + default : _zz_s0_countOnesLogic_1_1 = 2'b10; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_2_2) + 3'b000 : _zz_s0_countOnesLogic_2_1 = 2'b00; + 3'b001 : _zz_s0_countOnesLogic_2_1 = 2'b01; + 3'b010 : _zz_s0_countOnesLogic_2_1 = 2'b01; + 3'b011 : _zz_s0_countOnesLogic_2_1 = 2'b10; + 3'b100 : _zz_s0_countOnesLogic_2_1 = 2'b01; + 3'b101 : _zz_s0_countOnesLogic_2_1 = 2'b10; + 3'b110 : _zz_s0_countOnesLogic_2_1 = 2'b10; + default : _zz_s0_countOnesLogic_2_1 = 2'b11; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_3_10) + 3'b000 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_1; + 3'b001 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_2; + 3'b010 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_3; + 3'b011 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_4; + 3'b100 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_5; + 3'b101 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_6; + 3'b110 : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_7; + default : _zz_s0_countOnesLogic_3_9 = _zz_s0_countOnesLogic_3_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_3_12) + 3'b000 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_1; + 3'b001 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_2; + 3'b010 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_3; + 3'b011 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_4; + 3'b100 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_5; + 3'b101 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_6; + 3'b110 : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_7; + default : _zz_s0_countOnesLogic_3_11 = _zz_s0_countOnesLogic_3_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_4_10) + 3'b000 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_1; + 3'b001 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_2; + 3'b010 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_3; + 3'b011 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_4; + 3'b100 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_5; + 3'b101 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_6; + 3'b110 : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_7; + default : _zz_s0_countOnesLogic_4_9 = _zz_s0_countOnesLogic_4_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_4_12) + 3'b000 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_1; + 3'b001 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_2; + 3'b010 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_3; + 3'b011 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_4; + 3'b100 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_5; + 3'b101 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_6; + 3'b110 : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_7; + default : _zz_s0_countOnesLogic_4_11 = _zz_s0_countOnesLogic_4_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_5_10) + 3'b000 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_1; + 3'b001 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_2; + 3'b010 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_3; + 3'b011 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_4; + 3'b100 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_5; + 3'b101 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_6; + 3'b110 : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_7; + default : _zz_s0_countOnesLogic_5_9 = _zz_s0_countOnesLogic_5_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_5_12) + 3'b000 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_1; + 3'b001 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_2; + 3'b010 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_3; + 3'b011 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_4; + 3'b100 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_5; + 3'b101 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_6; + 3'b110 : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_7; + default : _zz_s0_countOnesLogic_5_11 = _zz_s0_countOnesLogic_5_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_6_11) + 3'b000 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_1; + 3'b001 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_2; + 3'b010 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_3; + 3'b011 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_4; + 3'b100 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_5; + 3'b101 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_6; + 3'b110 : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_7; + default : _zz_s0_countOnesLogic_6_10 = _zz_s0_countOnesLogic_6_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_6_13) + 3'b000 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_1; + 3'b001 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_2; + 3'b010 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_3; + 3'b011 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_4; + 3'b100 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_5; + 3'b101 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_6; + 3'b110 : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_7; + default : _zz_s0_countOnesLogic_6_12 = _zz_s0_countOnesLogic_6_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_6_15) + 3'b000 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_1; + 3'b001 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_2; + 3'b010 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_3; + 3'b011 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_4; + 3'b100 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_5; + 3'b101 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_6; + 3'b110 : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_7; + default : _zz_s0_countOnesLogic_6_14 = _zz_s0_countOnesLogic_6_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_7_11) + 3'b000 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_1; + 3'b001 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_2; + 3'b010 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_3; + 3'b011 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_4; + 3'b100 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_5; + 3'b101 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_6; + 3'b110 : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_7; + default : _zz_s0_countOnesLogic_7_10 = _zz_s0_countOnesLogic_7_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_7_13) + 3'b000 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_1; + 3'b001 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_2; + 3'b010 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_3; + 3'b011 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_4; + 3'b100 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_5; + 3'b101 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_6; + 3'b110 : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_7; + default : _zz_s0_countOnesLogic_7_12 = _zz_s0_countOnesLogic_7_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_7_15) + 3'b000 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_1; + 3'b001 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_2; + 3'b010 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_3; + 3'b011 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_4; + 3'b100 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_5; + 3'b101 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_6; + 3'b110 : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_7; + default : _zz_s0_countOnesLogic_7_14 = _zz_s0_countOnesLogic_7_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_8_11) + 3'b000 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_1; + 3'b001 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_2; + 3'b010 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_3; + 3'b011 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_4; + 3'b100 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_5; + 3'b101 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_6; + 3'b110 : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_7; + default : _zz_s0_countOnesLogic_8_10 = _zz_s0_countOnesLogic_8_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_8_13) + 3'b000 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_1; + 3'b001 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_2; + 3'b010 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_3; + 3'b011 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_4; + 3'b100 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_5; + 3'b101 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_6; + 3'b110 : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_7; + default : _zz_s0_countOnesLogic_8_12 = _zz_s0_countOnesLogic_8_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_8_15) + 3'b000 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_1; + 3'b001 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_2; + 3'b010 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_3; + 3'b011 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_4; + 3'b100 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_5; + 3'b101 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_6; + 3'b110 : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_7; + default : _zz_s0_countOnesLogic_8_14 = _zz_s0_countOnesLogic_8_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_9_11) + 3'b000 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_1; + 3'b001 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_2; + 3'b010 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_3; + 3'b011 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_4; + 3'b100 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_5; + 3'b101 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_6; + 3'b110 : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_7; + default : _zz_s0_countOnesLogic_9_10 = _zz_s0_countOnesLogic_9_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_9_13) + 3'b000 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_1; + 3'b001 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_2; + 3'b010 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_3; + 3'b011 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_4; + 3'b100 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_5; + 3'b101 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_6; + 3'b110 : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_7; + default : _zz_s0_countOnesLogic_9_12 = _zz_s0_countOnesLogic_9_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_9_16) + 3'b000 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_1; + 3'b001 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_2; + 3'b010 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_3; + 3'b011 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_4; + 3'b100 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_5; + 3'b101 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_6; + 3'b110 : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_7; + default : _zz_s0_countOnesLogic_9_15 = _zz_s0_countOnesLogic_9_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_9_18) + 3'b000 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_1; + 3'b001 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_2; + 3'b010 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_3; + 3'b011 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_4; + 3'b100 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_5; + 3'b101 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_6; + 3'b110 : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_7; + default : _zz_s0_countOnesLogic_9_17 = _zz_s0_countOnesLogic_9_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_10_11) + 3'b000 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_1; + 3'b001 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_2; + 3'b010 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_3; + 3'b011 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_4; + 3'b100 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_5; + 3'b101 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_6; + 3'b110 : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_7; + default : _zz_s0_countOnesLogic_10_10 = _zz_s0_countOnesLogic_10_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_10_13) + 3'b000 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_1; + 3'b001 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_2; + 3'b010 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_3; + 3'b011 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_4; + 3'b100 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_5; + 3'b101 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_6; + 3'b110 : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_7; + default : _zz_s0_countOnesLogic_10_12 = _zz_s0_countOnesLogic_10_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_10_16) + 3'b000 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_1; + 3'b001 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_2; + 3'b010 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_3; + 3'b011 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_4; + 3'b100 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_5; + 3'b101 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_6; + 3'b110 : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_7; + default : _zz_s0_countOnesLogic_10_15 = _zz_s0_countOnesLogic_10_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_10_18) + 3'b000 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_1; + 3'b001 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_2; + 3'b010 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_3; + 3'b011 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_4; + 3'b100 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_5; + 3'b101 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_6; + 3'b110 : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_7; + default : _zz_s0_countOnesLogic_10_17 = _zz_s0_countOnesLogic_10_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_11_11) + 3'b000 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_1; + 3'b001 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_2; + 3'b010 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_3; + 3'b011 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_4; + 3'b100 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_5; + 3'b101 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_6; + 3'b110 : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_7; + default : _zz_s0_countOnesLogic_11_10 = _zz_s0_countOnesLogic_11_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_11_13) + 3'b000 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_1; + 3'b001 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_2; + 3'b010 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_3; + 3'b011 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_4; + 3'b100 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_5; + 3'b101 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_6; + 3'b110 : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_7; + default : _zz_s0_countOnesLogic_11_12 = _zz_s0_countOnesLogic_11_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_11_16) + 3'b000 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_1; + 3'b001 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_2; + 3'b010 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_3; + 3'b011 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_4; + 3'b100 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_5; + 3'b101 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_6; + 3'b110 : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_7; + default : _zz_s0_countOnesLogic_11_15 = _zz_s0_countOnesLogic_11_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_11_18) + 3'b000 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_1; + 3'b001 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_2; + 3'b010 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_3; + 3'b011 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_4; + 3'b100 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_5; + 3'b101 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_6; + 3'b110 : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_7; + default : _zz_s0_countOnesLogic_11_17 = _zz_s0_countOnesLogic_11_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_12_12) + 3'b000 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_1; + 3'b001 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_2; + 3'b010 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_3; + 3'b011 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_4; + 3'b100 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_5; + 3'b101 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_6; + 3'b110 : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_7; + default : _zz_s0_countOnesLogic_12_11 = _zz_s0_countOnesLogic_12_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_12_14) + 3'b000 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_1; + 3'b001 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_2; + 3'b010 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_3; + 3'b011 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_4; + 3'b100 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_5; + 3'b101 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_6; + 3'b110 : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_7; + default : _zz_s0_countOnesLogic_12_13 = _zz_s0_countOnesLogic_12_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_12_17) + 3'b000 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_1; + 3'b001 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_2; + 3'b010 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_3; + 3'b011 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_4; + 3'b100 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_5; + 3'b101 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_6; + 3'b110 : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_7; + default : _zz_s0_countOnesLogic_12_16 = _zz_s0_countOnesLogic_12_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_12_19) + 3'b000 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_1; + 3'b001 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_2; + 3'b010 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_3; + 3'b011 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_4; + 3'b100 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_5; + 3'b101 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_6; + 3'b110 : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_7; + default : _zz_s0_countOnesLogic_12_18 = _zz_s0_countOnesLogic_12_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_12_21) + 3'b000 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_1; + 3'b001 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_2; + 3'b010 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_3; + 3'b011 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_4; + 3'b100 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_5; + 3'b101 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_6; + 3'b110 : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_7; + default : _zz_s0_countOnesLogic_12_20 = _zz_s0_countOnesLogic_12_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_13_12) + 3'b000 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_1; + 3'b001 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_2; + 3'b010 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_3; + 3'b011 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_4; + 3'b100 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_5; + 3'b101 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_6; + 3'b110 : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_7; + default : _zz_s0_countOnesLogic_13_11 = _zz_s0_countOnesLogic_13_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_13_14) + 3'b000 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_1; + 3'b001 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_2; + 3'b010 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_3; + 3'b011 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_4; + 3'b100 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_5; + 3'b101 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_6; + 3'b110 : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_7; + default : _zz_s0_countOnesLogic_13_13 = _zz_s0_countOnesLogic_13_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_13_17) + 3'b000 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_1; + 3'b001 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_2; + 3'b010 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_3; + 3'b011 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_4; + 3'b100 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_5; + 3'b101 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_6; + 3'b110 : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_7; + default : _zz_s0_countOnesLogic_13_16 = _zz_s0_countOnesLogic_13_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_13_19) + 3'b000 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_1; + 3'b001 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_2; + 3'b010 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_3; + 3'b011 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_4; + 3'b100 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_5; + 3'b101 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_6; + 3'b110 : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_7; + default : _zz_s0_countOnesLogic_13_18 = _zz_s0_countOnesLogic_13_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_13_21) + 3'b000 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_1; + 3'b001 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_2; + 3'b010 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_3; + 3'b011 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_4; + 3'b100 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_5; + 3'b101 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_6; + 3'b110 : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_7; + default : _zz_s0_countOnesLogic_13_20 = _zz_s0_countOnesLogic_13_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_14_12) + 3'b000 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_1; + 3'b001 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_2; + 3'b010 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_3; + 3'b011 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_4; + 3'b100 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_5; + 3'b101 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_6; + 3'b110 : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_7; + default : _zz_s0_countOnesLogic_14_11 = _zz_s0_countOnesLogic_14_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_14_14) + 3'b000 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_1; + 3'b001 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_2; + 3'b010 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_3; + 3'b011 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_4; + 3'b100 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_5; + 3'b101 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_6; + 3'b110 : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_7; + default : _zz_s0_countOnesLogic_14_13 = _zz_s0_countOnesLogic_14_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_14_17) + 3'b000 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_1; + 3'b001 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_2; + 3'b010 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_3; + 3'b011 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_4; + 3'b100 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_5; + 3'b101 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_6; + 3'b110 : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_7; + default : _zz_s0_countOnesLogic_14_16 = _zz_s0_countOnesLogic_14_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_14_19) + 3'b000 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_1; + 3'b001 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_2; + 3'b010 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_3; + 3'b011 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_4; + 3'b100 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_5; + 3'b101 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_6; + 3'b110 : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_7; + default : _zz_s0_countOnesLogic_14_18 = _zz_s0_countOnesLogic_14_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_14_21) + 3'b000 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_1; + 3'b001 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_2; + 3'b010 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_3; + 3'b011 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_4; + 3'b100 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_5; + 3'b101 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_6; + 3'b110 : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_7; + default : _zz_s0_countOnesLogic_14_20 = _zz_s0_countOnesLogic_14_8; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_11) + 3'b000 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_10 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_13) + 3'b000 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_12 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_16) + 3'b000 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_15 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_18) + 3'b000 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_17 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_21) + 3'b000 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_20 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(_zz_s0_countOnesLogic_15_23) + 3'b000 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15; + 3'b001 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_1; + 3'b010 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_2; + 3'b011 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_3; + 3'b100 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_4; + 3'b101 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_5; + 3'b110 : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_6; + default : _zz_s0_countOnesLogic_15_22 = _zz_s0_countOnesLogic_15_7; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_0) + 4'b0000 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_0_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_1) + 4'b0000 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_1_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_2) + 4'b0000 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_2_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_3) + 4'b0000 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_3_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_4) + 4'b0000 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_4_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_5) + 4'b0000 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_5_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_6) + 4'b0000 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_6_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_7) + 4'b0000 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_7_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_8) + 4'b0000 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_8_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_9) + 4'b0000 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_9_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_10) + 4'b0000 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_10_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_11) + 4'b0000 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_11_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_12) + 4'b0000 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_12_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_13) + 4'b0000 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_13_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_14) + 4'b0000 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_14_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(s2_input_payload_sel_15) + 4'b0000 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_0; + 4'b0001 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_1; + 4'b0010 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_2; + 4'b0011 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_3; + 4'b0100 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_4; + 4'b0101 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_5; + 4'b0110 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_6; + 4'b0111 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_7; + 4'b1000 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_8; + 4'b1001 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_9; + 4'b1010 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_10; + 4'b1011 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_11; + 4'b1100 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_12; + 4'b1101 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_13; + 4'b1110 : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_14; + default : _zz_s2_byteLogic_15_inputData = s2_inputDataBytes_15; + endcase + end + + always @(*) begin + case(_zz_io_output_usedUntil_5) + 4'b0000 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_0; + 4'b0001 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_1; + 4'b0010 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_2; + 4'b0011 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_3; + 4'b0100 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_4; + 4'b0101 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_5; + 4'b0110 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_6; + 4'b0111 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_7; + 4'b1000 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_8; + 4'b1001 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_9; + 4'b1010 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_10; + 4'b1011 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_11; + 4'b1100 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_12; + 4'b1101 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_13; + 4'b1110 : _zz_io_output_usedUntil_4 = s2_input_payload_sel_14; + default : _zz_io_output_usedUntil_4 = s2_input_payload_sel_15; + endcase + end + + always @(*) begin + io_input_ready = s0_input_ready; + if(when_Stream_l375) begin + io_input_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! s0_input_valid); + assign s0_input_valid = io_input_rValid; + assign s0_input_payload_data = io_input_rData_data; + assign s0_input_payload_mask = io_input_rData_mask; + assign _zz_s0_countOnesLogic_0 = s0_input_payload_mask[0]; + assign _zz_s0_countOnesLogic_1 = s0_input_payload_mask[1]; + assign _zz_s0_countOnesLogic_2 = s0_input_payload_mask[2]; + assign _zz_s0_countOnesLogic_3 = s0_input_payload_mask[3]; + assign _zz_s0_countOnesLogic_4 = s0_input_payload_mask[4]; + assign _zz_s0_countOnesLogic_5 = s0_input_payload_mask[5]; + assign _zz_s0_countOnesLogic_6 = s0_input_payload_mask[6]; + assign _zz_s0_countOnesLogic_7 = s0_input_payload_mask[7]; + assign _zz_s0_countOnesLogic_8 = s0_input_payload_mask[8]; + assign _zz_s0_countOnesLogic_9 = s0_input_payload_mask[9]; + assign _zz_s0_countOnesLogic_10 = s0_input_payload_mask[10]; + assign _zz_s0_countOnesLogic_11 = s0_input_payload_mask[11]; + assign _zz_s0_countOnesLogic_12 = s0_input_payload_mask[12]; + assign _zz_s0_countOnesLogic_13 = s0_input_payload_mask[13]; + assign _zz_s0_countOnesLogic_14 = s0_input_payload_mask[14]; + assign s0_countOnesLogic_0 = _zz_s0_countOnesLogic_0_1; + assign s0_countOnesLogic_1 = _zz_s0_countOnesLogic_1_1; + assign s0_countOnesLogic_2 = _zz_s0_countOnesLogic_2_1; + assign _zz_s0_countOnesLogic_3_1 = 3'b000; + assign _zz_s0_countOnesLogic_3_2 = 3'b001; + assign _zz_s0_countOnesLogic_3_3 = 3'b001; + assign _zz_s0_countOnesLogic_3_4 = 3'b010; + assign _zz_s0_countOnesLogic_3_5 = 3'b001; + assign _zz_s0_countOnesLogic_3_6 = 3'b010; + assign _zz_s0_countOnesLogic_3_7 = 3'b010; + assign _zz_s0_countOnesLogic_3_8 = 3'b011; + assign s0_countOnesLogic_3 = (_zz_s0_countOnesLogic_3_9 + _zz_s0_countOnesLogic_3_11); + assign _zz_s0_countOnesLogic_4_1 = 3'b000; + assign _zz_s0_countOnesLogic_4_2 = 3'b001; + assign _zz_s0_countOnesLogic_4_3 = 3'b001; + assign _zz_s0_countOnesLogic_4_4 = 3'b010; + assign _zz_s0_countOnesLogic_4_5 = 3'b001; + assign _zz_s0_countOnesLogic_4_6 = 3'b010; + assign _zz_s0_countOnesLogic_4_7 = 3'b010; + assign _zz_s0_countOnesLogic_4_8 = 3'b011; + assign s0_countOnesLogic_4 = (_zz_s0_countOnesLogic_4_9 + _zz_s0_countOnesLogic_4_11); + assign _zz_s0_countOnesLogic_5_1 = 3'b000; + assign _zz_s0_countOnesLogic_5_2 = 3'b001; + assign _zz_s0_countOnesLogic_5_3 = 3'b001; + assign _zz_s0_countOnesLogic_5_4 = 3'b010; + assign _zz_s0_countOnesLogic_5_5 = 3'b001; + assign _zz_s0_countOnesLogic_5_6 = 3'b010; + assign _zz_s0_countOnesLogic_5_7 = 3'b010; + assign _zz_s0_countOnesLogic_5_8 = 3'b011; + assign s0_countOnesLogic_5 = (_zz_s0_countOnesLogic_5_9 + _zz_s0_countOnesLogic_5_11); + assign _zz_s0_countOnesLogic_6_1 = 3'b000; + assign _zz_s0_countOnesLogic_6_2 = 3'b001; + assign _zz_s0_countOnesLogic_6_3 = 3'b001; + assign _zz_s0_countOnesLogic_6_4 = 3'b010; + assign _zz_s0_countOnesLogic_6_5 = 3'b001; + assign _zz_s0_countOnesLogic_6_6 = 3'b010; + assign _zz_s0_countOnesLogic_6_7 = 3'b010; + assign _zz_s0_countOnesLogic_6_8 = 3'b011; + assign s0_countOnesLogic_6 = (_zz_s0_countOnesLogic_6_9 + _zz_s0_countOnesLogic_6_14); + assign _zz_s0_countOnesLogic_7_1 = 4'b0000; + assign _zz_s0_countOnesLogic_7_2 = 4'b0001; + assign _zz_s0_countOnesLogic_7_3 = 4'b0001; + assign _zz_s0_countOnesLogic_7_4 = 4'b0010; + assign _zz_s0_countOnesLogic_7_5 = 4'b0001; + assign _zz_s0_countOnesLogic_7_6 = 4'b0010; + assign _zz_s0_countOnesLogic_7_7 = 4'b0010; + assign _zz_s0_countOnesLogic_7_8 = 4'b0011; + assign s0_countOnesLogic_7 = (_zz_s0_countOnesLogic_7_9 + _zz_s0_countOnesLogic_7_14); + assign _zz_s0_countOnesLogic_8_1 = 4'b0000; + assign _zz_s0_countOnesLogic_8_2 = 4'b0001; + assign _zz_s0_countOnesLogic_8_3 = 4'b0001; + assign _zz_s0_countOnesLogic_8_4 = 4'b0010; + assign _zz_s0_countOnesLogic_8_5 = 4'b0001; + assign _zz_s0_countOnesLogic_8_6 = 4'b0010; + assign _zz_s0_countOnesLogic_8_7 = 4'b0010; + assign _zz_s0_countOnesLogic_8_8 = 4'b0011; + assign s0_countOnesLogic_8 = (_zz_s0_countOnesLogic_8_9 + _zz_s0_countOnesLogic_8_14); + assign _zz_s0_countOnesLogic_9_1 = 4'b0000; + assign _zz_s0_countOnesLogic_9_2 = 4'b0001; + assign _zz_s0_countOnesLogic_9_3 = 4'b0001; + assign _zz_s0_countOnesLogic_9_4 = 4'b0010; + assign _zz_s0_countOnesLogic_9_5 = 4'b0001; + assign _zz_s0_countOnesLogic_9_6 = 4'b0010; + assign _zz_s0_countOnesLogic_9_7 = 4'b0010; + assign _zz_s0_countOnesLogic_9_8 = 4'b0011; + assign s0_countOnesLogic_9 = (_zz_s0_countOnesLogic_9_9 + _zz_s0_countOnesLogic_9_14); + assign _zz_s0_countOnesLogic_10_1 = 4'b0000; + assign _zz_s0_countOnesLogic_10_2 = 4'b0001; + assign _zz_s0_countOnesLogic_10_3 = 4'b0001; + assign _zz_s0_countOnesLogic_10_4 = 4'b0010; + assign _zz_s0_countOnesLogic_10_5 = 4'b0001; + assign _zz_s0_countOnesLogic_10_6 = 4'b0010; + assign _zz_s0_countOnesLogic_10_7 = 4'b0010; + assign _zz_s0_countOnesLogic_10_8 = 4'b0011; + assign s0_countOnesLogic_10 = (_zz_s0_countOnesLogic_10_9 + _zz_s0_countOnesLogic_10_14); + assign _zz_s0_countOnesLogic_11_1 = 4'b0000; + assign _zz_s0_countOnesLogic_11_2 = 4'b0001; + assign _zz_s0_countOnesLogic_11_3 = 4'b0001; + assign _zz_s0_countOnesLogic_11_4 = 4'b0010; + assign _zz_s0_countOnesLogic_11_5 = 4'b0001; + assign _zz_s0_countOnesLogic_11_6 = 4'b0010; + assign _zz_s0_countOnesLogic_11_7 = 4'b0010; + assign _zz_s0_countOnesLogic_11_8 = 4'b0011; + assign s0_countOnesLogic_11 = (_zz_s0_countOnesLogic_11_9 + _zz_s0_countOnesLogic_11_14); + assign _zz_s0_countOnesLogic_12_1 = 4'b0000; + assign _zz_s0_countOnesLogic_12_2 = 4'b0001; + assign _zz_s0_countOnesLogic_12_3 = 4'b0001; + assign _zz_s0_countOnesLogic_12_4 = 4'b0010; + assign _zz_s0_countOnesLogic_12_5 = 4'b0001; + assign _zz_s0_countOnesLogic_12_6 = 4'b0010; + assign _zz_s0_countOnesLogic_12_7 = 4'b0010; + assign _zz_s0_countOnesLogic_12_8 = 4'b0011; + assign s0_countOnesLogic_12 = (_zz_s0_countOnesLogic_12_9 + _zz_s0_countOnesLogic_12_20); + assign _zz_s0_countOnesLogic_13_1 = 4'b0000; + assign _zz_s0_countOnesLogic_13_2 = 4'b0001; + assign _zz_s0_countOnesLogic_13_3 = 4'b0001; + assign _zz_s0_countOnesLogic_13_4 = 4'b0010; + assign _zz_s0_countOnesLogic_13_5 = 4'b0001; + assign _zz_s0_countOnesLogic_13_6 = 4'b0010; + assign _zz_s0_countOnesLogic_13_7 = 4'b0010; + assign _zz_s0_countOnesLogic_13_8 = 4'b0011; + assign s0_countOnesLogic_13 = (_zz_s0_countOnesLogic_13_9 + _zz_s0_countOnesLogic_13_20); + assign _zz_s0_countOnesLogic_14_1 = 4'b0000; + assign _zz_s0_countOnesLogic_14_2 = 4'b0001; + assign _zz_s0_countOnesLogic_14_3 = 4'b0001; + assign _zz_s0_countOnesLogic_14_4 = 4'b0010; + assign _zz_s0_countOnesLogic_14_5 = 4'b0001; + assign _zz_s0_countOnesLogic_14_6 = 4'b0010; + assign _zz_s0_countOnesLogic_14_7 = 4'b0010; + assign _zz_s0_countOnesLogic_14_8 = 4'b0011; + assign s0_countOnesLogic_14 = (_zz_s0_countOnesLogic_14_9 + _zz_s0_countOnesLogic_14_20); + assign _zz_s0_countOnesLogic_15 = 5'h0; + assign _zz_s0_countOnesLogic_15_1 = 5'h01; + assign _zz_s0_countOnesLogic_15_2 = 5'h01; + assign _zz_s0_countOnesLogic_15_3 = 5'h02; + assign _zz_s0_countOnesLogic_15_4 = 5'h01; + assign _zz_s0_countOnesLogic_15_5 = 5'h02; + assign _zz_s0_countOnesLogic_15_6 = 5'h02; + assign _zz_s0_countOnesLogic_15_7 = 5'h03; + assign s0_countOnesLogic_15 = (_zz_s0_countOnesLogic_15_8 + _zz_s0_countOnesLogic_15_19); + assign s0_outputPayload_cmd_data = s0_input_payload_data; + assign s0_outputPayload_cmd_mask = s0_input_payload_mask; + assign s0_outputPayload_countOnes_0 = s0_countOnesLogic_0; + assign s0_outputPayload_countOnes_1 = s0_countOnesLogic_1; + assign s0_outputPayload_countOnes_2 = s0_countOnesLogic_2; + assign s0_outputPayload_countOnes_3 = s0_countOnesLogic_3; + assign s0_outputPayload_countOnes_4 = s0_countOnesLogic_4; + assign s0_outputPayload_countOnes_5 = s0_countOnesLogic_5; + assign s0_outputPayload_countOnes_6 = s0_countOnesLogic_6; + assign s0_outputPayload_countOnes_7 = s0_countOnesLogic_7; + assign s0_outputPayload_countOnes_8 = s0_countOnesLogic_8; + assign s0_outputPayload_countOnes_9 = s0_countOnesLogic_9; + assign s0_outputPayload_countOnes_10 = s0_countOnesLogic_10; + assign s0_outputPayload_countOnes_11 = s0_countOnesLogic_11; + assign s0_outputPayload_countOnes_12 = s0_countOnesLogic_12; + assign s0_outputPayload_countOnes_13 = s0_countOnesLogic_13; + assign s0_outputPayload_countOnes_14 = s0_countOnesLogic_14; + assign s0_outputPayload_countOnes_15 = s0_countOnesLogic_15; + assign s0_output_valid = s0_input_valid; + assign s0_input_ready = s0_output_ready; + assign s0_output_payload_cmd_data = s0_outputPayload_cmd_data; + assign s0_output_payload_cmd_mask = s0_outputPayload_cmd_mask; + assign s0_output_payload_countOnes_0 = s0_outputPayload_countOnes_0; + assign s0_output_payload_countOnes_1 = s0_outputPayload_countOnes_1; + assign s0_output_payload_countOnes_2 = s0_outputPayload_countOnes_2; + assign s0_output_payload_countOnes_3 = s0_outputPayload_countOnes_3; + assign s0_output_payload_countOnes_4 = s0_outputPayload_countOnes_4; + assign s0_output_payload_countOnes_5 = s0_outputPayload_countOnes_5; + assign s0_output_payload_countOnes_6 = s0_outputPayload_countOnes_6; + assign s0_output_payload_countOnes_7 = s0_outputPayload_countOnes_7; + assign s0_output_payload_countOnes_8 = s0_outputPayload_countOnes_8; + assign s0_output_payload_countOnes_9 = s0_outputPayload_countOnes_9; + assign s0_output_payload_countOnes_10 = s0_outputPayload_countOnes_10; + assign s0_output_payload_countOnes_11 = s0_outputPayload_countOnes_11; + assign s0_output_payload_countOnes_12 = s0_outputPayload_countOnes_12; + assign s0_output_payload_countOnes_13 = s0_outputPayload_countOnes_13; + assign s0_output_payload_countOnes_14 = s0_outputPayload_countOnes_14; + assign s0_output_payload_countOnes_15 = s0_outputPayload_countOnes_15; + always @(*) begin + s0_output_ready = s1_input_ready; + if(when_Stream_l375_1) begin + s0_output_ready = 1'b1; + end + end + + assign when_Stream_l375_1 = (! s1_input_valid); + assign s1_input_valid = s0_output_rValid; + assign s1_input_payload_cmd_data = s0_output_rData_cmd_data; + assign s1_input_payload_cmd_mask = s0_output_rData_cmd_mask; + assign s1_input_payload_countOnes_0 = s0_output_rData_countOnes_0; + assign s1_input_payload_countOnes_1 = s0_output_rData_countOnes_1; + assign s1_input_payload_countOnes_2 = s0_output_rData_countOnes_2; + assign s1_input_payload_countOnes_3 = s0_output_rData_countOnes_3; + assign s1_input_payload_countOnes_4 = s0_output_rData_countOnes_4; + assign s1_input_payload_countOnes_5 = s0_output_rData_countOnes_5; + assign s1_input_payload_countOnes_6 = s0_output_rData_countOnes_6; + assign s1_input_payload_countOnes_7 = s0_output_rData_countOnes_7; + assign s1_input_payload_countOnes_8 = s0_output_rData_countOnes_8; + assign s1_input_payload_countOnes_9 = s0_output_rData_countOnes_9; + assign s1_input_payload_countOnes_10 = s0_output_rData_countOnes_10; + assign s1_input_payload_countOnes_11 = s0_output_rData_countOnes_11; + assign s1_input_payload_countOnes_12 = s0_output_rData_countOnes_12; + assign s1_input_payload_countOnes_13 = s0_output_rData_countOnes_13; + assign s1_input_payload_countOnes_14 = s0_output_rData_countOnes_14; + assign s1_input_payload_countOnes_15 = s0_output_rData_countOnes_15; + assign s1_offsetNext = (_zz_s1_offsetNext + s1_input_payload_countOnes_15); + assign s1_input_fire = (s1_input_valid && s1_input_ready); + assign s1_inputIndexes_0 = (4'b0000 + s1_offset); + assign s1_inputIndexes_1 = (_zz_s1_inputIndexes_1 + s1_offset); + assign s1_inputIndexes_2 = (_zz_s1_inputIndexes_2 + s1_offset); + assign s1_inputIndexes_3 = (_zz_s1_inputIndexes_3 + s1_offset); + assign s1_inputIndexes_4 = (_zz_s1_inputIndexes_4 + s1_offset); + assign s1_inputIndexes_5 = (_zz_s1_inputIndexes_5 + s1_offset); + assign s1_inputIndexes_6 = (_zz_s1_inputIndexes_6 + s1_offset); + assign s1_inputIndexes_7 = (_zz_s1_inputIndexes_7 + s1_offset); + assign s1_inputIndexes_8 = (s1_input_payload_countOnes_7 + s1_offset); + assign s1_inputIndexes_9 = (s1_input_payload_countOnes_8 + s1_offset); + assign s1_inputIndexes_10 = (s1_input_payload_countOnes_9 + s1_offset); + assign s1_inputIndexes_11 = (s1_input_payload_countOnes_10 + s1_offset); + assign s1_inputIndexes_12 = (s1_input_payload_countOnes_11 + s1_offset); + assign s1_inputIndexes_13 = (s1_input_payload_countOnes_12 + s1_offset); + assign s1_inputIndexes_14 = (s1_input_payload_countOnes_13 + s1_offset); + assign s1_inputIndexes_15 = (s1_input_payload_countOnes_14 + s1_offset); + assign s1_outputPayload_cmd_data = s1_input_payload_cmd_data; + assign s1_outputPayload_cmd_mask = s1_input_payload_cmd_mask; + assign s1_outputPayload_index_0 = s1_inputIndexes_0; + assign s1_outputPayload_index_1 = s1_inputIndexes_1; + assign s1_outputPayload_index_2 = s1_inputIndexes_2; + assign s1_outputPayload_index_3 = s1_inputIndexes_3; + assign s1_outputPayload_index_4 = s1_inputIndexes_4; + assign s1_outputPayload_index_5 = s1_inputIndexes_5; + assign s1_outputPayload_index_6 = s1_inputIndexes_6; + assign s1_outputPayload_index_7 = s1_inputIndexes_7; + assign s1_outputPayload_index_8 = s1_inputIndexes_8; + assign s1_outputPayload_index_9 = s1_inputIndexes_9; + assign s1_outputPayload_index_10 = s1_inputIndexes_10; + assign s1_outputPayload_index_11 = s1_inputIndexes_11; + assign s1_outputPayload_index_12 = s1_inputIndexes_12; + assign s1_outputPayload_index_13 = s1_inputIndexes_13; + assign s1_outputPayload_index_14 = s1_inputIndexes_14; + assign s1_outputPayload_index_15 = s1_inputIndexes_15; + assign s1_outputPayload_last = s1_offsetNext[4]; + assign _zz_s1_outputPayload_selValid = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_1 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_2 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_3 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_4 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_5 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_6 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_7 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_8 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_9 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_10 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_11 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_12 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_13 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0000)); + assign _zz_s1_outputPayload_selValid_14 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0000)); + assign _zz_s1_outputPayload_sel_0 = (((((((_zz_s1_outputPayload_selValid || _zz_s1_outputPayload_selValid_2) || _zz_s1_outputPayload_selValid_4) || _zz_s1_outputPayload_selValid_6) || _zz_s1_outputPayload_selValid_8) || _zz_s1_outputPayload_selValid_10) || _zz_s1_outputPayload_selValid_12) || _zz_s1_outputPayload_selValid_14); + assign _zz_s1_outputPayload_sel_0_1 = (((((((_zz_s1_outputPayload_selValid_1 || _zz_s1_outputPayload_selValid_2) || _zz_s1_outputPayload_selValid_5) || _zz_s1_outputPayload_selValid_6) || _zz_s1_outputPayload_selValid_9) || _zz_s1_outputPayload_selValid_10) || _zz_s1_outputPayload_selValid_13) || _zz_s1_outputPayload_selValid_14); + assign _zz_s1_outputPayload_sel_0_2 = (((((((_zz_s1_outputPayload_selValid_3 || _zz_s1_outputPayload_selValid_4) || _zz_s1_outputPayload_selValid_5) || _zz_s1_outputPayload_selValid_6) || _zz_s1_outputPayload_selValid_11) || _zz_s1_outputPayload_selValid_12) || _zz_s1_outputPayload_selValid_13) || _zz_s1_outputPayload_selValid_14); + assign _zz_s1_outputPayload_sel_0_3 = (((((((_zz_s1_outputPayload_selValid_7 || _zz_s1_outputPayload_selValid_8) || _zz_s1_outputPayload_selValid_9) || _zz_s1_outputPayload_selValid_10) || _zz_s1_outputPayload_selValid_11) || _zz_s1_outputPayload_selValid_12) || _zz_s1_outputPayload_selValid_13) || _zz_s1_outputPayload_selValid_14); + assign s1_outputPayload_sel_0 = {_zz_s1_outputPayload_sel_0_3,{_zz_s1_outputPayload_sel_0_2,{_zz_s1_outputPayload_sel_0_1,_zz_s1_outputPayload_sel_0}}}; + always @(*) begin + s1_outputPayload_selValid[0] = ((|{_zz_s1_outputPayload_selValid_14,{_zz_s1_outputPayload_selValid_13,{_zz_s1_outputPayload_selValid_12,{_zz_s1_outputPayload_selValid_11,{_zz_s1_outputPayload_selValid_10,{_zz_s1_outputPayload_selValid_9,{_zz_s1_outputPayload_selValid_8,{_zz_s1_outputPayload_selValid_7,{_zz_s1_outputPayload_selValid_240,_zz_s1_outputPayload_selValid_241}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_0]); + s1_outputPayload_selValid[1] = ((|{_zz_s1_outputPayload_selValid_29,{_zz_s1_outputPayload_selValid_28,{_zz_s1_outputPayload_selValid_27,{_zz_s1_outputPayload_selValid_26,{_zz_s1_outputPayload_selValid_25,{_zz_s1_outputPayload_selValid_24,{_zz_s1_outputPayload_selValid_23,{_zz_s1_outputPayload_selValid_22,{_zz_s1_outputPayload_selValid_242,_zz_s1_outputPayload_selValid_243}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_1]); + s1_outputPayload_selValid[2] = ((|{_zz_s1_outputPayload_selValid_44,{_zz_s1_outputPayload_selValid_43,{_zz_s1_outputPayload_selValid_42,{_zz_s1_outputPayload_selValid_41,{_zz_s1_outputPayload_selValid_40,{_zz_s1_outputPayload_selValid_39,{_zz_s1_outputPayload_selValid_38,{_zz_s1_outputPayload_selValid_37,{_zz_s1_outputPayload_selValid_244,_zz_s1_outputPayload_selValid_245}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_2]); + s1_outputPayload_selValid[3] = ((|{_zz_s1_outputPayload_selValid_59,{_zz_s1_outputPayload_selValid_58,{_zz_s1_outputPayload_selValid_57,{_zz_s1_outputPayload_selValid_56,{_zz_s1_outputPayload_selValid_55,{_zz_s1_outputPayload_selValid_54,{_zz_s1_outputPayload_selValid_53,{_zz_s1_outputPayload_selValid_52,{_zz_s1_outputPayload_selValid_246,_zz_s1_outputPayload_selValid_247}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_3]); + s1_outputPayload_selValid[4] = ((|{_zz_s1_outputPayload_selValid_74,{_zz_s1_outputPayload_selValid_73,{_zz_s1_outputPayload_selValid_72,{_zz_s1_outputPayload_selValid_71,{_zz_s1_outputPayload_selValid_70,{_zz_s1_outputPayload_selValid_69,{_zz_s1_outputPayload_selValid_68,{_zz_s1_outputPayload_selValid_67,{_zz_s1_outputPayload_selValid_248,_zz_s1_outputPayload_selValid_249}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_4]); + s1_outputPayload_selValid[5] = ((|{_zz_s1_outputPayload_selValid_89,{_zz_s1_outputPayload_selValid_88,{_zz_s1_outputPayload_selValid_87,{_zz_s1_outputPayload_selValid_86,{_zz_s1_outputPayload_selValid_85,{_zz_s1_outputPayload_selValid_84,{_zz_s1_outputPayload_selValid_83,{_zz_s1_outputPayload_selValid_82,{_zz_s1_outputPayload_selValid_250,_zz_s1_outputPayload_selValid_251}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_5]); + s1_outputPayload_selValid[6] = ((|{_zz_s1_outputPayload_selValid_104,{_zz_s1_outputPayload_selValid_103,{_zz_s1_outputPayload_selValid_102,{_zz_s1_outputPayload_selValid_101,{_zz_s1_outputPayload_selValid_100,{_zz_s1_outputPayload_selValid_99,{_zz_s1_outputPayload_selValid_98,{_zz_s1_outputPayload_selValid_97,{_zz_s1_outputPayload_selValid_252,_zz_s1_outputPayload_selValid_253}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_6]); + s1_outputPayload_selValid[7] = ((|{_zz_s1_outputPayload_selValid_119,{_zz_s1_outputPayload_selValid_118,{_zz_s1_outputPayload_selValid_117,{_zz_s1_outputPayload_selValid_116,{_zz_s1_outputPayload_selValid_115,{_zz_s1_outputPayload_selValid_114,{_zz_s1_outputPayload_selValid_113,{_zz_s1_outputPayload_selValid_112,{_zz_s1_outputPayload_selValid_254,_zz_s1_outputPayload_selValid_255}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_7]); + s1_outputPayload_selValid[8] = ((|{_zz_s1_outputPayload_selValid_134,{_zz_s1_outputPayload_selValid_133,{_zz_s1_outputPayload_selValid_132,{_zz_s1_outputPayload_selValid_131,{_zz_s1_outputPayload_selValid_130,{_zz_s1_outputPayload_selValid_129,{_zz_s1_outputPayload_selValid_128,{_zz_s1_outputPayload_selValid_127,{_zz_s1_outputPayload_selValid_256,_zz_s1_outputPayload_selValid_257}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_8]); + s1_outputPayload_selValid[9] = ((|{_zz_s1_outputPayload_selValid_149,{_zz_s1_outputPayload_selValid_148,{_zz_s1_outputPayload_selValid_147,{_zz_s1_outputPayload_selValid_146,{_zz_s1_outputPayload_selValid_145,{_zz_s1_outputPayload_selValid_144,{_zz_s1_outputPayload_selValid_143,{_zz_s1_outputPayload_selValid_142,{_zz_s1_outputPayload_selValid_258,_zz_s1_outputPayload_selValid_259}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_9]); + s1_outputPayload_selValid[10] = ((|{_zz_s1_outputPayload_selValid_164,{_zz_s1_outputPayload_selValid_163,{_zz_s1_outputPayload_selValid_162,{_zz_s1_outputPayload_selValid_161,{_zz_s1_outputPayload_selValid_160,{_zz_s1_outputPayload_selValid_159,{_zz_s1_outputPayload_selValid_158,{_zz_s1_outputPayload_selValid_157,{_zz_s1_outputPayload_selValid_260,_zz_s1_outputPayload_selValid_261}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_10]); + s1_outputPayload_selValid[11] = ((|{_zz_s1_outputPayload_selValid_179,{_zz_s1_outputPayload_selValid_178,{_zz_s1_outputPayload_selValid_177,{_zz_s1_outputPayload_selValid_176,{_zz_s1_outputPayload_selValid_175,{_zz_s1_outputPayload_selValid_174,{_zz_s1_outputPayload_selValid_173,{_zz_s1_outputPayload_selValid_172,{_zz_s1_outputPayload_selValid_262,_zz_s1_outputPayload_selValid_263}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_11]); + s1_outputPayload_selValid[12] = ((|{_zz_s1_outputPayload_selValid_194,{_zz_s1_outputPayload_selValid_193,{_zz_s1_outputPayload_selValid_192,{_zz_s1_outputPayload_selValid_191,{_zz_s1_outputPayload_selValid_190,{_zz_s1_outputPayload_selValid_189,{_zz_s1_outputPayload_selValid_188,{_zz_s1_outputPayload_selValid_187,{_zz_s1_outputPayload_selValid_264,_zz_s1_outputPayload_selValid_265}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_12]); + s1_outputPayload_selValid[13] = ((|{_zz_s1_outputPayload_selValid_209,{_zz_s1_outputPayload_selValid_208,{_zz_s1_outputPayload_selValid_207,{_zz_s1_outputPayload_selValid_206,{_zz_s1_outputPayload_selValid_205,{_zz_s1_outputPayload_selValid_204,{_zz_s1_outputPayload_selValid_203,{_zz_s1_outputPayload_selValid_202,{_zz_s1_outputPayload_selValid_266,_zz_s1_outputPayload_selValid_267}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_13]); + s1_outputPayload_selValid[14] = ((|{_zz_s1_outputPayload_selValid_224,{_zz_s1_outputPayload_selValid_223,{_zz_s1_outputPayload_selValid_222,{_zz_s1_outputPayload_selValid_221,{_zz_s1_outputPayload_selValid_220,{_zz_s1_outputPayload_selValid_219,{_zz_s1_outputPayload_selValid_218,{_zz_s1_outputPayload_selValid_217,{_zz_s1_outputPayload_selValid_268,_zz_s1_outputPayload_selValid_269}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_14]); + s1_outputPayload_selValid[15] = ((|{_zz_s1_outputPayload_selValid_239,{_zz_s1_outputPayload_selValid_238,{_zz_s1_outputPayload_selValid_237,{_zz_s1_outputPayload_selValid_236,{_zz_s1_outputPayload_selValid_235,{_zz_s1_outputPayload_selValid_234,{_zz_s1_outputPayload_selValid_233,{_zz_s1_outputPayload_selValid_232,{_zz_s1_outputPayload_selValid_270,_zz_s1_outputPayload_selValid_271}}}}}}}}}) && s1_outputPayload_cmd_mask[s1_outputPayload_sel_15]); + end + + assign _zz_s1_outputPayload_selValid_15 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_16 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_17 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_18 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_19 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_20 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_21 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_22 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_23 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_24 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_25 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_26 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_27 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_28 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0001)); + assign _zz_s1_outputPayload_selValid_29 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0001)); + assign _zz_s1_outputPayload_sel_1 = (((((((_zz_s1_outputPayload_selValid_15 || _zz_s1_outputPayload_selValid_17) || _zz_s1_outputPayload_selValid_19) || _zz_s1_outputPayload_selValid_21) || _zz_s1_outputPayload_selValid_23) || _zz_s1_outputPayload_selValid_25) || _zz_s1_outputPayload_selValid_27) || _zz_s1_outputPayload_selValid_29); + assign _zz_s1_outputPayload_sel_1_1 = (((((((_zz_s1_outputPayload_selValid_16 || _zz_s1_outputPayload_selValid_17) || _zz_s1_outputPayload_selValid_20) || _zz_s1_outputPayload_selValid_21) || _zz_s1_outputPayload_selValid_24) || _zz_s1_outputPayload_selValid_25) || _zz_s1_outputPayload_selValid_28) || _zz_s1_outputPayload_selValid_29); + assign _zz_s1_outputPayload_sel_1_2 = (((((((_zz_s1_outputPayload_selValid_18 || _zz_s1_outputPayload_selValid_19) || _zz_s1_outputPayload_selValid_20) || _zz_s1_outputPayload_selValid_21) || _zz_s1_outputPayload_selValid_26) || _zz_s1_outputPayload_selValid_27) || _zz_s1_outputPayload_selValid_28) || _zz_s1_outputPayload_selValid_29); + assign _zz_s1_outputPayload_sel_1_3 = (((((((_zz_s1_outputPayload_selValid_22 || _zz_s1_outputPayload_selValid_23) || _zz_s1_outputPayload_selValid_24) || _zz_s1_outputPayload_selValid_25) || _zz_s1_outputPayload_selValid_26) || _zz_s1_outputPayload_selValid_27) || _zz_s1_outputPayload_selValid_28) || _zz_s1_outputPayload_selValid_29); + assign s1_outputPayload_sel_1 = {_zz_s1_outputPayload_sel_1_3,{_zz_s1_outputPayload_sel_1_2,{_zz_s1_outputPayload_sel_1_1,_zz_s1_outputPayload_sel_1}}}; + assign _zz_s1_outputPayload_selValid_30 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_31 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_32 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_33 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_34 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_35 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_36 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_37 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_38 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_39 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_40 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_41 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_42 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_43 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0010)); + assign _zz_s1_outputPayload_selValid_44 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0010)); + assign _zz_s1_outputPayload_sel_2 = (((((((_zz_s1_outputPayload_selValid_30 || _zz_s1_outputPayload_selValid_32) || _zz_s1_outputPayload_selValid_34) || _zz_s1_outputPayload_selValid_36) || _zz_s1_outputPayload_selValid_38) || _zz_s1_outputPayload_selValid_40) || _zz_s1_outputPayload_selValid_42) || _zz_s1_outputPayload_selValid_44); + assign _zz_s1_outputPayload_sel_2_1 = (((((((_zz_s1_outputPayload_selValid_31 || _zz_s1_outputPayload_selValid_32) || _zz_s1_outputPayload_selValid_35) || _zz_s1_outputPayload_selValid_36) || _zz_s1_outputPayload_selValid_39) || _zz_s1_outputPayload_selValid_40) || _zz_s1_outputPayload_selValid_43) || _zz_s1_outputPayload_selValid_44); + assign _zz_s1_outputPayload_sel_2_2 = (((((((_zz_s1_outputPayload_selValid_33 || _zz_s1_outputPayload_selValid_34) || _zz_s1_outputPayload_selValid_35) || _zz_s1_outputPayload_selValid_36) || _zz_s1_outputPayload_selValid_41) || _zz_s1_outputPayload_selValid_42) || _zz_s1_outputPayload_selValid_43) || _zz_s1_outputPayload_selValid_44); + assign _zz_s1_outputPayload_sel_2_3 = (((((((_zz_s1_outputPayload_selValid_37 || _zz_s1_outputPayload_selValid_38) || _zz_s1_outputPayload_selValid_39) || _zz_s1_outputPayload_selValid_40) || _zz_s1_outputPayload_selValid_41) || _zz_s1_outputPayload_selValid_42) || _zz_s1_outputPayload_selValid_43) || _zz_s1_outputPayload_selValid_44); + assign s1_outputPayload_sel_2 = {_zz_s1_outputPayload_sel_2_3,{_zz_s1_outputPayload_sel_2_2,{_zz_s1_outputPayload_sel_2_1,_zz_s1_outputPayload_sel_2}}}; + assign _zz_s1_outputPayload_selValid_45 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_46 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_47 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_48 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_49 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_50 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_51 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_52 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_53 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_54 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_55 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_56 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_57 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_58 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0011)); + assign _zz_s1_outputPayload_selValid_59 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0011)); + assign _zz_s1_outputPayload_sel_3 = (((((((_zz_s1_outputPayload_selValid_45 || _zz_s1_outputPayload_selValid_47) || _zz_s1_outputPayload_selValid_49) || _zz_s1_outputPayload_selValid_51) || _zz_s1_outputPayload_selValid_53) || _zz_s1_outputPayload_selValid_55) || _zz_s1_outputPayload_selValid_57) || _zz_s1_outputPayload_selValid_59); + assign _zz_s1_outputPayload_sel_3_1 = (((((((_zz_s1_outputPayload_selValid_46 || _zz_s1_outputPayload_selValid_47) || _zz_s1_outputPayload_selValid_50) || _zz_s1_outputPayload_selValid_51) || _zz_s1_outputPayload_selValid_54) || _zz_s1_outputPayload_selValid_55) || _zz_s1_outputPayload_selValid_58) || _zz_s1_outputPayload_selValid_59); + assign _zz_s1_outputPayload_sel_3_2 = (((((((_zz_s1_outputPayload_selValid_48 || _zz_s1_outputPayload_selValid_49) || _zz_s1_outputPayload_selValid_50) || _zz_s1_outputPayload_selValid_51) || _zz_s1_outputPayload_selValid_56) || _zz_s1_outputPayload_selValid_57) || _zz_s1_outputPayload_selValid_58) || _zz_s1_outputPayload_selValid_59); + assign _zz_s1_outputPayload_sel_3_3 = (((((((_zz_s1_outputPayload_selValid_52 || _zz_s1_outputPayload_selValid_53) || _zz_s1_outputPayload_selValid_54) || _zz_s1_outputPayload_selValid_55) || _zz_s1_outputPayload_selValid_56) || _zz_s1_outputPayload_selValid_57) || _zz_s1_outputPayload_selValid_58) || _zz_s1_outputPayload_selValid_59); + assign s1_outputPayload_sel_3 = {_zz_s1_outputPayload_sel_3_3,{_zz_s1_outputPayload_sel_3_2,{_zz_s1_outputPayload_sel_3_1,_zz_s1_outputPayload_sel_3}}}; + assign _zz_s1_outputPayload_selValid_60 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_61 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_62 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_63 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_64 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_65 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_66 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_67 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_68 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_69 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_70 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_71 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_72 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_73 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0100)); + assign _zz_s1_outputPayload_selValid_74 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0100)); + assign _zz_s1_outputPayload_sel_4 = (((((((_zz_s1_outputPayload_selValid_60 || _zz_s1_outputPayload_selValid_62) || _zz_s1_outputPayload_selValid_64) || _zz_s1_outputPayload_selValid_66) || _zz_s1_outputPayload_selValid_68) || _zz_s1_outputPayload_selValid_70) || _zz_s1_outputPayload_selValid_72) || _zz_s1_outputPayload_selValid_74); + assign _zz_s1_outputPayload_sel_4_1 = (((((((_zz_s1_outputPayload_selValid_61 || _zz_s1_outputPayload_selValid_62) || _zz_s1_outputPayload_selValid_65) || _zz_s1_outputPayload_selValid_66) || _zz_s1_outputPayload_selValid_69) || _zz_s1_outputPayload_selValid_70) || _zz_s1_outputPayload_selValid_73) || _zz_s1_outputPayload_selValid_74); + assign _zz_s1_outputPayload_sel_4_2 = (((((((_zz_s1_outputPayload_selValid_63 || _zz_s1_outputPayload_selValid_64) || _zz_s1_outputPayload_selValid_65) || _zz_s1_outputPayload_selValid_66) || _zz_s1_outputPayload_selValid_71) || _zz_s1_outputPayload_selValid_72) || _zz_s1_outputPayload_selValid_73) || _zz_s1_outputPayload_selValid_74); + assign _zz_s1_outputPayload_sel_4_3 = (((((((_zz_s1_outputPayload_selValid_67 || _zz_s1_outputPayload_selValid_68) || _zz_s1_outputPayload_selValid_69) || _zz_s1_outputPayload_selValid_70) || _zz_s1_outputPayload_selValid_71) || _zz_s1_outputPayload_selValid_72) || _zz_s1_outputPayload_selValid_73) || _zz_s1_outputPayload_selValid_74); + assign s1_outputPayload_sel_4 = {_zz_s1_outputPayload_sel_4_3,{_zz_s1_outputPayload_sel_4_2,{_zz_s1_outputPayload_sel_4_1,_zz_s1_outputPayload_sel_4}}}; + assign _zz_s1_outputPayload_selValid_75 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_76 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_77 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_78 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_79 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_80 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_81 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_82 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_83 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_84 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_85 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_86 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_87 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_88 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0101)); + assign _zz_s1_outputPayload_selValid_89 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0101)); + assign _zz_s1_outputPayload_sel_5 = (((((((_zz_s1_outputPayload_selValid_75 || _zz_s1_outputPayload_selValid_77) || _zz_s1_outputPayload_selValid_79) || _zz_s1_outputPayload_selValid_81) || _zz_s1_outputPayload_selValid_83) || _zz_s1_outputPayload_selValid_85) || _zz_s1_outputPayload_selValid_87) || _zz_s1_outputPayload_selValid_89); + assign _zz_s1_outputPayload_sel_5_1 = (((((((_zz_s1_outputPayload_selValid_76 || _zz_s1_outputPayload_selValid_77) || _zz_s1_outputPayload_selValid_80) || _zz_s1_outputPayload_selValid_81) || _zz_s1_outputPayload_selValid_84) || _zz_s1_outputPayload_selValid_85) || _zz_s1_outputPayload_selValid_88) || _zz_s1_outputPayload_selValid_89); + assign _zz_s1_outputPayload_sel_5_2 = (((((((_zz_s1_outputPayload_selValid_78 || _zz_s1_outputPayload_selValid_79) || _zz_s1_outputPayload_selValid_80) || _zz_s1_outputPayload_selValid_81) || _zz_s1_outputPayload_selValid_86) || _zz_s1_outputPayload_selValid_87) || _zz_s1_outputPayload_selValid_88) || _zz_s1_outputPayload_selValid_89); + assign _zz_s1_outputPayload_sel_5_3 = (((((((_zz_s1_outputPayload_selValid_82 || _zz_s1_outputPayload_selValid_83) || _zz_s1_outputPayload_selValid_84) || _zz_s1_outputPayload_selValid_85) || _zz_s1_outputPayload_selValid_86) || _zz_s1_outputPayload_selValid_87) || _zz_s1_outputPayload_selValid_88) || _zz_s1_outputPayload_selValid_89); + assign s1_outputPayload_sel_5 = {_zz_s1_outputPayload_sel_5_3,{_zz_s1_outputPayload_sel_5_2,{_zz_s1_outputPayload_sel_5_1,_zz_s1_outputPayload_sel_5}}}; + assign _zz_s1_outputPayload_selValid_90 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_91 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_92 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_93 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_94 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_95 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_96 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_97 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_98 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_99 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_100 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_101 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_102 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_103 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0110)); + assign _zz_s1_outputPayload_selValid_104 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0110)); + assign _zz_s1_outputPayload_sel_6 = (((((((_zz_s1_outputPayload_selValid_90 || _zz_s1_outputPayload_selValid_92) || _zz_s1_outputPayload_selValid_94) || _zz_s1_outputPayload_selValid_96) || _zz_s1_outputPayload_selValid_98) || _zz_s1_outputPayload_selValid_100) || _zz_s1_outputPayload_selValid_102) || _zz_s1_outputPayload_selValid_104); + assign _zz_s1_outputPayload_sel_6_1 = (((((((_zz_s1_outputPayload_selValid_91 || _zz_s1_outputPayload_selValid_92) || _zz_s1_outputPayload_selValid_95) || _zz_s1_outputPayload_selValid_96) || _zz_s1_outputPayload_selValid_99) || _zz_s1_outputPayload_selValid_100) || _zz_s1_outputPayload_selValid_103) || _zz_s1_outputPayload_selValid_104); + assign _zz_s1_outputPayload_sel_6_2 = (((((((_zz_s1_outputPayload_selValid_93 || _zz_s1_outputPayload_selValid_94) || _zz_s1_outputPayload_selValid_95) || _zz_s1_outputPayload_selValid_96) || _zz_s1_outputPayload_selValid_101) || _zz_s1_outputPayload_selValid_102) || _zz_s1_outputPayload_selValid_103) || _zz_s1_outputPayload_selValid_104); + assign _zz_s1_outputPayload_sel_6_3 = (((((((_zz_s1_outputPayload_selValid_97 || _zz_s1_outputPayload_selValid_98) || _zz_s1_outputPayload_selValid_99) || _zz_s1_outputPayload_selValid_100) || _zz_s1_outputPayload_selValid_101) || _zz_s1_outputPayload_selValid_102) || _zz_s1_outputPayload_selValid_103) || _zz_s1_outputPayload_selValid_104); + assign s1_outputPayload_sel_6 = {_zz_s1_outputPayload_sel_6_3,{_zz_s1_outputPayload_sel_6_2,{_zz_s1_outputPayload_sel_6_1,_zz_s1_outputPayload_sel_6}}}; + assign _zz_s1_outputPayload_selValid_105 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_106 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_107 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_108 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_109 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_110 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_111 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_112 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_113 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_114 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_115 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_116 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_117 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_118 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b0111)); + assign _zz_s1_outputPayload_selValid_119 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b0111)); + assign _zz_s1_outputPayload_sel_7 = (((((((_zz_s1_outputPayload_selValid_105 || _zz_s1_outputPayload_selValid_107) || _zz_s1_outputPayload_selValid_109) || _zz_s1_outputPayload_selValid_111) || _zz_s1_outputPayload_selValid_113) || _zz_s1_outputPayload_selValid_115) || _zz_s1_outputPayload_selValid_117) || _zz_s1_outputPayload_selValid_119); + assign _zz_s1_outputPayload_sel_7_1 = (((((((_zz_s1_outputPayload_selValid_106 || _zz_s1_outputPayload_selValid_107) || _zz_s1_outputPayload_selValid_110) || _zz_s1_outputPayload_selValid_111) || _zz_s1_outputPayload_selValid_114) || _zz_s1_outputPayload_selValid_115) || _zz_s1_outputPayload_selValid_118) || _zz_s1_outputPayload_selValid_119); + assign _zz_s1_outputPayload_sel_7_2 = (((((((_zz_s1_outputPayload_selValid_108 || _zz_s1_outputPayload_selValid_109) || _zz_s1_outputPayload_selValid_110) || _zz_s1_outputPayload_selValid_111) || _zz_s1_outputPayload_selValid_116) || _zz_s1_outputPayload_selValid_117) || _zz_s1_outputPayload_selValid_118) || _zz_s1_outputPayload_selValid_119); + assign _zz_s1_outputPayload_sel_7_3 = (((((((_zz_s1_outputPayload_selValid_112 || _zz_s1_outputPayload_selValid_113) || _zz_s1_outputPayload_selValid_114) || _zz_s1_outputPayload_selValid_115) || _zz_s1_outputPayload_selValid_116) || _zz_s1_outputPayload_selValid_117) || _zz_s1_outputPayload_selValid_118) || _zz_s1_outputPayload_selValid_119); + assign s1_outputPayload_sel_7 = {_zz_s1_outputPayload_sel_7_3,{_zz_s1_outputPayload_sel_7_2,{_zz_s1_outputPayload_sel_7_1,_zz_s1_outputPayload_sel_7}}}; + assign _zz_s1_outputPayload_selValid_120 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_121 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_122 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_123 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_124 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_125 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_126 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_127 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_128 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_129 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_130 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_131 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_132 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_133 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1000)); + assign _zz_s1_outputPayload_selValid_134 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1000)); + assign _zz_s1_outputPayload_sel_8 = (((((((_zz_s1_outputPayload_selValid_120 || _zz_s1_outputPayload_selValid_122) || _zz_s1_outputPayload_selValid_124) || _zz_s1_outputPayload_selValid_126) || _zz_s1_outputPayload_selValid_128) || _zz_s1_outputPayload_selValid_130) || _zz_s1_outputPayload_selValid_132) || _zz_s1_outputPayload_selValid_134); + assign _zz_s1_outputPayload_sel_8_1 = (((((((_zz_s1_outputPayload_selValid_121 || _zz_s1_outputPayload_selValid_122) || _zz_s1_outputPayload_selValid_125) || _zz_s1_outputPayload_selValid_126) || _zz_s1_outputPayload_selValid_129) || _zz_s1_outputPayload_selValid_130) || _zz_s1_outputPayload_selValid_133) || _zz_s1_outputPayload_selValid_134); + assign _zz_s1_outputPayload_sel_8_2 = (((((((_zz_s1_outputPayload_selValid_123 || _zz_s1_outputPayload_selValid_124) || _zz_s1_outputPayload_selValid_125) || _zz_s1_outputPayload_selValid_126) || _zz_s1_outputPayload_selValid_131) || _zz_s1_outputPayload_selValid_132) || _zz_s1_outputPayload_selValid_133) || _zz_s1_outputPayload_selValid_134); + assign _zz_s1_outputPayload_sel_8_3 = (((((((_zz_s1_outputPayload_selValid_127 || _zz_s1_outputPayload_selValid_128) || _zz_s1_outputPayload_selValid_129) || _zz_s1_outputPayload_selValid_130) || _zz_s1_outputPayload_selValid_131) || _zz_s1_outputPayload_selValid_132) || _zz_s1_outputPayload_selValid_133) || _zz_s1_outputPayload_selValid_134); + assign s1_outputPayload_sel_8 = {_zz_s1_outputPayload_sel_8_3,{_zz_s1_outputPayload_sel_8_2,{_zz_s1_outputPayload_sel_8_1,_zz_s1_outputPayload_sel_8}}}; + assign _zz_s1_outputPayload_selValid_135 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_136 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_137 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_138 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_139 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_140 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_141 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_142 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_143 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_144 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_145 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_146 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_147 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_148 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1001)); + assign _zz_s1_outputPayload_selValid_149 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1001)); + assign _zz_s1_outputPayload_sel_9 = (((((((_zz_s1_outputPayload_selValid_135 || _zz_s1_outputPayload_selValid_137) || _zz_s1_outputPayload_selValid_139) || _zz_s1_outputPayload_selValid_141) || _zz_s1_outputPayload_selValid_143) || _zz_s1_outputPayload_selValid_145) || _zz_s1_outputPayload_selValid_147) || _zz_s1_outputPayload_selValid_149); + assign _zz_s1_outputPayload_sel_9_1 = (((((((_zz_s1_outputPayload_selValid_136 || _zz_s1_outputPayload_selValid_137) || _zz_s1_outputPayload_selValid_140) || _zz_s1_outputPayload_selValid_141) || _zz_s1_outputPayload_selValid_144) || _zz_s1_outputPayload_selValid_145) || _zz_s1_outputPayload_selValid_148) || _zz_s1_outputPayload_selValid_149); + assign _zz_s1_outputPayload_sel_9_2 = (((((((_zz_s1_outputPayload_selValid_138 || _zz_s1_outputPayload_selValid_139) || _zz_s1_outputPayload_selValid_140) || _zz_s1_outputPayload_selValid_141) || _zz_s1_outputPayload_selValid_146) || _zz_s1_outputPayload_selValid_147) || _zz_s1_outputPayload_selValid_148) || _zz_s1_outputPayload_selValid_149); + assign _zz_s1_outputPayload_sel_9_3 = (((((((_zz_s1_outputPayload_selValid_142 || _zz_s1_outputPayload_selValid_143) || _zz_s1_outputPayload_selValid_144) || _zz_s1_outputPayload_selValid_145) || _zz_s1_outputPayload_selValid_146) || _zz_s1_outputPayload_selValid_147) || _zz_s1_outputPayload_selValid_148) || _zz_s1_outputPayload_selValid_149); + assign s1_outputPayload_sel_9 = {_zz_s1_outputPayload_sel_9_3,{_zz_s1_outputPayload_sel_9_2,{_zz_s1_outputPayload_sel_9_1,_zz_s1_outputPayload_sel_9}}}; + assign _zz_s1_outputPayload_selValid_150 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_151 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_152 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_153 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_154 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_155 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_156 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_157 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_158 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_159 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_160 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_161 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_162 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_163 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1010)); + assign _zz_s1_outputPayload_selValid_164 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1010)); + assign _zz_s1_outputPayload_sel_10 = (((((((_zz_s1_outputPayload_selValid_150 || _zz_s1_outputPayload_selValid_152) || _zz_s1_outputPayload_selValid_154) || _zz_s1_outputPayload_selValid_156) || _zz_s1_outputPayload_selValid_158) || _zz_s1_outputPayload_selValid_160) || _zz_s1_outputPayload_selValid_162) || _zz_s1_outputPayload_selValid_164); + assign _zz_s1_outputPayload_sel_10_1 = (((((((_zz_s1_outputPayload_selValid_151 || _zz_s1_outputPayload_selValid_152) || _zz_s1_outputPayload_selValid_155) || _zz_s1_outputPayload_selValid_156) || _zz_s1_outputPayload_selValid_159) || _zz_s1_outputPayload_selValid_160) || _zz_s1_outputPayload_selValid_163) || _zz_s1_outputPayload_selValid_164); + assign _zz_s1_outputPayload_sel_10_2 = (((((((_zz_s1_outputPayload_selValid_153 || _zz_s1_outputPayload_selValid_154) || _zz_s1_outputPayload_selValid_155) || _zz_s1_outputPayload_selValid_156) || _zz_s1_outputPayload_selValid_161) || _zz_s1_outputPayload_selValid_162) || _zz_s1_outputPayload_selValid_163) || _zz_s1_outputPayload_selValid_164); + assign _zz_s1_outputPayload_sel_10_3 = (((((((_zz_s1_outputPayload_selValid_157 || _zz_s1_outputPayload_selValid_158) || _zz_s1_outputPayload_selValid_159) || _zz_s1_outputPayload_selValid_160) || _zz_s1_outputPayload_selValid_161) || _zz_s1_outputPayload_selValid_162) || _zz_s1_outputPayload_selValid_163) || _zz_s1_outputPayload_selValid_164); + assign s1_outputPayload_sel_10 = {_zz_s1_outputPayload_sel_10_3,{_zz_s1_outputPayload_sel_10_2,{_zz_s1_outputPayload_sel_10_1,_zz_s1_outputPayload_sel_10}}}; + assign _zz_s1_outputPayload_selValid_165 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_166 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_167 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_168 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_169 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_170 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_171 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_172 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_173 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_174 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_175 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_176 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_177 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_178 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1011)); + assign _zz_s1_outputPayload_selValid_179 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1011)); + assign _zz_s1_outputPayload_sel_11 = (((((((_zz_s1_outputPayload_selValid_165 || _zz_s1_outputPayload_selValid_167) || _zz_s1_outputPayload_selValid_169) || _zz_s1_outputPayload_selValid_171) || _zz_s1_outputPayload_selValid_173) || _zz_s1_outputPayload_selValid_175) || _zz_s1_outputPayload_selValid_177) || _zz_s1_outputPayload_selValid_179); + assign _zz_s1_outputPayload_sel_11_1 = (((((((_zz_s1_outputPayload_selValid_166 || _zz_s1_outputPayload_selValid_167) || _zz_s1_outputPayload_selValid_170) || _zz_s1_outputPayload_selValid_171) || _zz_s1_outputPayload_selValid_174) || _zz_s1_outputPayload_selValid_175) || _zz_s1_outputPayload_selValid_178) || _zz_s1_outputPayload_selValid_179); + assign _zz_s1_outputPayload_sel_11_2 = (((((((_zz_s1_outputPayload_selValid_168 || _zz_s1_outputPayload_selValid_169) || _zz_s1_outputPayload_selValid_170) || _zz_s1_outputPayload_selValid_171) || _zz_s1_outputPayload_selValid_176) || _zz_s1_outputPayload_selValid_177) || _zz_s1_outputPayload_selValid_178) || _zz_s1_outputPayload_selValid_179); + assign _zz_s1_outputPayload_sel_11_3 = (((((((_zz_s1_outputPayload_selValid_172 || _zz_s1_outputPayload_selValid_173) || _zz_s1_outputPayload_selValid_174) || _zz_s1_outputPayload_selValid_175) || _zz_s1_outputPayload_selValid_176) || _zz_s1_outputPayload_selValid_177) || _zz_s1_outputPayload_selValid_178) || _zz_s1_outputPayload_selValid_179); + assign s1_outputPayload_sel_11 = {_zz_s1_outputPayload_sel_11_3,{_zz_s1_outputPayload_sel_11_2,{_zz_s1_outputPayload_sel_11_1,_zz_s1_outputPayload_sel_11}}}; + assign _zz_s1_outputPayload_selValid_180 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_181 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_182 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_183 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_184 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_185 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_186 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_187 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_188 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_189 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_190 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_191 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_192 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_193 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1100)); + assign _zz_s1_outputPayload_selValid_194 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1100)); + assign _zz_s1_outputPayload_sel_12 = (((((((_zz_s1_outputPayload_selValid_180 || _zz_s1_outputPayload_selValid_182) || _zz_s1_outputPayload_selValid_184) || _zz_s1_outputPayload_selValid_186) || _zz_s1_outputPayload_selValid_188) || _zz_s1_outputPayload_selValid_190) || _zz_s1_outputPayload_selValid_192) || _zz_s1_outputPayload_selValid_194); + assign _zz_s1_outputPayload_sel_12_1 = (((((((_zz_s1_outputPayload_selValid_181 || _zz_s1_outputPayload_selValid_182) || _zz_s1_outputPayload_selValid_185) || _zz_s1_outputPayload_selValid_186) || _zz_s1_outputPayload_selValid_189) || _zz_s1_outputPayload_selValid_190) || _zz_s1_outputPayload_selValid_193) || _zz_s1_outputPayload_selValid_194); + assign _zz_s1_outputPayload_sel_12_2 = (((((((_zz_s1_outputPayload_selValid_183 || _zz_s1_outputPayload_selValid_184) || _zz_s1_outputPayload_selValid_185) || _zz_s1_outputPayload_selValid_186) || _zz_s1_outputPayload_selValid_191) || _zz_s1_outputPayload_selValid_192) || _zz_s1_outputPayload_selValid_193) || _zz_s1_outputPayload_selValid_194); + assign _zz_s1_outputPayload_sel_12_3 = (((((((_zz_s1_outputPayload_selValid_187 || _zz_s1_outputPayload_selValid_188) || _zz_s1_outputPayload_selValid_189) || _zz_s1_outputPayload_selValid_190) || _zz_s1_outputPayload_selValid_191) || _zz_s1_outputPayload_selValid_192) || _zz_s1_outputPayload_selValid_193) || _zz_s1_outputPayload_selValid_194); + assign s1_outputPayload_sel_12 = {_zz_s1_outputPayload_sel_12_3,{_zz_s1_outputPayload_sel_12_2,{_zz_s1_outputPayload_sel_12_1,_zz_s1_outputPayload_sel_12}}}; + assign _zz_s1_outputPayload_selValid_195 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_196 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_197 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_198 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_199 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_200 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_201 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_202 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_203 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_204 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_205 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_206 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_207 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_208 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1101)); + assign _zz_s1_outputPayload_selValid_209 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1101)); + assign _zz_s1_outputPayload_sel_13 = (((((((_zz_s1_outputPayload_selValid_195 || _zz_s1_outputPayload_selValid_197) || _zz_s1_outputPayload_selValid_199) || _zz_s1_outputPayload_selValid_201) || _zz_s1_outputPayload_selValid_203) || _zz_s1_outputPayload_selValid_205) || _zz_s1_outputPayload_selValid_207) || _zz_s1_outputPayload_selValid_209); + assign _zz_s1_outputPayload_sel_13_1 = (((((((_zz_s1_outputPayload_selValid_196 || _zz_s1_outputPayload_selValid_197) || _zz_s1_outputPayload_selValid_200) || _zz_s1_outputPayload_selValid_201) || _zz_s1_outputPayload_selValid_204) || _zz_s1_outputPayload_selValid_205) || _zz_s1_outputPayload_selValid_208) || _zz_s1_outputPayload_selValid_209); + assign _zz_s1_outputPayload_sel_13_2 = (((((((_zz_s1_outputPayload_selValid_198 || _zz_s1_outputPayload_selValid_199) || _zz_s1_outputPayload_selValid_200) || _zz_s1_outputPayload_selValid_201) || _zz_s1_outputPayload_selValid_206) || _zz_s1_outputPayload_selValid_207) || _zz_s1_outputPayload_selValid_208) || _zz_s1_outputPayload_selValid_209); + assign _zz_s1_outputPayload_sel_13_3 = (((((((_zz_s1_outputPayload_selValid_202 || _zz_s1_outputPayload_selValid_203) || _zz_s1_outputPayload_selValid_204) || _zz_s1_outputPayload_selValid_205) || _zz_s1_outputPayload_selValid_206) || _zz_s1_outputPayload_selValid_207) || _zz_s1_outputPayload_selValid_208) || _zz_s1_outputPayload_selValid_209); + assign s1_outputPayload_sel_13 = {_zz_s1_outputPayload_sel_13_3,{_zz_s1_outputPayload_sel_13_2,{_zz_s1_outputPayload_sel_13_1,_zz_s1_outputPayload_sel_13}}}; + assign _zz_s1_outputPayload_selValid_210 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_211 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_212 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_213 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_214 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_215 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_216 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_217 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_218 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_219 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_220 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_221 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_222 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_223 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1110)); + assign _zz_s1_outputPayload_selValid_224 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1110)); + assign _zz_s1_outputPayload_sel_14 = (((((((_zz_s1_outputPayload_selValid_210 || _zz_s1_outputPayload_selValid_212) || _zz_s1_outputPayload_selValid_214) || _zz_s1_outputPayload_selValid_216) || _zz_s1_outputPayload_selValid_218) || _zz_s1_outputPayload_selValid_220) || _zz_s1_outputPayload_selValid_222) || _zz_s1_outputPayload_selValid_224); + assign _zz_s1_outputPayload_sel_14_1 = (((((((_zz_s1_outputPayload_selValid_211 || _zz_s1_outputPayload_selValid_212) || _zz_s1_outputPayload_selValid_215) || _zz_s1_outputPayload_selValid_216) || _zz_s1_outputPayload_selValid_219) || _zz_s1_outputPayload_selValid_220) || _zz_s1_outputPayload_selValid_223) || _zz_s1_outputPayload_selValid_224); + assign _zz_s1_outputPayload_sel_14_2 = (((((((_zz_s1_outputPayload_selValid_213 || _zz_s1_outputPayload_selValid_214) || _zz_s1_outputPayload_selValid_215) || _zz_s1_outputPayload_selValid_216) || _zz_s1_outputPayload_selValid_221) || _zz_s1_outputPayload_selValid_222) || _zz_s1_outputPayload_selValid_223) || _zz_s1_outputPayload_selValid_224); + assign _zz_s1_outputPayload_sel_14_3 = (((((((_zz_s1_outputPayload_selValid_217 || _zz_s1_outputPayload_selValid_218) || _zz_s1_outputPayload_selValid_219) || _zz_s1_outputPayload_selValid_220) || _zz_s1_outputPayload_selValid_221) || _zz_s1_outputPayload_selValid_222) || _zz_s1_outputPayload_selValid_223) || _zz_s1_outputPayload_selValid_224); + assign s1_outputPayload_sel_14 = {_zz_s1_outputPayload_sel_14_3,{_zz_s1_outputPayload_sel_14_2,{_zz_s1_outputPayload_sel_14_1,_zz_s1_outputPayload_sel_14}}}; + assign _zz_s1_outputPayload_selValid_225 = (s1_input_payload_cmd_mask[1] && (s1_inputIndexes_1 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_226 = (s1_input_payload_cmd_mask[2] && (s1_inputIndexes_2 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_227 = (s1_input_payload_cmd_mask[3] && (s1_inputIndexes_3 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_228 = (s1_input_payload_cmd_mask[4] && (s1_inputIndexes_4 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_229 = (s1_input_payload_cmd_mask[5] && (s1_inputIndexes_5 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_230 = (s1_input_payload_cmd_mask[6] && (s1_inputIndexes_6 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_231 = (s1_input_payload_cmd_mask[7] && (s1_inputIndexes_7 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_232 = (s1_input_payload_cmd_mask[8] && (s1_inputIndexes_8 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_233 = (s1_input_payload_cmd_mask[9] && (s1_inputIndexes_9 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_234 = (s1_input_payload_cmd_mask[10] && (s1_inputIndexes_10 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_235 = (s1_input_payload_cmd_mask[11] && (s1_inputIndexes_11 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_236 = (s1_input_payload_cmd_mask[12] && (s1_inputIndexes_12 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_237 = (s1_input_payload_cmd_mask[13] && (s1_inputIndexes_13 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_238 = (s1_input_payload_cmd_mask[14] && (s1_inputIndexes_14 == 4'b1111)); + assign _zz_s1_outputPayload_selValid_239 = (s1_input_payload_cmd_mask[15] && (s1_inputIndexes_15 == 4'b1111)); + assign _zz_s1_outputPayload_sel_15 = (((((((_zz_s1_outputPayload_selValid_225 || _zz_s1_outputPayload_selValid_227) || _zz_s1_outputPayload_selValid_229) || _zz_s1_outputPayload_selValid_231) || _zz_s1_outputPayload_selValid_233) || _zz_s1_outputPayload_selValid_235) || _zz_s1_outputPayload_selValid_237) || _zz_s1_outputPayload_selValid_239); + assign _zz_s1_outputPayload_sel_15_1 = (((((((_zz_s1_outputPayload_selValid_226 || _zz_s1_outputPayload_selValid_227) || _zz_s1_outputPayload_selValid_230) || _zz_s1_outputPayload_selValid_231) || _zz_s1_outputPayload_selValid_234) || _zz_s1_outputPayload_selValid_235) || _zz_s1_outputPayload_selValid_238) || _zz_s1_outputPayload_selValid_239); + assign _zz_s1_outputPayload_sel_15_2 = (((((((_zz_s1_outputPayload_selValid_228 || _zz_s1_outputPayload_selValid_229) || _zz_s1_outputPayload_selValid_230) || _zz_s1_outputPayload_selValid_231) || _zz_s1_outputPayload_selValid_236) || _zz_s1_outputPayload_selValid_237) || _zz_s1_outputPayload_selValid_238) || _zz_s1_outputPayload_selValid_239); + assign _zz_s1_outputPayload_sel_15_3 = (((((((_zz_s1_outputPayload_selValid_232 || _zz_s1_outputPayload_selValid_233) || _zz_s1_outputPayload_selValid_234) || _zz_s1_outputPayload_selValid_235) || _zz_s1_outputPayload_selValid_236) || _zz_s1_outputPayload_selValid_237) || _zz_s1_outputPayload_selValid_238) || _zz_s1_outputPayload_selValid_239); + assign s1_outputPayload_sel_15 = {_zz_s1_outputPayload_sel_15_3,{_zz_s1_outputPayload_sel_15_2,{_zz_s1_outputPayload_sel_15_1,_zz_s1_outputPayload_sel_15}}}; + assign s1_output_valid = s1_input_valid; + assign s1_input_ready = s1_output_ready; + assign s1_output_payload_cmd_data = s1_outputPayload_cmd_data; + assign s1_output_payload_cmd_mask = s1_outputPayload_cmd_mask; + assign s1_output_payload_index_0 = s1_outputPayload_index_0; + assign s1_output_payload_index_1 = s1_outputPayload_index_1; + assign s1_output_payload_index_2 = s1_outputPayload_index_2; + assign s1_output_payload_index_3 = s1_outputPayload_index_3; + assign s1_output_payload_index_4 = s1_outputPayload_index_4; + assign s1_output_payload_index_5 = s1_outputPayload_index_5; + assign s1_output_payload_index_6 = s1_outputPayload_index_6; + assign s1_output_payload_index_7 = s1_outputPayload_index_7; + assign s1_output_payload_index_8 = s1_outputPayload_index_8; + assign s1_output_payload_index_9 = s1_outputPayload_index_9; + assign s1_output_payload_index_10 = s1_outputPayload_index_10; + assign s1_output_payload_index_11 = s1_outputPayload_index_11; + assign s1_output_payload_index_12 = s1_outputPayload_index_12; + assign s1_output_payload_index_13 = s1_outputPayload_index_13; + assign s1_output_payload_index_14 = s1_outputPayload_index_14; + assign s1_output_payload_index_15 = s1_outputPayload_index_15; + assign s1_output_payload_last = s1_outputPayload_last; + assign s1_output_payload_sel_0 = s1_outputPayload_sel_0; + assign s1_output_payload_sel_1 = s1_outputPayload_sel_1; + assign s1_output_payload_sel_2 = s1_outputPayload_sel_2; + assign s1_output_payload_sel_3 = s1_outputPayload_sel_3; + assign s1_output_payload_sel_4 = s1_outputPayload_sel_4; + assign s1_output_payload_sel_5 = s1_outputPayload_sel_5; + assign s1_output_payload_sel_6 = s1_outputPayload_sel_6; + assign s1_output_payload_sel_7 = s1_outputPayload_sel_7; + assign s1_output_payload_sel_8 = s1_outputPayload_sel_8; + assign s1_output_payload_sel_9 = s1_outputPayload_sel_9; + assign s1_output_payload_sel_10 = s1_outputPayload_sel_10; + assign s1_output_payload_sel_11 = s1_outputPayload_sel_11; + assign s1_output_payload_sel_12 = s1_outputPayload_sel_12; + assign s1_output_payload_sel_13 = s1_outputPayload_sel_13; + assign s1_output_payload_sel_14 = s1_outputPayload_sel_14; + assign s1_output_payload_sel_15 = s1_outputPayload_sel_15; + assign s1_output_payload_selValid = s1_outputPayload_selValid; + always @(*) begin + s1_output_ready = s2_input_ready; + if(when_Stream_l375_2) begin + s1_output_ready = 1'b1; + end + end + + assign when_Stream_l375_2 = (! s2_input_valid); + assign s2_input_valid = s1_output_rValid; + assign s2_input_payload_cmd_data = s1_output_rData_cmd_data; + assign s2_input_payload_cmd_mask = s1_output_rData_cmd_mask; + assign s2_input_payload_index_0 = s1_output_rData_index_0; + assign s2_input_payload_index_1 = s1_output_rData_index_1; + assign s2_input_payload_index_2 = s1_output_rData_index_2; + assign s2_input_payload_index_3 = s1_output_rData_index_3; + assign s2_input_payload_index_4 = s1_output_rData_index_4; + assign s2_input_payload_index_5 = s1_output_rData_index_5; + assign s2_input_payload_index_6 = s1_output_rData_index_6; + assign s2_input_payload_index_7 = s1_output_rData_index_7; + assign s2_input_payload_index_8 = s1_output_rData_index_8; + assign s2_input_payload_index_9 = s1_output_rData_index_9; + assign s2_input_payload_index_10 = s1_output_rData_index_10; + assign s2_input_payload_index_11 = s1_output_rData_index_11; + assign s2_input_payload_index_12 = s1_output_rData_index_12; + assign s2_input_payload_index_13 = s1_output_rData_index_13; + assign s2_input_payload_index_14 = s1_output_rData_index_14; + assign s2_input_payload_index_15 = s1_output_rData_index_15; + assign s2_input_payload_last = s1_output_rData_last; + assign s2_input_payload_sel_0 = s1_output_rData_sel_0; + assign s2_input_payload_sel_1 = s1_output_rData_sel_1; + assign s2_input_payload_sel_2 = s1_output_rData_sel_2; + assign s2_input_payload_sel_3 = s1_output_rData_sel_3; + assign s2_input_payload_sel_4 = s1_output_rData_sel_4; + assign s2_input_payload_sel_5 = s1_output_rData_sel_5; + assign s2_input_payload_sel_6 = s1_output_rData_sel_6; + assign s2_input_payload_sel_7 = s1_output_rData_sel_7; + assign s2_input_payload_sel_8 = s1_output_rData_sel_8; + assign s2_input_payload_sel_9 = s1_output_rData_sel_9; + assign s2_input_payload_sel_10 = s1_output_rData_sel_10; + assign s2_input_payload_sel_11 = s1_output_rData_sel_11; + assign s2_input_payload_sel_12 = s1_output_rData_sel_12; + assign s2_input_payload_sel_13 = s1_output_rData_sel_13; + assign s2_input_payload_sel_14 = s1_output_rData_sel_14; + assign s2_input_payload_sel_15 = s1_output_rData_sel_15; + assign s2_input_payload_selValid = s1_output_rData_selValid; + always @(*) begin + s2_input_ready = ((! io_output_enough) || io_output_consume); + if(when_DmaSg_l1464) begin + s2_input_ready = 1'b0; + end + end + + assign when_DmaSg_l1464 = (_zz_when_DmaSg_l1464 < s1_byteCounter); + assign s2_input_fire = (s2_input_valid && s2_input_ready); + assign io_output_consumed = s2_input_fire; + assign s2_inputDataBytes_0 = s2_input_payload_cmd_data[7 : 0]; + assign s2_inputDataBytes_1 = s2_input_payload_cmd_data[15 : 8]; + assign s2_inputDataBytes_2 = s2_input_payload_cmd_data[23 : 16]; + assign s2_inputDataBytes_3 = s2_input_payload_cmd_data[31 : 24]; + assign s2_inputDataBytes_4 = s2_input_payload_cmd_data[39 : 32]; + assign s2_inputDataBytes_5 = s2_input_payload_cmd_data[47 : 40]; + assign s2_inputDataBytes_6 = s2_input_payload_cmd_data[55 : 48]; + assign s2_inputDataBytes_7 = s2_input_payload_cmd_data[63 : 56]; + assign s2_inputDataBytes_8 = s2_input_payload_cmd_data[71 : 64]; + assign s2_inputDataBytes_9 = s2_input_payload_cmd_data[79 : 72]; + assign s2_inputDataBytes_10 = s2_input_payload_cmd_data[87 : 80]; + assign s2_inputDataBytes_11 = s2_input_payload_cmd_data[95 : 88]; + assign s2_inputDataBytes_12 = s2_input_payload_cmd_data[103 : 96]; + assign s2_inputDataBytes_13 = s2_input_payload_cmd_data[111 : 104]; + assign s2_inputDataBytes_14 = s2_input_payload_cmd_data[119 : 112]; + assign s2_inputDataBytes_15 = s2_input_payload_cmd_data[127 : 120]; + assign s2_byteLogic_0_lastUsed = (4'b0000 == io_output_lastByteUsed); + assign s2_byteLogic_0_inputMask = s2_input_payload_selValid[0]; + assign s2_byteLogic_0_inputData = _zz_s2_byteLogic_0_inputData; + assign s2_byteLogic_0_outputMask = (s2_byteLogic_0_buffer_valid || (s2_input_valid && s2_byteLogic_0_inputMask)); + assign s2_byteLogic_0_outputData = (s2_byteLogic_0_buffer_valid ? s2_byteLogic_0_buffer_data : s2_byteLogic_0_inputData); + always @(*) begin + io_output_mask[0] = s2_byteLogic_0_outputMask; + io_output_mask[1] = s2_byteLogic_1_outputMask; + io_output_mask[2] = s2_byteLogic_2_outputMask; + io_output_mask[3] = s2_byteLogic_3_outputMask; + io_output_mask[4] = s2_byteLogic_4_outputMask; + io_output_mask[5] = s2_byteLogic_5_outputMask; + io_output_mask[6] = s2_byteLogic_6_outputMask; + io_output_mask[7] = s2_byteLogic_7_outputMask; + io_output_mask[8] = s2_byteLogic_8_outputMask; + io_output_mask[9] = s2_byteLogic_9_outputMask; + io_output_mask[10] = s2_byteLogic_10_outputMask; + io_output_mask[11] = s2_byteLogic_11_outputMask; + io_output_mask[12] = s2_byteLogic_12_outputMask; + io_output_mask[13] = s2_byteLogic_13_outputMask; + io_output_mask[14] = s2_byteLogic_14_outputMask; + io_output_mask[15] = s2_byteLogic_15_outputMask; + end + + always @(*) begin + io_output_data[7 : 0] = s2_byteLogic_0_outputData; + io_output_data[15 : 8] = s2_byteLogic_1_outputData; + io_output_data[23 : 16] = s2_byteLogic_2_outputData; + io_output_data[31 : 24] = s2_byteLogic_3_outputData; + io_output_data[39 : 32] = s2_byteLogic_4_outputData; + io_output_data[47 : 40] = s2_byteLogic_5_outputData; + io_output_data[55 : 48] = s2_byteLogic_6_outputData; + io_output_data[63 : 56] = s2_byteLogic_7_outputData; + io_output_data[71 : 64] = s2_byteLogic_8_outputData; + io_output_data[79 : 72] = s2_byteLogic_9_outputData; + io_output_data[87 : 80] = s2_byteLogic_10_outputData; + io_output_data[95 : 88] = s2_byteLogic_11_outputData; + io_output_data[103 : 96] = s2_byteLogic_12_outputData; + io_output_data[111 : 104] = s2_byteLogic_13_outputData; + io_output_data[119 : 112] = s2_byteLogic_14_outputData; + io_output_data[127 : 120] = s2_byteLogic_15_outputData; + end + + assign when_DmaSg_l1493 = (s2_byteLogic_0_inputMask && ((! io_output_consume) || s2_byteLogic_0_buffer_valid)); + assign s2_byteLogic_1_lastUsed = (4'b0001 == io_output_lastByteUsed); + assign s2_byteLogic_1_inputMask = s2_input_payload_selValid[1]; + assign s2_byteLogic_1_inputData = _zz_s2_byteLogic_1_inputData; + assign s2_byteLogic_1_outputMask = (s2_byteLogic_1_buffer_valid || (s2_input_valid && s2_byteLogic_1_inputMask)); + assign s2_byteLogic_1_outputData = (s2_byteLogic_1_buffer_valid ? s2_byteLogic_1_buffer_data : s2_byteLogic_1_inputData); + assign when_DmaSg_l1493_1 = (s2_byteLogic_1_inputMask && ((! io_output_consume) || s2_byteLogic_1_buffer_valid)); + assign s2_byteLogic_2_lastUsed = (4'b0010 == io_output_lastByteUsed); + assign s2_byteLogic_2_inputMask = s2_input_payload_selValid[2]; + assign s2_byteLogic_2_inputData = _zz_s2_byteLogic_2_inputData; + assign s2_byteLogic_2_outputMask = (s2_byteLogic_2_buffer_valid || (s2_input_valid && s2_byteLogic_2_inputMask)); + assign s2_byteLogic_2_outputData = (s2_byteLogic_2_buffer_valid ? s2_byteLogic_2_buffer_data : s2_byteLogic_2_inputData); + assign when_DmaSg_l1493_2 = (s2_byteLogic_2_inputMask && ((! io_output_consume) || s2_byteLogic_2_buffer_valid)); + assign s2_byteLogic_3_lastUsed = (4'b0011 == io_output_lastByteUsed); + assign s2_byteLogic_3_inputMask = s2_input_payload_selValid[3]; + assign s2_byteLogic_3_inputData = _zz_s2_byteLogic_3_inputData; + assign s2_byteLogic_3_outputMask = (s2_byteLogic_3_buffer_valid || (s2_input_valid && s2_byteLogic_3_inputMask)); + assign s2_byteLogic_3_outputData = (s2_byteLogic_3_buffer_valid ? s2_byteLogic_3_buffer_data : s2_byteLogic_3_inputData); + assign when_DmaSg_l1493_3 = (s2_byteLogic_3_inputMask && ((! io_output_consume) || s2_byteLogic_3_buffer_valid)); + assign s2_byteLogic_4_lastUsed = (4'b0100 == io_output_lastByteUsed); + assign s2_byteLogic_4_inputMask = s2_input_payload_selValid[4]; + assign s2_byteLogic_4_inputData = _zz_s2_byteLogic_4_inputData; + assign s2_byteLogic_4_outputMask = (s2_byteLogic_4_buffer_valid || (s2_input_valid && s2_byteLogic_4_inputMask)); + assign s2_byteLogic_4_outputData = (s2_byteLogic_4_buffer_valid ? s2_byteLogic_4_buffer_data : s2_byteLogic_4_inputData); + assign when_DmaSg_l1493_4 = (s2_byteLogic_4_inputMask && ((! io_output_consume) || s2_byteLogic_4_buffer_valid)); + assign s2_byteLogic_5_lastUsed = (4'b0101 == io_output_lastByteUsed); + assign s2_byteLogic_5_inputMask = s2_input_payload_selValid[5]; + assign s2_byteLogic_5_inputData = _zz_s2_byteLogic_5_inputData; + assign s2_byteLogic_5_outputMask = (s2_byteLogic_5_buffer_valid || (s2_input_valid && s2_byteLogic_5_inputMask)); + assign s2_byteLogic_5_outputData = (s2_byteLogic_5_buffer_valid ? s2_byteLogic_5_buffer_data : s2_byteLogic_5_inputData); + assign when_DmaSg_l1493_5 = (s2_byteLogic_5_inputMask && ((! io_output_consume) || s2_byteLogic_5_buffer_valid)); + assign s2_byteLogic_6_lastUsed = (4'b0110 == io_output_lastByteUsed); + assign s2_byteLogic_6_inputMask = s2_input_payload_selValid[6]; + assign s2_byteLogic_6_inputData = _zz_s2_byteLogic_6_inputData; + assign s2_byteLogic_6_outputMask = (s2_byteLogic_6_buffer_valid || (s2_input_valid && s2_byteLogic_6_inputMask)); + assign s2_byteLogic_6_outputData = (s2_byteLogic_6_buffer_valid ? s2_byteLogic_6_buffer_data : s2_byteLogic_6_inputData); + assign when_DmaSg_l1493_6 = (s2_byteLogic_6_inputMask && ((! io_output_consume) || s2_byteLogic_6_buffer_valid)); + assign s2_byteLogic_7_lastUsed = (4'b0111 == io_output_lastByteUsed); + assign s2_byteLogic_7_inputMask = s2_input_payload_selValid[7]; + assign s2_byteLogic_7_inputData = _zz_s2_byteLogic_7_inputData; + assign s2_byteLogic_7_outputMask = (s2_byteLogic_7_buffer_valid || (s2_input_valid && s2_byteLogic_7_inputMask)); + assign s2_byteLogic_7_outputData = (s2_byteLogic_7_buffer_valid ? s2_byteLogic_7_buffer_data : s2_byteLogic_7_inputData); + assign when_DmaSg_l1493_7 = (s2_byteLogic_7_inputMask && ((! io_output_consume) || s2_byteLogic_7_buffer_valid)); + assign s2_byteLogic_8_lastUsed = (4'b1000 == io_output_lastByteUsed); + assign s2_byteLogic_8_inputMask = s2_input_payload_selValid[8]; + assign s2_byteLogic_8_inputData = _zz_s2_byteLogic_8_inputData; + assign s2_byteLogic_8_outputMask = (s2_byteLogic_8_buffer_valid || (s2_input_valid && s2_byteLogic_8_inputMask)); + assign s2_byteLogic_8_outputData = (s2_byteLogic_8_buffer_valid ? s2_byteLogic_8_buffer_data : s2_byteLogic_8_inputData); + assign when_DmaSg_l1493_8 = (s2_byteLogic_8_inputMask && ((! io_output_consume) || s2_byteLogic_8_buffer_valid)); + assign s2_byteLogic_9_lastUsed = (4'b1001 == io_output_lastByteUsed); + assign s2_byteLogic_9_inputMask = s2_input_payload_selValid[9]; + assign s2_byteLogic_9_inputData = _zz_s2_byteLogic_9_inputData; + assign s2_byteLogic_9_outputMask = (s2_byteLogic_9_buffer_valid || (s2_input_valid && s2_byteLogic_9_inputMask)); + assign s2_byteLogic_9_outputData = (s2_byteLogic_9_buffer_valid ? s2_byteLogic_9_buffer_data : s2_byteLogic_9_inputData); + assign when_DmaSg_l1493_9 = (s2_byteLogic_9_inputMask && ((! io_output_consume) || s2_byteLogic_9_buffer_valid)); + assign s2_byteLogic_10_lastUsed = (4'b1010 == io_output_lastByteUsed); + assign s2_byteLogic_10_inputMask = s2_input_payload_selValid[10]; + assign s2_byteLogic_10_inputData = _zz_s2_byteLogic_10_inputData; + assign s2_byteLogic_10_outputMask = (s2_byteLogic_10_buffer_valid || (s2_input_valid && s2_byteLogic_10_inputMask)); + assign s2_byteLogic_10_outputData = (s2_byteLogic_10_buffer_valid ? s2_byteLogic_10_buffer_data : s2_byteLogic_10_inputData); + assign when_DmaSg_l1493_10 = (s2_byteLogic_10_inputMask && ((! io_output_consume) || s2_byteLogic_10_buffer_valid)); + assign s2_byteLogic_11_lastUsed = (4'b1011 == io_output_lastByteUsed); + assign s2_byteLogic_11_inputMask = s2_input_payload_selValid[11]; + assign s2_byteLogic_11_inputData = _zz_s2_byteLogic_11_inputData; + assign s2_byteLogic_11_outputMask = (s2_byteLogic_11_buffer_valid || (s2_input_valid && s2_byteLogic_11_inputMask)); + assign s2_byteLogic_11_outputData = (s2_byteLogic_11_buffer_valid ? s2_byteLogic_11_buffer_data : s2_byteLogic_11_inputData); + assign when_DmaSg_l1493_11 = (s2_byteLogic_11_inputMask && ((! io_output_consume) || s2_byteLogic_11_buffer_valid)); + assign s2_byteLogic_12_lastUsed = (4'b1100 == io_output_lastByteUsed); + assign s2_byteLogic_12_inputMask = s2_input_payload_selValid[12]; + assign s2_byteLogic_12_inputData = _zz_s2_byteLogic_12_inputData; + assign s2_byteLogic_12_outputMask = (s2_byteLogic_12_buffer_valid || (s2_input_valid && s2_byteLogic_12_inputMask)); + assign s2_byteLogic_12_outputData = (s2_byteLogic_12_buffer_valid ? s2_byteLogic_12_buffer_data : s2_byteLogic_12_inputData); + assign when_DmaSg_l1493_12 = (s2_byteLogic_12_inputMask && ((! io_output_consume) || s2_byteLogic_12_buffer_valid)); + assign s2_byteLogic_13_lastUsed = (4'b1101 == io_output_lastByteUsed); + assign s2_byteLogic_13_inputMask = s2_input_payload_selValid[13]; + assign s2_byteLogic_13_inputData = _zz_s2_byteLogic_13_inputData; + assign s2_byteLogic_13_outputMask = (s2_byteLogic_13_buffer_valid || (s2_input_valid && s2_byteLogic_13_inputMask)); + assign s2_byteLogic_13_outputData = (s2_byteLogic_13_buffer_valid ? s2_byteLogic_13_buffer_data : s2_byteLogic_13_inputData); + assign when_DmaSg_l1493_13 = (s2_byteLogic_13_inputMask && ((! io_output_consume) || s2_byteLogic_13_buffer_valid)); + assign s2_byteLogic_14_lastUsed = (4'b1110 == io_output_lastByteUsed); + assign s2_byteLogic_14_inputMask = s2_input_payload_selValid[14]; + assign s2_byteLogic_14_inputData = _zz_s2_byteLogic_14_inputData; + assign s2_byteLogic_14_outputMask = (s2_byteLogic_14_buffer_valid || (s2_input_valid && s2_byteLogic_14_inputMask)); + assign s2_byteLogic_14_outputData = (s2_byteLogic_14_buffer_valid ? s2_byteLogic_14_buffer_data : s2_byteLogic_14_inputData); + assign when_DmaSg_l1493_14 = (s2_byteLogic_14_inputMask && ((! io_output_consume) || s2_byteLogic_14_buffer_valid)); + assign s2_byteLogic_15_lastUsed = (4'b1111 == io_output_lastByteUsed); + assign s2_byteLogic_15_inputMask = s2_input_payload_selValid[15]; + assign s2_byteLogic_15_inputData = _zz_s2_byteLogic_15_inputData; + assign s2_byteLogic_15_outputMask = (s2_byteLogic_15_buffer_valid || (s2_input_valid && s2_byteLogic_15_inputMask)); + assign s2_byteLogic_15_outputData = (s2_byteLogic_15_buffer_valid ? s2_byteLogic_15_buffer_data : s2_byteLogic_15_inputData); + assign when_DmaSg_l1493_15 = (s2_byteLogic_15_inputMask && ((! io_output_consume) || s2_byteLogic_15_buffer_valid)); + assign _zz_io_output_usedUntil = (((((((s2_byteLogic_1_lastUsed || s2_byteLogic_3_lastUsed) || s2_byteLogic_5_lastUsed) || s2_byteLogic_7_lastUsed) || s2_byteLogic_9_lastUsed) || s2_byteLogic_11_lastUsed) || s2_byteLogic_13_lastUsed) || s2_byteLogic_15_lastUsed); + assign _zz_io_output_usedUntil_1 = (((((((s2_byteLogic_2_lastUsed || s2_byteLogic_3_lastUsed) || s2_byteLogic_6_lastUsed) || s2_byteLogic_7_lastUsed) || s2_byteLogic_10_lastUsed) || s2_byteLogic_11_lastUsed) || s2_byteLogic_14_lastUsed) || s2_byteLogic_15_lastUsed); + assign _zz_io_output_usedUntil_2 = (((((((s2_byteLogic_4_lastUsed || s2_byteLogic_5_lastUsed) || s2_byteLogic_6_lastUsed) || s2_byteLogic_7_lastUsed) || s2_byteLogic_12_lastUsed) || s2_byteLogic_13_lastUsed) || s2_byteLogic_14_lastUsed) || s2_byteLogic_15_lastUsed); + assign _zz_io_output_usedUntil_3 = (((((((s2_byteLogic_8_lastUsed || s2_byteLogic_9_lastUsed) || s2_byteLogic_10_lastUsed) || s2_byteLogic_11_lastUsed) || s2_byteLogic_12_lastUsed) || s2_byteLogic_13_lastUsed) || s2_byteLogic_14_lastUsed) || s2_byteLogic_15_lastUsed); + assign io_output_usedUntil = _zz_io_output_usedUntil_4; + always @(posedge clk) begin + if(reset) begin + io_input_rValid <= 1'b0; + s0_output_rValid <= 1'b0; + s1_output_rValid <= 1'b0; + end else begin + if(io_input_ready) begin + io_input_rValid <= io_input_valid; + end + if(io_flush) begin + io_input_rValid <= 1'b0; + end + if(s0_output_ready) begin + s0_output_rValid <= s0_output_valid; + end + if(io_flush) begin + s0_output_rValid <= 1'b0; + end + if(s1_output_ready) begin + s1_output_rValid <= s1_output_valid; + end + if(io_flush) begin + s1_output_rValid <= 1'b0; + end + end + end + + always @(posedge clk) begin + if(io_input_ready) begin + io_input_rData_data <= io_input_payload_data; + io_input_rData_mask <= io_input_payload_mask; + end + if(s0_output_ready) begin + s0_output_rData_cmd_data <= s0_output_payload_cmd_data; + s0_output_rData_cmd_mask <= s0_output_payload_cmd_mask; + s0_output_rData_countOnes_0 <= s0_output_payload_countOnes_0; + s0_output_rData_countOnes_1 <= s0_output_payload_countOnes_1; + s0_output_rData_countOnes_2 <= s0_output_payload_countOnes_2; + s0_output_rData_countOnes_3 <= s0_output_payload_countOnes_3; + s0_output_rData_countOnes_4 <= s0_output_payload_countOnes_4; + s0_output_rData_countOnes_5 <= s0_output_payload_countOnes_5; + s0_output_rData_countOnes_6 <= s0_output_payload_countOnes_6; + s0_output_rData_countOnes_7 <= s0_output_payload_countOnes_7; + s0_output_rData_countOnes_8 <= s0_output_payload_countOnes_8; + s0_output_rData_countOnes_9 <= s0_output_payload_countOnes_9; + s0_output_rData_countOnes_10 <= s0_output_payload_countOnes_10; + s0_output_rData_countOnes_11 <= s0_output_payload_countOnes_11; + s0_output_rData_countOnes_12 <= s0_output_payload_countOnes_12; + s0_output_rData_countOnes_13 <= s0_output_payload_countOnes_13; + s0_output_rData_countOnes_14 <= s0_output_payload_countOnes_14; + s0_output_rData_countOnes_15 <= s0_output_payload_countOnes_15; + end + if(s1_input_fire) begin + s1_offset <= s1_offsetNext[3:0]; + end + if(io_flush) begin + s1_offset <= io_offset; + end + if(s1_input_fire) begin + s1_byteCounter <= (s1_byteCounter + _zz_s1_byteCounter); + end + if(io_flush) begin + s1_byteCounter <= 13'h0; + end + if(s1_output_ready) begin + s1_output_rData_cmd_data <= s1_output_payload_cmd_data; + s1_output_rData_cmd_mask <= s1_output_payload_cmd_mask; + s1_output_rData_index_0 <= s1_output_payload_index_0; + s1_output_rData_index_1 <= s1_output_payload_index_1; + s1_output_rData_index_2 <= s1_output_payload_index_2; + s1_output_rData_index_3 <= s1_output_payload_index_3; + s1_output_rData_index_4 <= s1_output_payload_index_4; + s1_output_rData_index_5 <= s1_output_payload_index_5; + s1_output_rData_index_6 <= s1_output_payload_index_6; + s1_output_rData_index_7 <= s1_output_payload_index_7; + s1_output_rData_index_8 <= s1_output_payload_index_8; + s1_output_rData_index_9 <= s1_output_payload_index_9; + s1_output_rData_index_10 <= s1_output_payload_index_10; + s1_output_rData_index_11 <= s1_output_payload_index_11; + s1_output_rData_index_12 <= s1_output_payload_index_12; + s1_output_rData_index_13 <= s1_output_payload_index_13; + s1_output_rData_index_14 <= s1_output_payload_index_14; + s1_output_rData_index_15 <= s1_output_payload_index_15; + s1_output_rData_last <= s1_output_payload_last; + s1_output_rData_sel_0 <= s1_output_payload_sel_0; + s1_output_rData_sel_1 <= s1_output_payload_sel_1; + s1_output_rData_sel_2 <= s1_output_payload_sel_2; + s1_output_rData_sel_3 <= s1_output_payload_sel_3; + s1_output_rData_sel_4 <= s1_output_payload_sel_4; + s1_output_rData_sel_5 <= s1_output_payload_sel_5; + s1_output_rData_sel_6 <= s1_output_payload_sel_6; + s1_output_rData_sel_7 <= s1_output_payload_sel_7; + s1_output_rData_sel_8 <= s1_output_payload_sel_8; + s1_output_rData_sel_9 <= s1_output_payload_sel_9; + s1_output_rData_sel_10 <= s1_output_payload_sel_10; + s1_output_rData_sel_11 <= s1_output_payload_sel_11; + s1_output_rData_sel_12 <= s1_output_payload_sel_12; + s1_output_rData_sel_13 <= s1_output_payload_sel_13; + s1_output_rData_sel_14 <= s1_output_payload_sel_14; + s1_output_rData_sel_15 <= s1_output_payload_sel_15; + s1_output_rData_selValid <= s1_output_payload_selValid; + end + if(io_output_consume) begin + s2_byteLogic_0_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_0_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493) begin + s2_byteLogic_0_buffer_valid <= 1'b1; + s2_byteLogic_0_buffer_data <= s2_byteLogic_0_inputData; + end + end + if(io_flush) begin + s2_byteLogic_0_buffer_valid <= (4'b0000 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_1_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_1_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_1) begin + s2_byteLogic_1_buffer_valid <= 1'b1; + s2_byteLogic_1_buffer_data <= s2_byteLogic_1_inputData; + end + end + if(io_flush) begin + s2_byteLogic_1_buffer_valid <= (4'b0001 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_2_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_2_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_2) begin + s2_byteLogic_2_buffer_valid <= 1'b1; + s2_byteLogic_2_buffer_data <= s2_byteLogic_2_inputData; + end + end + if(io_flush) begin + s2_byteLogic_2_buffer_valid <= (4'b0010 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_3_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_3_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_3) begin + s2_byteLogic_3_buffer_valid <= 1'b1; + s2_byteLogic_3_buffer_data <= s2_byteLogic_3_inputData; + end + end + if(io_flush) begin + s2_byteLogic_3_buffer_valid <= (4'b0011 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_4_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_4_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_4) begin + s2_byteLogic_4_buffer_valid <= 1'b1; + s2_byteLogic_4_buffer_data <= s2_byteLogic_4_inputData; + end + end + if(io_flush) begin + s2_byteLogic_4_buffer_valid <= (4'b0100 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_5_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_5_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_5) begin + s2_byteLogic_5_buffer_valid <= 1'b1; + s2_byteLogic_5_buffer_data <= s2_byteLogic_5_inputData; + end + end + if(io_flush) begin + s2_byteLogic_5_buffer_valid <= (4'b0101 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_6_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_6_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_6) begin + s2_byteLogic_6_buffer_valid <= 1'b1; + s2_byteLogic_6_buffer_data <= s2_byteLogic_6_inputData; + end + end + if(io_flush) begin + s2_byteLogic_6_buffer_valid <= (4'b0110 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_7_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_7_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_7) begin + s2_byteLogic_7_buffer_valid <= 1'b1; + s2_byteLogic_7_buffer_data <= s2_byteLogic_7_inputData; + end + end + if(io_flush) begin + s2_byteLogic_7_buffer_valid <= (4'b0111 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_8_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_8_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_8) begin + s2_byteLogic_8_buffer_valid <= 1'b1; + s2_byteLogic_8_buffer_data <= s2_byteLogic_8_inputData; + end + end + if(io_flush) begin + s2_byteLogic_8_buffer_valid <= (4'b1000 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_9_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_9_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_9) begin + s2_byteLogic_9_buffer_valid <= 1'b1; + s2_byteLogic_9_buffer_data <= s2_byteLogic_9_inputData; + end + end + if(io_flush) begin + s2_byteLogic_9_buffer_valid <= (4'b1001 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_10_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_10_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_10) begin + s2_byteLogic_10_buffer_valid <= 1'b1; + s2_byteLogic_10_buffer_data <= s2_byteLogic_10_inputData; + end + end + if(io_flush) begin + s2_byteLogic_10_buffer_valid <= (4'b1010 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_11_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_11_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_11) begin + s2_byteLogic_11_buffer_valid <= 1'b1; + s2_byteLogic_11_buffer_data <= s2_byteLogic_11_inputData; + end + end + if(io_flush) begin + s2_byteLogic_11_buffer_valid <= (4'b1011 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_12_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_12_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_12) begin + s2_byteLogic_12_buffer_valid <= 1'b1; + s2_byteLogic_12_buffer_data <= s2_byteLogic_12_inputData; + end + end + if(io_flush) begin + s2_byteLogic_12_buffer_valid <= (4'b1100 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_13_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_13_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_13) begin + s2_byteLogic_13_buffer_valid <= 1'b1; + s2_byteLogic_13_buffer_data <= s2_byteLogic_13_inputData; + end + end + if(io_flush) begin + s2_byteLogic_13_buffer_valid <= (4'b1101 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_14_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_14_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_14) begin + s2_byteLogic_14_buffer_valid <= 1'b1; + s2_byteLogic_14_buffer_data <= s2_byteLogic_14_inputData; + end + end + if(io_flush) begin + s2_byteLogic_14_buffer_valid <= (4'b1110 < io_offset); + end + if(io_output_consume) begin + s2_byteLogic_15_buffer_valid <= 1'b0; + end + if(s2_input_fire) begin + if(s2_input_payload_last) begin + s2_byteLogic_15_buffer_valid <= 1'b0; + end + if(when_DmaSg_l1493_15) begin + s2_byteLogic_15_buffer_valid <= 1'b1; + s2_byteLogic_15_buffer_data <= s2_byteLogic_15_inputData; + end + end + if(io_flush) begin + s2_byteLogic_15_buffer_valid <= (4'b1111 < io_offset); + end + end + + +endmodule + +module EfxDMA_DmaMemoryCore ( + input wire io_writes_0_cmd_valid, + output wire io_writes_0_cmd_ready, + input wire [9:0] io_writes_0_cmd_payload_address, + input wire [63:0] io_writes_0_cmd_payload_data, + input wire [7:0] io_writes_0_cmd_payload_mask, + input wire [1:0] io_writes_0_cmd_payload_priority, + input wire [6:0] io_writes_0_cmd_payload_context, + output wire io_writes_0_rsp_valid, + output wire [6:0] io_writes_0_rsp_payload_context, + input wire io_writes_1_cmd_valid, + output wire io_writes_1_cmd_ready, + input wire [9:0] io_writes_1_cmd_payload_address, + input wire [127:0] io_writes_1_cmd_payload_data, + input wire [15:0] io_writes_1_cmd_payload_mask, + input wire [6:0] io_writes_1_cmd_payload_context, + output wire io_writes_1_rsp_valid, + output wire [6:0] io_writes_1_rsp_payload_context, + input wire io_reads_0_cmd_valid, + output wire io_reads_0_cmd_ready, + input wire [9:0] io_reads_0_cmd_payload_address, + input wire [1:0] io_reads_0_cmd_payload_priority, + input wire [2:0] io_reads_0_cmd_payload_context, + output wire io_reads_0_rsp_valid, + input wire io_reads_0_rsp_ready, + output wire [63:0] io_reads_0_rsp_payload_data, + output wire [7:0] io_reads_0_rsp_payload_mask, + output wire [2:0] io_reads_0_rsp_payload_context, + input wire io_reads_1_cmd_valid, + output wire io_reads_1_cmd_ready, + input wire [9:0] io_reads_1_cmd_payload_address, + input wire [11:0] io_reads_1_cmd_payload_context, + output wire io_reads_1_rsp_valid, + input wire io_reads_1_rsp_ready, + output wire [127:0] io_reads_1_rsp_payload_data, + output wire [15:0] io_reads_1_rsp_payload_mask, + output wire [11:0] io_reads_1_rsp_payload_context, + input wire clk, + input wire reset +); + + reg [71:0] banks_0_ram_spinal_port1; + reg [71:0] banks_1_ram_spinal_port1; + wire [71:0] _zz_banks_0_ram_port; + wire [71:0] _zz_banks_1_ram_port; + wire [3:0] _zz_write_ports_0_priority_value; + wire [9:0] _zz_when_MemoryCore_l136; + wire [9:0] _zz_when_MemoryCore_l136_1; + reg [63:0] _zz_read_ports_0_buffer_bufferIn_payload_data; + reg [7:0] _zz_read_ports_0_buffer_bufferIn_payload_mask; + wire [3:0] _zz_read_ports_0_priority_value; + wire [9:0] _zz_when_MemoryCore_l221; + wire [9:0] _zz_when_MemoryCore_l221_1; + reg _zz_1; + reg _zz_2; + reg banks_0_write_valid; + reg [8:0] banks_0_write_payload_address; + reg [63:0] banks_0_write_payload_data_data; + reg [7:0] banks_0_write_payload_data_mask; + wire banks_0_read_cmd_valid; + wire [8:0] banks_0_read_cmd_payload; + wire [63:0] banks_0_read_rsp_data; + wire [7:0] banks_0_read_rsp_mask; + wire [71:0] _zz_banks_0_read_rsp_data; + wire banks_0_writeOr_value_valid; + wire [8:0] banks_0_writeOr_value_payload_address; + wire [63:0] banks_0_writeOr_value_payload_data_data; + wire [7:0] banks_0_writeOr_value_payload_data_mask; + wire banks_0_readOr_value_valid; + wire [8:0] banks_0_readOr_value_payload; + reg banks_1_write_valid; + reg [8:0] banks_1_write_payload_address; + reg [63:0] banks_1_write_payload_data_data; + reg [7:0] banks_1_write_payload_data_mask; + wire banks_1_read_cmd_valid; + wire [8:0] banks_1_read_cmd_payload; + wire [63:0] banks_1_read_rsp_data; + wire [7:0] banks_1_read_rsp_mask; + wire [71:0] _zz_banks_1_read_rsp_data; + wire banks_1_writeOr_value_valid; + wire [8:0] banks_1_writeOr_value_payload_address; + wire [63:0] banks_1_writeOr_value_payload_data_data; + wire [7:0] banks_1_writeOr_value_payload_data_mask; + wire banks_1_readOr_value_valid; + wire [8:0] banks_1_readOr_value_payload; + reg [3:0] write_ports_0_priority_value; + wire write_nodes_0_0_priority; + wire write_nodes_0_0_conflict; + wire write_nodes_0_1_priority; + wire write_nodes_0_1_conflict; + wire write_nodes_1_0_priority; + wire write_nodes_1_0_conflict; + wire write_nodes_1_1_priority; + wire write_nodes_1_1_conflict; + wire [0:0] write_arbiter_0_losedAgainst; + reg write_arbiter_0_doIt; + reg _zz_banks_0_writeOr_value_valid; + reg [8:0] _zz_banks_0_writeOr_value_valid_1; + reg [63:0] _zz_banks_0_writeOr_value_valid_2; + reg [7:0] _zz_banks_0_writeOr_value_valid_3; + wire when_MemoryCore_l136; + reg _zz_banks_1_writeOr_value_valid; + reg [8:0] _zz_banks_1_writeOr_value_valid_1; + reg [63:0] _zz_banks_1_writeOr_value_valid_2; + reg [7:0] _zz_banks_1_writeOr_value_valid_3; + wire when_MemoryCore_l136_1; + reg write_arbiter_0_doIt_regNext; + reg [6:0] io_writes_0_cmd_payload_context_regNext; + wire [0:0] write_arbiter_1_losedAgainst; + reg write_arbiter_1_doIt; + reg _zz_banks_0_writeOr_value_valid_4; + reg [8:0] _zz_banks_0_writeOr_value_valid_5; + reg [63:0] _zz_banks_0_writeOr_value_valid_6; + reg [7:0] _zz_banks_0_writeOr_value_valid_7; + wire when_MemoryCore_l136_2; + reg _zz_banks_1_writeOr_value_valid_4; + reg [8:0] _zz_banks_1_writeOr_value_valid_5; + reg [63:0] _zz_banks_1_writeOr_value_valid_6; + reg [7:0] _zz_banks_1_writeOr_value_valid_7; + wire when_MemoryCore_l136_3; + reg write_arbiter_1_doIt_regNext; + reg [6:0] io_writes_1_cmd_payload_context_regNext; + wire read_ports_0_buffer_s0_valid; + wire [2:0] read_ports_0_buffer_s0_payload_context; + wire [9:0] read_ports_0_buffer_s0_payload_address; + reg read_ports_0_buffer_s1_valid; + reg [2:0] read_ports_0_buffer_s1_payload_context; + reg [9:0] read_ports_0_buffer_s1_payload_address; + wire [0:0] read_ports_0_buffer_groupSel; + wire read_ports_0_buffer_bufferIn_valid; + wire read_ports_0_buffer_bufferIn_ready; + wire [63:0] read_ports_0_buffer_bufferIn_payload_data; + wire [7:0] read_ports_0_buffer_bufferIn_payload_mask; + wire [2:0] read_ports_0_buffer_bufferIn_payload_context; + wire read_ports_0_buffer_bufferOut_valid; + wire read_ports_0_buffer_bufferOut_ready; + wire [63:0] read_ports_0_buffer_bufferOut_payload_data; + wire [7:0] read_ports_0_buffer_bufferOut_payload_mask; + wire [2:0] read_ports_0_buffer_bufferOut_payload_context; + reg read_ports_0_buffer_bufferIn_rValidN; + reg [63:0] read_ports_0_buffer_bufferIn_rData_data; + reg [7:0] read_ports_0_buffer_bufferIn_rData_mask; + reg [2:0] read_ports_0_buffer_bufferIn_rData_context; + wire read_ports_0_buffer_full; + wire _zz_io_reads_0_cmd_ready; + wire read_ports_0_cmd_valid; + wire read_ports_0_cmd_ready; + wire [9:0] read_ports_0_cmd_payload_address; + wire [1:0] read_ports_0_cmd_payload_priority; + wire [2:0] read_ports_0_cmd_payload_context; + reg [3:0] read_ports_0_priority_value; + wire read_ports_1_buffer_s0_valid; + wire [11:0] read_ports_1_buffer_s0_payload_context; + wire [9:0] read_ports_1_buffer_s0_payload_address; + reg read_ports_1_buffer_s1_valid; + reg [11:0] read_ports_1_buffer_s1_payload_context; + reg [9:0] read_ports_1_buffer_s1_payload_address; + wire read_ports_1_buffer_bufferIn_valid; + wire read_ports_1_buffer_bufferIn_ready; + wire [127:0] read_ports_1_buffer_bufferIn_payload_data; + wire [15:0] read_ports_1_buffer_bufferIn_payload_mask; + wire [11:0] read_ports_1_buffer_bufferIn_payload_context; + wire read_ports_1_buffer_bufferOut_valid; + wire read_ports_1_buffer_bufferOut_ready; + wire [127:0] read_ports_1_buffer_bufferOut_payload_data; + wire [15:0] read_ports_1_buffer_bufferOut_payload_mask; + wire [11:0] read_ports_1_buffer_bufferOut_payload_context; + reg read_ports_1_buffer_bufferIn_rValidN; + reg [127:0] read_ports_1_buffer_bufferIn_rData_data; + reg [15:0] read_ports_1_buffer_bufferIn_rData_mask; + reg [11:0] read_ports_1_buffer_bufferIn_rData_context; + wire read_ports_1_buffer_full; + wire _zz_io_reads_1_cmd_ready; + wire read_ports_1_cmd_valid; + wire read_ports_1_cmd_ready; + wire [9:0] read_ports_1_cmd_payload_address; + wire [11:0] read_ports_1_cmd_payload_context; + wire read_nodes_0_0_priority; + wire read_nodes_0_0_conflict; + wire read_nodes_0_1_priority; + wire read_nodes_0_1_conflict; + wire read_nodes_1_0_priority; + wire read_nodes_1_0_conflict; + wire read_nodes_1_1_priority; + wire read_nodes_1_1_conflict; + wire [0:0] read_arbiter_0_losedAgainst; + wire read_arbiter_0_doIt; + reg _zz_banks_0_readOr_value_valid; + reg [8:0] _zz_banks_0_readOr_value_valid_1; + wire when_MemoryCore_l221; + reg _zz_banks_1_readOr_value_valid; + reg [8:0] _zz_banks_1_readOr_value_valid_1; + wire when_MemoryCore_l221_1; + wire [0:0] read_arbiter_1_losedAgainst; + wire read_arbiter_1_doIt; + reg _zz_banks_0_readOr_value_valid_2; + reg [8:0] _zz_banks_0_readOr_value_valid_3; + wire when_MemoryCore_l221_2; + reg _zz_banks_1_readOr_value_valid_2; + reg [8:0] _zz_banks_1_readOr_value_valid_3; + wire when_MemoryCore_l221_3; + reg [9:0] initialiser_counter; + wire initialiser_done; + wire when_MemoryCore_l239; + wire [71:0] _zz_banks_0_write_payload_data_data; + wire [71:0] _zz_banks_1_write_payload_data_data; + wire [81:0] _zz_banks_0_writeOr_value_valid_8; + wire [80:0] _zz_banks_0_writeOr_value_payload_address; + wire [71:0] _zz_banks_0_writeOr_value_payload_data_data; + wire [9:0] _zz_banks_0_readOr_value_valid_4; + wire [81:0] _zz_banks_1_writeOr_value_valid_8; + wire [80:0] _zz_banks_1_writeOr_value_payload_address; + wire [71:0] _zz_banks_1_writeOr_value_payload_data_data; + wire [9:0] _zz_banks_1_readOr_value_valid_4; + (* ram_style = "block" *) reg [71:0] banks_0_ram [0:511]; + (* ram_style = "block" *) reg [71:0] banks_1_ram [0:511]; + + assign _zz_write_ports_0_priority_value = {2'd0, io_writes_0_cmd_payload_priority}; + assign _zz_when_MemoryCore_l136 = (io_writes_0_cmd_payload_address ^ 10'h0); + assign _zz_when_MemoryCore_l136_1 = (io_writes_0_cmd_payload_address ^ 10'h001); + assign _zz_read_ports_0_priority_value = {2'd0, read_ports_0_cmd_payload_priority}; + assign _zz_when_MemoryCore_l221 = (read_ports_0_cmd_payload_address ^ 10'h0); + assign _zz_when_MemoryCore_l221_1 = (read_ports_0_cmd_payload_address ^ 10'h001); + assign _zz_banks_0_ram_port = {banks_0_write_payload_data_mask,banks_0_write_payload_data_data}; + assign _zz_banks_1_ram_port = {banks_1_write_payload_data_mask,banks_1_write_payload_data_data}; + always @(posedge clk) begin + if(_zz_2) begin + banks_0_ram[banks_0_write_payload_address] <= _zz_banks_0_ram_port; + end + end + + always @(posedge clk) begin + if(banks_0_read_cmd_valid) begin + banks_0_ram_spinal_port1 <= banks_0_ram[banks_0_read_cmd_payload]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin + banks_1_ram[banks_1_write_payload_address] <= _zz_banks_1_ram_port; + end + end + + always @(posedge clk) begin + if(banks_1_read_cmd_valid) begin + banks_1_ram_spinal_port1 <= banks_1_ram[banks_1_read_cmd_payload]; + end + end + + initial begin + `ifndef SYNTHESIS + write_ports_0_priority_value = {$urandom}; + read_ports_0_priority_value = {$urandom}; + `endif + end + + always @(*) begin + case(read_ports_0_buffer_groupSel) + 1'b0 : begin + _zz_read_ports_0_buffer_bufferIn_payload_data = banks_0_read_rsp_data; + _zz_read_ports_0_buffer_bufferIn_payload_mask = banks_0_read_rsp_mask; + end + default : begin + _zz_read_ports_0_buffer_bufferIn_payload_data = banks_1_read_rsp_data; + _zz_read_ports_0_buffer_bufferIn_payload_mask = banks_1_read_rsp_mask; + end + endcase + end + + always @(*) begin + _zz_1 = 1'b0; + if(banks_1_write_valid) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + _zz_2 = 1'b0; + if(banks_0_write_valid) begin + _zz_2 = 1'b1; + end + end + + assign _zz_banks_0_read_rsp_data = banks_0_ram_spinal_port1; + assign banks_0_read_rsp_data = _zz_banks_0_read_rsp_data[63 : 0]; + assign banks_0_read_rsp_mask = _zz_banks_0_read_rsp_data[71 : 64]; + always @(*) begin + banks_0_write_valid = banks_0_writeOr_value_valid; + if(when_MemoryCore_l239) begin + banks_0_write_valid = 1'b1; + end + end + + always @(*) begin + banks_0_write_payload_address = banks_0_writeOr_value_payload_address; + if(when_MemoryCore_l239) begin + banks_0_write_payload_address = initialiser_counter[8:0]; + end + end + + always @(*) begin + banks_0_write_payload_data_data = banks_0_writeOr_value_payload_data_data; + if(when_MemoryCore_l239) begin + banks_0_write_payload_data_data = _zz_banks_0_write_payload_data_data[63 : 0]; + end + end + + always @(*) begin + banks_0_write_payload_data_mask = banks_0_writeOr_value_payload_data_mask; + if(when_MemoryCore_l239) begin + banks_0_write_payload_data_mask = _zz_banks_0_write_payload_data_data[71 : 64]; + end + end + + assign banks_0_read_cmd_valid = banks_0_readOr_value_valid; + assign banks_0_read_cmd_payload = banks_0_readOr_value_payload; + assign _zz_banks_1_read_rsp_data = banks_1_ram_spinal_port1; + assign banks_1_read_rsp_data = _zz_banks_1_read_rsp_data[63 : 0]; + assign banks_1_read_rsp_mask = _zz_banks_1_read_rsp_data[71 : 64]; + always @(*) begin + banks_1_write_valid = banks_1_writeOr_value_valid; + if(when_MemoryCore_l239) begin + banks_1_write_valid = 1'b1; + end + end + + always @(*) begin + banks_1_write_payload_address = banks_1_writeOr_value_payload_address; + if(when_MemoryCore_l239) begin + banks_1_write_payload_address = initialiser_counter[8:0]; + end + end + + always @(*) begin + banks_1_write_payload_data_data = banks_1_writeOr_value_payload_data_data; + if(when_MemoryCore_l239) begin + banks_1_write_payload_data_data = _zz_banks_1_write_payload_data_data[63 : 0]; + end + end + + always @(*) begin + banks_1_write_payload_data_mask = banks_1_writeOr_value_payload_data_mask; + if(when_MemoryCore_l239) begin + banks_1_write_payload_data_mask = _zz_banks_1_write_payload_data_data[71 : 64]; + end + end + + assign banks_1_read_cmd_valid = banks_1_readOr_value_valid; + assign banks_1_read_cmd_payload = banks_1_readOr_value_payload; + assign write_nodes_0_1_priority = 1'b0; + assign write_nodes_1_0_priority = 1'b1; + assign write_nodes_0_1_conflict = ((io_writes_0_cmd_valid && io_writes_1_cmd_valid) && (((io_writes_0_cmd_payload_address ^ io_writes_1_cmd_payload_address) & 10'h0) == 10'h0)); + assign write_nodes_1_0_conflict = write_nodes_0_1_conflict; + assign write_arbiter_0_losedAgainst = (write_nodes_0_1_conflict && (! write_nodes_0_1_priority)); + always @(*) begin + write_arbiter_0_doIt = (io_writes_0_cmd_valid && (write_arbiter_0_losedAgainst == 1'b0)); + if(when_MemoryCore_l239) begin + write_arbiter_0_doIt = 1'b0; + end + end + + assign when_MemoryCore_l136 = (write_arbiter_0_doIt && (_zz_when_MemoryCore_l136[0 : 0] == 1'b0)); + always @(*) begin + if(when_MemoryCore_l136) begin + _zz_banks_0_writeOr_value_valid = 1'b1; + end else begin + _zz_banks_0_writeOr_value_valid = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l136) begin + _zz_banks_0_writeOr_value_valid_1 = (io_writes_0_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_0_writeOr_value_valid_1 = 9'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136) begin + _zz_banks_0_writeOr_value_valid_2 = io_writes_0_cmd_payload_data[63 : 0]; + end else begin + _zz_banks_0_writeOr_value_valid_2 = 64'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136) begin + _zz_banks_0_writeOr_value_valid_3 = io_writes_0_cmd_payload_mask[7 : 0]; + end else begin + _zz_banks_0_writeOr_value_valid_3 = 8'h0; + end + end + + assign when_MemoryCore_l136_1 = (write_arbiter_0_doIt && (_zz_when_MemoryCore_l136_1[0 : 0] == 1'b0)); + always @(*) begin + if(when_MemoryCore_l136_1) begin + _zz_banks_1_writeOr_value_valid = 1'b1; + end else begin + _zz_banks_1_writeOr_value_valid = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_1) begin + _zz_banks_1_writeOr_value_valid_1 = (io_writes_0_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_1_writeOr_value_valid_1 = 9'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_1) begin + _zz_banks_1_writeOr_value_valid_2 = io_writes_0_cmd_payload_data[63 : 0]; + end else begin + _zz_banks_1_writeOr_value_valid_2 = 64'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_1) begin + _zz_banks_1_writeOr_value_valid_3 = io_writes_0_cmd_payload_mask[7 : 0]; + end else begin + _zz_banks_1_writeOr_value_valid_3 = 8'h0; + end + end + + assign io_writes_0_cmd_ready = write_arbiter_0_doIt; + assign io_writes_0_rsp_valid = write_arbiter_0_doIt_regNext; + assign io_writes_0_rsp_payload_context = io_writes_0_cmd_payload_context_regNext; + assign write_arbiter_1_losedAgainst = (write_nodes_1_0_conflict && (! write_nodes_1_0_priority)); + always @(*) begin + write_arbiter_1_doIt = (io_writes_1_cmd_valid && (write_arbiter_1_losedAgainst == 1'b0)); + if(when_MemoryCore_l239) begin + write_arbiter_1_doIt = 1'b0; + end + end + + assign when_MemoryCore_l136_2 = (write_arbiter_1_doIt && 1'b1); + always @(*) begin + if(when_MemoryCore_l136_2) begin + _zz_banks_0_writeOr_value_valid_4 = 1'b1; + end else begin + _zz_banks_0_writeOr_value_valid_4 = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_2) begin + _zz_banks_0_writeOr_value_valid_5 = (io_writes_1_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_0_writeOr_value_valid_5 = 9'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_2) begin + _zz_banks_0_writeOr_value_valid_6 = io_writes_1_cmd_payload_data[63 : 0]; + end else begin + _zz_banks_0_writeOr_value_valid_6 = 64'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_2) begin + _zz_banks_0_writeOr_value_valid_7 = io_writes_1_cmd_payload_mask[7 : 0]; + end else begin + _zz_banks_0_writeOr_value_valid_7 = 8'h0; + end + end + + assign when_MemoryCore_l136_3 = (write_arbiter_1_doIt && 1'b1); + always @(*) begin + if(when_MemoryCore_l136_3) begin + _zz_banks_1_writeOr_value_valid_4 = 1'b1; + end else begin + _zz_banks_1_writeOr_value_valid_4 = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_3) begin + _zz_banks_1_writeOr_value_valid_5 = (io_writes_1_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_1_writeOr_value_valid_5 = 9'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_3) begin + _zz_banks_1_writeOr_value_valid_6 = io_writes_1_cmd_payload_data[127 : 64]; + end else begin + _zz_banks_1_writeOr_value_valid_6 = 64'h0; + end + end + + always @(*) begin + if(when_MemoryCore_l136_3) begin + _zz_banks_1_writeOr_value_valid_7 = io_writes_1_cmd_payload_mask[15 : 8]; + end else begin + _zz_banks_1_writeOr_value_valid_7 = 8'h0; + end + end + + assign io_writes_1_cmd_ready = write_arbiter_1_doIt; + assign io_writes_1_rsp_valid = write_arbiter_1_doIt_regNext; + assign io_writes_1_rsp_payload_context = io_writes_1_cmd_payload_context_regNext; + assign read_ports_0_buffer_groupSel = read_ports_0_buffer_s1_payload_address[0 : 0]; + assign read_ports_0_buffer_bufferIn_valid = read_ports_0_buffer_s1_valid; + assign read_ports_0_buffer_bufferIn_payload_context = read_ports_0_buffer_s1_payload_context; + assign read_ports_0_buffer_bufferIn_payload_data = _zz_read_ports_0_buffer_bufferIn_payload_data; + assign read_ports_0_buffer_bufferIn_payload_mask = _zz_read_ports_0_buffer_bufferIn_payload_mask; + assign read_ports_0_buffer_bufferIn_ready = read_ports_0_buffer_bufferIn_rValidN; + assign read_ports_0_buffer_bufferOut_valid = (read_ports_0_buffer_bufferIn_valid || (! read_ports_0_buffer_bufferIn_rValidN)); + assign read_ports_0_buffer_bufferOut_payload_data = (read_ports_0_buffer_bufferIn_rValidN ? read_ports_0_buffer_bufferIn_payload_data : read_ports_0_buffer_bufferIn_rData_data); + assign read_ports_0_buffer_bufferOut_payload_mask = (read_ports_0_buffer_bufferIn_rValidN ? read_ports_0_buffer_bufferIn_payload_mask : read_ports_0_buffer_bufferIn_rData_mask); + assign read_ports_0_buffer_bufferOut_payload_context = (read_ports_0_buffer_bufferIn_rValidN ? read_ports_0_buffer_bufferIn_payload_context : read_ports_0_buffer_bufferIn_rData_context); + assign io_reads_0_rsp_valid = read_ports_0_buffer_bufferOut_valid; + assign read_ports_0_buffer_bufferOut_ready = io_reads_0_rsp_ready; + assign io_reads_0_rsp_payload_data = read_ports_0_buffer_bufferOut_payload_data; + assign io_reads_0_rsp_payload_mask = read_ports_0_buffer_bufferOut_payload_mask; + assign io_reads_0_rsp_payload_context = read_ports_0_buffer_bufferOut_payload_context; + assign read_ports_0_buffer_full = (read_ports_0_buffer_bufferOut_valid && (! read_ports_0_buffer_bufferOut_ready)); + assign _zz_io_reads_0_cmd_ready = (! read_ports_0_buffer_full); + assign read_ports_0_cmd_valid = (io_reads_0_cmd_valid && _zz_io_reads_0_cmd_ready); + assign io_reads_0_cmd_ready = (read_ports_0_cmd_ready && _zz_io_reads_0_cmd_ready); + assign read_ports_0_cmd_payload_address = io_reads_0_cmd_payload_address; + assign read_ports_0_cmd_payload_priority = io_reads_0_cmd_payload_priority; + assign read_ports_0_cmd_payload_context = io_reads_0_cmd_payload_context; + assign read_ports_1_buffer_bufferIn_valid = read_ports_1_buffer_s1_valid; + assign read_ports_1_buffer_bufferIn_payload_context = read_ports_1_buffer_s1_payload_context; + assign read_ports_1_buffer_bufferIn_payload_data = {banks_1_read_rsp_data,banks_0_read_rsp_data}; + assign read_ports_1_buffer_bufferIn_payload_mask = {banks_1_read_rsp_mask,banks_0_read_rsp_mask}; + assign read_ports_1_buffer_bufferIn_ready = read_ports_1_buffer_bufferIn_rValidN; + assign read_ports_1_buffer_bufferOut_valid = (read_ports_1_buffer_bufferIn_valid || (! read_ports_1_buffer_bufferIn_rValidN)); + assign read_ports_1_buffer_bufferOut_payload_data = (read_ports_1_buffer_bufferIn_rValidN ? read_ports_1_buffer_bufferIn_payload_data : read_ports_1_buffer_bufferIn_rData_data); + assign read_ports_1_buffer_bufferOut_payload_mask = (read_ports_1_buffer_bufferIn_rValidN ? read_ports_1_buffer_bufferIn_payload_mask : read_ports_1_buffer_bufferIn_rData_mask); + assign read_ports_1_buffer_bufferOut_payload_context = (read_ports_1_buffer_bufferIn_rValidN ? read_ports_1_buffer_bufferIn_payload_context : read_ports_1_buffer_bufferIn_rData_context); + assign io_reads_1_rsp_valid = read_ports_1_buffer_bufferOut_valid; + assign read_ports_1_buffer_bufferOut_ready = io_reads_1_rsp_ready; + assign io_reads_1_rsp_payload_data = read_ports_1_buffer_bufferOut_payload_data; + assign io_reads_1_rsp_payload_mask = read_ports_1_buffer_bufferOut_payload_mask; + assign io_reads_1_rsp_payload_context = read_ports_1_buffer_bufferOut_payload_context; + assign read_ports_1_buffer_full = (read_ports_1_buffer_bufferOut_valid && (! read_ports_1_buffer_bufferOut_ready)); + assign _zz_io_reads_1_cmd_ready = (! read_ports_1_buffer_full); + assign read_ports_1_cmd_valid = (io_reads_1_cmd_valid && _zz_io_reads_1_cmd_ready); + assign io_reads_1_cmd_ready = (read_ports_1_cmd_ready && _zz_io_reads_1_cmd_ready); + assign read_ports_1_cmd_payload_address = io_reads_1_cmd_payload_address; + assign read_ports_1_cmd_payload_context = io_reads_1_cmd_payload_context; + assign read_nodes_0_1_priority = 1'b0; + assign read_nodes_1_0_priority = 1'b1; + assign read_nodes_0_1_conflict = ((read_ports_0_cmd_valid && read_ports_1_cmd_valid) && (((read_ports_0_cmd_payload_address ^ io_reads_1_cmd_payload_address) & 10'h0) == 10'h0)); + assign read_nodes_1_0_conflict = read_nodes_0_1_conflict; + assign read_arbiter_0_losedAgainst = (read_nodes_0_1_conflict && (! read_nodes_0_1_priority)); + assign read_arbiter_0_doIt = (read_ports_0_cmd_valid && (read_arbiter_0_losedAgainst == 1'b0)); + assign when_MemoryCore_l221 = (read_arbiter_0_doIt && (_zz_when_MemoryCore_l221[0 : 0] == 1'b0)); + always @(*) begin + if(when_MemoryCore_l221) begin + _zz_banks_0_readOr_value_valid = 1'b1; + end else begin + _zz_banks_0_readOr_value_valid = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l221) begin + _zz_banks_0_readOr_value_valid_1 = (read_ports_0_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_0_readOr_value_valid_1 = 9'h0; + end + end + + assign when_MemoryCore_l221_1 = (read_arbiter_0_doIt && (_zz_when_MemoryCore_l221_1[0 : 0] == 1'b0)); + always @(*) begin + if(when_MemoryCore_l221_1) begin + _zz_banks_1_readOr_value_valid = 1'b1; + end else begin + _zz_banks_1_readOr_value_valid = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l221_1) begin + _zz_banks_1_readOr_value_valid_1 = (read_ports_0_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_1_readOr_value_valid_1 = 9'h0; + end + end + + assign read_ports_0_cmd_ready = read_arbiter_0_doIt; + assign read_ports_0_buffer_s0_valid = read_arbiter_0_doIt; + assign read_ports_0_buffer_s0_payload_context = read_ports_0_cmd_payload_context; + assign read_ports_0_buffer_s0_payload_address = read_ports_0_cmd_payload_address; + assign read_arbiter_1_losedAgainst = (read_nodes_1_0_conflict && (! read_nodes_1_0_priority)); + assign read_arbiter_1_doIt = (read_ports_1_cmd_valid && (read_arbiter_1_losedAgainst == 1'b0)); + assign when_MemoryCore_l221_2 = (read_arbiter_1_doIt && 1'b1); + always @(*) begin + if(when_MemoryCore_l221_2) begin + _zz_banks_0_readOr_value_valid_2 = 1'b1; + end else begin + _zz_banks_0_readOr_value_valid_2 = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l221_2) begin + _zz_banks_0_readOr_value_valid_3 = (read_ports_1_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_0_readOr_value_valid_3 = 9'h0; + end + end + + assign when_MemoryCore_l221_3 = (read_arbiter_1_doIt && 1'b1); + always @(*) begin + if(when_MemoryCore_l221_3) begin + _zz_banks_1_readOr_value_valid_2 = 1'b1; + end else begin + _zz_banks_1_readOr_value_valid_2 = 1'b0; + end + end + + always @(*) begin + if(when_MemoryCore_l221_3) begin + _zz_banks_1_readOr_value_valid_3 = (read_ports_1_cmd_payload_address >>> 1'd1); + end else begin + _zz_banks_1_readOr_value_valid_3 = 9'h0; + end + end + + assign read_ports_1_cmd_ready = read_arbiter_1_doIt; + assign read_ports_1_buffer_s0_valid = read_arbiter_1_doIt; + assign read_ports_1_buffer_s0_payload_context = read_ports_1_cmd_payload_context; + assign read_ports_1_buffer_s0_payload_address = read_ports_1_cmd_payload_address; + assign initialiser_done = initialiser_counter[9]; + assign when_MemoryCore_l239 = (! initialiser_done); + assign _zz_banks_0_write_payload_data_data = 72'h0; + assign _zz_banks_1_write_payload_data_data = 72'h0; + assign _zz_banks_0_writeOr_value_valid_8 = ({{{_zz_banks_0_writeOr_value_valid_3,_zz_banks_0_writeOr_value_valid_2},_zz_banks_0_writeOr_value_valid_1},_zz_banks_0_writeOr_value_valid} | {{{_zz_banks_0_writeOr_value_valid_7,_zz_banks_0_writeOr_value_valid_6},_zz_banks_0_writeOr_value_valid_5},_zz_banks_0_writeOr_value_valid_4}); + assign banks_0_writeOr_value_valid = _zz_banks_0_writeOr_value_valid_8[0]; + assign _zz_banks_0_writeOr_value_payload_address = _zz_banks_0_writeOr_value_valid_8[81 : 1]; + assign banks_0_writeOr_value_payload_address = _zz_banks_0_writeOr_value_payload_address[8 : 0]; + assign _zz_banks_0_writeOr_value_payload_data_data = _zz_banks_0_writeOr_value_payload_address[80 : 9]; + assign banks_0_writeOr_value_payload_data_data = _zz_banks_0_writeOr_value_payload_data_data[63 : 0]; + assign banks_0_writeOr_value_payload_data_mask = _zz_banks_0_writeOr_value_payload_data_data[71 : 64]; + assign _zz_banks_0_readOr_value_valid_4 = ({_zz_banks_0_readOr_value_valid_1,_zz_banks_0_readOr_value_valid} | {_zz_banks_0_readOr_value_valid_3,_zz_banks_0_readOr_value_valid_2}); + assign banks_0_readOr_value_valid = _zz_banks_0_readOr_value_valid_4[0]; + assign banks_0_readOr_value_payload = _zz_banks_0_readOr_value_valid_4[9 : 1]; + assign _zz_banks_1_writeOr_value_valid_8 = ({{{_zz_banks_1_writeOr_value_valid_3,_zz_banks_1_writeOr_value_valid_2},_zz_banks_1_writeOr_value_valid_1},_zz_banks_1_writeOr_value_valid} | {{{_zz_banks_1_writeOr_value_valid_7,_zz_banks_1_writeOr_value_valid_6},_zz_banks_1_writeOr_value_valid_5},_zz_banks_1_writeOr_value_valid_4}); + assign banks_1_writeOr_value_valid = _zz_banks_1_writeOr_value_valid_8[0]; + assign _zz_banks_1_writeOr_value_payload_address = _zz_banks_1_writeOr_value_valid_8[81 : 1]; + assign banks_1_writeOr_value_payload_address = _zz_banks_1_writeOr_value_payload_address[8 : 0]; + assign _zz_banks_1_writeOr_value_payload_data_data = _zz_banks_1_writeOr_value_payload_address[80 : 9]; + assign banks_1_writeOr_value_payload_data_data = _zz_banks_1_writeOr_value_payload_data_data[63 : 0]; + assign banks_1_writeOr_value_payload_data_mask = _zz_banks_1_writeOr_value_payload_data_data[71 : 64]; + assign _zz_banks_1_readOr_value_valid_4 = ({_zz_banks_1_readOr_value_valid_1,_zz_banks_1_readOr_value_valid} | {_zz_banks_1_readOr_value_valid_3,_zz_banks_1_readOr_value_valid_2}); + assign banks_1_readOr_value_valid = _zz_banks_1_readOr_value_valid_4[0]; + assign banks_1_readOr_value_payload = _zz_banks_1_readOr_value_valid_4[9 : 1]; + always @(posedge clk) begin + if(io_writes_0_cmd_valid) begin + write_ports_0_priority_value <= (write_ports_0_priority_value + _zz_write_ports_0_priority_value); + if(io_writes_0_cmd_ready) begin + write_ports_0_priority_value <= 4'b0000; + end + end + io_writes_0_cmd_payload_context_regNext <= io_writes_0_cmd_payload_context; + io_writes_1_cmd_payload_context_regNext <= io_writes_1_cmd_payload_context; + read_ports_0_buffer_s1_payload_context <= read_ports_0_buffer_s0_payload_context; + read_ports_0_buffer_s1_payload_address <= read_ports_0_buffer_s0_payload_address; + if(read_ports_0_buffer_bufferIn_ready) begin + read_ports_0_buffer_bufferIn_rData_data <= read_ports_0_buffer_bufferIn_payload_data; + read_ports_0_buffer_bufferIn_rData_mask <= read_ports_0_buffer_bufferIn_payload_mask; + read_ports_0_buffer_bufferIn_rData_context <= read_ports_0_buffer_bufferIn_payload_context; + end + if(read_ports_0_cmd_valid) begin + read_ports_0_priority_value <= (read_ports_0_priority_value + _zz_read_ports_0_priority_value); + if(read_ports_0_cmd_ready) begin + read_ports_0_priority_value <= 4'b0000; + end + end + read_ports_1_buffer_s1_payload_context <= read_ports_1_buffer_s0_payload_context; + read_ports_1_buffer_s1_payload_address <= read_ports_1_buffer_s0_payload_address; + if(read_ports_1_buffer_bufferIn_ready) begin + read_ports_1_buffer_bufferIn_rData_data <= read_ports_1_buffer_bufferIn_payload_data; + read_ports_1_buffer_bufferIn_rData_mask <= read_ports_1_buffer_bufferIn_payload_mask; + read_ports_1_buffer_bufferIn_rData_context <= read_ports_1_buffer_bufferIn_payload_context; + end + end + + always @(posedge clk) begin + if(reset) begin + write_arbiter_0_doIt_regNext <= 1'b0; + write_arbiter_1_doIt_regNext <= 1'b0; + read_ports_0_buffer_s1_valid <= 1'b0; + read_ports_0_buffer_bufferIn_rValidN <= 1'b1; + read_ports_1_buffer_s1_valid <= 1'b0; + read_ports_1_buffer_bufferIn_rValidN <= 1'b1; + initialiser_counter <= 10'h0; + end else begin + write_arbiter_0_doIt_regNext <= write_arbiter_0_doIt; + write_arbiter_1_doIt_regNext <= write_arbiter_1_doIt; + read_ports_0_buffer_s1_valid <= read_ports_0_buffer_s0_valid; + if(read_ports_0_buffer_bufferIn_valid) begin + read_ports_0_buffer_bufferIn_rValidN <= 1'b0; + end + if(read_ports_0_buffer_bufferOut_ready) begin + read_ports_0_buffer_bufferIn_rValidN <= 1'b1; + end + read_ports_1_buffer_s1_valid <= read_ports_1_buffer_s0_valid; + if(read_ports_1_buffer_bufferIn_valid) begin + read_ports_1_buffer_bufferIn_rValidN <= 1'b0; + end + if(read_ports_1_buffer_bufferOut_ready) begin + read_ports_1_buffer_bufferIn_rValidN <= 1'b1; + end + if(when_MemoryCore_l239) begin + initialiser_counter <= (initialiser_counter + 10'h001); + end + end + end + + +endmodule + +module EfxDMA_StreamFifo_1 ( + input wire io_push_valid, + output wire io_push_ready, + input wire [13:0] io_push_payload_context, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [13:0] io_pop_payload_context, + input wire io_flush, + output wire [2:0] io_occupancy, + output wire [2:0] io_availability, + input wire clk, + input wire reset +); + + reg [13:0] logic_ram_spinal_port1; + wire [2:0] _zz_logic_ptr_notPow2_counter; + wire [2:0] _zz_logic_ptr_notPow2_counter_1; + wire [0:0] _zz_logic_ptr_notPow2_counter_2; + wire [2:0] _zz_logic_ptr_notPow2_counter_3; + wire [0:0] _zz_logic_ptr_notPow2_counter_4; + reg _zz_1; + wire logic_ptr_doPush; + wire logic_ptr_doPop; + wire logic_ptr_full; + wire logic_ptr_empty; + reg [2:0] logic_ptr_push; + reg [2:0] logic_ptr_pop; + wire [2:0] logic_ptr_occupancy; + wire [2:0] logic_ptr_popOnIo; + wire when_Stream_l1248; + reg logic_ptr_wentUp; + wire when_Stream_l1283; + wire when_Stream_l1287; + reg [2:0] logic_ptr_notPow2_counter; + wire io_push_fire; + wire io_pop_fire; + wire logic_push_onRam_write_valid; + wire [2:0] logic_push_onRam_write_payload_address; + wire [13:0] logic_push_onRam_write_payload_data_context; + wire logic_pop_addressGen_valid; + reg logic_pop_addressGen_ready; + wire [2:0] logic_pop_addressGen_payload; + wire logic_pop_addressGen_fire; + wire logic_pop_sync_readArbitation_valid; + wire logic_pop_sync_readArbitation_ready; + wire [2:0] logic_pop_sync_readArbitation_payload; + reg logic_pop_addressGen_rValid; + reg [2:0] logic_pop_addressGen_rData; + wire when_Stream_l375; + wire logic_pop_sync_readPort_cmd_valid; + wire [2:0] logic_pop_sync_readPort_cmd_payload; + wire [13:0] logic_pop_sync_readPort_rsp_context; + wire logic_pop_sync_readArbitation_translated_valid; + wire logic_pop_sync_readArbitation_translated_ready; + wire [13:0] logic_pop_sync_readArbitation_translated_payload_context; + wire logic_pop_sync_readArbitation_fire; + reg [2:0] logic_pop_sync_popReg; + reg [13:0] logic_ram [0:6]; + + assign _zz_logic_ptr_notPow2_counter = (logic_ptr_notPow2_counter + _zz_logic_ptr_notPow2_counter_1); + assign _zz_logic_ptr_notPow2_counter_2 = io_push_fire; + assign _zz_logic_ptr_notPow2_counter_1 = {2'd0, _zz_logic_ptr_notPow2_counter_2}; + assign _zz_logic_ptr_notPow2_counter_4 = io_pop_fire; + assign _zz_logic_ptr_notPow2_counter_3 = {2'd0, _zz_logic_ptr_notPow2_counter_4}; + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data_context; + end + end + + always @(posedge clk) begin + if(logic_pop_sync_readPort_cmd_valid) begin + logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_push_onRam_write_valid) begin + _zz_1 = 1'b1; + end + end + + assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); + assign logic_ptr_full = ((logic_ptr_push == logic_ptr_popOnIo) && logic_ptr_wentUp); + assign logic_ptr_empty = ((logic_ptr_push == logic_ptr_pop) && (! logic_ptr_wentUp)); + assign when_Stream_l1283 = (logic_ptr_push == 3'b110); + assign when_Stream_l1287 = (logic_ptr_pop == 3'b110); + assign io_push_fire = (io_push_valid && io_push_ready); + assign io_pop_fire = (io_pop_valid && io_pop_ready); + assign logic_ptr_occupancy = logic_ptr_notPow2_counter; + assign io_push_ready = (! logic_ptr_full); + assign logic_ptr_doPush = io_push_fire; + assign logic_push_onRam_write_valid = io_push_fire; + assign logic_push_onRam_write_payload_address = logic_ptr_push; + assign logic_push_onRam_write_payload_data_context = io_push_payload_context; + assign logic_pop_addressGen_valid = (! logic_ptr_empty); + assign logic_pop_addressGen_payload = logic_ptr_pop; + assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); + assign logic_ptr_doPop = logic_pop_addressGen_fire; + always @(*) begin + logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; + if(when_Stream_l375) begin + logic_pop_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); + assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; + assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; + assign logic_pop_sync_readPort_rsp_context = logic_ram_spinal_port1[13 : 0]; + assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; + assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; + assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; + assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; + assign logic_pop_sync_readArbitation_translated_payload_context = logic_pop_sync_readPort_rsp_context; + assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; + assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_context = logic_pop_sync_readArbitation_translated_payload_context; + assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); + assign logic_ptr_popOnIo = logic_pop_sync_popReg; + assign io_occupancy = logic_ptr_occupancy; + assign io_availability = (3'b111 - logic_ptr_occupancy); + always @(posedge clk) begin + if(reset) begin + logic_ptr_push <= 3'b000; + logic_ptr_pop <= 3'b000; + logic_ptr_wentUp <= 1'b0; + logic_ptr_notPow2_counter <= 3'b000; + logic_pop_addressGen_rValid <= 1'b0; + logic_pop_sync_popReg <= 3'b000; + end else begin + if(when_Stream_l1248) begin + logic_ptr_wentUp <= logic_ptr_doPush; + end + if(io_flush) begin + logic_ptr_wentUp <= 1'b0; + end + if(logic_ptr_doPush) begin + logic_ptr_push <= (logic_ptr_push + 3'b001); + if(when_Stream_l1283) begin + logic_ptr_push <= 3'b000; + end + end + if(logic_ptr_doPop) begin + logic_ptr_pop <= (logic_ptr_pop + 3'b001); + if(when_Stream_l1287) begin + logic_ptr_pop <= 3'b000; + end + end + if(io_flush) begin + logic_ptr_push <= 3'b000; + logic_ptr_pop <= 3'b000; + end + logic_ptr_notPow2_counter <= (_zz_logic_ptr_notPow2_counter - _zz_logic_ptr_notPow2_counter_3); + if(io_flush) begin + logic_ptr_notPow2_counter <= 3'b000; + end + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; + end + if(io_flush) begin + logic_pop_addressGen_rValid <= 1'b0; + end + if(logic_pop_sync_readArbitation_fire) begin + logic_pop_sync_popReg <= logic_ptr_pop; + end + if(io_flush) begin + logic_pop_sync_popReg <= 3'b000; + end + end + end + + always @(posedge clk) begin + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rData <= logic_pop_addressGen_payload; + end + end + + +endmodule + +module EfxDMA_StreamFifo ( + input wire io_push_valid, + output wire io_push_ready, + input wire [21:0] io_push_payload_context, + output wire io_pop_valid, + input wire io_pop_ready, + output wire [21:0] io_pop_payload_context, + input wire io_flush, + output wire [2:0] io_occupancy, + output wire [2:0] io_availability, + input wire clk, + input wire reset +); + + reg [21:0] logic_ram_spinal_port1; + wire [2:0] _zz_logic_ptr_notPow2_counter; + wire [2:0] _zz_logic_ptr_notPow2_counter_1; + wire [0:0] _zz_logic_ptr_notPow2_counter_2; + wire [2:0] _zz_logic_ptr_notPow2_counter_3; + wire [0:0] _zz_logic_ptr_notPow2_counter_4; + reg _zz_1; + wire logic_ptr_doPush; + wire logic_ptr_doPop; + wire logic_ptr_full; + wire logic_ptr_empty; + reg [2:0] logic_ptr_push; + reg [2:0] logic_ptr_pop; + wire [2:0] logic_ptr_occupancy; + wire [2:0] logic_ptr_popOnIo; + wire when_Stream_l1248; + reg logic_ptr_wentUp; + wire when_Stream_l1283; + wire when_Stream_l1287; + reg [2:0] logic_ptr_notPow2_counter; + wire io_push_fire; + wire io_pop_fire; + wire logic_push_onRam_write_valid; + wire [2:0] logic_push_onRam_write_payload_address; + wire [21:0] logic_push_onRam_write_payload_data_context; + wire logic_pop_addressGen_valid; + reg logic_pop_addressGen_ready; + wire [2:0] logic_pop_addressGen_payload; + wire logic_pop_addressGen_fire; + wire logic_pop_sync_readArbitation_valid; + wire logic_pop_sync_readArbitation_ready; + wire [2:0] logic_pop_sync_readArbitation_payload; + reg logic_pop_addressGen_rValid; + reg [2:0] logic_pop_addressGen_rData; + wire when_Stream_l375; + wire logic_pop_sync_readPort_cmd_valid; + wire [2:0] logic_pop_sync_readPort_cmd_payload; + wire [21:0] logic_pop_sync_readPort_rsp_context; + wire logic_pop_sync_readArbitation_translated_valid; + wire logic_pop_sync_readArbitation_translated_ready; + wire [21:0] logic_pop_sync_readArbitation_translated_payload_context; + wire logic_pop_sync_readArbitation_fire; + reg [2:0] logic_pop_sync_popReg; + reg [21:0] logic_ram [0:6]; + + assign _zz_logic_ptr_notPow2_counter = (logic_ptr_notPow2_counter + _zz_logic_ptr_notPow2_counter_1); + assign _zz_logic_ptr_notPow2_counter_2 = io_push_fire; + assign _zz_logic_ptr_notPow2_counter_1 = {2'd0, _zz_logic_ptr_notPow2_counter_2}; + assign _zz_logic_ptr_notPow2_counter_4 = io_pop_fire; + assign _zz_logic_ptr_notPow2_counter_3 = {2'd0, _zz_logic_ptr_notPow2_counter_4}; + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_push_onRam_write_payload_address] <= logic_push_onRam_write_payload_data_context; + end + end + + always @(posedge clk) begin + if(logic_pop_sync_readPort_cmd_valid) begin + logic_ram_spinal_port1 <= logic_ram[logic_pop_sync_readPort_cmd_payload]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_push_onRam_write_valid) begin + _zz_1 = 1'b1; + end + end + + assign when_Stream_l1248 = (logic_ptr_doPush != logic_ptr_doPop); + assign logic_ptr_full = ((logic_ptr_push == logic_ptr_popOnIo) && logic_ptr_wentUp); + assign logic_ptr_empty = ((logic_ptr_push == logic_ptr_pop) && (! logic_ptr_wentUp)); + assign when_Stream_l1283 = (logic_ptr_push == 3'b110); + assign when_Stream_l1287 = (logic_ptr_pop == 3'b110); + assign io_push_fire = (io_push_valid && io_push_ready); + assign io_pop_fire = (io_pop_valid && io_pop_ready); + assign logic_ptr_occupancy = logic_ptr_notPow2_counter; + assign io_push_ready = (! logic_ptr_full); + assign logic_ptr_doPush = io_push_fire; + assign logic_push_onRam_write_valid = io_push_fire; + assign logic_push_onRam_write_payload_address = logic_ptr_push; + assign logic_push_onRam_write_payload_data_context = io_push_payload_context; + assign logic_pop_addressGen_valid = (! logic_ptr_empty); + assign logic_pop_addressGen_payload = logic_ptr_pop; + assign logic_pop_addressGen_fire = (logic_pop_addressGen_valid && logic_pop_addressGen_ready); + assign logic_ptr_doPop = logic_pop_addressGen_fire; + always @(*) begin + logic_pop_addressGen_ready = logic_pop_sync_readArbitation_ready; + if(when_Stream_l375) begin + logic_pop_addressGen_ready = 1'b1; + end + end + + assign when_Stream_l375 = (! logic_pop_sync_readArbitation_valid); + assign logic_pop_sync_readArbitation_valid = logic_pop_addressGen_rValid; + assign logic_pop_sync_readArbitation_payload = logic_pop_addressGen_rData; + assign logic_pop_sync_readPort_rsp_context = logic_ram_spinal_port1[21 : 0]; + assign logic_pop_sync_readPort_cmd_valid = logic_pop_addressGen_fire; + assign logic_pop_sync_readPort_cmd_payload = logic_pop_addressGen_payload; + assign logic_pop_sync_readArbitation_translated_valid = logic_pop_sync_readArbitation_valid; + assign logic_pop_sync_readArbitation_ready = logic_pop_sync_readArbitation_translated_ready; + assign logic_pop_sync_readArbitation_translated_payload_context = logic_pop_sync_readPort_rsp_context; + assign io_pop_valid = logic_pop_sync_readArbitation_translated_valid; + assign logic_pop_sync_readArbitation_translated_ready = io_pop_ready; + assign io_pop_payload_context = logic_pop_sync_readArbitation_translated_payload_context; + assign logic_pop_sync_readArbitation_fire = (logic_pop_sync_readArbitation_valid && logic_pop_sync_readArbitation_ready); + assign logic_ptr_popOnIo = logic_pop_sync_popReg; + assign io_occupancy = logic_ptr_occupancy; + assign io_availability = (3'b111 - logic_ptr_occupancy); + always @(posedge clk) begin + if(reset) begin + logic_ptr_push <= 3'b000; + logic_ptr_pop <= 3'b000; + logic_ptr_wentUp <= 1'b0; + logic_ptr_notPow2_counter <= 3'b000; + logic_pop_addressGen_rValid <= 1'b0; + logic_pop_sync_popReg <= 3'b000; + end else begin + if(when_Stream_l1248) begin + logic_ptr_wentUp <= logic_ptr_doPush; + end + if(io_flush) begin + logic_ptr_wentUp <= 1'b0; + end + if(logic_ptr_doPush) begin + logic_ptr_push <= (logic_ptr_push + 3'b001); + if(when_Stream_l1283) begin + logic_ptr_push <= 3'b000; + end + end + if(logic_ptr_doPop) begin + logic_ptr_pop <= (logic_ptr_pop + 3'b001); + if(when_Stream_l1287) begin + logic_ptr_pop <= 3'b000; + end + end + if(io_flush) begin + logic_ptr_push <= 3'b000; + logic_ptr_pop <= 3'b000; + end + logic_ptr_notPow2_counter <= (_zz_logic_ptr_notPow2_counter - _zz_logic_ptr_notPow2_counter_3); + if(io_flush) begin + logic_ptr_notPow2_counter <= 3'b000; + end + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rValid <= logic_pop_addressGen_valid; + end + if(io_flush) begin + logic_pop_addressGen_rValid <= 1'b0; + end + if(logic_pop_sync_readArbitation_fire) begin + logic_pop_sync_popReg <= logic_ptr_pop; + end + if(io_flush) begin + logic_pop_sync_popReg <= 3'b000; + end + end + end + + always @(posedge clk) begin + if(logic_pop_addressGen_ready) begin + logic_pop_addressGen_rData <= logic_pop_addressGen_payload; + end + end + + +endmodule + +module EfxDMA_BufferCC_1 ( + input wire io_dataIn, + output wire io_dataOut, + input wire ctrl_clk, + input wire ctrl_reset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge ctrl_clk) begin + if(ctrl_reset) begin + buffers_0 <= 1'b0; + buffers_1 <= 1'b0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule + +module EfxDMA_BufferCC ( + input wire io_dataIn, + output wire io_dataOut, + input wire clk, + input wire reset +); + + (* async_reg = "true" *) reg buffers_0; + (* async_reg = "true" *) reg buffers_1; + + assign io_dataOut = buffers_1; + always @(posedge clk) begin + if(reset) begin + buffers_0 <= 1'b0; + buffers_1 <= 1'b0; + end else begin + buffers_0 <= io_dataIn; + buffers_1 <= buffers_0; + end + end + + +endmodule diff --git a/Ti375C529_devkit/ip/gDMA/source/dma_config.json b/Ti375C529_devkit/ip/gDMA/source/dma_config.json new file mode 100644 index 0000000..1229f91 --- /dev/null +++ b/Ti375C529_devkit/ip/gDMA/source/dma_config.json @@ -0,0 +1,71 @@ +{ + "name": "EfxDMA", + "efinix_ddr": false, + "with_sg_bus": false, + "with_ddr_write_queue": false, + "with_ddr_read_queue": false, + "ctrl": { + "asynchronous": true + }, + "buffer": { + "bank_count": 2, + "bank_width": 64, + "bank_words": 512 + }, + "read": { + "address_width": 32, + "data_width_external": 128, + "data_width_internal": 128 + }, + "write": { + "address_width": 32, + "data_width_external": 128, + "data_width_internal": 128 + }, + "channels": { + "c0": { + "progress_probe": true, + "direct_ctrl_capable": true, + "linked_list_capable": true, + "memory_to_memory": false, + "inputs": [ + "dat0_i" + ], + "half_completion_interrupt": false, + "self_restart_capable": false, + "bytes_per_burst": 1024, + "buffer_address": 0, + "buffer_size": 4096 + }, + "c1": { + "progress_probe": true, + "direct_ctrl_capable": true, + "linked_list_capable": true, + "memory_to_memory": false, + "outputs": [ + "dat1_o" + ], + "half_completion_interrupt": false, + "self_restart_capable": false, + "bytes_per_burst": 1024, + "buffer_address": 4096, + "buffer_size": 4096 + } + }, + "inputs": { + "dat0_i": { + "data_width": 8, + "tid_width": 0, + "tdest_width": 4, + "asynchronous": true + } + }, + "outputs": { + "dat1_o": { + "data_width": 8, + "tid_width": 0, + "tdest_width": 4, + "asynchronous": true + } + } +} \ No newline at end of file diff --git a/Ti375C529_devkit/ip/gSDHC/gSDHC.v b/Ti375C529_devkit/ip/gSDHC/gSDHC.v new file mode 100644 index 0000000..718f399 --- /dev/null +++ b/Ti375C529_devkit/ip/gSDHC/gSDHC.v @@ -0,0 +1,12571 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 6.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _5b3f2212c953407c83e1cf8c9cc77ea9 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module gSDHC +( + input sd_rst, + input sd_base_clk, + output sd_int, + input sd_cd_n, + input sd_wp, + input [9:0] s_axi_awaddr, + input s_axi_aclk, + output s_axi_awready, + input s_axi_awvalid, + input [31:0] s_axi_wdata, + output s_axi_wready, + input s_axi_wvalid, + output [1:0] s_axi_bresp, + output s_axi_bvalid, + input [9:0] s_axi_araddr, + input s_axi_bready, + output s_axi_arready, + input s_axi_arvalid, + output [1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + output s_axi_rvalid, + input s_axi_rready, + output [31:0] m_axi_awaddr, + output m_axi_awvalid, + input m_axi_clk, + output [7:0] m_axi_awlen, + input m_axi_awready, + output [2:0] m_axi_awsize, + output [3:0] m_axi_awcache, + output [1:0] m_axi_awlock, + output [2:0] m_axi_awprot, + output m_axi_wlast, + output m_axi_wvalid, + input m_axi_wready, + input [1:0] m_axi_bresp, + input m_axi_bvalid, + output m_axi_bready, + output m_axi_arvalid, + output [31:0] m_axi_araddr, + output [7:0] m_axi_arlen, + output [2:0] m_axi_arsize, + output [1:0] m_axi_arburst, + output [2:0] m_axi_arprot, + output [1:0] m_axi_arlock, + output [3:0] m_axi_arcache, + input m_axi_arready, + input m_axi_rvalid, + input m_axi_rlast, + input [1:0] m_axi_rresp, + output m_axi_rready, + output sd_clk_hi, + output sd_clk_lo, + input sd_cmd_i, + output sd_cmd_o, + output sd_cmd_oe, + input [3:0] sd_dat_i, + output [3:0] sd_dat_o, + output sd_dat_oe, + output [1:0] m_axi_awburst, + output [127:0] m_axi_wdata, + output [15:0] m_axi_wstrb, + input [127:0] m_axi_rdata, + input [3:0] s_axi_wstrb +); +`IP_MODULE_NAME(sdhc) +#( + .DATA_BUFFER_DEPTH (512), + .ADMA_DATA_WIDTH (128) +) +u_sdhc +( + .sd_rst ( sd_rst ), + .sd_base_clk ( sd_base_clk ), + .sd_int ( sd_int ), + .sd_cd_n ( sd_cd_n ), + .sd_wp ( sd_wp ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_aclk ( s_axi_aclk ), + .s_axi_awready ( s_axi_awready ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_wready ( s_axi_wready ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_bready ( s_axi_bready ), + .s_axi_arready ( s_axi_arready ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rready ( s_axi_rready ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_clk ( m_axi_clk ), + .m_axi_awlen ( m_axi_awlen ), + .m_axi_awready ( m_axi_awready ), + .m_axi_awsize ( m_axi_awsize ), + .m_axi_awcache ( m_axi_awcache ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awprot ( m_axi_awprot ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wready ( m_axi_wready ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_bready ( m_axi_bready ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlen ( m_axi_arlen ), + .m_axi_arsize ( m_axi_arsize ), + .m_axi_arburst ( m_axi_arburst ), + .m_axi_arprot ( m_axi_arprot ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arcache ( m_axi_arcache ), + .m_axi_arready ( m_axi_arready ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_rready ( m_axi_rready ), + .sd_clk_hi ( sd_clk_hi ), + .sd_clk_lo ( sd_clk_lo ), + .sd_cmd_i ( sd_cmd_i ), + .sd_cmd_o ( sd_cmd_o ), + .sd_cmd_oe ( sd_cmd_oe ), + .sd_dat_i ( sd_dat_i ), + .sd_dat_o ( sd_dat_o ), + .sd_dat_oe ( sd_dat_oe ), + .m_axi_awburst ( m_axi_awburst ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_rdata ( m_axi_rdata ), + .s_axi_wstrb ( s_axi_wstrb ) +); +endmodule + +// Generator : SpinalHDL dev git head : 9cdee03b276638ef8e7a948b606bb7acc6e4c8d0 +// Component : Asic32To128UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 +// Git hash : cd16421fb7a4d44431a2445f9a92b82070ab9b8a + +`timescale 1ns/1ps + +module Asic32To128UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_aw_valid, + output io_input_aw_ready, + input [31:0] io_input_aw_payload_addr, + input [7:0] io_input_aw_payload_id, + input [3:0] io_input_aw_payload_region, + input [7:0] io_input_aw_payload_len, + input [2:0] io_input_aw_payload_size, + input [1:0] io_input_aw_payload_burst, + input [0:0] io_input_aw_payload_lock, + input [3:0] io_input_aw_payload_cache, + input [3:0] io_input_aw_payload_qos, + input [2:0] io_input_aw_payload_prot, + input io_input_w_valid, + output io_input_w_ready, + input [31:0] io_input_w_payload_data, + input [3:0] io_input_w_payload_strb, + input io_input_w_payload_last, + output io_input_b_valid, + input io_input_b_ready, + output [7:0] io_input_b_payload_id, + output [1:0] io_input_b_payload_resp, + input io_input_ar_valid, + output io_input_ar_ready, + input [31:0] io_input_ar_payload_addr, + input [7:0] io_input_ar_payload_id, + input [3:0] io_input_ar_payload_region, + input [7:0] io_input_ar_payload_len, + input [2:0] io_input_ar_payload_size, + input [1:0] io_input_ar_payload_burst, + input [0:0] io_input_ar_payload_lock, + input [3:0] io_input_ar_payload_cache, + input [3:0] io_input_ar_payload_qos, + input [2:0] io_input_ar_payload_prot, + output io_input_r_valid, + input io_input_r_ready, + output [31:0] io_input_r_payload_data, + output [7:0] io_input_r_payload_id, + output [1:0] io_input_r_payload_resp, + output io_input_r_payload_last, + output io_output_aw_valid, + input io_output_aw_ready, + output [31:0] io_output_aw_payload_addr, + output [7:0] io_output_aw_payload_id, + output [3:0] io_output_aw_payload_region, + output [7:0] io_output_aw_payload_len, + output [2:0] io_output_aw_payload_size, + output [1:0] io_output_aw_payload_burst, + output [0:0] io_output_aw_payload_lock, + output [3:0] io_output_aw_payload_cache, + output [3:0] io_output_aw_payload_qos, + output [2:0] io_output_aw_payload_prot, + output io_output_w_valid, + input io_output_w_ready, + output [127:0] io_output_w_payload_data, + output [15:0] io_output_w_payload_strb, + output io_output_w_payload_last, + input io_output_b_valid, + output io_output_b_ready, + input [7:0] io_output_b_payload_id, + input [1:0] io_output_b_payload_resp, + output io_output_ar_valid, + input io_output_ar_ready, + output [31:0] io_output_ar_payload_addr, + output [7:0] io_output_ar_payload_id, + output [3:0] io_output_ar_payload_region, + output [7:0] io_output_ar_payload_len, + output [2:0] io_output_ar_payload_size, + output [1:0] io_output_ar_payload_burst, + output [0:0] io_output_ar_payload_lock, + output [3:0] io_output_ar_payload_cache, + output [3:0] io_output_ar_payload_qos, + output [2:0] io_output_ar_payload_prot, + input io_output_r_valid, + output io_output_r_ready, + input [127:0] io_output_r_payload_data, + input [7:0] io_output_r_payload_id, + input [1:0] io_output_r_payload_resp, + input io_output_r_payload_last, + input clk, + input reset +); + + wire readOnly_io_input_ar_ready; + wire readOnly_io_input_r_valid; + wire [31:0] readOnly_io_input_r_payload_data; + wire [7:0] readOnly_io_input_r_payload_id; + wire [1:0] readOnly_io_input_r_payload_resp; + wire readOnly_io_input_r_payload_last; + wire readOnly_io_output_ar_valid; + wire [31:0] readOnly_io_output_ar_payload_addr; + wire [7:0] readOnly_io_output_ar_payload_id; + wire [3:0] readOnly_io_output_ar_payload_region; + wire [7:0] readOnly_io_output_ar_payload_len; + wire [2:0] readOnly_io_output_ar_payload_size; + wire [1:0] readOnly_io_output_ar_payload_burst; + wire [0:0] readOnly_io_output_ar_payload_lock; + wire [3:0] readOnly_io_output_ar_payload_cache; + wire [3:0] readOnly_io_output_ar_payload_qos; + wire [2:0] readOnly_io_output_ar_payload_prot; + wire readOnly_io_output_r_ready; + wire writeOnly_io_input_aw_ready; + wire writeOnly_io_input_w_ready; + wire writeOnly_io_input_b_valid; + wire [7:0] writeOnly_io_input_b_payload_id; + wire [1:0] writeOnly_io_input_b_payload_resp; + wire writeOnly_io_output_aw_valid; + wire [31:0] writeOnly_io_output_aw_payload_addr; + wire [7:0] writeOnly_io_output_aw_payload_id; + wire [3:0] writeOnly_io_output_aw_payload_region; + wire [7:0] writeOnly_io_output_aw_payload_len; + wire [2:0] writeOnly_io_output_aw_payload_size; + wire [1:0] writeOnly_io_output_aw_payload_burst; + wire [0:0] writeOnly_io_output_aw_payload_lock; + wire [3:0] writeOnly_io_output_aw_payload_cache; + wire [3:0] writeOnly_io_output_aw_payload_qos; + wire [2:0] writeOnly_io_output_aw_payload_prot; + wire writeOnly_io_output_w_valid; + wire [127:0] writeOnly_io_output_w_payload_data; + wire [15:0] writeOnly_io_output_w_payload_strb; + wire writeOnly_io_output_w_payload_last; + wire writeOnly_io_output_b_ready; + + Asic32To128UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 readOnly ( + .io_input_ar_valid (io_input_ar_valid ), //i + .io_input_ar_ready (readOnly_io_input_ar_ready ), //o + .io_input_ar_payload_addr (io_input_ar_payload_addr[31:0] ), //i + .io_input_ar_payload_id (io_input_ar_payload_id[7:0] ), //i + .io_input_ar_payload_region (io_input_ar_payload_region[3:0] ), //i + .io_input_ar_payload_len (io_input_ar_payload_len[7:0] ), //i + .io_input_ar_payload_size (io_input_ar_payload_size[2:0] ), //i + .io_input_ar_payload_burst (io_input_ar_payload_burst[1:0] ), //i + .io_input_ar_payload_lock (io_input_ar_payload_lock ), //i + .io_input_ar_payload_cache (io_input_ar_payload_cache[3:0] ), //i + .io_input_ar_payload_qos (io_input_ar_payload_qos[3:0] ), //i + .io_input_ar_payload_prot (io_input_ar_payload_prot[2:0] ), //i + .io_input_r_valid (readOnly_io_input_r_valid ), //o + .io_input_r_ready (io_input_r_ready ), //i + .io_input_r_payload_data (readOnly_io_input_r_payload_data[31:0] ), //o + .io_input_r_payload_id (readOnly_io_input_r_payload_id[7:0] ), //o + .io_input_r_payload_resp (readOnly_io_input_r_payload_resp[1:0] ), //o + .io_input_r_payload_last (readOnly_io_input_r_payload_last ), //o + .io_output_ar_valid (readOnly_io_output_ar_valid ), //o + .io_output_ar_ready (io_output_ar_ready ), //i + .io_output_ar_payload_addr (readOnly_io_output_ar_payload_addr[31:0] ), //o + .io_output_ar_payload_id (readOnly_io_output_ar_payload_id[7:0] ), //o + .io_output_ar_payload_region (readOnly_io_output_ar_payload_region[3:0]), //o + .io_output_ar_payload_len (readOnly_io_output_ar_payload_len[7:0] ), //o + .io_output_ar_payload_size (readOnly_io_output_ar_payload_size[2:0] ), //o + .io_output_ar_payload_burst (readOnly_io_output_ar_payload_burst[1:0] ), //o + .io_output_ar_payload_lock (readOnly_io_output_ar_payload_lock ), //o + .io_output_ar_payload_cache (readOnly_io_output_ar_payload_cache[3:0] ), //o + .io_output_ar_payload_qos (readOnly_io_output_ar_payload_qos[3:0] ), //o + .io_output_ar_payload_prot (readOnly_io_output_ar_payload_prot[2:0] ), //o + .io_output_r_valid (io_output_r_valid ), //i + .io_output_r_ready (readOnly_io_output_r_ready ), //o + .io_output_r_payload_data (io_output_r_payload_data[127:0] ), //i + .io_output_r_payload_id (io_output_r_payload_id[7:0] ), //i + .io_output_r_payload_resp (io_output_r_payload_resp[1:0] ), //i + .io_output_r_payload_last (io_output_r_payload_last ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Asic32To128UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 writeOnly ( + .io_input_aw_valid (io_input_aw_valid ), //i + .io_input_aw_ready (writeOnly_io_input_aw_ready ), //o + .io_input_aw_payload_addr (io_input_aw_payload_addr[31:0] ), //i + .io_input_aw_payload_id (io_input_aw_payload_id[7:0] ), //i + .io_input_aw_payload_region (io_input_aw_payload_region[3:0] ), //i + .io_input_aw_payload_len (io_input_aw_payload_len[7:0] ), //i + .io_input_aw_payload_size (io_input_aw_payload_size[2:0] ), //i + .io_input_aw_payload_burst (io_input_aw_payload_burst[1:0] ), //i + .io_input_aw_payload_lock (io_input_aw_payload_lock ), //i + .io_input_aw_payload_cache (io_input_aw_payload_cache[3:0] ), //i + .io_input_aw_payload_qos (io_input_aw_payload_qos[3:0] ), //i + .io_input_aw_payload_prot (io_input_aw_payload_prot[2:0] ), //i + .io_input_w_valid (io_input_w_valid ), //i + .io_input_w_ready (writeOnly_io_input_w_ready ), //o + .io_input_w_payload_data (io_input_w_payload_data[31:0] ), //i + .io_input_w_payload_strb (io_input_w_payload_strb[3:0] ), //i + .io_input_w_payload_last (io_input_w_payload_last ), //i + .io_input_b_valid (writeOnly_io_input_b_valid ), //o + .io_input_b_ready (io_input_b_ready ), //i + .io_input_b_payload_id (writeOnly_io_input_b_payload_id[7:0] ), //o + .io_input_b_payload_resp (writeOnly_io_input_b_payload_resp[1:0] ), //o + .io_output_aw_valid (writeOnly_io_output_aw_valid ), //o + .io_output_aw_ready (io_output_aw_ready ), //i + .io_output_aw_payload_addr (writeOnly_io_output_aw_payload_addr[31:0] ), //o + .io_output_aw_payload_id (writeOnly_io_output_aw_payload_id[7:0] ), //o + .io_output_aw_payload_region (writeOnly_io_output_aw_payload_region[3:0]), //o + .io_output_aw_payload_len (writeOnly_io_output_aw_payload_len[7:0] ), //o + .io_output_aw_payload_size (writeOnly_io_output_aw_payload_size[2:0] ), //o + .io_output_aw_payload_burst (writeOnly_io_output_aw_payload_burst[1:0] ), //o + .io_output_aw_payload_lock (writeOnly_io_output_aw_payload_lock ), //o + .io_output_aw_payload_cache (writeOnly_io_output_aw_payload_cache[3:0] ), //o + .io_output_aw_payload_qos (writeOnly_io_output_aw_payload_qos[3:0] ), //o + .io_output_aw_payload_prot (writeOnly_io_output_aw_payload_prot[2:0] ), //o + .io_output_w_valid (writeOnly_io_output_w_valid ), //o + .io_output_w_ready (io_output_w_ready ), //i + .io_output_w_payload_data (writeOnly_io_output_w_payload_data[127:0] ), //o + .io_output_w_payload_strb (writeOnly_io_output_w_payload_strb[15:0] ), //o + .io_output_w_payload_last (writeOnly_io_output_w_payload_last ), //o + .io_output_b_valid (io_output_b_valid ), //i + .io_output_b_ready (writeOnly_io_output_b_ready ), //o + .io_output_b_payload_id (io_output_b_payload_id[7:0] ), //i + .io_output_b_payload_resp (io_output_b_payload_resp[1:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign io_input_ar_ready = readOnly_io_input_ar_ready; + assign io_input_r_valid = readOnly_io_input_r_valid; + assign io_input_r_payload_data = readOnly_io_input_r_payload_data; + assign io_input_r_payload_id = readOnly_io_input_r_payload_id; + assign io_input_r_payload_resp = readOnly_io_input_r_payload_resp; + assign io_input_r_payload_last = readOnly_io_input_r_payload_last; + assign io_input_aw_ready = writeOnly_io_input_aw_ready; + assign io_input_w_ready = writeOnly_io_input_w_ready; + assign io_input_b_valid = writeOnly_io_input_b_valid; + assign io_input_b_payload_id = writeOnly_io_input_b_payload_id; + assign io_input_b_payload_resp = writeOnly_io_input_b_payload_resp; + assign io_output_ar_valid = readOnly_io_output_ar_valid; + assign io_output_ar_payload_addr = readOnly_io_output_ar_payload_addr; + assign io_output_ar_payload_id = readOnly_io_output_ar_payload_id; + assign io_output_ar_payload_region = readOnly_io_output_ar_payload_region; + assign io_output_ar_payload_len = readOnly_io_output_ar_payload_len; + assign io_output_ar_payload_size = readOnly_io_output_ar_payload_size; + assign io_output_ar_payload_burst = readOnly_io_output_ar_payload_burst; + assign io_output_ar_payload_lock = readOnly_io_output_ar_payload_lock; + assign io_output_ar_payload_cache = readOnly_io_output_ar_payload_cache; + assign io_output_ar_payload_qos = readOnly_io_output_ar_payload_qos; + assign io_output_ar_payload_prot = readOnly_io_output_ar_payload_prot; + assign io_output_r_ready = readOnly_io_output_r_ready; + assign io_output_aw_valid = writeOnly_io_output_aw_valid; + assign io_output_aw_payload_addr = writeOnly_io_output_aw_payload_addr; + assign io_output_aw_payload_id = writeOnly_io_output_aw_payload_id; + assign io_output_aw_payload_region = writeOnly_io_output_aw_payload_region; + assign io_output_aw_payload_len = writeOnly_io_output_aw_payload_len; + assign io_output_aw_payload_size = writeOnly_io_output_aw_payload_size; + assign io_output_aw_payload_burst = writeOnly_io_output_aw_payload_burst; + assign io_output_aw_payload_lock = writeOnly_io_output_aw_payload_lock; + assign io_output_aw_payload_cache = writeOnly_io_output_aw_payload_cache; + assign io_output_aw_payload_qos = writeOnly_io_output_aw_payload_qos; + assign io_output_aw_payload_prot = writeOnly_io_output_aw_payload_prot; + assign io_output_w_valid = writeOnly_io_output_w_valid; + assign io_output_w_payload_data = writeOnly_io_output_w_payload_data; + assign io_output_w_payload_strb = writeOnly_io_output_w_payload_strb; + assign io_output_w_payload_last = writeOnly_io_output_w_payload_last; + assign io_output_b_ready = writeOnly_io_output_b_ready; + +endmodule + +module Asic32To128UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_aw_valid, + output reg io_input_aw_ready, + input [31:0] io_input_aw_payload_addr, + input [7:0] io_input_aw_payload_id, + input [3:0] io_input_aw_payload_region, + input [7:0] io_input_aw_payload_len, + input [2:0] io_input_aw_payload_size, + input [1:0] io_input_aw_payload_burst, + input [0:0] io_input_aw_payload_lock, + input [3:0] io_input_aw_payload_cache, + input [3:0] io_input_aw_payload_qos, + input [2:0] io_input_aw_payload_prot, + input io_input_w_valid, + output io_input_w_ready, + input [31:0] io_input_w_payload_data, + input [3:0] io_input_w_payload_strb, + input io_input_w_payload_last, + output io_input_b_valid, + input io_input_b_ready, + output [7:0] io_input_b_payload_id, + output [1:0] io_input_b_payload_resp, + output io_output_aw_valid, + input io_output_aw_ready, + output [31:0] io_output_aw_payload_addr, + output [7:0] io_output_aw_payload_id, + output [3:0] io_output_aw_payload_region, + output reg [7:0] io_output_aw_payload_len, + output reg [2:0] io_output_aw_payload_size, + output [1:0] io_output_aw_payload_burst, + output [0:0] io_output_aw_payload_lock, + output [3:0] io_output_aw_payload_cache, + output [3:0] io_output_aw_payload_qos, + output [2:0] io_output_aw_payload_prot, + output io_output_w_valid, + input io_output_w_ready, + output [127:0] io_output_w_payload_data, + output [15:0] io_output_w_payload_strb, + output io_output_w_payload_last, + input io_output_b_valid, + output io_output_b_ready, + input [7:0] io_output_b_payload_id, + input [1:0] io_output_b_payload_resp, + input clk, + input reset +); + + wire [14:0] _zz_cmdLogic_byteCount; + wire [10:0] _zz_cmdLogic_incrLen; + wire [10:0] _zz_cmdLogic_incrLen_1; + wire [3:0] _zz_cmdLogic_incrLen_2; + wire [4:0] _zz_dataLogic_byteCounterNext; + wire [7:0] _zz_dataLogic_byteCounterNext_1; + reg [15:0] _zz_dataLogic_byteActivity; + wire [1:0] _zz_dataLogic_byteActivity_1; + wire cmdLogic_outputFork_valid; + wire cmdLogic_outputFork_ready; + wire [31:0] cmdLogic_outputFork_payload_addr; + wire [7:0] cmdLogic_outputFork_payload_id; + wire [3:0] cmdLogic_outputFork_payload_region; + wire [7:0] cmdLogic_outputFork_payload_len; + wire [2:0] cmdLogic_outputFork_payload_size; + wire [1:0] cmdLogic_outputFork_payload_burst; + wire [0:0] cmdLogic_outputFork_payload_lock; + wire [3:0] cmdLogic_outputFork_payload_cache; + wire [3:0] cmdLogic_outputFork_payload_qos; + wire [2:0] cmdLogic_outputFork_payload_prot; + wire cmdLogic_dataFork_valid; + wire cmdLogic_dataFork_ready; + wire [31:0] cmdLogic_dataFork_payload_addr; + wire [7:0] cmdLogic_dataFork_payload_id; + wire [3:0] cmdLogic_dataFork_payload_region; + wire [7:0] cmdLogic_dataFork_payload_len; + wire [2:0] cmdLogic_dataFork_payload_size; + wire [1:0] cmdLogic_dataFork_payload_burst; + wire [0:0] cmdLogic_dataFork_payload_lock; + wire [3:0] cmdLogic_dataFork_payload_cache; + wire [3:0] cmdLogic_dataFork_payload_qos; + wire [2:0] cmdLogic_dataFork_payload_prot; + reg io_input_aw_fork2_logic_linkEnable_0; + reg io_input_aw_fork2_logic_linkEnable_1; + wire when_Stream_l993; + wire when_Stream_l993_1; + wire cmdLogic_outputFork_fire; + wire cmdLogic_dataFork_fire; + wire [9:0] cmdLogic_byteCount; + wire [6:0] cmdLogic_incrLen; + wire when_Axi4Upsizer_l21; + wire when_Axi4Upsizer_l24; + reg [3:0] dataLogic_byteCounter; + reg [2:0] dataLogic_size; + reg dataLogic_outputValid; + reg dataLogic_outputLast; + reg dataLogic_busy; + reg dataLogic_incrementByteCounter; + reg dataLogic_alwaysFire; + wire [4:0] dataLogic_byteCounterNext; + reg [127:0] dataLogic_dataBuffer; + reg [15:0] dataLogic_maskBuffer; + wire [15:0] dataLogic_byteActivity; + wire io_output_w_fire; + wire io_output_w_isStall; + wire io_input_w_fire; + wire when_Axi4Upsizer_l59; + wire when_Axi4Upsizer_l59_1; + wire when_Axi4Upsizer_l59_2; + wire when_Axi4Upsizer_l59_3; + wire when_Axi4Upsizer_l59_4; + wire when_Axi4Upsizer_l59_5; + wire when_Axi4Upsizer_l59_6; + wire when_Axi4Upsizer_l59_7; + wire when_Axi4Upsizer_l59_8; + wire when_Axi4Upsizer_l59_9; + wire when_Axi4Upsizer_l59_10; + wire when_Axi4Upsizer_l59_11; + wire when_Axi4Upsizer_l59_12; + wire when_Axi4Upsizer_l59_13; + wire when_Axi4Upsizer_l59_14; + wire when_Axi4Upsizer_l59_15; + wire cmdLogic_dataFork_fire_1; + wire when_Axi4Upsizer_l68; + wire when_Axi4Upsizer_l68_1; + wire when_Axi4Upsizer_l68_2; + wire when_Axi4Upsizer_l68_3; + + assign _zz_cmdLogic_byteCount = ({7'd0,io_input_aw_payload_len} <<< io_input_aw_payload_size); + assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); + assign _zz_cmdLogic_incrLen_2 = io_input_aw_payload_addr[3 : 0]; + assign _zz_cmdLogic_incrLen_1 = {7'd0, _zz_cmdLogic_incrLen_2}; + assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); + assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[4:0]; + assign _zz_dataLogic_byteActivity_1 = dataLogic_size[1:0]; + always @(*) begin + case(_zz_dataLogic_byteActivity_1) + 2'b00 : _zz_dataLogic_byteActivity = 16'h0001; + 2'b01 : _zz_dataLogic_byteActivity = 16'h0003; + 2'b10 : _zz_dataLogic_byteActivity = 16'h000f; + default : _zz_dataLogic_byteActivity = 16'h00ff; + endcase + end + + always @(*) begin + io_input_aw_ready = 1'b1; + if(when_Stream_l993) begin + io_input_aw_ready = 1'b0; + end + if(when_Stream_l993_1) begin + io_input_aw_ready = 1'b0; + end + end + + assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_aw_fork2_logic_linkEnable_0); + assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_aw_fork2_logic_linkEnable_1); + assign cmdLogic_outputFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_0); + assign cmdLogic_outputFork_payload_addr = io_input_aw_payload_addr; + assign cmdLogic_outputFork_payload_id = io_input_aw_payload_id; + assign cmdLogic_outputFork_payload_region = io_input_aw_payload_region; + assign cmdLogic_outputFork_payload_len = io_input_aw_payload_len; + assign cmdLogic_outputFork_payload_size = io_input_aw_payload_size; + assign cmdLogic_outputFork_payload_burst = io_input_aw_payload_burst; + assign cmdLogic_outputFork_payload_lock = io_input_aw_payload_lock; + assign cmdLogic_outputFork_payload_cache = io_input_aw_payload_cache; + assign cmdLogic_outputFork_payload_qos = io_input_aw_payload_qos; + assign cmdLogic_outputFork_payload_prot = io_input_aw_payload_prot; + assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); + assign cmdLogic_dataFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_1); + assign cmdLogic_dataFork_payload_addr = io_input_aw_payload_addr; + assign cmdLogic_dataFork_payload_id = io_input_aw_payload_id; + assign cmdLogic_dataFork_payload_region = io_input_aw_payload_region; + assign cmdLogic_dataFork_payload_len = io_input_aw_payload_len; + assign cmdLogic_dataFork_payload_size = io_input_aw_payload_size; + assign cmdLogic_dataFork_payload_burst = io_input_aw_payload_burst; + assign cmdLogic_dataFork_payload_lock = io_input_aw_payload_lock; + assign cmdLogic_dataFork_payload_cache = io_input_aw_payload_cache; + assign cmdLogic_dataFork_payload_qos = io_input_aw_payload_qos; + assign cmdLogic_dataFork_payload_prot = io_input_aw_payload_prot; + assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign io_output_aw_valid = cmdLogic_outputFork_valid; + assign cmdLogic_outputFork_ready = io_output_aw_ready; + assign io_output_aw_payload_addr = cmdLogic_outputFork_payload_addr; + assign io_output_aw_payload_id = cmdLogic_outputFork_payload_id; + assign io_output_aw_payload_region = cmdLogic_outputFork_payload_region; + always @(*) begin + io_output_aw_payload_len = cmdLogic_outputFork_payload_len; + if(when_Axi4Upsizer_l21) begin + io_output_aw_payload_len = {1'd0, cmdLogic_incrLen}; + end + end + + always @(*) begin + io_output_aw_payload_size = cmdLogic_outputFork_payload_size; + if(when_Axi4Upsizer_l21) begin + io_output_aw_payload_size = 3'b100; + if(when_Axi4Upsizer_l24) begin + io_output_aw_payload_size = io_input_aw_payload_size; + end + end + end + + assign io_output_aw_payload_burst = cmdLogic_outputFork_payload_burst; + assign io_output_aw_payload_lock = cmdLogic_outputFork_payload_lock; + assign io_output_aw_payload_cache = cmdLogic_outputFork_payload_cache; + assign io_output_aw_payload_qos = cmdLogic_outputFork_payload_qos; + assign io_output_aw_payload_prot = cmdLogic_outputFork_payload_prot; + assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; + assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 4]; + assign when_Axi4Upsizer_l21 = (io_output_aw_payload_burst == 2'b01); + assign when_Axi4Upsizer_l24 = (io_input_aw_payload_len == 8'h00); + assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); + assign dataLogic_byteActivity = (_zz_dataLogic_byteActivity <<< dataLogic_byteCounter); + assign io_output_w_fire = (io_output_w_valid && io_output_w_ready); + assign io_output_w_valid = dataLogic_outputValid; + assign io_output_w_isStall = (io_output_w_valid && (! io_output_w_ready)); + assign io_input_w_ready = (dataLogic_busy && (! io_output_w_isStall)); + assign io_output_w_payload_data = dataLogic_dataBuffer; + assign io_output_w_payload_strb = dataLogic_maskBuffer; + assign io_output_w_payload_last = dataLogic_outputLast; + assign io_input_w_fire = (io_input_w_valid && io_input_w_ready); + assign when_Axi4Upsizer_l59 = dataLogic_byteActivity[0]; + assign when_Axi4Upsizer_l59_1 = dataLogic_byteActivity[1]; + assign when_Axi4Upsizer_l59_2 = dataLogic_byteActivity[2]; + assign when_Axi4Upsizer_l59_3 = dataLogic_byteActivity[3]; + assign when_Axi4Upsizer_l59_4 = dataLogic_byteActivity[4]; + assign when_Axi4Upsizer_l59_5 = dataLogic_byteActivity[5]; + assign when_Axi4Upsizer_l59_6 = dataLogic_byteActivity[6]; + assign when_Axi4Upsizer_l59_7 = dataLogic_byteActivity[7]; + assign when_Axi4Upsizer_l59_8 = dataLogic_byteActivity[8]; + assign when_Axi4Upsizer_l59_9 = dataLogic_byteActivity[9]; + assign when_Axi4Upsizer_l59_10 = dataLogic_byteActivity[10]; + assign when_Axi4Upsizer_l59_11 = dataLogic_byteActivity[11]; + assign when_Axi4Upsizer_l59_12 = dataLogic_byteActivity[12]; + assign when_Axi4Upsizer_l59_13 = dataLogic_byteActivity[13]; + assign when_Axi4Upsizer_l59_14 = dataLogic_byteActivity[14]; + assign when_Axi4Upsizer_l59_15 = dataLogic_byteActivity[15]; + assign cmdLogic_dataFork_fire_1 = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign when_Axi4Upsizer_l68 = (3'b000 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_1 = (3'b001 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_2 = (3'b010 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_3 = (3'b011 < cmdLogic_dataFork_payload_size); + assign cmdLogic_dataFork_ready = (! dataLogic_busy); + assign io_input_b_valid = io_output_b_valid; + assign io_output_b_ready = io_input_b_ready; + assign io_input_b_payload_id = io_output_b_payload_id; + assign io_input_b_payload_resp = io_output_b_payload_resp; + always @(posedge clk or posedge reset) begin + if(reset) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; + io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; + dataLogic_outputValid <= 1'b0; + dataLogic_busy <= 1'b0; + dataLogic_maskBuffer <= 16'h0000; + end else begin + if(cmdLogic_outputFork_fire) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdLogic_dataFork_fire) begin + io_input_aw_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_aw_ready) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; + io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; + end + if(io_output_w_ready) begin + dataLogic_outputValid <= 1'b0; + end + if(io_output_w_fire) begin + dataLogic_maskBuffer <= 16'h0000; + end + if(io_input_w_fire) begin + dataLogic_outputValid <= ((dataLogic_byteCounterNext[4] || io_input_w_payload_last) || dataLogic_alwaysFire); + if(io_input_w_payload_last) begin + dataLogic_busy <= 1'b0; + end + if(when_Axi4Upsizer_l59) begin + dataLogic_maskBuffer[0] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_1) begin + dataLogic_maskBuffer[1] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_2) begin + dataLogic_maskBuffer[2] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_3) begin + dataLogic_maskBuffer[3] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_4) begin + dataLogic_maskBuffer[4] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_5) begin + dataLogic_maskBuffer[5] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_6) begin + dataLogic_maskBuffer[6] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_7) begin + dataLogic_maskBuffer[7] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_8) begin + dataLogic_maskBuffer[8] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_9) begin + dataLogic_maskBuffer[9] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_10) begin + dataLogic_maskBuffer[10] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_11) begin + dataLogic_maskBuffer[11] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_12) begin + dataLogic_maskBuffer[12] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_13) begin + dataLogic_maskBuffer[13] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_14) begin + dataLogic_maskBuffer[14] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_15) begin + dataLogic_maskBuffer[15] <= io_input_w_payload_strb[3]; + end + end + if(cmdLogic_dataFork_fire_1) begin + dataLogic_busy <= 1'b1; + end + end + end + + always @(posedge clk) begin + if(io_input_w_fire) begin + if(dataLogic_incrementByteCounter) begin + dataLogic_byteCounter <= dataLogic_byteCounterNext[3:0]; + end + dataLogic_outputLast <= io_input_w_payload_last; + if(when_Axi4Upsizer_l59) begin + dataLogic_dataBuffer[7 : 0] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_1) begin + dataLogic_dataBuffer[15 : 8] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_2) begin + dataLogic_dataBuffer[23 : 16] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_3) begin + dataLogic_dataBuffer[31 : 24] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_4) begin + dataLogic_dataBuffer[39 : 32] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_5) begin + dataLogic_dataBuffer[47 : 40] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_6) begin + dataLogic_dataBuffer[55 : 48] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_7) begin + dataLogic_dataBuffer[63 : 56] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_8) begin + dataLogic_dataBuffer[71 : 64] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_9) begin + dataLogic_dataBuffer[79 : 72] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_10) begin + dataLogic_dataBuffer[87 : 80] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_11) begin + dataLogic_dataBuffer[95 : 88] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_12) begin + dataLogic_dataBuffer[103 : 96] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_13) begin + dataLogic_dataBuffer[111 : 104] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_14) begin + dataLogic_dataBuffer[119 : 112] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_15) begin + dataLogic_dataBuffer[127 : 120] <= io_input_w_payload_data[31 : 24]; + end + end + if(cmdLogic_dataFork_fire_1) begin + dataLogic_byteCounter <= cmdLogic_dataFork_payload_addr[3:0]; + if(when_Axi4Upsizer_l68) begin + dataLogic_byteCounter[0] <= 1'b0; + end + if(when_Axi4Upsizer_l68_1) begin + dataLogic_byteCounter[1] <= 1'b0; + end + if(when_Axi4Upsizer_l68_2) begin + dataLogic_byteCounter[2] <= 1'b0; + end + if(when_Axi4Upsizer_l68_3) begin + dataLogic_byteCounter[3] <= 1'b0; + end + dataLogic_size <= cmdLogic_dataFork_payload_size; + dataLogic_alwaysFire <= (! (cmdLogic_dataFork_payload_burst == 2'b01)); + dataLogic_incrementByteCounter <= (! (cmdLogic_dataFork_payload_burst == 2'b00)); + end + end + + +endmodule + +module Asic32To128UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_ar_valid, + output reg io_input_ar_ready, + input [31:0] io_input_ar_payload_addr, + input [7:0] io_input_ar_payload_id, + input [3:0] io_input_ar_payload_region, + input [7:0] io_input_ar_payload_len, + input [2:0] io_input_ar_payload_size, + input [1:0] io_input_ar_payload_burst, + input [0:0] io_input_ar_payload_lock, + input [3:0] io_input_ar_payload_cache, + input [3:0] io_input_ar_payload_qos, + input [2:0] io_input_ar_payload_prot, + output io_input_r_valid, + input io_input_r_ready, + output [31:0] io_input_r_payload_data, + output [7:0] io_input_r_payload_id, + output [1:0] io_input_r_payload_resp, + output io_input_r_payload_last, + output io_output_ar_valid, + input io_output_ar_ready, + output [31:0] io_output_ar_payload_addr, + output [7:0] io_output_ar_payload_id, + output [3:0] io_output_ar_payload_region, + output [7:0] io_output_ar_payload_len, + output reg [2:0] io_output_ar_payload_size, + output [1:0] io_output_ar_payload_burst, + output [0:0] io_output_ar_payload_lock, + output [3:0] io_output_ar_payload_cache, + output [3:0] io_output_ar_payload_qos, + output [2:0] io_output_ar_payload_prot, + input io_output_r_valid, + output io_output_r_ready, + input [127:0] io_output_r_payload_data, + input [7:0] io_output_r_payload_id, + input [1:0] io_output_r_payload_resp, + input io_output_r_payload_last, + input clk, + input reset +); + + wire dataLogic_cmdPush_fifo_io_pop_ready; + wire dataLogic_cmdPush_fifo_io_push_ready; + wire dataLogic_cmdPush_fifo_io_pop_valid; + wire [3:0] dataLogic_cmdPush_fifo_io_pop_payload_startAt; + wire [3:0] dataLogic_cmdPush_fifo_io_pop_payload_endAt; + wire [2:0] dataLogic_cmdPush_fifo_io_pop_payload_size; + wire [7:0] dataLogic_cmdPush_fifo_io_pop_payload_id; + wire [4:0] dataLogic_cmdPush_fifo_io_occupancy; + wire [4:0] dataLogic_cmdPush_fifo_io_availability; + wire [14:0] _zz_cmdLogic_byteCount; + wire [10:0] _zz_cmdLogic_incrLen; + wire [10:0] _zz_cmdLogic_incrLen_1; + wire [3:0] _zz_cmdLogic_incrLen_2; + wire [31:0] _zz_dataLogic_cmdPush_payload_endAt; + wire [31:0] _zz_dataLogic_cmdPush_payload_endAt_1; + wire [14:0] _zz_dataLogic_cmdPush_payload_endAt_2; + wire [4:0] _zz_dataLogic_byteCounterNext; + wire [7:0] _zz_dataLogic_byteCounterNext_1; + reg [31:0] _zz_io_input_r_payload_data; + wire [1:0] _zz_io_input_r_payload_data_1; + wire cmdLogic_outputFork_valid; + wire cmdLogic_outputFork_ready; + wire [31:0] cmdLogic_outputFork_payload_addr; + wire [7:0] cmdLogic_outputFork_payload_id; + wire [3:0] cmdLogic_outputFork_payload_region; + wire [7:0] cmdLogic_outputFork_payload_len; + wire [2:0] cmdLogic_outputFork_payload_size; + wire [1:0] cmdLogic_outputFork_payload_burst; + wire [0:0] cmdLogic_outputFork_payload_lock; + wire [3:0] cmdLogic_outputFork_payload_cache; + wire [3:0] cmdLogic_outputFork_payload_qos; + wire [2:0] cmdLogic_outputFork_payload_prot; + wire cmdLogic_dataFork_valid; + wire cmdLogic_dataFork_ready; + wire [31:0] cmdLogic_dataFork_payload_addr; + wire [7:0] cmdLogic_dataFork_payload_id; + wire [3:0] cmdLogic_dataFork_payload_region; + wire [7:0] cmdLogic_dataFork_payload_len; + wire [2:0] cmdLogic_dataFork_payload_size; + wire [1:0] cmdLogic_dataFork_payload_burst; + wire [0:0] cmdLogic_dataFork_payload_lock; + wire [3:0] cmdLogic_dataFork_payload_cache; + wire [3:0] cmdLogic_dataFork_payload_qos; + wire [2:0] cmdLogic_dataFork_payload_prot; + reg io_input_ar_fork2_logic_linkEnable_0; + reg io_input_ar_fork2_logic_linkEnable_1; + wire when_Stream_l993; + wire when_Stream_l993_1; + wire cmdLogic_outputFork_fire; + wire cmdLogic_dataFork_fire; + wire [9:0] cmdLogic_byteCount; + wire [6:0] cmdLogic_incrLen; + wire when_Axi4Upsizer_l108; + wire dataLogic_cmdPush_valid; + wire dataLogic_cmdPush_ready; + wire [3:0] dataLogic_cmdPush_payload_startAt; + wire [3:0] dataLogic_cmdPush_payload_endAt; + wire [2:0] dataLogic_cmdPush_payload_size; + wire [7:0] dataLogic_cmdPush_payload_id; + reg [2:0] dataLogic_size; + reg dataLogic_busy; + reg [7:0] dataLogic_id; + reg [3:0] dataLogic_byteCounter; + reg [3:0] dataLogic_byteCounterLast; + wire [4:0] dataLogic_byteCounterNext; + wire readOnly_dataLogic_cmdPush_fifo_io_pop_fire; + wire io_input_r_fire; + + assign _zz_cmdLogic_byteCount = ({7'd0,io_input_ar_payload_len} <<< io_input_ar_payload_size); + assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); + assign _zz_cmdLogic_incrLen_2 = io_input_ar_payload_addr[3 : 0]; + assign _zz_cmdLogic_incrLen_1 = {7'd0, _zz_cmdLogic_incrLen_2}; + assign _zz_dataLogic_cmdPush_payload_endAt = (cmdLogic_dataFork_payload_addr + _zz_dataLogic_cmdPush_payload_endAt_1); + assign _zz_dataLogic_cmdPush_payload_endAt_2 = ({7'd0,cmdLogic_dataFork_payload_len} <<< cmdLogic_dataFork_payload_size); + assign _zz_dataLogic_cmdPush_payload_endAt_1 = {17'd0, _zz_dataLogic_cmdPush_payload_endAt_2}; + assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); + assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[4:0]; + assign _zz_io_input_r_payload_data_1 = (dataLogic_byteCounter >>> 2'd2); + Asic32To128UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 dataLogic_cmdPush_fifo ( + .io_push_valid (dataLogic_cmdPush_valid ), //i + .io_push_ready (dataLogic_cmdPush_fifo_io_push_ready ), //o + .io_push_payload_startAt (dataLogic_cmdPush_payload_startAt[3:0] ), //i + .io_push_payload_endAt (dataLogic_cmdPush_payload_endAt[3:0] ), //i + .io_push_payload_size (dataLogic_cmdPush_payload_size[2:0] ), //i + .io_push_payload_id (dataLogic_cmdPush_payload_id[7:0] ), //i + .io_pop_valid (dataLogic_cmdPush_fifo_io_pop_valid ), //o + .io_pop_ready (dataLogic_cmdPush_fifo_io_pop_ready ), //i + .io_pop_payload_startAt (dataLogic_cmdPush_fifo_io_pop_payload_startAt[3:0]), //o + .io_pop_payload_endAt (dataLogic_cmdPush_fifo_io_pop_payload_endAt[3:0] ), //o + .io_pop_payload_size (dataLogic_cmdPush_fifo_io_pop_payload_size[2:0] ), //o + .io_pop_payload_id (dataLogic_cmdPush_fifo_io_pop_payload_id[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (dataLogic_cmdPush_fifo_io_occupancy[4:0] ), //o + .io_availability (dataLogic_cmdPush_fifo_io_availability[4:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_io_input_r_payload_data_1) + 2'b00 : _zz_io_input_r_payload_data = io_output_r_payload_data[31 : 0]; + 2'b01 : _zz_io_input_r_payload_data = io_output_r_payload_data[63 : 32]; + 2'b10 : _zz_io_input_r_payload_data = io_output_r_payload_data[95 : 64]; + default : _zz_io_input_r_payload_data = io_output_r_payload_data[127 : 96]; + endcase + end + + always @(*) begin + io_input_ar_ready = 1'b1; + if(when_Stream_l993) begin + io_input_ar_ready = 1'b0; + end + if(when_Stream_l993_1) begin + io_input_ar_ready = 1'b0; + end + end + + assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_ar_fork2_logic_linkEnable_0); + assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_ar_fork2_logic_linkEnable_1); + assign cmdLogic_outputFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_0); + assign cmdLogic_outputFork_payload_addr = io_input_ar_payload_addr; + assign cmdLogic_outputFork_payload_id = io_input_ar_payload_id; + assign cmdLogic_outputFork_payload_region = io_input_ar_payload_region; + assign cmdLogic_outputFork_payload_len = io_input_ar_payload_len; + assign cmdLogic_outputFork_payload_size = io_input_ar_payload_size; + assign cmdLogic_outputFork_payload_burst = io_input_ar_payload_burst; + assign cmdLogic_outputFork_payload_lock = io_input_ar_payload_lock; + assign cmdLogic_outputFork_payload_cache = io_input_ar_payload_cache; + assign cmdLogic_outputFork_payload_qos = io_input_ar_payload_qos; + assign cmdLogic_outputFork_payload_prot = io_input_ar_payload_prot; + assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); + assign cmdLogic_dataFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_1); + assign cmdLogic_dataFork_payload_addr = io_input_ar_payload_addr; + assign cmdLogic_dataFork_payload_id = io_input_ar_payload_id; + assign cmdLogic_dataFork_payload_region = io_input_ar_payload_region; + assign cmdLogic_dataFork_payload_len = io_input_ar_payload_len; + assign cmdLogic_dataFork_payload_size = io_input_ar_payload_size; + assign cmdLogic_dataFork_payload_burst = io_input_ar_payload_burst; + assign cmdLogic_dataFork_payload_lock = io_input_ar_payload_lock; + assign cmdLogic_dataFork_payload_cache = io_input_ar_payload_cache; + assign cmdLogic_dataFork_payload_qos = io_input_ar_payload_qos; + assign cmdLogic_dataFork_payload_prot = io_input_ar_payload_prot; + assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign io_output_ar_valid = cmdLogic_outputFork_valid; + assign cmdLogic_outputFork_ready = io_output_ar_ready; + assign io_output_ar_payload_addr = cmdLogic_outputFork_payload_addr; + assign io_output_ar_payload_region = cmdLogic_outputFork_payload_region; + assign io_output_ar_payload_burst = cmdLogic_outputFork_payload_burst; + assign io_output_ar_payload_lock = cmdLogic_outputFork_payload_lock; + assign io_output_ar_payload_cache = cmdLogic_outputFork_payload_cache; + assign io_output_ar_payload_qos = cmdLogic_outputFork_payload_qos; + assign io_output_ar_payload_prot = cmdLogic_outputFork_payload_prot; + assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; + assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 4]; + always @(*) begin + io_output_ar_payload_size = 3'b100; + if(when_Axi4Upsizer_l108) begin + io_output_ar_payload_size = io_input_ar_payload_size; + end + end + + assign io_output_ar_payload_len = {1'd0, cmdLogic_incrLen}; + assign io_output_ar_payload_id = 8'h00; + assign when_Axi4Upsizer_l108 = (io_input_ar_payload_len == 8'h00); + assign dataLogic_cmdPush_valid = cmdLogic_dataFork_valid; + assign cmdLogic_dataFork_ready = dataLogic_cmdPush_ready; + assign dataLogic_cmdPush_payload_startAt = cmdLogic_dataFork_payload_addr[3:0]; + assign dataLogic_cmdPush_payload_endAt = _zz_dataLogic_cmdPush_payload_endAt[3:0]; + assign dataLogic_cmdPush_payload_size = cmdLogic_dataFork_payload_size; + assign dataLogic_cmdPush_payload_id = cmdLogic_dataFork_payload_id; + assign dataLogic_cmdPush_ready = dataLogic_cmdPush_fifo_io_push_ready; + assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); + assign readOnly_dataLogic_cmdPush_fifo_io_pop_fire = (dataLogic_cmdPush_fifo_io_pop_valid && dataLogic_cmdPush_fifo_io_pop_ready); + assign dataLogic_cmdPush_fifo_io_pop_ready = (! dataLogic_busy); + assign io_input_r_fire = (io_input_r_valid && io_input_r_ready); + assign io_input_r_valid = (io_output_r_valid && dataLogic_busy); + assign io_input_r_payload_last = (io_output_r_payload_last && (dataLogic_byteCounter == dataLogic_byteCounterLast)); + assign io_input_r_payload_resp = io_output_r_payload_resp; + assign io_input_r_payload_data = _zz_io_input_r_payload_data; + assign io_input_r_payload_id = dataLogic_id; + assign io_output_r_ready = ((dataLogic_busy && io_input_r_ready) && (io_input_r_payload_last || dataLogic_byteCounterNext[4])); + always @(posedge clk or posedge reset) begin + if(reset) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; + io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; + dataLogic_busy <= 1'b0; + end else begin + if(cmdLogic_outputFork_fire) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdLogic_dataFork_fire) begin + io_input_ar_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_ar_ready) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; + io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; + end + if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin + dataLogic_busy <= 1'b1; + end + if(io_input_r_fire) begin + if(io_input_r_payload_last) begin + dataLogic_busy <= 1'b0; + end + end + end + end + + always @(posedge clk) begin + if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin + dataLogic_byteCounter <= dataLogic_cmdPush_fifo_io_pop_payload_startAt; + dataLogic_byteCounterLast <= dataLogic_cmdPush_fifo_io_pop_payload_endAt; + dataLogic_size <= dataLogic_cmdPush_fifo_io_pop_payload_size; + dataLogic_id <= dataLogic_cmdPush_fifo_io_pop_payload_id; + end + if(io_input_r_fire) begin + dataLogic_byteCounter <= dataLogic_byteCounterNext[3:0]; + end + end + + +endmodule + +module Asic32To128UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_push_valid, + output io_push_ready, + input [3:0] io_push_payload_startAt, + input [3:0] io_push_payload_endAt, + input [2:0] io_push_payload_size, + input [7:0] io_push_payload_id, + output io_pop_valid, + input io_pop_ready, + output [3:0] io_pop_payload_startAt, + output [3:0] io_pop_payload_endAt, + output [2:0] io_pop_payload_size, + output [7:0] io_pop_payload_id, + input io_flush, + output [4:0] io_occupancy, + output [4:0] io_availability, + input clk, + input reset +); + + reg [18:0] _zz_logic_ram_port0; + wire [3:0] _zz_logic_pushPtr_valueNext; + wire [0:0] _zz_logic_pushPtr_valueNext_1; + wire [3:0] _zz_logic_popPtr_valueNext; + wire [0:0] _zz_logic_popPtr_valueNext_1; + wire _zz__zz_logic_ram_port0; + wire _zz__zz_io_pop_payload_startAt; + wire [18:0] _zz__zz_logic_ram_port1; + wire [3:0] _zz_io_availability; + reg _zz_1; + reg logic_pushPtr_willIncrement; + reg logic_pushPtr_willClear; + reg [3:0] logic_pushPtr_valueNext; + reg [3:0] logic_pushPtr_value; + wire logic_pushPtr_willOverflowIfInc; + wire logic_pushPtr_willOverflow; + reg logic_popPtr_willIncrement; + reg logic_popPtr_willClear; + reg [3:0] logic_popPtr_valueNext; + reg [3:0] logic_popPtr_value; + wire logic_popPtr_willOverflowIfInc; + wire logic_popPtr_willOverflow; + wire logic_ptrMatch; + reg logic_risingOccupancy; + wire logic_pushing; + wire logic_popping; + wire logic_empty; + wire logic_full; + reg _zz_io_pop_valid; + wire [18:0] _zz_io_pop_payload_startAt; + wire when_Stream_l1123; + wire [3:0] logic_ptrDif; + reg [18:0] logic_ram [0:15]; + + assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; + assign _zz_logic_pushPtr_valueNext = {3'd0, _zz_logic_pushPtr_valueNext_1}; + assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; + assign _zz_logic_popPtr_valueNext = {3'd0, _zz_logic_popPtr_valueNext_1}; + assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); + assign _zz__zz_io_pop_payload_startAt = 1'b1; + assign _zz__zz_logic_ram_port1 = {io_push_payload_id,{io_push_payload_size,{io_push_payload_endAt,io_push_payload_startAt}}}; + always @(posedge clk) begin + if(_zz__zz_io_pop_payload_startAt) begin + _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_pushPtr_value] <= _zz__zz_logic_ram_port1; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_pushing) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willIncrement = 1'b0; + if(logic_pushing) begin + logic_pushPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willClear = 1'b0; + if(io_flush) begin + logic_pushPtr_willClear = 1'b1; + end + end + + assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 4'b1111); + assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); + always @(*) begin + logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); + if(logic_pushPtr_willClear) begin + logic_pushPtr_valueNext = 4'b0000; + end + end + + always @(*) begin + logic_popPtr_willIncrement = 1'b0; + if(logic_popping) begin + logic_popPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_popPtr_willClear = 1'b0; + if(io_flush) begin + logic_popPtr_willClear = 1'b1; + end + end + + assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 4'b1111); + assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); + always @(*) begin + logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); + if(logic_popPtr_willClear) begin + logic_popPtr_valueNext = 4'b0000; + end + end + + assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); + assign logic_pushing = (io_push_valid && io_push_ready); + assign logic_popping = (io_pop_valid && io_pop_ready); + assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); + assign logic_full = (logic_ptrMatch && logic_risingOccupancy); + assign io_push_ready = (! logic_full); + assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); + assign _zz_io_pop_payload_startAt = _zz_logic_ram_port0; + assign io_pop_payload_startAt = _zz_io_pop_payload_startAt[3 : 0]; + assign io_pop_payload_endAt = _zz_io_pop_payload_startAt[7 : 4]; + assign io_pop_payload_size = _zz_io_pop_payload_startAt[10 : 8]; + assign io_pop_payload_id = _zz_io_pop_payload_startAt[18 : 11]; + assign when_Stream_l1123 = (logic_pushing != logic_popping); + assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); + assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; + assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; + always @(posedge clk or posedge reset) begin + if(reset) begin + logic_pushPtr_value <= 4'b0000; + logic_popPtr_value <= 4'b0000; + logic_risingOccupancy <= 1'b0; + _zz_io_pop_valid <= 1'b0; + end else begin + logic_pushPtr_value <= logic_pushPtr_valueNext; + logic_popPtr_value <= logic_popPtr_valueNext; + _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); + if(when_Stream_l1123) begin + logic_risingOccupancy <= logic_pushing; + end + if(io_flush) begin + logic_risingOccupancy <= 1'b0; + end + end + end + + +endmodule + + +// Generator : SpinalHDL dev git head : 9cdee03b276638ef8e7a948b606bb7acc6e4c8d0 +// Component : Asic32To256UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 +// Git hash : cd16421fb7a4d44431a2445f9a92b82070ab9b8a + +`timescale 1ns/1ps + +module Asic32To256UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_aw_valid, + output io_input_aw_ready, + input [31:0] io_input_aw_payload_addr, + input [7:0] io_input_aw_payload_id, + input [3:0] io_input_aw_payload_region, + input [7:0] io_input_aw_payload_len, + input [2:0] io_input_aw_payload_size, + input [1:0] io_input_aw_payload_burst, + input [0:0] io_input_aw_payload_lock, + input [3:0] io_input_aw_payload_cache, + input [3:0] io_input_aw_payload_qos, + input [2:0] io_input_aw_payload_prot, + input io_input_w_valid, + output io_input_w_ready, + input [31:0] io_input_w_payload_data, + input [3:0] io_input_w_payload_strb, + input io_input_w_payload_last, + output io_input_b_valid, + input io_input_b_ready, + output [7:0] io_input_b_payload_id, + output [1:0] io_input_b_payload_resp, + input io_input_ar_valid, + output io_input_ar_ready, + input [31:0] io_input_ar_payload_addr, + input [7:0] io_input_ar_payload_id, + input [3:0] io_input_ar_payload_region, + input [7:0] io_input_ar_payload_len, + input [2:0] io_input_ar_payload_size, + input [1:0] io_input_ar_payload_burst, + input [0:0] io_input_ar_payload_lock, + input [3:0] io_input_ar_payload_cache, + input [3:0] io_input_ar_payload_qos, + input [2:0] io_input_ar_payload_prot, + output io_input_r_valid, + input io_input_r_ready, + output [31:0] io_input_r_payload_data, + output [7:0] io_input_r_payload_id, + output [1:0] io_input_r_payload_resp, + output io_input_r_payload_last, + output io_output_aw_valid, + input io_output_aw_ready, + output [31:0] io_output_aw_payload_addr, + output [7:0] io_output_aw_payload_id, + output [3:0] io_output_aw_payload_region, + output [7:0] io_output_aw_payload_len, + output [2:0] io_output_aw_payload_size, + output [1:0] io_output_aw_payload_burst, + output [0:0] io_output_aw_payload_lock, + output [3:0] io_output_aw_payload_cache, + output [3:0] io_output_aw_payload_qos, + output [2:0] io_output_aw_payload_prot, + output io_output_w_valid, + input io_output_w_ready, + output [255:0] io_output_w_payload_data, + output [31:0] io_output_w_payload_strb, + output io_output_w_payload_last, + input io_output_b_valid, + output io_output_b_ready, + input [7:0] io_output_b_payload_id, + input [1:0] io_output_b_payload_resp, + output io_output_ar_valid, + input io_output_ar_ready, + output [31:0] io_output_ar_payload_addr, + output [7:0] io_output_ar_payload_id, + output [3:0] io_output_ar_payload_region, + output [7:0] io_output_ar_payload_len, + output [2:0] io_output_ar_payload_size, + output [1:0] io_output_ar_payload_burst, + output [0:0] io_output_ar_payload_lock, + output [3:0] io_output_ar_payload_cache, + output [3:0] io_output_ar_payload_qos, + output [2:0] io_output_ar_payload_prot, + input io_output_r_valid, + output io_output_r_ready, + input [255:0] io_output_r_payload_data, + input [7:0] io_output_r_payload_id, + input [1:0] io_output_r_payload_resp, + input io_output_r_payload_last, + input clk, + input reset +); + + wire readOnly_io_input_ar_ready; + wire readOnly_io_input_r_valid; + wire [31:0] readOnly_io_input_r_payload_data; + wire [7:0] readOnly_io_input_r_payload_id; + wire [1:0] readOnly_io_input_r_payload_resp; + wire readOnly_io_input_r_payload_last; + wire readOnly_io_output_ar_valid; + wire [31:0] readOnly_io_output_ar_payload_addr; + wire [7:0] readOnly_io_output_ar_payload_id; + wire [3:0] readOnly_io_output_ar_payload_region; + wire [7:0] readOnly_io_output_ar_payload_len; + wire [2:0] readOnly_io_output_ar_payload_size; + wire [1:0] readOnly_io_output_ar_payload_burst; + wire [0:0] readOnly_io_output_ar_payload_lock; + wire [3:0] readOnly_io_output_ar_payload_cache; + wire [3:0] readOnly_io_output_ar_payload_qos; + wire [2:0] readOnly_io_output_ar_payload_prot; + wire readOnly_io_output_r_ready; + wire writeOnly_io_input_aw_ready; + wire writeOnly_io_input_w_ready; + wire writeOnly_io_input_b_valid; + wire [7:0] writeOnly_io_input_b_payload_id; + wire [1:0] writeOnly_io_input_b_payload_resp; + wire writeOnly_io_output_aw_valid; + wire [31:0] writeOnly_io_output_aw_payload_addr; + wire [7:0] writeOnly_io_output_aw_payload_id; + wire [3:0] writeOnly_io_output_aw_payload_region; + wire [7:0] writeOnly_io_output_aw_payload_len; + wire [2:0] writeOnly_io_output_aw_payload_size; + wire [1:0] writeOnly_io_output_aw_payload_burst; + wire [0:0] writeOnly_io_output_aw_payload_lock; + wire [3:0] writeOnly_io_output_aw_payload_cache; + wire [3:0] writeOnly_io_output_aw_payload_qos; + wire [2:0] writeOnly_io_output_aw_payload_prot; + wire writeOnly_io_output_w_valid; + wire [255:0] writeOnly_io_output_w_payload_data; + wire [31:0] writeOnly_io_output_w_payload_strb; + wire writeOnly_io_output_w_payload_last; + wire writeOnly_io_output_b_ready; + + Asic32To256UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 readOnly ( + .io_input_ar_valid (io_input_ar_valid ), //i + .io_input_ar_ready (readOnly_io_input_ar_ready ), //o + .io_input_ar_payload_addr (io_input_ar_payload_addr[31:0] ), //i + .io_input_ar_payload_id (io_input_ar_payload_id[7:0] ), //i + .io_input_ar_payload_region (io_input_ar_payload_region[3:0] ), //i + .io_input_ar_payload_len (io_input_ar_payload_len[7:0] ), //i + .io_input_ar_payload_size (io_input_ar_payload_size[2:0] ), //i + .io_input_ar_payload_burst (io_input_ar_payload_burst[1:0] ), //i + .io_input_ar_payload_lock (io_input_ar_payload_lock ), //i + .io_input_ar_payload_cache (io_input_ar_payload_cache[3:0] ), //i + .io_input_ar_payload_qos (io_input_ar_payload_qos[3:0] ), //i + .io_input_ar_payload_prot (io_input_ar_payload_prot[2:0] ), //i + .io_input_r_valid (readOnly_io_input_r_valid ), //o + .io_input_r_ready (io_input_r_ready ), //i + .io_input_r_payload_data (readOnly_io_input_r_payload_data[31:0] ), //o + .io_input_r_payload_id (readOnly_io_input_r_payload_id[7:0] ), //o + .io_input_r_payload_resp (readOnly_io_input_r_payload_resp[1:0] ), //o + .io_input_r_payload_last (readOnly_io_input_r_payload_last ), //o + .io_output_ar_valid (readOnly_io_output_ar_valid ), //o + .io_output_ar_ready (io_output_ar_ready ), //i + .io_output_ar_payload_addr (readOnly_io_output_ar_payload_addr[31:0] ), //o + .io_output_ar_payload_id (readOnly_io_output_ar_payload_id[7:0] ), //o + .io_output_ar_payload_region (readOnly_io_output_ar_payload_region[3:0]), //o + .io_output_ar_payload_len (readOnly_io_output_ar_payload_len[7:0] ), //o + .io_output_ar_payload_size (readOnly_io_output_ar_payload_size[2:0] ), //o + .io_output_ar_payload_burst (readOnly_io_output_ar_payload_burst[1:0] ), //o + .io_output_ar_payload_lock (readOnly_io_output_ar_payload_lock ), //o + .io_output_ar_payload_cache (readOnly_io_output_ar_payload_cache[3:0] ), //o + .io_output_ar_payload_qos (readOnly_io_output_ar_payload_qos[3:0] ), //o + .io_output_ar_payload_prot (readOnly_io_output_ar_payload_prot[2:0] ), //o + .io_output_r_valid (io_output_r_valid ), //i + .io_output_r_ready (readOnly_io_output_r_ready ), //o + .io_output_r_payload_data (io_output_r_payload_data[255:0] ), //i + .io_output_r_payload_id (io_output_r_payload_id[7:0] ), //i + .io_output_r_payload_resp (io_output_r_payload_resp[1:0] ), //i + .io_output_r_payload_last (io_output_r_payload_last ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Asic32To256UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 writeOnly ( + .io_input_aw_valid (io_input_aw_valid ), //i + .io_input_aw_ready (writeOnly_io_input_aw_ready ), //o + .io_input_aw_payload_addr (io_input_aw_payload_addr[31:0] ), //i + .io_input_aw_payload_id (io_input_aw_payload_id[7:0] ), //i + .io_input_aw_payload_region (io_input_aw_payload_region[3:0] ), //i + .io_input_aw_payload_len (io_input_aw_payload_len[7:0] ), //i + .io_input_aw_payload_size (io_input_aw_payload_size[2:0] ), //i + .io_input_aw_payload_burst (io_input_aw_payload_burst[1:0] ), //i + .io_input_aw_payload_lock (io_input_aw_payload_lock ), //i + .io_input_aw_payload_cache (io_input_aw_payload_cache[3:0] ), //i + .io_input_aw_payload_qos (io_input_aw_payload_qos[3:0] ), //i + .io_input_aw_payload_prot (io_input_aw_payload_prot[2:0] ), //i + .io_input_w_valid (io_input_w_valid ), //i + .io_input_w_ready (writeOnly_io_input_w_ready ), //o + .io_input_w_payload_data (io_input_w_payload_data[31:0] ), //i + .io_input_w_payload_strb (io_input_w_payload_strb[3:0] ), //i + .io_input_w_payload_last (io_input_w_payload_last ), //i + .io_input_b_valid (writeOnly_io_input_b_valid ), //o + .io_input_b_ready (io_input_b_ready ), //i + .io_input_b_payload_id (writeOnly_io_input_b_payload_id[7:0] ), //o + .io_input_b_payload_resp (writeOnly_io_input_b_payload_resp[1:0] ), //o + .io_output_aw_valid (writeOnly_io_output_aw_valid ), //o + .io_output_aw_ready (io_output_aw_ready ), //i + .io_output_aw_payload_addr (writeOnly_io_output_aw_payload_addr[31:0] ), //o + .io_output_aw_payload_id (writeOnly_io_output_aw_payload_id[7:0] ), //o + .io_output_aw_payload_region (writeOnly_io_output_aw_payload_region[3:0]), //o + .io_output_aw_payload_len (writeOnly_io_output_aw_payload_len[7:0] ), //o + .io_output_aw_payload_size (writeOnly_io_output_aw_payload_size[2:0] ), //o + .io_output_aw_payload_burst (writeOnly_io_output_aw_payload_burst[1:0] ), //o + .io_output_aw_payload_lock (writeOnly_io_output_aw_payload_lock ), //o + .io_output_aw_payload_cache (writeOnly_io_output_aw_payload_cache[3:0] ), //o + .io_output_aw_payload_qos (writeOnly_io_output_aw_payload_qos[3:0] ), //o + .io_output_aw_payload_prot (writeOnly_io_output_aw_payload_prot[2:0] ), //o + .io_output_w_valid (writeOnly_io_output_w_valid ), //o + .io_output_w_ready (io_output_w_ready ), //i + .io_output_w_payload_data (writeOnly_io_output_w_payload_data[255:0] ), //o + .io_output_w_payload_strb (writeOnly_io_output_w_payload_strb[31:0] ), //o + .io_output_w_payload_last (writeOnly_io_output_w_payload_last ), //o + .io_output_b_valid (io_output_b_valid ), //i + .io_output_b_ready (writeOnly_io_output_b_ready ), //o + .io_output_b_payload_id (io_output_b_payload_id[7:0] ), //i + .io_output_b_payload_resp (io_output_b_payload_resp[1:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign io_input_ar_ready = readOnly_io_input_ar_ready; + assign io_input_r_valid = readOnly_io_input_r_valid; + assign io_input_r_payload_data = readOnly_io_input_r_payload_data; + assign io_input_r_payload_id = readOnly_io_input_r_payload_id; + assign io_input_r_payload_resp = readOnly_io_input_r_payload_resp; + assign io_input_r_payload_last = readOnly_io_input_r_payload_last; + assign io_input_aw_ready = writeOnly_io_input_aw_ready; + assign io_input_w_ready = writeOnly_io_input_w_ready; + assign io_input_b_valid = writeOnly_io_input_b_valid; + assign io_input_b_payload_id = writeOnly_io_input_b_payload_id; + assign io_input_b_payload_resp = writeOnly_io_input_b_payload_resp; + assign io_output_ar_valid = readOnly_io_output_ar_valid; + assign io_output_ar_payload_addr = readOnly_io_output_ar_payload_addr; + assign io_output_ar_payload_id = readOnly_io_output_ar_payload_id; + assign io_output_ar_payload_region = readOnly_io_output_ar_payload_region; + assign io_output_ar_payload_len = readOnly_io_output_ar_payload_len; + assign io_output_ar_payload_size = readOnly_io_output_ar_payload_size; + assign io_output_ar_payload_burst = readOnly_io_output_ar_payload_burst; + assign io_output_ar_payload_lock = readOnly_io_output_ar_payload_lock; + assign io_output_ar_payload_cache = readOnly_io_output_ar_payload_cache; + assign io_output_ar_payload_qos = readOnly_io_output_ar_payload_qos; + assign io_output_ar_payload_prot = readOnly_io_output_ar_payload_prot; + assign io_output_r_ready = readOnly_io_output_r_ready; + assign io_output_aw_valid = writeOnly_io_output_aw_valid; + assign io_output_aw_payload_addr = writeOnly_io_output_aw_payload_addr; + assign io_output_aw_payload_id = writeOnly_io_output_aw_payload_id; + assign io_output_aw_payload_region = writeOnly_io_output_aw_payload_region; + assign io_output_aw_payload_len = writeOnly_io_output_aw_payload_len; + assign io_output_aw_payload_size = writeOnly_io_output_aw_payload_size; + assign io_output_aw_payload_burst = writeOnly_io_output_aw_payload_burst; + assign io_output_aw_payload_lock = writeOnly_io_output_aw_payload_lock; + assign io_output_aw_payload_cache = writeOnly_io_output_aw_payload_cache; + assign io_output_aw_payload_qos = writeOnly_io_output_aw_payload_qos; + assign io_output_aw_payload_prot = writeOnly_io_output_aw_payload_prot; + assign io_output_w_valid = writeOnly_io_output_w_valid; + assign io_output_w_payload_data = writeOnly_io_output_w_payload_data; + assign io_output_w_payload_strb = writeOnly_io_output_w_payload_strb; + assign io_output_w_payload_last = writeOnly_io_output_w_payload_last; + assign io_output_b_ready = writeOnly_io_output_b_ready; + +endmodule + +module Asic32To256UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_aw_valid, + output reg io_input_aw_ready, + input [31:0] io_input_aw_payload_addr, + input [7:0] io_input_aw_payload_id, + input [3:0] io_input_aw_payload_region, + input [7:0] io_input_aw_payload_len, + input [2:0] io_input_aw_payload_size, + input [1:0] io_input_aw_payload_burst, + input [0:0] io_input_aw_payload_lock, + input [3:0] io_input_aw_payload_cache, + input [3:0] io_input_aw_payload_qos, + input [2:0] io_input_aw_payload_prot, + input io_input_w_valid, + output io_input_w_ready, + input [31:0] io_input_w_payload_data, + input [3:0] io_input_w_payload_strb, + input io_input_w_payload_last, + output io_input_b_valid, + input io_input_b_ready, + output [7:0] io_input_b_payload_id, + output [1:0] io_input_b_payload_resp, + output io_output_aw_valid, + input io_output_aw_ready, + output [31:0] io_output_aw_payload_addr, + output [7:0] io_output_aw_payload_id, + output [3:0] io_output_aw_payload_region, + output reg [7:0] io_output_aw_payload_len, + output reg [2:0] io_output_aw_payload_size, + output [1:0] io_output_aw_payload_burst, + output [0:0] io_output_aw_payload_lock, + output [3:0] io_output_aw_payload_cache, + output [3:0] io_output_aw_payload_qos, + output [2:0] io_output_aw_payload_prot, + output io_output_w_valid, + input io_output_w_ready, + output [255:0] io_output_w_payload_data, + output [31:0] io_output_w_payload_strb, + output io_output_w_payload_last, + input io_output_b_valid, + output io_output_b_ready, + input [7:0] io_output_b_payload_id, + input [1:0] io_output_b_payload_resp, + input clk, + input reset +); + + wire [14:0] _zz_cmdLogic_byteCount; + wire [10:0] _zz_cmdLogic_incrLen; + wire [10:0] _zz_cmdLogic_incrLen_1; + wire [4:0] _zz_cmdLogic_incrLen_2; + wire [5:0] _zz_dataLogic_byteCounterNext; + wire [7:0] _zz_dataLogic_byteCounterNext_1; + reg [31:0] _zz_dataLogic_byteActivity; + wire cmdLogic_outputFork_valid; + wire cmdLogic_outputFork_ready; + wire [31:0] cmdLogic_outputFork_payload_addr; + wire [7:0] cmdLogic_outputFork_payload_id; + wire [3:0] cmdLogic_outputFork_payload_region; + wire [7:0] cmdLogic_outputFork_payload_len; + wire [2:0] cmdLogic_outputFork_payload_size; + wire [1:0] cmdLogic_outputFork_payload_burst; + wire [0:0] cmdLogic_outputFork_payload_lock; + wire [3:0] cmdLogic_outputFork_payload_cache; + wire [3:0] cmdLogic_outputFork_payload_qos; + wire [2:0] cmdLogic_outputFork_payload_prot; + wire cmdLogic_dataFork_valid; + wire cmdLogic_dataFork_ready; + wire [31:0] cmdLogic_dataFork_payload_addr; + wire [7:0] cmdLogic_dataFork_payload_id; + wire [3:0] cmdLogic_dataFork_payload_region; + wire [7:0] cmdLogic_dataFork_payload_len; + wire [2:0] cmdLogic_dataFork_payload_size; + wire [1:0] cmdLogic_dataFork_payload_burst; + wire [0:0] cmdLogic_dataFork_payload_lock; + wire [3:0] cmdLogic_dataFork_payload_cache; + wire [3:0] cmdLogic_dataFork_payload_qos; + wire [2:0] cmdLogic_dataFork_payload_prot; + reg io_input_aw_fork2_logic_linkEnable_0; + reg io_input_aw_fork2_logic_linkEnable_1; + wire when_Stream_l993; + wire when_Stream_l993_1; + wire cmdLogic_outputFork_fire; + wire cmdLogic_dataFork_fire; + wire [9:0] cmdLogic_byteCount; + wire [5:0] cmdLogic_incrLen; + wire when_Axi4Upsizer_l21; + wire when_Axi4Upsizer_l24; + reg [4:0] dataLogic_byteCounter; + reg [2:0] dataLogic_size; + reg dataLogic_outputValid; + reg dataLogic_outputLast; + reg dataLogic_busy; + reg dataLogic_incrementByteCounter; + reg dataLogic_alwaysFire; + wire [5:0] dataLogic_byteCounterNext; + reg [255:0] dataLogic_dataBuffer; + reg [31:0] dataLogic_maskBuffer; + wire [31:0] dataLogic_byteActivity; + wire io_output_w_fire; + wire io_output_w_isStall; + wire io_input_w_fire; + wire when_Axi4Upsizer_l59; + wire when_Axi4Upsizer_l59_1; + wire when_Axi4Upsizer_l59_2; + wire when_Axi4Upsizer_l59_3; + wire when_Axi4Upsizer_l59_4; + wire when_Axi4Upsizer_l59_5; + wire when_Axi4Upsizer_l59_6; + wire when_Axi4Upsizer_l59_7; + wire when_Axi4Upsizer_l59_8; + wire when_Axi4Upsizer_l59_9; + wire when_Axi4Upsizer_l59_10; + wire when_Axi4Upsizer_l59_11; + wire when_Axi4Upsizer_l59_12; + wire when_Axi4Upsizer_l59_13; + wire when_Axi4Upsizer_l59_14; + wire when_Axi4Upsizer_l59_15; + wire when_Axi4Upsizer_l59_16; + wire when_Axi4Upsizer_l59_17; + wire when_Axi4Upsizer_l59_18; + wire when_Axi4Upsizer_l59_19; + wire when_Axi4Upsizer_l59_20; + wire when_Axi4Upsizer_l59_21; + wire when_Axi4Upsizer_l59_22; + wire when_Axi4Upsizer_l59_23; + wire when_Axi4Upsizer_l59_24; + wire when_Axi4Upsizer_l59_25; + wire when_Axi4Upsizer_l59_26; + wire when_Axi4Upsizer_l59_27; + wire when_Axi4Upsizer_l59_28; + wire when_Axi4Upsizer_l59_29; + wire when_Axi4Upsizer_l59_30; + wire when_Axi4Upsizer_l59_31; + wire cmdLogic_dataFork_fire_1; + wire when_Axi4Upsizer_l68; + wire when_Axi4Upsizer_l68_1; + wire when_Axi4Upsizer_l68_2; + wire when_Axi4Upsizer_l68_3; + wire when_Axi4Upsizer_l68_4; + + assign _zz_cmdLogic_byteCount = ({7'd0,io_input_aw_payload_len} <<< io_input_aw_payload_size); + assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); + assign _zz_cmdLogic_incrLen_2 = io_input_aw_payload_addr[4 : 0]; + assign _zz_cmdLogic_incrLen_1 = {6'd0, _zz_cmdLogic_incrLen_2}; + assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); + assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[5:0]; + always @(*) begin + case(dataLogic_size) + 3'b000 : _zz_dataLogic_byteActivity = 32'h00000001; + 3'b001 : _zz_dataLogic_byteActivity = 32'h00000003; + 3'b010 : _zz_dataLogic_byteActivity = 32'h0000000f; + 3'b011 : _zz_dataLogic_byteActivity = 32'h000000ff; + default : _zz_dataLogic_byteActivity = 32'h0000ffff; + endcase + end + + always @(*) begin + io_input_aw_ready = 1'b1; + if(when_Stream_l993) begin + io_input_aw_ready = 1'b0; + end + if(when_Stream_l993_1) begin + io_input_aw_ready = 1'b0; + end + end + + assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_aw_fork2_logic_linkEnable_0); + assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_aw_fork2_logic_linkEnable_1); + assign cmdLogic_outputFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_0); + assign cmdLogic_outputFork_payload_addr = io_input_aw_payload_addr; + assign cmdLogic_outputFork_payload_id = io_input_aw_payload_id; + assign cmdLogic_outputFork_payload_region = io_input_aw_payload_region; + assign cmdLogic_outputFork_payload_len = io_input_aw_payload_len; + assign cmdLogic_outputFork_payload_size = io_input_aw_payload_size; + assign cmdLogic_outputFork_payload_burst = io_input_aw_payload_burst; + assign cmdLogic_outputFork_payload_lock = io_input_aw_payload_lock; + assign cmdLogic_outputFork_payload_cache = io_input_aw_payload_cache; + assign cmdLogic_outputFork_payload_qos = io_input_aw_payload_qos; + assign cmdLogic_outputFork_payload_prot = io_input_aw_payload_prot; + assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); + assign cmdLogic_dataFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_1); + assign cmdLogic_dataFork_payload_addr = io_input_aw_payload_addr; + assign cmdLogic_dataFork_payload_id = io_input_aw_payload_id; + assign cmdLogic_dataFork_payload_region = io_input_aw_payload_region; + assign cmdLogic_dataFork_payload_len = io_input_aw_payload_len; + assign cmdLogic_dataFork_payload_size = io_input_aw_payload_size; + assign cmdLogic_dataFork_payload_burst = io_input_aw_payload_burst; + assign cmdLogic_dataFork_payload_lock = io_input_aw_payload_lock; + assign cmdLogic_dataFork_payload_cache = io_input_aw_payload_cache; + assign cmdLogic_dataFork_payload_qos = io_input_aw_payload_qos; + assign cmdLogic_dataFork_payload_prot = io_input_aw_payload_prot; + assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign io_output_aw_valid = cmdLogic_outputFork_valid; + assign cmdLogic_outputFork_ready = io_output_aw_ready; + assign io_output_aw_payload_addr = cmdLogic_outputFork_payload_addr; + assign io_output_aw_payload_id = cmdLogic_outputFork_payload_id; + assign io_output_aw_payload_region = cmdLogic_outputFork_payload_region; + always @(*) begin + io_output_aw_payload_len = cmdLogic_outputFork_payload_len; + if(when_Axi4Upsizer_l21) begin + io_output_aw_payload_len = {2'd0, cmdLogic_incrLen}; + end + end + + always @(*) begin + io_output_aw_payload_size = cmdLogic_outputFork_payload_size; + if(when_Axi4Upsizer_l21) begin + io_output_aw_payload_size = 3'b101; + if(when_Axi4Upsizer_l24) begin + io_output_aw_payload_size = io_input_aw_payload_size; + end + end + end + + assign io_output_aw_payload_burst = cmdLogic_outputFork_payload_burst; + assign io_output_aw_payload_lock = cmdLogic_outputFork_payload_lock; + assign io_output_aw_payload_cache = cmdLogic_outputFork_payload_cache; + assign io_output_aw_payload_qos = cmdLogic_outputFork_payload_qos; + assign io_output_aw_payload_prot = cmdLogic_outputFork_payload_prot; + assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; + assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 5]; + assign when_Axi4Upsizer_l21 = (io_output_aw_payload_burst == 2'b01); + assign when_Axi4Upsizer_l24 = (io_input_aw_payload_len == 8'h00); + assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); + assign dataLogic_byteActivity = (_zz_dataLogic_byteActivity <<< dataLogic_byteCounter); + assign io_output_w_fire = (io_output_w_valid && io_output_w_ready); + assign io_output_w_valid = dataLogic_outputValid; + assign io_output_w_isStall = (io_output_w_valid && (! io_output_w_ready)); + assign io_input_w_ready = (dataLogic_busy && (! io_output_w_isStall)); + assign io_output_w_payload_data = dataLogic_dataBuffer; + assign io_output_w_payload_strb = dataLogic_maskBuffer; + assign io_output_w_payload_last = dataLogic_outputLast; + assign io_input_w_fire = (io_input_w_valid && io_input_w_ready); + assign when_Axi4Upsizer_l59 = dataLogic_byteActivity[0]; + assign when_Axi4Upsizer_l59_1 = dataLogic_byteActivity[1]; + assign when_Axi4Upsizer_l59_2 = dataLogic_byteActivity[2]; + assign when_Axi4Upsizer_l59_3 = dataLogic_byteActivity[3]; + assign when_Axi4Upsizer_l59_4 = dataLogic_byteActivity[4]; + assign when_Axi4Upsizer_l59_5 = dataLogic_byteActivity[5]; + assign when_Axi4Upsizer_l59_6 = dataLogic_byteActivity[6]; + assign when_Axi4Upsizer_l59_7 = dataLogic_byteActivity[7]; + assign when_Axi4Upsizer_l59_8 = dataLogic_byteActivity[8]; + assign when_Axi4Upsizer_l59_9 = dataLogic_byteActivity[9]; + assign when_Axi4Upsizer_l59_10 = dataLogic_byteActivity[10]; + assign when_Axi4Upsizer_l59_11 = dataLogic_byteActivity[11]; + assign when_Axi4Upsizer_l59_12 = dataLogic_byteActivity[12]; + assign when_Axi4Upsizer_l59_13 = dataLogic_byteActivity[13]; + assign when_Axi4Upsizer_l59_14 = dataLogic_byteActivity[14]; + assign when_Axi4Upsizer_l59_15 = dataLogic_byteActivity[15]; + assign when_Axi4Upsizer_l59_16 = dataLogic_byteActivity[16]; + assign when_Axi4Upsizer_l59_17 = dataLogic_byteActivity[17]; + assign when_Axi4Upsizer_l59_18 = dataLogic_byteActivity[18]; + assign when_Axi4Upsizer_l59_19 = dataLogic_byteActivity[19]; + assign when_Axi4Upsizer_l59_20 = dataLogic_byteActivity[20]; + assign when_Axi4Upsizer_l59_21 = dataLogic_byteActivity[21]; + assign when_Axi4Upsizer_l59_22 = dataLogic_byteActivity[22]; + assign when_Axi4Upsizer_l59_23 = dataLogic_byteActivity[23]; + assign when_Axi4Upsizer_l59_24 = dataLogic_byteActivity[24]; + assign when_Axi4Upsizer_l59_25 = dataLogic_byteActivity[25]; + assign when_Axi4Upsizer_l59_26 = dataLogic_byteActivity[26]; + assign when_Axi4Upsizer_l59_27 = dataLogic_byteActivity[27]; + assign when_Axi4Upsizer_l59_28 = dataLogic_byteActivity[28]; + assign when_Axi4Upsizer_l59_29 = dataLogic_byteActivity[29]; + assign when_Axi4Upsizer_l59_30 = dataLogic_byteActivity[30]; + assign when_Axi4Upsizer_l59_31 = dataLogic_byteActivity[31]; + assign cmdLogic_dataFork_fire_1 = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign when_Axi4Upsizer_l68 = (3'b000 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_1 = (3'b001 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_2 = (3'b010 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_3 = (3'b011 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_4 = (3'b100 < cmdLogic_dataFork_payload_size); + assign cmdLogic_dataFork_ready = (! dataLogic_busy); + assign io_input_b_valid = io_output_b_valid; + assign io_output_b_ready = io_input_b_ready; + assign io_input_b_payload_id = io_output_b_payload_id; + assign io_input_b_payload_resp = io_output_b_payload_resp; + always @(posedge clk or posedge reset) begin + if(reset) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; + io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; + dataLogic_outputValid <= 1'b0; + dataLogic_busy <= 1'b0; + dataLogic_maskBuffer <= 32'h00000000; + end else begin + if(cmdLogic_outputFork_fire) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdLogic_dataFork_fire) begin + io_input_aw_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_aw_ready) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; + io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; + end + if(io_output_w_ready) begin + dataLogic_outputValid <= 1'b0; + end + if(io_output_w_fire) begin + dataLogic_maskBuffer <= 32'h00000000; + end + if(io_input_w_fire) begin + dataLogic_outputValid <= ((dataLogic_byteCounterNext[5] || io_input_w_payload_last) || dataLogic_alwaysFire); + if(io_input_w_payload_last) begin + dataLogic_busy <= 1'b0; + end + if(when_Axi4Upsizer_l59) begin + dataLogic_maskBuffer[0] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_1) begin + dataLogic_maskBuffer[1] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_2) begin + dataLogic_maskBuffer[2] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_3) begin + dataLogic_maskBuffer[3] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_4) begin + dataLogic_maskBuffer[4] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_5) begin + dataLogic_maskBuffer[5] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_6) begin + dataLogic_maskBuffer[6] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_7) begin + dataLogic_maskBuffer[7] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_8) begin + dataLogic_maskBuffer[8] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_9) begin + dataLogic_maskBuffer[9] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_10) begin + dataLogic_maskBuffer[10] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_11) begin + dataLogic_maskBuffer[11] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_12) begin + dataLogic_maskBuffer[12] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_13) begin + dataLogic_maskBuffer[13] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_14) begin + dataLogic_maskBuffer[14] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_15) begin + dataLogic_maskBuffer[15] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_16) begin + dataLogic_maskBuffer[16] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_17) begin + dataLogic_maskBuffer[17] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_18) begin + dataLogic_maskBuffer[18] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_19) begin + dataLogic_maskBuffer[19] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_20) begin + dataLogic_maskBuffer[20] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_21) begin + dataLogic_maskBuffer[21] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_22) begin + dataLogic_maskBuffer[22] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_23) begin + dataLogic_maskBuffer[23] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_24) begin + dataLogic_maskBuffer[24] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_25) begin + dataLogic_maskBuffer[25] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_26) begin + dataLogic_maskBuffer[26] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_27) begin + dataLogic_maskBuffer[27] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_28) begin + dataLogic_maskBuffer[28] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_29) begin + dataLogic_maskBuffer[29] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_30) begin + dataLogic_maskBuffer[30] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_31) begin + dataLogic_maskBuffer[31] <= io_input_w_payload_strb[3]; + end + end + if(cmdLogic_dataFork_fire_1) begin + dataLogic_busy <= 1'b1; + end + end + end + + always @(posedge clk) begin + if(io_input_w_fire) begin + if(dataLogic_incrementByteCounter) begin + dataLogic_byteCounter <= dataLogic_byteCounterNext[4:0]; + end + dataLogic_outputLast <= io_input_w_payload_last; + if(when_Axi4Upsizer_l59) begin + dataLogic_dataBuffer[7 : 0] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_1) begin + dataLogic_dataBuffer[15 : 8] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_2) begin + dataLogic_dataBuffer[23 : 16] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_3) begin + dataLogic_dataBuffer[31 : 24] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_4) begin + dataLogic_dataBuffer[39 : 32] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_5) begin + dataLogic_dataBuffer[47 : 40] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_6) begin + dataLogic_dataBuffer[55 : 48] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_7) begin + dataLogic_dataBuffer[63 : 56] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_8) begin + dataLogic_dataBuffer[71 : 64] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_9) begin + dataLogic_dataBuffer[79 : 72] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_10) begin + dataLogic_dataBuffer[87 : 80] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_11) begin + dataLogic_dataBuffer[95 : 88] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_12) begin + dataLogic_dataBuffer[103 : 96] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_13) begin + dataLogic_dataBuffer[111 : 104] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_14) begin + dataLogic_dataBuffer[119 : 112] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_15) begin + dataLogic_dataBuffer[127 : 120] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_16) begin + dataLogic_dataBuffer[135 : 128] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_17) begin + dataLogic_dataBuffer[143 : 136] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_18) begin + dataLogic_dataBuffer[151 : 144] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_19) begin + dataLogic_dataBuffer[159 : 152] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_20) begin + dataLogic_dataBuffer[167 : 160] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_21) begin + dataLogic_dataBuffer[175 : 168] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_22) begin + dataLogic_dataBuffer[183 : 176] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_23) begin + dataLogic_dataBuffer[191 : 184] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_24) begin + dataLogic_dataBuffer[199 : 192] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_25) begin + dataLogic_dataBuffer[207 : 200] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_26) begin + dataLogic_dataBuffer[215 : 208] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_27) begin + dataLogic_dataBuffer[223 : 216] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_28) begin + dataLogic_dataBuffer[231 : 224] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_29) begin + dataLogic_dataBuffer[239 : 232] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_30) begin + dataLogic_dataBuffer[247 : 240] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_31) begin + dataLogic_dataBuffer[255 : 248] <= io_input_w_payload_data[31 : 24]; + end + end + if(cmdLogic_dataFork_fire_1) begin + dataLogic_byteCounter <= cmdLogic_dataFork_payload_addr[4:0]; + if(when_Axi4Upsizer_l68) begin + dataLogic_byteCounter[0] <= 1'b0; + end + if(when_Axi4Upsizer_l68_1) begin + dataLogic_byteCounter[1] <= 1'b0; + end + if(when_Axi4Upsizer_l68_2) begin + dataLogic_byteCounter[2] <= 1'b0; + end + if(when_Axi4Upsizer_l68_3) begin + dataLogic_byteCounter[3] <= 1'b0; + end + if(when_Axi4Upsizer_l68_4) begin + dataLogic_byteCounter[4] <= 1'b0; + end + dataLogic_size <= cmdLogic_dataFork_payload_size; + dataLogic_alwaysFire <= (! (cmdLogic_dataFork_payload_burst == 2'b01)); + dataLogic_incrementByteCounter <= (! (cmdLogic_dataFork_payload_burst == 2'b00)); + end + end + + +endmodule + +module Asic32To256UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_ar_valid, + output reg io_input_ar_ready, + input [31:0] io_input_ar_payload_addr, + input [7:0] io_input_ar_payload_id, + input [3:0] io_input_ar_payload_region, + input [7:0] io_input_ar_payload_len, + input [2:0] io_input_ar_payload_size, + input [1:0] io_input_ar_payload_burst, + input [0:0] io_input_ar_payload_lock, + input [3:0] io_input_ar_payload_cache, + input [3:0] io_input_ar_payload_qos, + input [2:0] io_input_ar_payload_prot, + output io_input_r_valid, + input io_input_r_ready, + output [31:0] io_input_r_payload_data, + output [7:0] io_input_r_payload_id, + output [1:0] io_input_r_payload_resp, + output io_input_r_payload_last, + output io_output_ar_valid, + input io_output_ar_ready, + output [31:0] io_output_ar_payload_addr, + output [7:0] io_output_ar_payload_id, + output [3:0] io_output_ar_payload_region, + output [7:0] io_output_ar_payload_len, + output reg [2:0] io_output_ar_payload_size, + output [1:0] io_output_ar_payload_burst, + output [0:0] io_output_ar_payload_lock, + output [3:0] io_output_ar_payload_cache, + output [3:0] io_output_ar_payload_qos, + output [2:0] io_output_ar_payload_prot, + input io_output_r_valid, + output io_output_r_ready, + input [255:0] io_output_r_payload_data, + input [7:0] io_output_r_payload_id, + input [1:0] io_output_r_payload_resp, + input io_output_r_payload_last, + input clk, + input reset +); + + wire dataLogic_cmdPush_fifo_io_pop_ready; + wire dataLogic_cmdPush_fifo_io_push_ready; + wire dataLogic_cmdPush_fifo_io_pop_valid; + wire [4:0] dataLogic_cmdPush_fifo_io_pop_payload_startAt; + wire [4:0] dataLogic_cmdPush_fifo_io_pop_payload_endAt; + wire [2:0] dataLogic_cmdPush_fifo_io_pop_payload_size; + wire [7:0] dataLogic_cmdPush_fifo_io_pop_payload_id; + wire [4:0] dataLogic_cmdPush_fifo_io_occupancy; + wire [4:0] dataLogic_cmdPush_fifo_io_availability; + wire [14:0] _zz_cmdLogic_byteCount; + wire [10:0] _zz_cmdLogic_incrLen; + wire [10:0] _zz_cmdLogic_incrLen_1; + wire [4:0] _zz_cmdLogic_incrLen_2; + wire [31:0] _zz_dataLogic_cmdPush_payload_endAt; + wire [31:0] _zz_dataLogic_cmdPush_payload_endAt_1; + wire [14:0] _zz_dataLogic_cmdPush_payload_endAt_2; + wire [5:0] _zz_dataLogic_byteCounterNext; + wire [7:0] _zz_dataLogic_byteCounterNext_1; + reg [31:0] _zz_io_input_r_payload_data; + wire [2:0] _zz_io_input_r_payload_data_1; + wire cmdLogic_outputFork_valid; + wire cmdLogic_outputFork_ready; + wire [31:0] cmdLogic_outputFork_payload_addr; + wire [7:0] cmdLogic_outputFork_payload_id; + wire [3:0] cmdLogic_outputFork_payload_region; + wire [7:0] cmdLogic_outputFork_payload_len; + wire [2:0] cmdLogic_outputFork_payload_size; + wire [1:0] cmdLogic_outputFork_payload_burst; + wire [0:0] cmdLogic_outputFork_payload_lock; + wire [3:0] cmdLogic_outputFork_payload_cache; + wire [3:0] cmdLogic_outputFork_payload_qos; + wire [2:0] cmdLogic_outputFork_payload_prot; + wire cmdLogic_dataFork_valid; + wire cmdLogic_dataFork_ready; + wire [31:0] cmdLogic_dataFork_payload_addr; + wire [7:0] cmdLogic_dataFork_payload_id; + wire [3:0] cmdLogic_dataFork_payload_region; + wire [7:0] cmdLogic_dataFork_payload_len; + wire [2:0] cmdLogic_dataFork_payload_size; + wire [1:0] cmdLogic_dataFork_payload_burst; + wire [0:0] cmdLogic_dataFork_payload_lock; + wire [3:0] cmdLogic_dataFork_payload_cache; + wire [3:0] cmdLogic_dataFork_payload_qos; + wire [2:0] cmdLogic_dataFork_payload_prot; + reg io_input_ar_fork2_logic_linkEnable_0; + reg io_input_ar_fork2_logic_linkEnable_1; + wire when_Stream_l993; + wire when_Stream_l993_1; + wire cmdLogic_outputFork_fire; + wire cmdLogic_dataFork_fire; + wire [9:0] cmdLogic_byteCount; + wire [5:0] cmdLogic_incrLen; + wire when_Axi4Upsizer_l108; + wire dataLogic_cmdPush_valid; + wire dataLogic_cmdPush_ready; + wire [4:0] dataLogic_cmdPush_payload_startAt; + wire [4:0] dataLogic_cmdPush_payload_endAt; + wire [2:0] dataLogic_cmdPush_payload_size; + wire [7:0] dataLogic_cmdPush_payload_id; + reg [2:0] dataLogic_size; + reg dataLogic_busy; + reg [7:0] dataLogic_id; + reg [4:0] dataLogic_byteCounter; + reg [4:0] dataLogic_byteCounterLast; + wire [5:0] dataLogic_byteCounterNext; + wire readOnly_dataLogic_cmdPush_fifo_io_pop_fire; + wire io_input_r_fire; + + assign _zz_cmdLogic_byteCount = ({7'd0,io_input_ar_payload_len} <<< io_input_ar_payload_size); + assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); + assign _zz_cmdLogic_incrLen_2 = io_input_ar_payload_addr[4 : 0]; + assign _zz_cmdLogic_incrLen_1 = {6'd0, _zz_cmdLogic_incrLen_2}; + assign _zz_dataLogic_cmdPush_payload_endAt = (cmdLogic_dataFork_payload_addr + _zz_dataLogic_cmdPush_payload_endAt_1); + assign _zz_dataLogic_cmdPush_payload_endAt_2 = ({7'd0,cmdLogic_dataFork_payload_len} <<< cmdLogic_dataFork_payload_size); + assign _zz_dataLogic_cmdPush_payload_endAt_1 = {17'd0, _zz_dataLogic_cmdPush_payload_endAt_2}; + assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); + assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[5:0]; + assign _zz_io_input_r_payload_data_1 = (dataLogic_byteCounter >>> 2'd2); + Asic32To256UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 dataLogic_cmdPush_fifo ( + .io_push_valid (dataLogic_cmdPush_valid ), //i + .io_push_ready (dataLogic_cmdPush_fifo_io_push_ready ), //o + .io_push_payload_startAt (dataLogic_cmdPush_payload_startAt[4:0] ), //i + .io_push_payload_endAt (dataLogic_cmdPush_payload_endAt[4:0] ), //i + .io_push_payload_size (dataLogic_cmdPush_payload_size[2:0] ), //i + .io_push_payload_id (dataLogic_cmdPush_payload_id[7:0] ), //i + .io_pop_valid (dataLogic_cmdPush_fifo_io_pop_valid ), //o + .io_pop_ready (dataLogic_cmdPush_fifo_io_pop_ready ), //i + .io_pop_payload_startAt (dataLogic_cmdPush_fifo_io_pop_payload_startAt[4:0]), //o + .io_pop_payload_endAt (dataLogic_cmdPush_fifo_io_pop_payload_endAt[4:0] ), //o + .io_pop_payload_size (dataLogic_cmdPush_fifo_io_pop_payload_size[2:0] ), //o + .io_pop_payload_id (dataLogic_cmdPush_fifo_io_pop_payload_id[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (dataLogic_cmdPush_fifo_io_occupancy[4:0] ), //o + .io_availability (dataLogic_cmdPush_fifo_io_availability[4:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_io_input_r_payload_data_1) + 3'b000 : _zz_io_input_r_payload_data = io_output_r_payload_data[31 : 0]; + 3'b001 : _zz_io_input_r_payload_data = io_output_r_payload_data[63 : 32]; + 3'b010 : _zz_io_input_r_payload_data = io_output_r_payload_data[95 : 64]; + 3'b011 : _zz_io_input_r_payload_data = io_output_r_payload_data[127 : 96]; + 3'b100 : _zz_io_input_r_payload_data = io_output_r_payload_data[159 : 128]; + 3'b101 : _zz_io_input_r_payload_data = io_output_r_payload_data[191 : 160]; + 3'b110 : _zz_io_input_r_payload_data = io_output_r_payload_data[223 : 192]; + default : _zz_io_input_r_payload_data = io_output_r_payload_data[255 : 224]; + endcase + end + + always @(*) begin + io_input_ar_ready = 1'b1; + if(when_Stream_l993) begin + io_input_ar_ready = 1'b0; + end + if(when_Stream_l993_1) begin + io_input_ar_ready = 1'b0; + end + end + + assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_ar_fork2_logic_linkEnable_0); + assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_ar_fork2_logic_linkEnable_1); + assign cmdLogic_outputFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_0); + assign cmdLogic_outputFork_payload_addr = io_input_ar_payload_addr; + assign cmdLogic_outputFork_payload_id = io_input_ar_payload_id; + assign cmdLogic_outputFork_payload_region = io_input_ar_payload_region; + assign cmdLogic_outputFork_payload_len = io_input_ar_payload_len; + assign cmdLogic_outputFork_payload_size = io_input_ar_payload_size; + assign cmdLogic_outputFork_payload_burst = io_input_ar_payload_burst; + assign cmdLogic_outputFork_payload_lock = io_input_ar_payload_lock; + assign cmdLogic_outputFork_payload_cache = io_input_ar_payload_cache; + assign cmdLogic_outputFork_payload_qos = io_input_ar_payload_qos; + assign cmdLogic_outputFork_payload_prot = io_input_ar_payload_prot; + assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); + assign cmdLogic_dataFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_1); + assign cmdLogic_dataFork_payload_addr = io_input_ar_payload_addr; + assign cmdLogic_dataFork_payload_id = io_input_ar_payload_id; + assign cmdLogic_dataFork_payload_region = io_input_ar_payload_region; + assign cmdLogic_dataFork_payload_len = io_input_ar_payload_len; + assign cmdLogic_dataFork_payload_size = io_input_ar_payload_size; + assign cmdLogic_dataFork_payload_burst = io_input_ar_payload_burst; + assign cmdLogic_dataFork_payload_lock = io_input_ar_payload_lock; + assign cmdLogic_dataFork_payload_cache = io_input_ar_payload_cache; + assign cmdLogic_dataFork_payload_qos = io_input_ar_payload_qos; + assign cmdLogic_dataFork_payload_prot = io_input_ar_payload_prot; + assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign io_output_ar_valid = cmdLogic_outputFork_valid; + assign cmdLogic_outputFork_ready = io_output_ar_ready; + assign io_output_ar_payload_addr = cmdLogic_outputFork_payload_addr; + assign io_output_ar_payload_region = cmdLogic_outputFork_payload_region; + assign io_output_ar_payload_burst = cmdLogic_outputFork_payload_burst; + assign io_output_ar_payload_lock = cmdLogic_outputFork_payload_lock; + assign io_output_ar_payload_cache = cmdLogic_outputFork_payload_cache; + assign io_output_ar_payload_qos = cmdLogic_outputFork_payload_qos; + assign io_output_ar_payload_prot = cmdLogic_outputFork_payload_prot; + assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; + assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 5]; + always @(*) begin + io_output_ar_payload_size = 3'b101; + if(when_Axi4Upsizer_l108) begin + io_output_ar_payload_size = io_input_ar_payload_size; + end + end + + assign io_output_ar_payload_len = {2'd0, cmdLogic_incrLen}; + assign io_output_ar_payload_id = 8'h00; + assign when_Axi4Upsizer_l108 = (io_input_ar_payload_len == 8'h00); + assign dataLogic_cmdPush_valid = cmdLogic_dataFork_valid; + assign cmdLogic_dataFork_ready = dataLogic_cmdPush_ready; + assign dataLogic_cmdPush_payload_startAt = cmdLogic_dataFork_payload_addr[4:0]; + assign dataLogic_cmdPush_payload_endAt = _zz_dataLogic_cmdPush_payload_endAt[4:0]; + assign dataLogic_cmdPush_payload_size = cmdLogic_dataFork_payload_size; + assign dataLogic_cmdPush_payload_id = cmdLogic_dataFork_payload_id; + assign dataLogic_cmdPush_ready = dataLogic_cmdPush_fifo_io_push_ready; + assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); + assign readOnly_dataLogic_cmdPush_fifo_io_pop_fire = (dataLogic_cmdPush_fifo_io_pop_valid && dataLogic_cmdPush_fifo_io_pop_ready); + assign dataLogic_cmdPush_fifo_io_pop_ready = (! dataLogic_busy); + assign io_input_r_fire = (io_input_r_valid && io_input_r_ready); + assign io_input_r_valid = (io_output_r_valid && dataLogic_busy); + assign io_input_r_payload_last = (io_output_r_payload_last && (dataLogic_byteCounter == dataLogic_byteCounterLast)); + assign io_input_r_payload_resp = io_output_r_payload_resp; + assign io_input_r_payload_data = _zz_io_input_r_payload_data; + assign io_input_r_payload_id = dataLogic_id; + assign io_output_r_ready = ((dataLogic_busy && io_input_r_ready) && (io_input_r_payload_last || dataLogic_byteCounterNext[5])); + always @(posedge clk or posedge reset) begin + if(reset) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; + io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; + dataLogic_busy <= 1'b0; + end else begin + if(cmdLogic_outputFork_fire) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdLogic_dataFork_fire) begin + io_input_ar_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_ar_ready) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; + io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; + end + if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin + dataLogic_busy <= 1'b1; + end + if(io_input_r_fire) begin + if(io_input_r_payload_last) begin + dataLogic_busy <= 1'b0; + end + end + end + end + + always @(posedge clk) begin + if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin + dataLogic_byteCounter <= dataLogic_cmdPush_fifo_io_pop_payload_startAt; + dataLogic_byteCounterLast <= dataLogic_cmdPush_fifo_io_pop_payload_endAt; + dataLogic_size <= dataLogic_cmdPush_fifo_io_pop_payload_size; + dataLogic_id <= dataLogic_cmdPush_fifo_io_pop_payload_id; + end + if(io_input_r_fire) begin + dataLogic_byteCounter <= dataLogic_byteCounterNext[4:0]; + end + end + + +endmodule + +module Asic32To256UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_push_valid, + output io_push_ready, + input [4:0] io_push_payload_startAt, + input [4:0] io_push_payload_endAt, + input [2:0] io_push_payload_size, + input [7:0] io_push_payload_id, + output io_pop_valid, + input io_pop_ready, + output [4:0] io_pop_payload_startAt, + output [4:0] io_pop_payload_endAt, + output [2:0] io_pop_payload_size, + output [7:0] io_pop_payload_id, + input io_flush, + output [4:0] io_occupancy, + output [4:0] io_availability, + input clk, + input reset +); + + reg [20:0] _zz_logic_ram_port0; + wire [3:0] _zz_logic_pushPtr_valueNext; + wire [0:0] _zz_logic_pushPtr_valueNext_1; + wire [3:0] _zz_logic_popPtr_valueNext; + wire [0:0] _zz_logic_popPtr_valueNext_1; + wire _zz__zz_logic_ram_port0; + wire _zz__zz_io_pop_payload_startAt; + wire [20:0] _zz__zz_logic_ram_port1; + wire [3:0] _zz_io_availability; + reg _zz_1; + reg logic_pushPtr_willIncrement; + reg logic_pushPtr_willClear; + reg [3:0] logic_pushPtr_valueNext; + reg [3:0] logic_pushPtr_value; + wire logic_pushPtr_willOverflowIfInc; + wire logic_pushPtr_willOverflow; + reg logic_popPtr_willIncrement; + reg logic_popPtr_willClear; + reg [3:0] logic_popPtr_valueNext; + reg [3:0] logic_popPtr_value; + wire logic_popPtr_willOverflowIfInc; + wire logic_popPtr_willOverflow; + wire logic_ptrMatch; + reg logic_risingOccupancy; + wire logic_pushing; + wire logic_popping; + wire logic_empty; + wire logic_full; + reg _zz_io_pop_valid; + wire [20:0] _zz_io_pop_payload_startAt; + wire when_Stream_l1123; + wire [3:0] logic_ptrDif; + reg [20:0] logic_ram [0:15]; + + assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; + assign _zz_logic_pushPtr_valueNext = {3'd0, _zz_logic_pushPtr_valueNext_1}; + assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; + assign _zz_logic_popPtr_valueNext = {3'd0, _zz_logic_popPtr_valueNext_1}; + assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); + assign _zz__zz_io_pop_payload_startAt = 1'b1; + assign _zz__zz_logic_ram_port1 = {io_push_payload_id,{io_push_payload_size,{io_push_payload_endAt,io_push_payload_startAt}}}; + always @(posedge clk) begin + if(_zz__zz_io_pop_payload_startAt) begin + _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_pushPtr_value] <= _zz__zz_logic_ram_port1; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_pushing) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willIncrement = 1'b0; + if(logic_pushing) begin + logic_pushPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willClear = 1'b0; + if(io_flush) begin + logic_pushPtr_willClear = 1'b1; + end + end + + assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 4'b1111); + assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); + always @(*) begin + logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); + if(logic_pushPtr_willClear) begin + logic_pushPtr_valueNext = 4'b0000; + end + end + + always @(*) begin + logic_popPtr_willIncrement = 1'b0; + if(logic_popping) begin + logic_popPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_popPtr_willClear = 1'b0; + if(io_flush) begin + logic_popPtr_willClear = 1'b1; + end + end + + assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 4'b1111); + assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); + always @(*) begin + logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); + if(logic_popPtr_willClear) begin + logic_popPtr_valueNext = 4'b0000; + end + end + + assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); + assign logic_pushing = (io_push_valid && io_push_ready); + assign logic_popping = (io_pop_valid && io_pop_ready); + assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); + assign logic_full = (logic_ptrMatch && logic_risingOccupancy); + assign io_push_ready = (! logic_full); + assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); + assign _zz_io_pop_payload_startAt = _zz_logic_ram_port0; + assign io_pop_payload_startAt = _zz_io_pop_payload_startAt[4 : 0]; + assign io_pop_payload_endAt = _zz_io_pop_payload_startAt[9 : 5]; + assign io_pop_payload_size = _zz_io_pop_payload_startAt[12 : 10]; + assign io_pop_payload_id = _zz_io_pop_payload_startAt[20 : 13]; + assign when_Stream_l1123 = (logic_pushing != logic_popping); + assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); + assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; + assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; + always @(posedge clk or posedge reset) begin + if(reset) begin + logic_pushPtr_value <= 4'b0000; + logic_popPtr_value <= 4'b0000; + logic_risingOccupancy <= 1'b0; + _zz_io_pop_valid <= 1'b0; + end else begin + logic_pushPtr_value <= logic_pushPtr_valueNext; + logic_popPtr_value <= logic_popPtr_valueNext; + _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); + if(when_Stream_l1123) begin + logic_risingOccupancy <= logic_pushing; + end + if(io_flush) begin + logic_risingOccupancy <= 1'b0; + end + end + end + + +endmodule + + +// Generator : SpinalHDL dev git head : 9cdee03b276638ef8e7a948b606bb7acc6e4c8d0 +// Component : Asic32To512UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 +// Git hash : cd16421fb7a4d44431a2445f9a92b82070ab9b8a + +`timescale 1ns/1ps + +module Asic32To512UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_aw_valid, + output io_input_aw_ready, + input [31:0] io_input_aw_payload_addr, + input [7:0] io_input_aw_payload_id, + input [3:0] io_input_aw_payload_region, + input [7:0] io_input_aw_payload_len, + input [2:0] io_input_aw_payload_size, + input [1:0] io_input_aw_payload_burst, + input [0:0] io_input_aw_payload_lock, + input [3:0] io_input_aw_payload_cache, + input [3:0] io_input_aw_payload_qos, + input [2:0] io_input_aw_payload_prot, + input io_input_w_valid, + output io_input_w_ready, + input [31:0] io_input_w_payload_data, + input [3:0] io_input_w_payload_strb, + input io_input_w_payload_last, + output io_input_b_valid, + input io_input_b_ready, + output [7:0] io_input_b_payload_id, + output [1:0] io_input_b_payload_resp, + input io_input_ar_valid, + output io_input_ar_ready, + input [31:0] io_input_ar_payload_addr, + input [7:0] io_input_ar_payload_id, + input [3:0] io_input_ar_payload_region, + input [7:0] io_input_ar_payload_len, + input [2:0] io_input_ar_payload_size, + input [1:0] io_input_ar_payload_burst, + input [0:0] io_input_ar_payload_lock, + input [3:0] io_input_ar_payload_cache, + input [3:0] io_input_ar_payload_qos, + input [2:0] io_input_ar_payload_prot, + output io_input_r_valid, + input io_input_r_ready, + output [31:0] io_input_r_payload_data, + output [7:0] io_input_r_payload_id, + output [1:0] io_input_r_payload_resp, + output io_input_r_payload_last, + output io_output_aw_valid, + input io_output_aw_ready, + output [31:0] io_output_aw_payload_addr, + output [7:0] io_output_aw_payload_id, + output [3:0] io_output_aw_payload_region, + output [7:0] io_output_aw_payload_len, + output [2:0] io_output_aw_payload_size, + output [1:0] io_output_aw_payload_burst, + output [0:0] io_output_aw_payload_lock, + output [3:0] io_output_aw_payload_cache, + output [3:0] io_output_aw_payload_qos, + output [2:0] io_output_aw_payload_prot, + output io_output_w_valid, + input io_output_w_ready, + output [511:0] io_output_w_payload_data, + output [63:0] io_output_w_payload_strb, + output io_output_w_payload_last, + input io_output_b_valid, + output io_output_b_ready, + input [7:0] io_output_b_payload_id, + input [1:0] io_output_b_payload_resp, + output io_output_ar_valid, + input io_output_ar_ready, + output [31:0] io_output_ar_payload_addr, + output [7:0] io_output_ar_payload_id, + output [3:0] io_output_ar_payload_region, + output [7:0] io_output_ar_payload_len, + output [2:0] io_output_ar_payload_size, + output [1:0] io_output_ar_payload_burst, + output [0:0] io_output_ar_payload_lock, + output [3:0] io_output_ar_payload_cache, + output [3:0] io_output_ar_payload_qos, + output [2:0] io_output_ar_payload_prot, + input io_output_r_valid, + output io_output_r_ready, + input [511:0] io_output_r_payload_data, + input [7:0] io_output_r_payload_id, + input [1:0] io_output_r_payload_resp, + input io_output_r_payload_last, + input clk, + input reset +); + + wire readOnly_io_input_ar_ready; + wire readOnly_io_input_r_valid; + wire [31:0] readOnly_io_input_r_payload_data; + wire [7:0] readOnly_io_input_r_payload_id; + wire [1:0] readOnly_io_input_r_payload_resp; + wire readOnly_io_input_r_payload_last; + wire readOnly_io_output_ar_valid; + wire [31:0] readOnly_io_output_ar_payload_addr; + wire [7:0] readOnly_io_output_ar_payload_id; + wire [3:0] readOnly_io_output_ar_payload_region; + wire [7:0] readOnly_io_output_ar_payload_len; + wire [2:0] readOnly_io_output_ar_payload_size; + wire [1:0] readOnly_io_output_ar_payload_burst; + wire [0:0] readOnly_io_output_ar_payload_lock; + wire [3:0] readOnly_io_output_ar_payload_cache; + wire [3:0] readOnly_io_output_ar_payload_qos; + wire [2:0] readOnly_io_output_ar_payload_prot; + wire readOnly_io_output_r_ready; + wire writeOnly_io_input_aw_ready; + wire writeOnly_io_input_w_ready; + wire writeOnly_io_input_b_valid; + wire [7:0] writeOnly_io_input_b_payload_id; + wire [1:0] writeOnly_io_input_b_payload_resp; + wire writeOnly_io_output_aw_valid; + wire [31:0] writeOnly_io_output_aw_payload_addr; + wire [7:0] writeOnly_io_output_aw_payload_id; + wire [3:0] writeOnly_io_output_aw_payload_region; + wire [7:0] writeOnly_io_output_aw_payload_len; + wire [2:0] writeOnly_io_output_aw_payload_size; + wire [1:0] writeOnly_io_output_aw_payload_burst; + wire [0:0] writeOnly_io_output_aw_payload_lock; + wire [3:0] writeOnly_io_output_aw_payload_cache; + wire [3:0] writeOnly_io_output_aw_payload_qos; + wire [2:0] writeOnly_io_output_aw_payload_prot; + wire writeOnly_io_output_w_valid; + wire [511:0] writeOnly_io_output_w_payload_data; + wire [63:0] writeOnly_io_output_w_payload_strb; + wire writeOnly_io_output_w_payload_last; + wire writeOnly_io_output_b_ready; + + Asic32To512UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 readOnly ( + .io_input_ar_valid (io_input_ar_valid ), //i + .io_input_ar_ready (readOnly_io_input_ar_ready ), //o + .io_input_ar_payload_addr (io_input_ar_payload_addr[31:0] ), //i + .io_input_ar_payload_id (io_input_ar_payload_id[7:0] ), //i + .io_input_ar_payload_region (io_input_ar_payload_region[3:0] ), //i + .io_input_ar_payload_len (io_input_ar_payload_len[7:0] ), //i + .io_input_ar_payload_size (io_input_ar_payload_size[2:0] ), //i + .io_input_ar_payload_burst (io_input_ar_payload_burst[1:0] ), //i + .io_input_ar_payload_lock (io_input_ar_payload_lock ), //i + .io_input_ar_payload_cache (io_input_ar_payload_cache[3:0] ), //i + .io_input_ar_payload_qos (io_input_ar_payload_qos[3:0] ), //i + .io_input_ar_payload_prot (io_input_ar_payload_prot[2:0] ), //i + .io_input_r_valid (readOnly_io_input_r_valid ), //o + .io_input_r_ready (io_input_r_ready ), //i + .io_input_r_payload_data (readOnly_io_input_r_payload_data[31:0] ), //o + .io_input_r_payload_id (readOnly_io_input_r_payload_id[7:0] ), //o + .io_input_r_payload_resp (readOnly_io_input_r_payload_resp[1:0] ), //o + .io_input_r_payload_last (readOnly_io_input_r_payload_last ), //o + .io_output_ar_valid (readOnly_io_output_ar_valid ), //o + .io_output_ar_ready (io_output_ar_ready ), //i + .io_output_ar_payload_addr (readOnly_io_output_ar_payload_addr[31:0] ), //o + .io_output_ar_payload_id (readOnly_io_output_ar_payload_id[7:0] ), //o + .io_output_ar_payload_region (readOnly_io_output_ar_payload_region[3:0]), //o + .io_output_ar_payload_len (readOnly_io_output_ar_payload_len[7:0] ), //o + .io_output_ar_payload_size (readOnly_io_output_ar_payload_size[2:0] ), //o + .io_output_ar_payload_burst (readOnly_io_output_ar_payload_burst[1:0] ), //o + .io_output_ar_payload_lock (readOnly_io_output_ar_payload_lock ), //o + .io_output_ar_payload_cache (readOnly_io_output_ar_payload_cache[3:0] ), //o + .io_output_ar_payload_qos (readOnly_io_output_ar_payload_qos[3:0] ), //o + .io_output_ar_payload_prot (readOnly_io_output_ar_payload_prot[2:0] ), //o + .io_output_r_valid (io_output_r_valid ), //i + .io_output_r_ready (readOnly_io_output_r_ready ), //o + .io_output_r_payload_data (io_output_r_payload_data[511:0] ), //i + .io_output_r_payload_id (io_output_r_payload_id[7:0] ), //i + .io_output_r_payload_resp (io_output_r_payload_resp[1:0] ), //i + .io_output_r_payload_last (io_output_r_payload_last ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Asic32To512UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 writeOnly ( + .io_input_aw_valid (io_input_aw_valid ), //i + .io_input_aw_ready (writeOnly_io_input_aw_ready ), //o + .io_input_aw_payload_addr (io_input_aw_payload_addr[31:0] ), //i + .io_input_aw_payload_id (io_input_aw_payload_id[7:0] ), //i + .io_input_aw_payload_region (io_input_aw_payload_region[3:0] ), //i + .io_input_aw_payload_len (io_input_aw_payload_len[7:0] ), //i + .io_input_aw_payload_size (io_input_aw_payload_size[2:0] ), //i + .io_input_aw_payload_burst (io_input_aw_payload_burst[1:0] ), //i + .io_input_aw_payload_lock (io_input_aw_payload_lock ), //i + .io_input_aw_payload_cache (io_input_aw_payload_cache[3:0] ), //i + .io_input_aw_payload_qos (io_input_aw_payload_qos[3:0] ), //i + .io_input_aw_payload_prot (io_input_aw_payload_prot[2:0] ), //i + .io_input_w_valid (io_input_w_valid ), //i + .io_input_w_ready (writeOnly_io_input_w_ready ), //o + .io_input_w_payload_data (io_input_w_payload_data[31:0] ), //i + .io_input_w_payload_strb (io_input_w_payload_strb[3:0] ), //i + .io_input_w_payload_last (io_input_w_payload_last ), //i + .io_input_b_valid (writeOnly_io_input_b_valid ), //o + .io_input_b_ready (io_input_b_ready ), //i + .io_input_b_payload_id (writeOnly_io_input_b_payload_id[7:0] ), //o + .io_input_b_payload_resp (writeOnly_io_input_b_payload_resp[1:0] ), //o + .io_output_aw_valid (writeOnly_io_output_aw_valid ), //o + .io_output_aw_ready (io_output_aw_ready ), //i + .io_output_aw_payload_addr (writeOnly_io_output_aw_payload_addr[31:0] ), //o + .io_output_aw_payload_id (writeOnly_io_output_aw_payload_id[7:0] ), //o + .io_output_aw_payload_region (writeOnly_io_output_aw_payload_region[3:0]), //o + .io_output_aw_payload_len (writeOnly_io_output_aw_payload_len[7:0] ), //o + .io_output_aw_payload_size (writeOnly_io_output_aw_payload_size[2:0] ), //o + .io_output_aw_payload_burst (writeOnly_io_output_aw_payload_burst[1:0] ), //o + .io_output_aw_payload_lock (writeOnly_io_output_aw_payload_lock ), //o + .io_output_aw_payload_cache (writeOnly_io_output_aw_payload_cache[3:0] ), //o + .io_output_aw_payload_qos (writeOnly_io_output_aw_payload_qos[3:0] ), //o + .io_output_aw_payload_prot (writeOnly_io_output_aw_payload_prot[2:0] ), //o + .io_output_w_valid (writeOnly_io_output_w_valid ), //o + .io_output_w_ready (io_output_w_ready ), //i + .io_output_w_payload_data (writeOnly_io_output_w_payload_data[511:0] ), //o + .io_output_w_payload_strb (writeOnly_io_output_w_payload_strb[63:0] ), //o + .io_output_w_payload_last (writeOnly_io_output_w_payload_last ), //o + .io_output_b_valid (io_output_b_valid ), //i + .io_output_b_ready (writeOnly_io_output_b_ready ), //o + .io_output_b_payload_id (io_output_b_payload_id[7:0] ), //i + .io_output_b_payload_resp (io_output_b_payload_resp[1:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign io_input_ar_ready = readOnly_io_input_ar_ready; + assign io_input_r_valid = readOnly_io_input_r_valid; + assign io_input_r_payload_data = readOnly_io_input_r_payload_data; + assign io_input_r_payload_id = readOnly_io_input_r_payload_id; + assign io_input_r_payload_resp = readOnly_io_input_r_payload_resp; + assign io_input_r_payload_last = readOnly_io_input_r_payload_last; + assign io_input_aw_ready = writeOnly_io_input_aw_ready; + assign io_input_w_ready = writeOnly_io_input_w_ready; + assign io_input_b_valid = writeOnly_io_input_b_valid; + assign io_input_b_payload_id = writeOnly_io_input_b_payload_id; + assign io_input_b_payload_resp = writeOnly_io_input_b_payload_resp; + assign io_output_ar_valid = readOnly_io_output_ar_valid; + assign io_output_ar_payload_addr = readOnly_io_output_ar_payload_addr; + assign io_output_ar_payload_id = readOnly_io_output_ar_payload_id; + assign io_output_ar_payload_region = readOnly_io_output_ar_payload_region; + assign io_output_ar_payload_len = readOnly_io_output_ar_payload_len; + assign io_output_ar_payload_size = readOnly_io_output_ar_payload_size; + assign io_output_ar_payload_burst = readOnly_io_output_ar_payload_burst; + assign io_output_ar_payload_lock = readOnly_io_output_ar_payload_lock; + assign io_output_ar_payload_cache = readOnly_io_output_ar_payload_cache; + assign io_output_ar_payload_qos = readOnly_io_output_ar_payload_qos; + assign io_output_ar_payload_prot = readOnly_io_output_ar_payload_prot; + assign io_output_r_ready = readOnly_io_output_r_ready; + assign io_output_aw_valid = writeOnly_io_output_aw_valid; + assign io_output_aw_payload_addr = writeOnly_io_output_aw_payload_addr; + assign io_output_aw_payload_id = writeOnly_io_output_aw_payload_id; + assign io_output_aw_payload_region = writeOnly_io_output_aw_payload_region; + assign io_output_aw_payload_len = writeOnly_io_output_aw_payload_len; + assign io_output_aw_payload_size = writeOnly_io_output_aw_payload_size; + assign io_output_aw_payload_burst = writeOnly_io_output_aw_payload_burst; + assign io_output_aw_payload_lock = writeOnly_io_output_aw_payload_lock; + assign io_output_aw_payload_cache = writeOnly_io_output_aw_payload_cache; + assign io_output_aw_payload_qos = writeOnly_io_output_aw_payload_qos; + assign io_output_aw_payload_prot = writeOnly_io_output_aw_payload_prot; + assign io_output_w_valid = writeOnly_io_output_w_valid; + assign io_output_w_payload_data = writeOnly_io_output_w_payload_data; + assign io_output_w_payload_strb = writeOnly_io_output_w_payload_strb; + assign io_output_w_payload_last = writeOnly_io_output_w_payload_last; + assign io_output_b_ready = writeOnly_io_output_b_ready; + +endmodule + +module Asic32To512UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_aw_valid, + output reg io_input_aw_ready, + input [31:0] io_input_aw_payload_addr, + input [7:0] io_input_aw_payload_id, + input [3:0] io_input_aw_payload_region, + input [7:0] io_input_aw_payload_len, + input [2:0] io_input_aw_payload_size, + input [1:0] io_input_aw_payload_burst, + input [0:0] io_input_aw_payload_lock, + input [3:0] io_input_aw_payload_cache, + input [3:0] io_input_aw_payload_qos, + input [2:0] io_input_aw_payload_prot, + input io_input_w_valid, + output io_input_w_ready, + input [31:0] io_input_w_payload_data, + input [3:0] io_input_w_payload_strb, + input io_input_w_payload_last, + output io_input_b_valid, + input io_input_b_ready, + output [7:0] io_input_b_payload_id, + output [1:0] io_input_b_payload_resp, + output io_output_aw_valid, + input io_output_aw_ready, + output [31:0] io_output_aw_payload_addr, + output [7:0] io_output_aw_payload_id, + output [3:0] io_output_aw_payload_region, + output reg [7:0] io_output_aw_payload_len, + output reg [2:0] io_output_aw_payload_size, + output [1:0] io_output_aw_payload_burst, + output [0:0] io_output_aw_payload_lock, + output [3:0] io_output_aw_payload_cache, + output [3:0] io_output_aw_payload_qos, + output [2:0] io_output_aw_payload_prot, + output io_output_w_valid, + input io_output_w_ready, + output [511:0] io_output_w_payload_data, + output [63:0] io_output_w_payload_strb, + output io_output_w_payload_last, + input io_output_b_valid, + output io_output_b_ready, + input [7:0] io_output_b_payload_id, + input [1:0] io_output_b_payload_resp, + input clk, + input reset +); + + wire [14:0] _zz_cmdLogic_byteCount; + wire [10:0] _zz_cmdLogic_incrLen; + wire [10:0] _zz_cmdLogic_incrLen_1; + wire [5:0] _zz_cmdLogic_incrLen_2; + wire [6:0] _zz_dataLogic_byteCounterNext; + wire [7:0] _zz_dataLogic_byteCounterNext_1; + reg [63:0] _zz_dataLogic_byteActivity; + wire cmdLogic_outputFork_valid; + wire cmdLogic_outputFork_ready; + wire [31:0] cmdLogic_outputFork_payload_addr; + wire [7:0] cmdLogic_outputFork_payload_id; + wire [3:0] cmdLogic_outputFork_payload_region; + wire [7:0] cmdLogic_outputFork_payload_len; + wire [2:0] cmdLogic_outputFork_payload_size; + wire [1:0] cmdLogic_outputFork_payload_burst; + wire [0:0] cmdLogic_outputFork_payload_lock; + wire [3:0] cmdLogic_outputFork_payload_cache; + wire [3:0] cmdLogic_outputFork_payload_qos; + wire [2:0] cmdLogic_outputFork_payload_prot; + wire cmdLogic_dataFork_valid; + wire cmdLogic_dataFork_ready; + wire [31:0] cmdLogic_dataFork_payload_addr; + wire [7:0] cmdLogic_dataFork_payload_id; + wire [3:0] cmdLogic_dataFork_payload_region; + wire [7:0] cmdLogic_dataFork_payload_len; + wire [2:0] cmdLogic_dataFork_payload_size; + wire [1:0] cmdLogic_dataFork_payload_burst; + wire [0:0] cmdLogic_dataFork_payload_lock; + wire [3:0] cmdLogic_dataFork_payload_cache; + wire [3:0] cmdLogic_dataFork_payload_qos; + wire [2:0] cmdLogic_dataFork_payload_prot; + reg io_input_aw_fork2_logic_linkEnable_0; + reg io_input_aw_fork2_logic_linkEnable_1; + wire when_Stream_l993; + wire when_Stream_l993_1; + wire cmdLogic_outputFork_fire; + wire cmdLogic_dataFork_fire; + wire [9:0] cmdLogic_byteCount; + wire [4:0] cmdLogic_incrLen; + wire when_Axi4Upsizer_l21; + wire when_Axi4Upsizer_l24; + reg [5:0] dataLogic_byteCounter; + reg [2:0] dataLogic_size; + reg dataLogic_outputValid; + reg dataLogic_outputLast; + reg dataLogic_busy; + reg dataLogic_incrementByteCounter; + reg dataLogic_alwaysFire; + wire [6:0] dataLogic_byteCounterNext; + reg [511:0] dataLogic_dataBuffer; + reg [63:0] dataLogic_maskBuffer; + wire [63:0] dataLogic_byteActivity; + wire io_output_w_fire; + wire io_output_w_isStall; + wire io_input_w_fire; + wire when_Axi4Upsizer_l59; + wire when_Axi4Upsizer_l59_1; + wire when_Axi4Upsizer_l59_2; + wire when_Axi4Upsizer_l59_3; + wire when_Axi4Upsizer_l59_4; + wire when_Axi4Upsizer_l59_5; + wire when_Axi4Upsizer_l59_6; + wire when_Axi4Upsizer_l59_7; + wire when_Axi4Upsizer_l59_8; + wire when_Axi4Upsizer_l59_9; + wire when_Axi4Upsizer_l59_10; + wire when_Axi4Upsizer_l59_11; + wire when_Axi4Upsizer_l59_12; + wire when_Axi4Upsizer_l59_13; + wire when_Axi4Upsizer_l59_14; + wire when_Axi4Upsizer_l59_15; + wire when_Axi4Upsizer_l59_16; + wire when_Axi4Upsizer_l59_17; + wire when_Axi4Upsizer_l59_18; + wire when_Axi4Upsizer_l59_19; + wire when_Axi4Upsizer_l59_20; + wire when_Axi4Upsizer_l59_21; + wire when_Axi4Upsizer_l59_22; + wire when_Axi4Upsizer_l59_23; + wire when_Axi4Upsizer_l59_24; + wire when_Axi4Upsizer_l59_25; + wire when_Axi4Upsizer_l59_26; + wire when_Axi4Upsizer_l59_27; + wire when_Axi4Upsizer_l59_28; + wire when_Axi4Upsizer_l59_29; + wire when_Axi4Upsizer_l59_30; + wire when_Axi4Upsizer_l59_31; + wire when_Axi4Upsizer_l59_32; + wire when_Axi4Upsizer_l59_33; + wire when_Axi4Upsizer_l59_34; + wire when_Axi4Upsizer_l59_35; + wire when_Axi4Upsizer_l59_36; + wire when_Axi4Upsizer_l59_37; + wire when_Axi4Upsizer_l59_38; + wire when_Axi4Upsizer_l59_39; + wire when_Axi4Upsizer_l59_40; + wire when_Axi4Upsizer_l59_41; + wire when_Axi4Upsizer_l59_42; + wire when_Axi4Upsizer_l59_43; + wire when_Axi4Upsizer_l59_44; + wire when_Axi4Upsizer_l59_45; + wire when_Axi4Upsizer_l59_46; + wire when_Axi4Upsizer_l59_47; + wire when_Axi4Upsizer_l59_48; + wire when_Axi4Upsizer_l59_49; + wire when_Axi4Upsizer_l59_50; + wire when_Axi4Upsizer_l59_51; + wire when_Axi4Upsizer_l59_52; + wire when_Axi4Upsizer_l59_53; + wire when_Axi4Upsizer_l59_54; + wire when_Axi4Upsizer_l59_55; + wire when_Axi4Upsizer_l59_56; + wire when_Axi4Upsizer_l59_57; + wire when_Axi4Upsizer_l59_58; + wire when_Axi4Upsizer_l59_59; + wire when_Axi4Upsizer_l59_60; + wire when_Axi4Upsizer_l59_61; + wire when_Axi4Upsizer_l59_62; + wire when_Axi4Upsizer_l59_63; + wire cmdLogic_dataFork_fire_1; + wire when_Axi4Upsizer_l68; + wire when_Axi4Upsizer_l68_1; + wire when_Axi4Upsizer_l68_2; + wire when_Axi4Upsizer_l68_3; + wire when_Axi4Upsizer_l68_4; + wire when_Axi4Upsizer_l68_5; + + assign _zz_cmdLogic_byteCount = ({7'd0,io_input_aw_payload_len} <<< io_input_aw_payload_size); + assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); + assign _zz_cmdLogic_incrLen_2 = io_input_aw_payload_addr[5 : 0]; + assign _zz_cmdLogic_incrLen_1 = {5'd0, _zz_cmdLogic_incrLen_2}; + assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); + assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[6:0]; + always @(*) begin + case(dataLogic_size) + 3'b000 : _zz_dataLogic_byteActivity = 64'h0000000000000001; + 3'b001 : _zz_dataLogic_byteActivity = 64'h0000000000000003; + 3'b010 : _zz_dataLogic_byteActivity = 64'h000000000000000f; + 3'b011 : _zz_dataLogic_byteActivity = 64'h00000000000000ff; + 3'b100 : _zz_dataLogic_byteActivity = 64'h000000000000ffff; + default : _zz_dataLogic_byteActivity = 64'h00000000ffffffff; + endcase + end + + always @(*) begin + io_input_aw_ready = 1'b1; + if(when_Stream_l993) begin + io_input_aw_ready = 1'b0; + end + if(when_Stream_l993_1) begin + io_input_aw_ready = 1'b0; + end + end + + assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_aw_fork2_logic_linkEnable_0); + assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_aw_fork2_logic_linkEnable_1); + assign cmdLogic_outputFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_0); + assign cmdLogic_outputFork_payload_addr = io_input_aw_payload_addr; + assign cmdLogic_outputFork_payload_id = io_input_aw_payload_id; + assign cmdLogic_outputFork_payload_region = io_input_aw_payload_region; + assign cmdLogic_outputFork_payload_len = io_input_aw_payload_len; + assign cmdLogic_outputFork_payload_size = io_input_aw_payload_size; + assign cmdLogic_outputFork_payload_burst = io_input_aw_payload_burst; + assign cmdLogic_outputFork_payload_lock = io_input_aw_payload_lock; + assign cmdLogic_outputFork_payload_cache = io_input_aw_payload_cache; + assign cmdLogic_outputFork_payload_qos = io_input_aw_payload_qos; + assign cmdLogic_outputFork_payload_prot = io_input_aw_payload_prot; + assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); + assign cmdLogic_dataFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_1); + assign cmdLogic_dataFork_payload_addr = io_input_aw_payload_addr; + assign cmdLogic_dataFork_payload_id = io_input_aw_payload_id; + assign cmdLogic_dataFork_payload_region = io_input_aw_payload_region; + assign cmdLogic_dataFork_payload_len = io_input_aw_payload_len; + assign cmdLogic_dataFork_payload_size = io_input_aw_payload_size; + assign cmdLogic_dataFork_payload_burst = io_input_aw_payload_burst; + assign cmdLogic_dataFork_payload_lock = io_input_aw_payload_lock; + assign cmdLogic_dataFork_payload_cache = io_input_aw_payload_cache; + assign cmdLogic_dataFork_payload_qos = io_input_aw_payload_qos; + assign cmdLogic_dataFork_payload_prot = io_input_aw_payload_prot; + assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign io_output_aw_valid = cmdLogic_outputFork_valid; + assign cmdLogic_outputFork_ready = io_output_aw_ready; + assign io_output_aw_payload_addr = cmdLogic_outputFork_payload_addr; + assign io_output_aw_payload_id = cmdLogic_outputFork_payload_id; + assign io_output_aw_payload_region = cmdLogic_outputFork_payload_region; + always @(*) begin + io_output_aw_payload_len = cmdLogic_outputFork_payload_len; + if(when_Axi4Upsizer_l21) begin + io_output_aw_payload_len = {3'd0, cmdLogic_incrLen}; + end + end + + always @(*) begin + io_output_aw_payload_size = cmdLogic_outputFork_payload_size; + if(when_Axi4Upsizer_l21) begin + io_output_aw_payload_size = 3'b110; + if(when_Axi4Upsizer_l24) begin + io_output_aw_payload_size = io_input_aw_payload_size; + end + end + end + + assign io_output_aw_payload_burst = cmdLogic_outputFork_payload_burst; + assign io_output_aw_payload_lock = cmdLogic_outputFork_payload_lock; + assign io_output_aw_payload_cache = cmdLogic_outputFork_payload_cache; + assign io_output_aw_payload_qos = cmdLogic_outputFork_payload_qos; + assign io_output_aw_payload_prot = cmdLogic_outputFork_payload_prot; + assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; + assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 6]; + assign when_Axi4Upsizer_l21 = (io_output_aw_payload_burst == 2'b01); + assign when_Axi4Upsizer_l24 = (io_input_aw_payload_len == 8'h00); + assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); + assign dataLogic_byteActivity = (_zz_dataLogic_byteActivity <<< dataLogic_byteCounter); + assign io_output_w_fire = (io_output_w_valid && io_output_w_ready); + assign io_output_w_valid = dataLogic_outputValid; + assign io_output_w_isStall = (io_output_w_valid && (! io_output_w_ready)); + assign io_input_w_ready = (dataLogic_busy && (! io_output_w_isStall)); + assign io_output_w_payload_data = dataLogic_dataBuffer; + assign io_output_w_payload_strb = dataLogic_maskBuffer; + assign io_output_w_payload_last = dataLogic_outputLast; + assign io_input_w_fire = (io_input_w_valid && io_input_w_ready); + assign when_Axi4Upsizer_l59 = dataLogic_byteActivity[0]; + assign when_Axi4Upsizer_l59_1 = dataLogic_byteActivity[1]; + assign when_Axi4Upsizer_l59_2 = dataLogic_byteActivity[2]; + assign when_Axi4Upsizer_l59_3 = dataLogic_byteActivity[3]; + assign when_Axi4Upsizer_l59_4 = dataLogic_byteActivity[4]; + assign when_Axi4Upsizer_l59_5 = dataLogic_byteActivity[5]; + assign when_Axi4Upsizer_l59_6 = dataLogic_byteActivity[6]; + assign when_Axi4Upsizer_l59_7 = dataLogic_byteActivity[7]; + assign when_Axi4Upsizer_l59_8 = dataLogic_byteActivity[8]; + assign when_Axi4Upsizer_l59_9 = dataLogic_byteActivity[9]; + assign when_Axi4Upsizer_l59_10 = dataLogic_byteActivity[10]; + assign when_Axi4Upsizer_l59_11 = dataLogic_byteActivity[11]; + assign when_Axi4Upsizer_l59_12 = dataLogic_byteActivity[12]; + assign when_Axi4Upsizer_l59_13 = dataLogic_byteActivity[13]; + assign when_Axi4Upsizer_l59_14 = dataLogic_byteActivity[14]; + assign when_Axi4Upsizer_l59_15 = dataLogic_byteActivity[15]; + assign when_Axi4Upsizer_l59_16 = dataLogic_byteActivity[16]; + assign when_Axi4Upsizer_l59_17 = dataLogic_byteActivity[17]; + assign when_Axi4Upsizer_l59_18 = dataLogic_byteActivity[18]; + assign when_Axi4Upsizer_l59_19 = dataLogic_byteActivity[19]; + assign when_Axi4Upsizer_l59_20 = dataLogic_byteActivity[20]; + assign when_Axi4Upsizer_l59_21 = dataLogic_byteActivity[21]; + assign when_Axi4Upsizer_l59_22 = dataLogic_byteActivity[22]; + assign when_Axi4Upsizer_l59_23 = dataLogic_byteActivity[23]; + assign when_Axi4Upsizer_l59_24 = dataLogic_byteActivity[24]; + assign when_Axi4Upsizer_l59_25 = dataLogic_byteActivity[25]; + assign when_Axi4Upsizer_l59_26 = dataLogic_byteActivity[26]; + assign when_Axi4Upsizer_l59_27 = dataLogic_byteActivity[27]; + assign when_Axi4Upsizer_l59_28 = dataLogic_byteActivity[28]; + assign when_Axi4Upsizer_l59_29 = dataLogic_byteActivity[29]; + assign when_Axi4Upsizer_l59_30 = dataLogic_byteActivity[30]; + assign when_Axi4Upsizer_l59_31 = dataLogic_byteActivity[31]; + assign when_Axi4Upsizer_l59_32 = dataLogic_byteActivity[32]; + assign when_Axi4Upsizer_l59_33 = dataLogic_byteActivity[33]; + assign when_Axi4Upsizer_l59_34 = dataLogic_byteActivity[34]; + assign when_Axi4Upsizer_l59_35 = dataLogic_byteActivity[35]; + assign when_Axi4Upsizer_l59_36 = dataLogic_byteActivity[36]; + assign when_Axi4Upsizer_l59_37 = dataLogic_byteActivity[37]; + assign when_Axi4Upsizer_l59_38 = dataLogic_byteActivity[38]; + assign when_Axi4Upsizer_l59_39 = dataLogic_byteActivity[39]; + assign when_Axi4Upsizer_l59_40 = dataLogic_byteActivity[40]; + assign when_Axi4Upsizer_l59_41 = dataLogic_byteActivity[41]; + assign when_Axi4Upsizer_l59_42 = dataLogic_byteActivity[42]; + assign when_Axi4Upsizer_l59_43 = dataLogic_byteActivity[43]; + assign when_Axi4Upsizer_l59_44 = dataLogic_byteActivity[44]; + assign when_Axi4Upsizer_l59_45 = dataLogic_byteActivity[45]; + assign when_Axi4Upsizer_l59_46 = dataLogic_byteActivity[46]; + assign when_Axi4Upsizer_l59_47 = dataLogic_byteActivity[47]; + assign when_Axi4Upsizer_l59_48 = dataLogic_byteActivity[48]; + assign when_Axi4Upsizer_l59_49 = dataLogic_byteActivity[49]; + assign when_Axi4Upsizer_l59_50 = dataLogic_byteActivity[50]; + assign when_Axi4Upsizer_l59_51 = dataLogic_byteActivity[51]; + assign when_Axi4Upsizer_l59_52 = dataLogic_byteActivity[52]; + assign when_Axi4Upsizer_l59_53 = dataLogic_byteActivity[53]; + assign when_Axi4Upsizer_l59_54 = dataLogic_byteActivity[54]; + assign when_Axi4Upsizer_l59_55 = dataLogic_byteActivity[55]; + assign when_Axi4Upsizer_l59_56 = dataLogic_byteActivity[56]; + assign when_Axi4Upsizer_l59_57 = dataLogic_byteActivity[57]; + assign when_Axi4Upsizer_l59_58 = dataLogic_byteActivity[58]; + assign when_Axi4Upsizer_l59_59 = dataLogic_byteActivity[59]; + assign when_Axi4Upsizer_l59_60 = dataLogic_byteActivity[60]; + assign when_Axi4Upsizer_l59_61 = dataLogic_byteActivity[61]; + assign when_Axi4Upsizer_l59_62 = dataLogic_byteActivity[62]; + assign when_Axi4Upsizer_l59_63 = dataLogic_byteActivity[63]; + assign cmdLogic_dataFork_fire_1 = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign when_Axi4Upsizer_l68 = (3'b000 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_1 = (3'b001 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_2 = (3'b010 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_3 = (3'b011 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_4 = (3'b100 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_5 = (3'b101 < cmdLogic_dataFork_payload_size); + assign cmdLogic_dataFork_ready = (! dataLogic_busy); + assign io_input_b_valid = io_output_b_valid; + assign io_output_b_ready = io_input_b_ready; + assign io_input_b_payload_id = io_output_b_payload_id; + assign io_input_b_payload_resp = io_output_b_payload_resp; + always @(posedge clk or posedge reset) begin + if(reset) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; + io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; + dataLogic_outputValid <= 1'b0; + dataLogic_busy <= 1'b0; + dataLogic_maskBuffer <= 64'h0000000000000000; + end else begin + if(cmdLogic_outputFork_fire) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdLogic_dataFork_fire) begin + io_input_aw_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_aw_ready) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; + io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; + end + if(io_output_w_ready) begin + dataLogic_outputValid <= 1'b0; + end + if(io_output_w_fire) begin + dataLogic_maskBuffer <= 64'h0000000000000000; + end + if(io_input_w_fire) begin + dataLogic_outputValid <= ((dataLogic_byteCounterNext[6] || io_input_w_payload_last) || dataLogic_alwaysFire); + if(io_input_w_payload_last) begin + dataLogic_busy <= 1'b0; + end + if(when_Axi4Upsizer_l59) begin + dataLogic_maskBuffer[0] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_1) begin + dataLogic_maskBuffer[1] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_2) begin + dataLogic_maskBuffer[2] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_3) begin + dataLogic_maskBuffer[3] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_4) begin + dataLogic_maskBuffer[4] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_5) begin + dataLogic_maskBuffer[5] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_6) begin + dataLogic_maskBuffer[6] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_7) begin + dataLogic_maskBuffer[7] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_8) begin + dataLogic_maskBuffer[8] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_9) begin + dataLogic_maskBuffer[9] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_10) begin + dataLogic_maskBuffer[10] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_11) begin + dataLogic_maskBuffer[11] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_12) begin + dataLogic_maskBuffer[12] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_13) begin + dataLogic_maskBuffer[13] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_14) begin + dataLogic_maskBuffer[14] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_15) begin + dataLogic_maskBuffer[15] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_16) begin + dataLogic_maskBuffer[16] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_17) begin + dataLogic_maskBuffer[17] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_18) begin + dataLogic_maskBuffer[18] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_19) begin + dataLogic_maskBuffer[19] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_20) begin + dataLogic_maskBuffer[20] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_21) begin + dataLogic_maskBuffer[21] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_22) begin + dataLogic_maskBuffer[22] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_23) begin + dataLogic_maskBuffer[23] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_24) begin + dataLogic_maskBuffer[24] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_25) begin + dataLogic_maskBuffer[25] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_26) begin + dataLogic_maskBuffer[26] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_27) begin + dataLogic_maskBuffer[27] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_28) begin + dataLogic_maskBuffer[28] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_29) begin + dataLogic_maskBuffer[29] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_30) begin + dataLogic_maskBuffer[30] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_31) begin + dataLogic_maskBuffer[31] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_32) begin + dataLogic_maskBuffer[32] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_33) begin + dataLogic_maskBuffer[33] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_34) begin + dataLogic_maskBuffer[34] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_35) begin + dataLogic_maskBuffer[35] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_36) begin + dataLogic_maskBuffer[36] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_37) begin + dataLogic_maskBuffer[37] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_38) begin + dataLogic_maskBuffer[38] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_39) begin + dataLogic_maskBuffer[39] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_40) begin + dataLogic_maskBuffer[40] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_41) begin + dataLogic_maskBuffer[41] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_42) begin + dataLogic_maskBuffer[42] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_43) begin + dataLogic_maskBuffer[43] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_44) begin + dataLogic_maskBuffer[44] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_45) begin + dataLogic_maskBuffer[45] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_46) begin + dataLogic_maskBuffer[46] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_47) begin + dataLogic_maskBuffer[47] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_48) begin + dataLogic_maskBuffer[48] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_49) begin + dataLogic_maskBuffer[49] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_50) begin + dataLogic_maskBuffer[50] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_51) begin + dataLogic_maskBuffer[51] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_52) begin + dataLogic_maskBuffer[52] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_53) begin + dataLogic_maskBuffer[53] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_54) begin + dataLogic_maskBuffer[54] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_55) begin + dataLogic_maskBuffer[55] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_56) begin + dataLogic_maskBuffer[56] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_57) begin + dataLogic_maskBuffer[57] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_58) begin + dataLogic_maskBuffer[58] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_59) begin + dataLogic_maskBuffer[59] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_60) begin + dataLogic_maskBuffer[60] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_61) begin + dataLogic_maskBuffer[61] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_62) begin + dataLogic_maskBuffer[62] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_63) begin + dataLogic_maskBuffer[63] <= io_input_w_payload_strb[3]; + end + end + if(cmdLogic_dataFork_fire_1) begin + dataLogic_busy <= 1'b1; + end + end + end + + always @(posedge clk) begin + if(io_input_w_fire) begin + if(dataLogic_incrementByteCounter) begin + dataLogic_byteCounter <= dataLogic_byteCounterNext[5:0]; + end + dataLogic_outputLast <= io_input_w_payload_last; + if(when_Axi4Upsizer_l59) begin + dataLogic_dataBuffer[7 : 0] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_1) begin + dataLogic_dataBuffer[15 : 8] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_2) begin + dataLogic_dataBuffer[23 : 16] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_3) begin + dataLogic_dataBuffer[31 : 24] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_4) begin + dataLogic_dataBuffer[39 : 32] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_5) begin + dataLogic_dataBuffer[47 : 40] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_6) begin + dataLogic_dataBuffer[55 : 48] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_7) begin + dataLogic_dataBuffer[63 : 56] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_8) begin + dataLogic_dataBuffer[71 : 64] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_9) begin + dataLogic_dataBuffer[79 : 72] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_10) begin + dataLogic_dataBuffer[87 : 80] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_11) begin + dataLogic_dataBuffer[95 : 88] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_12) begin + dataLogic_dataBuffer[103 : 96] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_13) begin + dataLogic_dataBuffer[111 : 104] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_14) begin + dataLogic_dataBuffer[119 : 112] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_15) begin + dataLogic_dataBuffer[127 : 120] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_16) begin + dataLogic_dataBuffer[135 : 128] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_17) begin + dataLogic_dataBuffer[143 : 136] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_18) begin + dataLogic_dataBuffer[151 : 144] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_19) begin + dataLogic_dataBuffer[159 : 152] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_20) begin + dataLogic_dataBuffer[167 : 160] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_21) begin + dataLogic_dataBuffer[175 : 168] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_22) begin + dataLogic_dataBuffer[183 : 176] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_23) begin + dataLogic_dataBuffer[191 : 184] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_24) begin + dataLogic_dataBuffer[199 : 192] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_25) begin + dataLogic_dataBuffer[207 : 200] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_26) begin + dataLogic_dataBuffer[215 : 208] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_27) begin + dataLogic_dataBuffer[223 : 216] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_28) begin + dataLogic_dataBuffer[231 : 224] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_29) begin + dataLogic_dataBuffer[239 : 232] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_30) begin + dataLogic_dataBuffer[247 : 240] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_31) begin + dataLogic_dataBuffer[255 : 248] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_32) begin + dataLogic_dataBuffer[263 : 256] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_33) begin + dataLogic_dataBuffer[271 : 264] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_34) begin + dataLogic_dataBuffer[279 : 272] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_35) begin + dataLogic_dataBuffer[287 : 280] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_36) begin + dataLogic_dataBuffer[295 : 288] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_37) begin + dataLogic_dataBuffer[303 : 296] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_38) begin + dataLogic_dataBuffer[311 : 304] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_39) begin + dataLogic_dataBuffer[319 : 312] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_40) begin + dataLogic_dataBuffer[327 : 320] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_41) begin + dataLogic_dataBuffer[335 : 328] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_42) begin + dataLogic_dataBuffer[343 : 336] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_43) begin + dataLogic_dataBuffer[351 : 344] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_44) begin + dataLogic_dataBuffer[359 : 352] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_45) begin + dataLogic_dataBuffer[367 : 360] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_46) begin + dataLogic_dataBuffer[375 : 368] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_47) begin + dataLogic_dataBuffer[383 : 376] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_48) begin + dataLogic_dataBuffer[391 : 384] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_49) begin + dataLogic_dataBuffer[399 : 392] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_50) begin + dataLogic_dataBuffer[407 : 400] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_51) begin + dataLogic_dataBuffer[415 : 408] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_52) begin + dataLogic_dataBuffer[423 : 416] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_53) begin + dataLogic_dataBuffer[431 : 424] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_54) begin + dataLogic_dataBuffer[439 : 432] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_55) begin + dataLogic_dataBuffer[447 : 440] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_56) begin + dataLogic_dataBuffer[455 : 448] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_57) begin + dataLogic_dataBuffer[463 : 456] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_58) begin + dataLogic_dataBuffer[471 : 464] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_59) begin + dataLogic_dataBuffer[479 : 472] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_60) begin + dataLogic_dataBuffer[487 : 480] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_61) begin + dataLogic_dataBuffer[495 : 488] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_62) begin + dataLogic_dataBuffer[503 : 496] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_63) begin + dataLogic_dataBuffer[511 : 504] <= io_input_w_payload_data[31 : 24]; + end + end + if(cmdLogic_dataFork_fire_1) begin + dataLogic_byteCounter <= cmdLogic_dataFork_payload_addr[5:0]; + if(when_Axi4Upsizer_l68) begin + dataLogic_byteCounter[0] <= 1'b0; + end + if(when_Axi4Upsizer_l68_1) begin + dataLogic_byteCounter[1] <= 1'b0; + end + if(when_Axi4Upsizer_l68_2) begin + dataLogic_byteCounter[2] <= 1'b0; + end + if(when_Axi4Upsizer_l68_3) begin + dataLogic_byteCounter[3] <= 1'b0; + end + if(when_Axi4Upsizer_l68_4) begin + dataLogic_byteCounter[4] <= 1'b0; + end + if(when_Axi4Upsizer_l68_5) begin + dataLogic_byteCounter[5] <= 1'b0; + end + dataLogic_size <= cmdLogic_dataFork_payload_size; + dataLogic_alwaysFire <= (! (cmdLogic_dataFork_payload_burst == 2'b01)); + dataLogic_incrementByteCounter <= (! (cmdLogic_dataFork_payload_burst == 2'b00)); + end + end + + +endmodule + +module Asic32To512UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_ar_valid, + output reg io_input_ar_ready, + input [31:0] io_input_ar_payload_addr, + input [7:0] io_input_ar_payload_id, + input [3:0] io_input_ar_payload_region, + input [7:0] io_input_ar_payload_len, + input [2:0] io_input_ar_payload_size, + input [1:0] io_input_ar_payload_burst, + input [0:0] io_input_ar_payload_lock, + input [3:0] io_input_ar_payload_cache, + input [3:0] io_input_ar_payload_qos, + input [2:0] io_input_ar_payload_prot, + output io_input_r_valid, + input io_input_r_ready, + output [31:0] io_input_r_payload_data, + output [7:0] io_input_r_payload_id, + output [1:0] io_input_r_payload_resp, + output io_input_r_payload_last, + output io_output_ar_valid, + input io_output_ar_ready, + output [31:0] io_output_ar_payload_addr, + output [7:0] io_output_ar_payload_id, + output [3:0] io_output_ar_payload_region, + output [7:0] io_output_ar_payload_len, + output reg [2:0] io_output_ar_payload_size, + output [1:0] io_output_ar_payload_burst, + output [0:0] io_output_ar_payload_lock, + output [3:0] io_output_ar_payload_cache, + output [3:0] io_output_ar_payload_qos, + output [2:0] io_output_ar_payload_prot, + input io_output_r_valid, + output io_output_r_ready, + input [511:0] io_output_r_payload_data, + input [7:0] io_output_r_payload_id, + input [1:0] io_output_r_payload_resp, + input io_output_r_payload_last, + input clk, + input reset +); + + wire dataLogic_cmdPush_fifo_io_pop_ready; + wire dataLogic_cmdPush_fifo_io_push_ready; + wire dataLogic_cmdPush_fifo_io_pop_valid; + wire [5:0] dataLogic_cmdPush_fifo_io_pop_payload_startAt; + wire [5:0] dataLogic_cmdPush_fifo_io_pop_payload_endAt; + wire [2:0] dataLogic_cmdPush_fifo_io_pop_payload_size; + wire [7:0] dataLogic_cmdPush_fifo_io_pop_payload_id; + wire [4:0] dataLogic_cmdPush_fifo_io_occupancy; + wire [4:0] dataLogic_cmdPush_fifo_io_availability; + wire [14:0] _zz_cmdLogic_byteCount; + wire [10:0] _zz_cmdLogic_incrLen; + wire [10:0] _zz_cmdLogic_incrLen_1; + wire [5:0] _zz_cmdLogic_incrLen_2; + wire [31:0] _zz_dataLogic_cmdPush_payload_endAt; + wire [31:0] _zz_dataLogic_cmdPush_payload_endAt_1; + wire [14:0] _zz_dataLogic_cmdPush_payload_endAt_2; + wire [6:0] _zz_dataLogic_byteCounterNext; + wire [7:0] _zz_dataLogic_byteCounterNext_1; + reg [31:0] _zz_io_input_r_payload_data; + wire [3:0] _zz_io_input_r_payload_data_1; + wire cmdLogic_outputFork_valid; + wire cmdLogic_outputFork_ready; + wire [31:0] cmdLogic_outputFork_payload_addr; + wire [7:0] cmdLogic_outputFork_payload_id; + wire [3:0] cmdLogic_outputFork_payload_region; + wire [7:0] cmdLogic_outputFork_payload_len; + wire [2:0] cmdLogic_outputFork_payload_size; + wire [1:0] cmdLogic_outputFork_payload_burst; + wire [0:0] cmdLogic_outputFork_payload_lock; + wire [3:0] cmdLogic_outputFork_payload_cache; + wire [3:0] cmdLogic_outputFork_payload_qos; + wire [2:0] cmdLogic_outputFork_payload_prot; + wire cmdLogic_dataFork_valid; + wire cmdLogic_dataFork_ready; + wire [31:0] cmdLogic_dataFork_payload_addr; + wire [7:0] cmdLogic_dataFork_payload_id; + wire [3:0] cmdLogic_dataFork_payload_region; + wire [7:0] cmdLogic_dataFork_payload_len; + wire [2:0] cmdLogic_dataFork_payload_size; + wire [1:0] cmdLogic_dataFork_payload_burst; + wire [0:0] cmdLogic_dataFork_payload_lock; + wire [3:0] cmdLogic_dataFork_payload_cache; + wire [3:0] cmdLogic_dataFork_payload_qos; + wire [2:0] cmdLogic_dataFork_payload_prot; + reg io_input_ar_fork2_logic_linkEnable_0; + reg io_input_ar_fork2_logic_linkEnable_1; + wire when_Stream_l993; + wire when_Stream_l993_1; + wire cmdLogic_outputFork_fire; + wire cmdLogic_dataFork_fire; + wire [9:0] cmdLogic_byteCount; + wire [4:0] cmdLogic_incrLen; + wire when_Axi4Upsizer_l108; + wire dataLogic_cmdPush_valid; + wire dataLogic_cmdPush_ready; + wire [5:0] dataLogic_cmdPush_payload_startAt; + wire [5:0] dataLogic_cmdPush_payload_endAt; + wire [2:0] dataLogic_cmdPush_payload_size; + wire [7:0] dataLogic_cmdPush_payload_id; + reg [2:0] dataLogic_size; + reg dataLogic_busy; + reg [7:0] dataLogic_id; + reg [5:0] dataLogic_byteCounter; + reg [5:0] dataLogic_byteCounterLast; + wire [6:0] dataLogic_byteCounterNext; + wire readOnly_dataLogic_cmdPush_fifo_io_pop_fire; + wire io_input_r_fire; + + assign _zz_cmdLogic_byteCount = ({7'd0,io_input_ar_payload_len} <<< io_input_ar_payload_size); + assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); + assign _zz_cmdLogic_incrLen_2 = io_input_ar_payload_addr[5 : 0]; + assign _zz_cmdLogic_incrLen_1 = {5'd0, _zz_cmdLogic_incrLen_2}; + assign _zz_dataLogic_cmdPush_payload_endAt = (cmdLogic_dataFork_payload_addr + _zz_dataLogic_cmdPush_payload_endAt_1); + assign _zz_dataLogic_cmdPush_payload_endAt_2 = ({7'd0,cmdLogic_dataFork_payload_len} <<< cmdLogic_dataFork_payload_size); + assign _zz_dataLogic_cmdPush_payload_endAt_1 = {17'd0, _zz_dataLogic_cmdPush_payload_endAt_2}; + assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); + assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[6:0]; + assign _zz_io_input_r_payload_data_1 = (dataLogic_byteCounter >>> 2'd2); + Asic32To512UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 dataLogic_cmdPush_fifo ( + .io_push_valid (dataLogic_cmdPush_valid ), //i + .io_push_ready (dataLogic_cmdPush_fifo_io_push_ready ), //o + .io_push_payload_startAt (dataLogic_cmdPush_payload_startAt[5:0] ), //i + .io_push_payload_endAt (dataLogic_cmdPush_payload_endAt[5:0] ), //i + .io_push_payload_size (dataLogic_cmdPush_payload_size[2:0] ), //i + .io_push_payload_id (dataLogic_cmdPush_payload_id[7:0] ), //i + .io_pop_valid (dataLogic_cmdPush_fifo_io_pop_valid ), //o + .io_pop_ready (dataLogic_cmdPush_fifo_io_pop_ready ), //i + .io_pop_payload_startAt (dataLogic_cmdPush_fifo_io_pop_payload_startAt[5:0]), //o + .io_pop_payload_endAt (dataLogic_cmdPush_fifo_io_pop_payload_endAt[5:0] ), //o + .io_pop_payload_size (dataLogic_cmdPush_fifo_io_pop_payload_size[2:0] ), //o + .io_pop_payload_id (dataLogic_cmdPush_fifo_io_pop_payload_id[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (dataLogic_cmdPush_fifo_io_occupancy[4:0] ), //o + .io_availability (dataLogic_cmdPush_fifo_io_availability[4:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_io_input_r_payload_data_1) + 4'b0000 : _zz_io_input_r_payload_data = io_output_r_payload_data[31 : 0]; + 4'b0001 : _zz_io_input_r_payload_data = io_output_r_payload_data[63 : 32]; + 4'b0010 : _zz_io_input_r_payload_data = io_output_r_payload_data[95 : 64]; + 4'b0011 : _zz_io_input_r_payload_data = io_output_r_payload_data[127 : 96]; + 4'b0100 : _zz_io_input_r_payload_data = io_output_r_payload_data[159 : 128]; + 4'b0101 : _zz_io_input_r_payload_data = io_output_r_payload_data[191 : 160]; + 4'b0110 : _zz_io_input_r_payload_data = io_output_r_payload_data[223 : 192]; + 4'b0111 : _zz_io_input_r_payload_data = io_output_r_payload_data[255 : 224]; + 4'b1000 : _zz_io_input_r_payload_data = io_output_r_payload_data[287 : 256]; + 4'b1001 : _zz_io_input_r_payload_data = io_output_r_payload_data[319 : 288]; + 4'b1010 : _zz_io_input_r_payload_data = io_output_r_payload_data[351 : 320]; + 4'b1011 : _zz_io_input_r_payload_data = io_output_r_payload_data[383 : 352]; + 4'b1100 : _zz_io_input_r_payload_data = io_output_r_payload_data[415 : 384]; + 4'b1101 : _zz_io_input_r_payload_data = io_output_r_payload_data[447 : 416]; + 4'b1110 : _zz_io_input_r_payload_data = io_output_r_payload_data[479 : 448]; + default : _zz_io_input_r_payload_data = io_output_r_payload_data[511 : 480]; + endcase + end + + always @(*) begin + io_input_ar_ready = 1'b1; + if(when_Stream_l993) begin + io_input_ar_ready = 1'b0; + end + if(when_Stream_l993_1) begin + io_input_ar_ready = 1'b0; + end + end + + assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_ar_fork2_logic_linkEnable_0); + assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_ar_fork2_logic_linkEnable_1); + assign cmdLogic_outputFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_0); + assign cmdLogic_outputFork_payload_addr = io_input_ar_payload_addr; + assign cmdLogic_outputFork_payload_id = io_input_ar_payload_id; + assign cmdLogic_outputFork_payload_region = io_input_ar_payload_region; + assign cmdLogic_outputFork_payload_len = io_input_ar_payload_len; + assign cmdLogic_outputFork_payload_size = io_input_ar_payload_size; + assign cmdLogic_outputFork_payload_burst = io_input_ar_payload_burst; + assign cmdLogic_outputFork_payload_lock = io_input_ar_payload_lock; + assign cmdLogic_outputFork_payload_cache = io_input_ar_payload_cache; + assign cmdLogic_outputFork_payload_qos = io_input_ar_payload_qos; + assign cmdLogic_outputFork_payload_prot = io_input_ar_payload_prot; + assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); + assign cmdLogic_dataFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_1); + assign cmdLogic_dataFork_payload_addr = io_input_ar_payload_addr; + assign cmdLogic_dataFork_payload_id = io_input_ar_payload_id; + assign cmdLogic_dataFork_payload_region = io_input_ar_payload_region; + assign cmdLogic_dataFork_payload_len = io_input_ar_payload_len; + assign cmdLogic_dataFork_payload_size = io_input_ar_payload_size; + assign cmdLogic_dataFork_payload_burst = io_input_ar_payload_burst; + assign cmdLogic_dataFork_payload_lock = io_input_ar_payload_lock; + assign cmdLogic_dataFork_payload_cache = io_input_ar_payload_cache; + assign cmdLogic_dataFork_payload_qos = io_input_ar_payload_qos; + assign cmdLogic_dataFork_payload_prot = io_input_ar_payload_prot; + assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign io_output_ar_valid = cmdLogic_outputFork_valid; + assign cmdLogic_outputFork_ready = io_output_ar_ready; + assign io_output_ar_payload_addr = cmdLogic_outputFork_payload_addr; + assign io_output_ar_payload_region = cmdLogic_outputFork_payload_region; + assign io_output_ar_payload_burst = cmdLogic_outputFork_payload_burst; + assign io_output_ar_payload_lock = cmdLogic_outputFork_payload_lock; + assign io_output_ar_payload_cache = cmdLogic_outputFork_payload_cache; + assign io_output_ar_payload_qos = cmdLogic_outputFork_payload_qos; + assign io_output_ar_payload_prot = cmdLogic_outputFork_payload_prot; + assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; + assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 6]; + always @(*) begin + io_output_ar_payload_size = 3'b110; + if(when_Axi4Upsizer_l108) begin + io_output_ar_payload_size = io_input_ar_payload_size; + end + end + + assign io_output_ar_payload_len = {3'd0, cmdLogic_incrLen}; + assign io_output_ar_payload_id = 8'h00; + assign when_Axi4Upsizer_l108 = (io_input_ar_payload_len == 8'h00); + assign dataLogic_cmdPush_valid = cmdLogic_dataFork_valid; + assign cmdLogic_dataFork_ready = dataLogic_cmdPush_ready; + assign dataLogic_cmdPush_payload_startAt = cmdLogic_dataFork_payload_addr[5:0]; + assign dataLogic_cmdPush_payload_endAt = _zz_dataLogic_cmdPush_payload_endAt[5:0]; + assign dataLogic_cmdPush_payload_size = cmdLogic_dataFork_payload_size; + assign dataLogic_cmdPush_payload_id = cmdLogic_dataFork_payload_id; + assign dataLogic_cmdPush_ready = dataLogic_cmdPush_fifo_io_push_ready; + assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); + assign readOnly_dataLogic_cmdPush_fifo_io_pop_fire = (dataLogic_cmdPush_fifo_io_pop_valid && dataLogic_cmdPush_fifo_io_pop_ready); + assign dataLogic_cmdPush_fifo_io_pop_ready = (! dataLogic_busy); + assign io_input_r_fire = (io_input_r_valid && io_input_r_ready); + assign io_input_r_valid = (io_output_r_valid && dataLogic_busy); + assign io_input_r_payload_last = (io_output_r_payload_last && (dataLogic_byteCounter == dataLogic_byteCounterLast)); + assign io_input_r_payload_resp = io_output_r_payload_resp; + assign io_input_r_payload_data = _zz_io_input_r_payload_data; + assign io_input_r_payload_id = dataLogic_id; + assign io_output_r_ready = ((dataLogic_busy && io_input_r_ready) && (io_input_r_payload_last || dataLogic_byteCounterNext[6])); + always @(posedge clk or posedge reset) begin + if(reset) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; + io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; + dataLogic_busy <= 1'b0; + end else begin + if(cmdLogic_outputFork_fire) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdLogic_dataFork_fire) begin + io_input_ar_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_ar_ready) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; + io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; + end + if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin + dataLogic_busy <= 1'b1; + end + if(io_input_r_fire) begin + if(io_input_r_payload_last) begin + dataLogic_busy <= 1'b0; + end + end + end + end + + always @(posedge clk) begin + if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin + dataLogic_byteCounter <= dataLogic_cmdPush_fifo_io_pop_payload_startAt; + dataLogic_byteCounterLast <= dataLogic_cmdPush_fifo_io_pop_payload_endAt; + dataLogic_size <= dataLogic_cmdPush_fifo_io_pop_payload_size; + dataLogic_id <= dataLogic_cmdPush_fifo_io_pop_payload_id; + end + if(io_input_r_fire) begin + dataLogic_byteCounter <= dataLogic_byteCounterNext[5:0]; + end + end + + +endmodule + +module Asic32To512UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_push_valid, + output io_push_ready, + input [5:0] io_push_payload_startAt, + input [5:0] io_push_payload_endAt, + input [2:0] io_push_payload_size, + input [7:0] io_push_payload_id, + output io_pop_valid, + input io_pop_ready, + output [5:0] io_pop_payload_startAt, + output [5:0] io_pop_payload_endAt, + output [2:0] io_pop_payload_size, + output [7:0] io_pop_payload_id, + input io_flush, + output [4:0] io_occupancy, + output [4:0] io_availability, + input clk, + input reset +); + + reg [22:0] _zz_logic_ram_port0; + wire [3:0] _zz_logic_pushPtr_valueNext; + wire [0:0] _zz_logic_pushPtr_valueNext_1; + wire [3:0] _zz_logic_popPtr_valueNext; + wire [0:0] _zz_logic_popPtr_valueNext_1; + wire _zz__zz_logic_ram_port0; + wire _zz__zz_io_pop_payload_startAt; + wire [22:0] _zz__zz_logic_ram_port1; + wire [3:0] _zz_io_availability; + reg _zz_1; + reg logic_pushPtr_willIncrement; + reg logic_pushPtr_willClear; + reg [3:0] logic_pushPtr_valueNext; + reg [3:0] logic_pushPtr_value; + wire logic_pushPtr_willOverflowIfInc; + wire logic_pushPtr_willOverflow; + reg logic_popPtr_willIncrement; + reg logic_popPtr_willClear; + reg [3:0] logic_popPtr_valueNext; + reg [3:0] logic_popPtr_value; + wire logic_popPtr_willOverflowIfInc; + wire logic_popPtr_willOverflow; + wire logic_ptrMatch; + reg logic_risingOccupancy; + wire logic_pushing; + wire logic_popping; + wire logic_empty; + wire logic_full; + reg _zz_io_pop_valid; + wire [22:0] _zz_io_pop_payload_startAt; + wire when_Stream_l1123; + wire [3:0] logic_ptrDif; + reg [22:0] logic_ram [0:15]; + + assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; + assign _zz_logic_pushPtr_valueNext = {3'd0, _zz_logic_pushPtr_valueNext_1}; + assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; + assign _zz_logic_popPtr_valueNext = {3'd0, _zz_logic_popPtr_valueNext_1}; + assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); + assign _zz__zz_io_pop_payload_startAt = 1'b1; + assign _zz__zz_logic_ram_port1 = {io_push_payload_id,{io_push_payload_size,{io_push_payload_endAt,io_push_payload_startAt}}}; + always @(posedge clk) begin + if(_zz__zz_io_pop_payload_startAt) begin + _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_pushPtr_value] <= _zz__zz_logic_ram_port1; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_pushing) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willIncrement = 1'b0; + if(logic_pushing) begin + logic_pushPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willClear = 1'b0; + if(io_flush) begin + logic_pushPtr_willClear = 1'b1; + end + end + + assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 4'b1111); + assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); + always @(*) begin + logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); + if(logic_pushPtr_willClear) begin + logic_pushPtr_valueNext = 4'b0000; + end + end + + always @(*) begin + logic_popPtr_willIncrement = 1'b0; + if(logic_popping) begin + logic_popPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_popPtr_willClear = 1'b0; + if(io_flush) begin + logic_popPtr_willClear = 1'b1; + end + end + + assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 4'b1111); + assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); + always @(*) begin + logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); + if(logic_popPtr_willClear) begin + logic_popPtr_valueNext = 4'b0000; + end + end + + assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); + assign logic_pushing = (io_push_valid && io_push_ready); + assign logic_popping = (io_pop_valid && io_pop_ready); + assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); + assign logic_full = (logic_ptrMatch && logic_risingOccupancy); + assign io_push_ready = (! logic_full); + assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); + assign _zz_io_pop_payload_startAt = _zz_logic_ram_port0; + assign io_pop_payload_startAt = _zz_io_pop_payload_startAt[5 : 0]; + assign io_pop_payload_endAt = _zz_io_pop_payload_startAt[11 : 6]; + assign io_pop_payload_size = _zz_io_pop_payload_startAt[14 : 12]; + assign io_pop_payload_id = _zz_io_pop_payload_startAt[22 : 15]; + assign when_Stream_l1123 = (logic_pushing != logic_popping); + assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); + assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; + assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; + always @(posedge clk or posedge reset) begin + if(reset) begin + logic_pushPtr_value <= 4'b0000; + logic_popPtr_value <= 4'b0000; + logic_risingOccupancy <= 1'b0; + _zz_io_pop_valid <= 1'b0; + end else begin + logic_pushPtr_value <= logic_pushPtr_valueNext; + logic_popPtr_value <= logic_popPtr_valueNext; + _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); + if(when_Stream_l1123) begin + logic_risingOccupancy <= logic_pushing; + end + if(io_flush) begin + logic_risingOccupancy <= 1'b0; + end + end + end + + +endmodule + + +// Generator : SpinalHDL dev git head : 9cdee03b276638ef8e7a948b606bb7acc6e4c8d0 +// Component : Asic32To64UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 +// Git hash : cd16421fb7a4d44431a2445f9a92b82070ab9b8a + +`timescale 1ns/1ps + +module Asic32To64UpsizerAxi4Upsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_aw_valid, + output io_input_aw_ready, + input [31:0] io_input_aw_payload_addr, + input [7:0] io_input_aw_payload_id, + input [3:0] io_input_aw_payload_region, + input [7:0] io_input_aw_payload_len, + input [2:0] io_input_aw_payload_size, + input [1:0] io_input_aw_payload_burst, + input [0:0] io_input_aw_payload_lock, + input [3:0] io_input_aw_payload_cache, + input [3:0] io_input_aw_payload_qos, + input [2:0] io_input_aw_payload_prot, + input io_input_w_valid, + output io_input_w_ready, + input [31:0] io_input_w_payload_data, + input [3:0] io_input_w_payload_strb, + input io_input_w_payload_last, + output io_input_b_valid, + input io_input_b_ready, + output [7:0] io_input_b_payload_id, + output [1:0] io_input_b_payload_resp, + input io_input_ar_valid, + output io_input_ar_ready, + input [31:0] io_input_ar_payload_addr, + input [7:0] io_input_ar_payload_id, + input [3:0] io_input_ar_payload_region, + input [7:0] io_input_ar_payload_len, + input [2:0] io_input_ar_payload_size, + input [1:0] io_input_ar_payload_burst, + input [0:0] io_input_ar_payload_lock, + input [3:0] io_input_ar_payload_cache, + input [3:0] io_input_ar_payload_qos, + input [2:0] io_input_ar_payload_prot, + output io_input_r_valid, + input io_input_r_ready, + output [31:0] io_input_r_payload_data, + output [7:0] io_input_r_payload_id, + output [1:0] io_input_r_payload_resp, + output io_input_r_payload_last, + output io_output_aw_valid, + input io_output_aw_ready, + output [31:0] io_output_aw_payload_addr, + output [7:0] io_output_aw_payload_id, + output [3:0] io_output_aw_payload_region, + output [7:0] io_output_aw_payload_len, + output [2:0] io_output_aw_payload_size, + output [1:0] io_output_aw_payload_burst, + output [0:0] io_output_aw_payload_lock, + output [3:0] io_output_aw_payload_cache, + output [3:0] io_output_aw_payload_qos, + output [2:0] io_output_aw_payload_prot, + output io_output_w_valid, + input io_output_w_ready, + output [63:0] io_output_w_payload_data, + output [7:0] io_output_w_payload_strb, + output io_output_w_payload_last, + input io_output_b_valid, + output io_output_b_ready, + input [7:0] io_output_b_payload_id, + input [1:0] io_output_b_payload_resp, + output io_output_ar_valid, + input io_output_ar_ready, + output [31:0] io_output_ar_payload_addr, + output [7:0] io_output_ar_payload_id, + output [3:0] io_output_ar_payload_region, + output [7:0] io_output_ar_payload_len, + output [2:0] io_output_ar_payload_size, + output [1:0] io_output_ar_payload_burst, + output [0:0] io_output_ar_payload_lock, + output [3:0] io_output_ar_payload_cache, + output [3:0] io_output_ar_payload_qos, + output [2:0] io_output_ar_payload_prot, + input io_output_r_valid, + output io_output_r_ready, + input [63:0] io_output_r_payload_data, + input [7:0] io_output_r_payload_id, + input [1:0] io_output_r_payload_resp, + input io_output_r_payload_last, + input clk, + input reset +); + + wire readOnly_io_input_ar_ready; + wire readOnly_io_input_r_valid; + wire [31:0] readOnly_io_input_r_payload_data; + wire [7:0] readOnly_io_input_r_payload_id; + wire [1:0] readOnly_io_input_r_payload_resp; + wire readOnly_io_input_r_payload_last; + wire readOnly_io_output_ar_valid; + wire [31:0] readOnly_io_output_ar_payload_addr; + wire [7:0] readOnly_io_output_ar_payload_id; + wire [3:0] readOnly_io_output_ar_payload_region; + wire [7:0] readOnly_io_output_ar_payload_len; + wire [2:0] readOnly_io_output_ar_payload_size; + wire [1:0] readOnly_io_output_ar_payload_burst; + wire [0:0] readOnly_io_output_ar_payload_lock; + wire [3:0] readOnly_io_output_ar_payload_cache; + wire [3:0] readOnly_io_output_ar_payload_qos; + wire [2:0] readOnly_io_output_ar_payload_prot; + wire readOnly_io_output_r_ready; + wire writeOnly_io_input_aw_ready; + wire writeOnly_io_input_w_ready; + wire writeOnly_io_input_b_valid; + wire [7:0] writeOnly_io_input_b_payload_id; + wire [1:0] writeOnly_io_input_b_payload_resp; + wire writeOnly_io_output_aw_valid; + wire [31:0] writeOnly_io_output_aw_payload_addr; + wire [7:0] writeOnly_io_output_aw_payload_id; + wire [3:0] writeOnly_io_output_aw_payload_region; + wire [7:0] writeOnly_io_output_aw_payload_len; + wire [2:0] writeOnly_io_output_aw_payload_size; + wire [1:0] writeOnly_io_output_aw_payload_burst; + wire [0:0] writeOnly_io_output_aw_payload_lock; + wire [3:0] writeOnly_io_output_aw_payload_cache; + wire [3:0] writeOnly_io_output_aw_payload_qos; + wire [2:0] writeOnly_io_output_aw_payload_prot; + wire writeOnly_io_output_w_valid; + wire [63:0] writeOnly_io_output_w_payload_data; + wire [7:0] writeOnly_io_output_w_payload_strb; + wire writeOnly_io_output_w_payload_last; + wire writeOnly_io_output_b_ready; + + Asic32To64UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 readOnly ( + .io_input_ar_valid (io_input_ar_valid ), //i + .io_input_ar_ready (readOnly_io_input_ar_ready ), //o + .io_input_ar_payload_addr (io_input_ar_payload_addr[31:0] ), //i + .io_input_ar_payload_id (io_input_ar_payload_id[7:0] ), //i + .io_input_ar_payload_region (io_input_ar_payload_region[3:0] ), //i + .io_input_ar_payload_len (io_input_ar_payload_len[7:0] ), //i + .io_input_ar_payload_size (io_input_ar_payload_size[2:0] ), //i + .io_input_ar_payload_burst (io_input_ar_payload_burst[1:0] ), //i + .io_input_ar_payload_lock (io_input_ar_payload_lock ), //i + .io_input_ar_payload_cache (io_input_ar_payload_cache[3:0] ), //i + .io_input_ar_payload_qos (io_input_ar_payload_qos[3:0] ), //i + .io_input_ar_payload_prot (io_input_ar_payload_prot[2:0] ), //i + .io_input_r_valid (readOnly_io_input_r_valid ), //o + .io_input_r_ready (io_input_r_ready ), //i + .io_input_r_payload_data (readOnly_io_input_r_payload_data[31:0] ), //o + .io_input_r_payload_id (readOnly_io_input_r_payload_id[7:0] ), //o + .io_input_r_payload_resp (readOnly_io_input_r_payload_resp[1:0] ), //o + .io_input_r_payload_last (readOnly_io_input_r_payload_last ), //o + .io_output_ar_valid (readOnly_io_output_ar_valid ), //o + .io_output_ar_ready (io_output_ar_ready ), //i + .io_output_ar_payload_addr (readOnly_io_output_ar_payload_addr[31:0] ), //o + .io_output_ar_payload_id (readOnly_io_output_ar_payload_id[7:0] ), //o + .io_output_ar_payload_region (readOnly_io_output_ar_payload_region[3:0]), //o + .io_output_ar_payload_len (readOnly_io_output_ar_payload_len[7:0] ), //o + .io_output_ar_payload_size (readOnly_io_output_ar_payload_size[2:0] ), //o + .io_output_ar_payload_burst (readOnly_io_output_ar_payload_burst[1:0] ), //o + .io_output_ar_payload_lock (readOnly_io_output_ar_payload_lock ), //o + .io_output_ar_payload_cache (readOnly_io_output_ar_payload_cache[3:0] ), //o + .io_output_ar_payload_qos (readOnly_io_output_ar_payload_qos[3:0] ), //o + .io_output_ar_payload_prot (readOnly_io_output_ar_payload_prot[2:0] ), //o + .io_output_r_valid (io_output_r_valid ), //i + .io_output_r_ready (readOnly_io_output_r_ready ), //o + .io_output_r_payload_data (io_output_r_payload_data[63:0] ), //i + .io_output_r_payload_id (io_output_r_payload_id[7:0] ), //i + .io_output_r_payload_resp (io_output_r_payload_resp[1:0] ), //i + .io_output_r_payload_last (io_output_r_payload_last ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + Asic32To64UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 writeOnly ( + .io_input_aw_valid (io_input_aw_valid ), //i + .io_input_aw_ready (writeOnly_io_input_aw_ready ), //o + .io_input_aw_payload_addr (io_input_aw_payload_addr[31:0] ), //i + .io_input_aw_payload_id (io_input_aw_payload_id[7:0] ), //i + .io_input_aw_payload_region (io_input_aw_payload_region[3:0] ), //i + .io_input_aw_payload_len (io_input_aw_payload_len[7:0] ), //i + .io_input_aw_payload_size (io_input_aw_payload_size[2:0] ), //i + .io_input_aw_payload_burst (io_input_aw_payload_burst[1:0] ), //i + .io_input_aw_payload_lock (io_input_aw_payload_lock ), //i + .io_input_aw_payload_cache (io_input_aw_payload_cache[3:0] ), //i + .io_input_aw_payload_qos (io_input_aw_payload_qos[3:0] ), //i + .io_input_aw_payload_prot (io_input_aw_payload_prot[2:0] ), //i + .io_input_w_valid (io_input_w_valid ), //i + .io_input_w_ready (writeOnly_io_input_w_ready ), //o + .io_input_w_payload_data (io_input_w_payload_data[31:0] ), //i + .io_input_w_payload_strb (io_input_w_payload_strb[3:0] ), //i + .io_input_w_payload_last (io_input_w_payload_last ), //i + .io_input_b_valid (writeOnly_io_input_b_valid ), //o + .io_input_b_ready (io_input_b_ready ), //i + .io_input_b_payload_id (writeOnly_io_input_b_payload_id[7:0] ), //o + .io_input_b_payload_resp (writeOnly_io_input_b_payload_resp[1:0] ), //o + .io_output_aw_valid (writeOnly_io_output_aw_valid ), //o + .io_output_aw_ready (io_output_aw_ready ), //i + .io_output_aw_payload_addr (writeOnly_io_output_aw_payload_addr[31:0] ), //o + .io_output_aw_payload_id (writeOnly_io_output_aw_payload_id[7:0] ), //o + .io_output_aw_payload_region (writeOnly_io_output_aw_payload_region[3:0]), //o + .io_output_aw_payload_len (writeOnly_io_output_aw_payload_len[7:0] ), //o + .io_output_aw_payload_size (writeOnly_io_output_aw_payload_size[2:0] ), //o + .io_output_aw_payload_burst (writeOnly_io_output_aw_payload_burst[1:0] ), //o + .io_output_aw_payload_lock (writeOnly_io_output_aw_payload_lock ), //o + .io_output_aw_payload_cache (writeOnly_io_output_aw_payload_cache[3:0] ), //o + .io_output_aw_payload_qos (writeOnly_io_output_aw_payload_qos[3:0] ), //o + .io_output_aw_payload_prot (writeOnly_io_output_aw_payload_prot[2:0] ), //o + .io_output_w_valid (writeOnly_io_output_w_valid ), //o + .io_output_w_ready (io_output_w_ready ), //i + .io_output_w_payload_data (writeOnly_io_output_w_payload_data[63:0] ), //o + .io_output_w_payload_strb (writeOnly_io_output_w_payload_strb[7:0] ), //o + .io_output_w_payload_last (writeOnly_io_output_w_payload_last ), //o + .io_output_b_valid (io_output_b_valid ), //i + .io_output_b_ready (writeOnly_io_output_b_ready ), //o + .io_output_b_payload_id (io_output_b_payload_id[7:0] ), //i + .io_output_b_payload_resp (io_output_b_payload_resp[1:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + assign io_input_ar_ready = readOnly_io_input_ar_ready; + assign io_input_r_valid = readOnly_io_input_r_valid; + assign io_input_r_payload_data = readOnly_io_input_r_payload_data; + assign io_input_r_payload_id = readOnly_io_input_r_payload_id; + assign io_input_r_payload_resp = readOnly_io_input_r_payload_resp; + assign io_input_r_payload_last = readOnly_io_input_r_payload_last; + assign io_input_aw_ready = writeOnly_io_input_aw_ready; + assign io_input_w_ready = writeOnly_io_input_w_ready; + assign io_input_b_valid = writeOnly_io_input_b_valid; + assign io_input_b_payload_id = writeOnly_io_input_b_payload_id; + assign io_input_b_payload_resp = writeOnly_io_input_b_payload_resp; + assign io_output_ar_valid = readOnly_io_output_ar_valid; + assign io_output_ar_payload_addr = readOnly_io_output_ar_payload_addr; + assign io_output_ar_payload_id = readOnly_io_output_ar_payload_id; + assign io_output_ar_payload_region = readOnly_io_output_ar_payload_region; + assign io_output_ar_payload_len = readOnly_io_output_ar_payload_len; + assign io_output_ar_payload_size = readOnly_io_output_ar_payload_size; + assign io_output_ar_payload_burst = readOnly_io_output_ar_payload_burst; + assign io_output_ar_payload_lock = readOnly_io_output_ar_payload_lock; + assign io_output_ar_payload_cache = readOnly_io_output_ar_payload_cache; + assign io_output_ar_payload_qos = readOnly_io_output_ar_payload_qos; + assign io_output_ar_payload_prot = readOnly_io_output_ar_payload_prot; + assign io_output_r_ready = readOnly_io_output_r_ready; + assign io_output_aw_valid = writeOnly_io_output_aw_valid; + assign io_output_aw_payload_addr = writeOnly_io_output_aw_payload_addr; + assign io_output_aw_payload_id = writeOnly_io_output_aw_payload_id; + assign io_output_aw_payload_region = writeOnly_io_output_aw_payload_region; + assign io_output_aw_payload_len = writeOnly_io_output_aw_payload_len; + assign io_output_aw_payload_size = writeOnly_io_output_aw_payload_size; + assign io_output_aw_payload_burst = writeOnly_io_output_aw_payload_burst; + assign io_output_aw_payload_lock = writeOnly_io_output_aw_payload_lock; + assign io_output_aw_payload_cache = writeOnly_io_output_aw_payload_cache; + assign io_output_aw_payload_qos = writeOnly_io_output_aw_payload_qos; + assign io_output_aw_payload_prot = writeOnly_io_output_aw_payload_prot; + assign io_output_w_valid = writeOnly_io_output_w_valid; + assign io_output_w_payload_data = writeOnly_io_output_w_payload_data; + assign io_output_w_payload_strb = writeOnly_io_output_w_payload_strb; + assign io_output_w_payload_last = writeOnly_io_output_w_payload_last; + assign io_output_b_ready = writeOnly_io_output_b_ready; + +endmodule + +module Asic32To64UpsizerAxi4WriteOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_aw_valid, + output reg io_input_aw_ready, + input [31:0] io_input_aw_payload_addr, + input [7:0] io_input_aw_payload_id, + input [3:0] io_input_aw_payload_region, + input [7:0] io_input_aw_payload_len, + input [2:0] io_input_aw_payload_size, + input [1:0] io_input_aw_payload_burst, + input [0:0] io_input_aw_payload_lock, + input [3:0] io_input_aw_payload_cache, + input [3:0] io_input_aw_payload_qos, + input [2:0] io_input_aw_payload_prot, + input io_input_w_valid, + output io_input_w_ready, + input [31:0] io_input_w_payload_data, + input [3:0] io_input_w_payload_strb, + input io_input_w_payload_last, + output io_input_b_valid, + input io_input_b_ready, + output [7:0] io_input_b_payload_id, + output [1:0] io_input_b_payload_resp, + output io_output_aw_valid, + input io_output_aw_ready, + output [31:0] io_output_aw_payload_addr, + output [7:0] io_output_aw_payload_id, + output [3:0] io_output_aw_payload_region, + output reg [7:0] io_output_aw_payload_len, + output reg [2:0] io_output_aw_payload_size, + output [1:0] io_output_aw_payload_burst, + output [0:0] io_output_aw_payload_lock, + output [3:0] io_output_aw_payload_cache, + output [3:0] io_output_aw_payload_qos, + output [2:0] io_output_aw_payload_prot, + output io_output_w_valid, + input io_output_w_ready, + output [63:0] io_output_w_payload_data, + output [7:0] io_output_w_payload_strb, + output io_output_w_payload_last, + input io_output_b_valid, + output io_output_b_ready, + input [7:0] io_output_b_payload_id, + input [1:0] io_output_b_payload_resp, + input clk, + input reset +); + + wire [14:0] _zz_cmdLogic_byteCount; + wire [10:0] _zz_cmdLogic_incrLen; + wire [10:0] _zz_cmdLogic_incrLen_1; + wire [2:0] _zz_cmdLogic_incrLen_2; + wire [3:0] _zz_dataLogic_byteCounterNext; + wire [7:0] _zz_dataLogic_byteCounterNext_1; + reg [7:0] _zz_dataLogic_byteActivity; + wire [1:0] _zz_dataLogic_byteActivity_1; + wire cmdLogic_outputFork_valid; + wire cmdLogic_outputFork_ready; + wire [31:0] cmdLogic_outputFork_payload_addr; + wire [7:0] cmdLogic_outputFork_payload_id; + wire [3:0] cmdLogic_outputFork_payload_region; + wire [7:0] cmdLogic_outputFork_payload_len; + wire [2:0] cmdLogic_outputFork_payload_size; + wire [1:0] cmdLogic_outputFork_payload_burst; + wire [0:0] cmdLogic_outputFork_payload_lock; + wire [3:0] cmdLogic_outputFork_payload_cache; + wire [3:0] cmdLogic_outputFork_payload_qos; + wire [2:0] cmdLogic_outputFork_payload_prot; + wire cmdLogic_dataFork_valid; + wire cmdLogic_dataFork_ready; + wire [31:0] cmdLogic_dataFork_payload_addr; + wire [7:0] cmdLogic_dataFork_payload_id; + wire [3:0] cmdLogic_dataFork_payload_region; + wire [7:0] cmdLogic_dataFork_payload_len; + wire [2:0] cmdLogic_dataFork_payload_size; + wire [1:0] cmdLogic_dataFork_payload_burst; + wire [0:0] cmdLogic_dataFork_payload_lock; + wire [3:0] cmdLogic_dataFork_payload_cache; + wire [3:0] cmdLogic_dataFork_payload_qos; + wire [2:0] cmdLogic_dataFork_payload_prot; + reg io_input_aw_fork2_logic_linkEnable_0; + reg io_input_aw_fork2_logic_linkEnable_1; + wire when_Stream_l993; + wire when_Stream_l993_1; + wire cmdLogic_outputFork_fire; + wire cmdLogic_dataFork_fire; + wire [9:0] cmdLogic_byteCount; + wire [7:0] cmdLogic_incrLen; + wire when_Axi4Upsizer_l21; + wire when_Axi4Upsizer_l24; + reg [2:0] dataLogic_byteCounter; + reg [2:0] dataLogic_size; + reg dataLogic_outputValid; + reg dataLogic_outputLast; + reg dataLogic_busy; + reg dataLogic_incrementByteCounter; + reg dataLogic_alwaysFire; + wire [3:0] dataLogic_byteCounterNext; + reg [63:0] dataLogic_dataBuffer; + reg [7:0] dataLogic_maskBuffer; + wire [7:0] dataLogic_byteActivity; + wire io_output_w_fire; + wire io_output_w_isStall; + wire io_input_w_fire; + wire when_Axi4Upsizer_l59; + wire when_Axi4Upsizer_l59_1; + wire when_Axi4Upsizer_l59_2; + wire when_Axi4Upsizer_l59_3; + wire when_Axi4Upsizer_l59_4; + wire when_Axi4Upsizer_l59_5; + wire when_Axi4Upsizer_l59_6; + wire when_Axi4Upsizer_l59_7; + wire cmdLogic_dataFork_fire_1; + wire when_Axi4Upsizer_l68; + wire when_Axi4Upsizer_l68_1; + wire when_Axi4Upsizer_l68_2; + + assign _zz_cmdLogic_byteCount = ({7'd0,io_input_aw_payload_len} <<< io_input_aw_payload_size); + assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); + assign _zz_cmdLogic_incrLen_2 = io_input_aw_payload_addr[2 : 0]; + assign _zz_cmdLogic_incrLen_1 = {8'd0, _zz_cmdLogic_incrLen_2}; + assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); + assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[3:0]; + assign _zz_dataLogic_byteActivity_1 = dataLogic_size[1:0]; + always @(*) begin + case(_zz_dataLogic_byteActivity_1) + 2'b00 : _zz_dataLogic_byteActivity = 8'h01; + 2'b01 : _zz_dataLogic_byteActivity = 8'h03; + default : _zz_dataLogic_byteActivity = 8'h0f; + endcase + end + + always @(*) begin + io_input_aw_ready = 1'b1; + if(when_Stream_l993) begin + io_input_aw_ready = 1'b0; + end + if(when_Stream_l993_1) begin + io_input_aw_ready = 1'b0; + end + end + + assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_aw_fork2_logic_linkEnable_0); + assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_aw_fork2_logic_linkEnable_1); + assign cmdLogic_outputFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_0); + assign cmdLogic_outputFork_payload_addr = io_input_aw_payload_addr; + assign cmdLogic_outputFork_payload_id = io_input_aw_payload_id; + assign cmdLogic_outputFork_payload_region = io_input_aw_payload_region; + assign cmdLogic_outputFork_payload_len = io_input_aw_payload_len; + assign cmdLogic_outputFork_payload_size = io_input_aw_payload_size; + assign cmdLogic_outputFork_payload_burst = io_input_aw_payload_burst; + assign cmdLogic_outputFork_payload_lock = io_input_aw_payload_lock; + assign cmdLogic_outputFork_payload_cache = io_input_aw_payload_cache; + assign cmdLogic_outputFork_payload_qos = io_input_aw_payload_qos; + assign cmdLogic_outputFork_payload_prot = io_input_aw_payload_prot; + assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); + assign cmdLogic_dataFork_valid = (io_input_aw_valid && io_input_aw_fork2_logic_linkEnable_1); + assign cmdLogic_dataFork_payload_addr = io_input_aw_payload_addr; + assign cmdLogic_dataFork_payload_id = io_input_aw_payload_id; + assign cmdLogic_dataFork_payload_region = io_input_aw_payload_region; + assign cmdLogic_dataFork_payload_len = io_input_aw_payload_len; + assign cmdLogic_dataFork_payload_size = io_input_aw_payload_size; + assign cmdLogic_dataFork_payload_burst = io_input_aw_payload_burst; + assign cmdLogic_dataFork_payload_lock = io_input_aw_payload_lock; + assign cmdLogic_dataFork_payload_cache = io_input_aw_payload_cache; + assign cmdLogic_dataFork_payload_qos = io_input_aw_payload_qos; + assign cmdLogic_dataFork_payload_prot = io_input_aw_payload_prot; + assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign io_output_aw_valid = cmdLogic_outputFork_valid; + assign cmdLogic_outputFork_ready = io_output_aw_ready; + assign io_output_aw_payload_addr = cmdLogic_outputFork_payload_addr; + assign io_output_aw_payload_id = cmdLogic_outputFork_payload_id; + assign io_output_aw_payload_region = cmdLogic_outputFork_payload_region; + always @(*) begin + io_output_aw_payload_len = cmdLogic_outputFork_payload_len; + if(when_Axi4Upsizer_l21) begin + io_output_aw_payload_len = cmdLogic_incrLen; + end + end + + always @(*) begin + io_output_aw_payload_size = cmdLogic_outputFork_payload_size; + if(when_Axi4Upsizer_l21) begin + io_output_aw_payload_size = 3'b011; + if(when_Axi4Upsizer_l24) begin + io_output_aw_payload_size = io_input_aw_payload_size; + end + end + end + + assign io_output_aw_payload_burst = cmdLogic_outputFork_payload_burst; + assign io_output_aw_payload_lock = cmdLogic_outputFork_payload_lock; + assign io_output_aw_payload_cache = cmdLogic_outputFork_payload_cache; + assign io_output_aw_payload_qos = cmdLogic_outputFork_payload_qos; + assign io_output_aw_payload_prot = cmdLogic_outputFork_payload_prot; + assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; + assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 3]; + assign when_Axi4Upsizer_l21 = (io_output_aw_payload_burst == 2'b01); + assign when_Axi4Upsizer_l24 = (io_input_aw_payload_len == 8'h00); + assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); + assign dataLogic_byteActivity = (_zz_dataLogic_byteActivity <<< dataLogic_byteCounter); + assign io_output_w_fire = (io_output_w_valid && io_output_w_ready); + assign io_output_w_valid = dataLogic_outputValid; + assign io_output_w_isStall = (io_output_w_valid && (! io_output_w_ready)); + assign io_input_w_ready = (dataLogic_busy && (! io_output_w_isStall)); + assign io_output_w_payload_data = dataLogic_dataBuffer; + assign io_output_w_payload_strb = dataLogic_maskBuffer; + assign io_output_w_payload_last = dataLogic_outputLast; + assign io_input_w_fire = (io_input_w_valid && io_input_w_ready); + assign when_Axi4Upsizer_l59 = dataLogic_byteActivity[0]; + assign when_Axi4Upsizer_l59_1 = dataLogic_byteActivity[1]; + assign when_Axi4Upsizer_l59_2 = dataLogic_byteActivity[2]; + assign when_Axi4Upsizer_l59_3 = dataLogic_byteActivity[3]; + assign when_Axi4Upsizer_l59_4 = dataLogic_byteActivity[4]; + assign when_Axi4Upsizer_l59_5 = dataLogic_byteActivity[5]; + assign when_Axi4Upsizer_l59_6 = dataLogic_byteActivity[6]; + assign when_Axi4Upsizer_l59_7 = dataLogic_byteActivity[7]; + assign cmdLogic_dataFork_fire_1 = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign when_Axi4Upsizer_l68 = (3'b000 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_1 = (3'b001 < cmdLogic_dataFork_payload_size); + assign when_Axi4Upsizer_l68_2 = (3'b010 < cmdLogic_dataFork_payload_size); + assign cmdLogic_dataFork_ready = (! dataLogic_busy); + assign io_input_b_valid = io_output_b_valid; + assign io_output_b_ready = io_input_b_ready; + assign io_input_b_payload_id = io_output_b_payload_id; + assign io_input_b_payload_resp = io_output_b_payload_resp; + always @(posedge clk or posedge reset) begin + if(reset) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; + io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; + dataLogic_outputValid <= 1'b0; + dataLogic_busy <= 1'b0; + dataLogic_maskBuffer <= 8'h00; + end else begin + if(cmdLogic_outputFork_fire) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdLogic_dataFork_fire) begin + io_input_aw_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_aw_ready) begin + io_input_aw_fork2_logic_linkEnable_0 <= 1'b1; + io_input_aw_fork2_logic_linkEnable_1 <= 1'b1; + end + if(io_output_w_ready) begin + dataLogic_outputValid <= 1'b0; + end + if(io_output_w_fire) begin + dataLogic_maskBuffer <= 8'h00; + end + if(io_input_w_fire) begin + dataLogic_outputValid <= ((dataLogic_byteCounterNext[3] || io_input_w_payload_last) || dataLogic_alwaysFire); + if(io_input_w_payload_last) begin + dataLogic_busy <= 1'b0; + end + if(when_Axi4Upsizer_l59) begin + dataLogic_maskBuffer[0] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_1) begin + dataLogic_maskBuffer[1] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_2) begin + dataLogic_maskBuffer[2] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_3) begin + dataLogic_maskBuffer[3] <= io_input_w_payload_strb[3]; + end + if(when_Axi4Upsizer_l59_4) begin + dataLogic_maskBuffer[4] <= io_input_w_payload_strb[0]; + end + if(when_Axi4Upsizer_l59_5) begin + dataLogic_maskBuffer[5] <= io_input_w_payload_strb[1]; + end + if(when_Axi4Upsizer_l59_6) begin + dataLogic_maskBuffer[6] <= io_input_w_payload_strb[2]; + end + if(when_Axi4Upsizer_l59_7) begin + dataLogic_maskBuffer[7] <= io_input_w_payload_strb[3]; + end + end + if(cmdLogic_dataFork_fire_1) begin + dataLogic_busy <= 1'b1; + end + end + end + + always @(posedge clk) begin + if(io_input_w_fire) begin + if(dataLogic_incrementByteCounter) begin + dataLogic_byteCounter <= dataLogic_byteCounterNext[2:0]; + end + dataLogic_outputLast <= io_input_w_payload_last; + if(when_Axi4Upsizer_l59) begin + dataLogic_dataBuffer[7 : 0] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_1) begin + dataLogic_dataBuffer[15 : 8] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_2) begin + dataLogic_dataBuffer[23 : 16] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_3) begin + dataLogic_dataBuffer[31 : 24] <= io_input_w_payload_data[31 : 24]; + end + if(when_Axi4Upsizer_l59_4) begin + dataLogic_dataBuffer[39 : 32] <= io_input_w_payload_data[7 : 0]; + end + if(when_Axi4Upsizer_l59_5) begin + dataLogic_dataBuffer[47 : 40] <= io_input_w_payload_data[15 : 8]; + end + if(when_Axi4Upsizer_l59_6) begin + dataLogic_dataBuffer[55 : 48] <= io_input_w_payload_data[23 : 16]; + end + if(when_Axi4Upsizer_l59_7) begin + dataLogic_dataBuffer[63 : 56] <= io_input_w_payload_data[31 : 24]; + end + end + if(cmdLogic_dataFork_fire_1) begin + dataLogic_byteCounter <= cmdLogic_dataFork_payload_addr[2:0]; + if(when_Axi4Upsizer_l68) begin + dataLogic_byteCounter[0] <= 1'b0; + end + if(when_Axi4Upsizer_l68_1) begin + dataLogic_byteCounter[1] <= 1'b0; + end + if(when_Axi4Upsizer_l68_2) begin + dataLogic_byteCounter[2] <= 1'b0; + end + dataLogic_size <= cmdLogic_dataFork_payload_size; + dataLogic_alwaysFire <= (! (cmdLogic_dataFork_payload_burst == 2'b01)); + dataLogic_incrementByteCounter <= (! (cmdLogic_dataFork_payload_burst == 2'b00)); + end + end + + +endmodule + +module Asic32To64UpsizerAxi4ReadOnlyUpsizer_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_input_ar_valid, + output reg io_input_ar_ready, + input [31:0] io_input_ar_payload_addr, + input [7:0] io_input_ar_payload_id, + input [3:0] io_input_ar_payload_region, + input [7:0] io_input_ar_payload_len, + input [2:0] io_input_ar_payload_size, + input [1:0] io_input_ar_payload_burst, + input [0:0] io_input_ar_payload_lock, + input [3:0] io_input_ar_payload_cache, + input [3:0] io_input_ar_payload_qos, + input [2:0] io_input_ar_payload_prot, + output io_input_r_valid, + input io_input_r_ready, + output [31:0] io_input_r_payload_data, + output [7:0] io_input_r_payload_id, + output [1:0] io_input_r_payload_resp, + output io_input_r_payload_last, + output io_output_ar_valid, + input io_output_ar_ready, + output [31:0] io_output_ar_payload_addr, + output [7:0] io_output_ar_payload_id, + output [3:0] io_output_ar_payload_region, + output [7:0] io_output_ar_payload_len, + output reg [2:0] io_output_ar_payload_size, + output [1:0] io_output_ar_payload_burst, + output [0:0] io_output_ar_payload_lock, + output [3:0] io_output_ar_payload_cache, + output [3:0] io_output_ar_payload_qos, + output [2:0] io_output_ar_payload_prot, + input io_output_r_valid, + output io_output_r_ready, + input [63:0] io_output_r_payload_data, + input [7:0] io_output_r_payload_id, + input [1:0] io_output_r_payload_resp, + input io_output_r_payload_last, + input clk, + input reset +); + + wire dataLogic_cmdPush_fifo_io_pop_ready; + wire dataLogic_cmdPush_fifo_io_push_ready; + wire dataLogic_cmdPush_fifo_io_pop_valid; + wire [2:0] dataLogic_cmdPush_fifo_io_pop_payload_startAt; + wire [2:0] dataLogic_cmdPush_fifo_io_pop_payload_endAt; + wire [2:0] dataLogic_cmdPush_fifo_io_pop_payload_size; + wire [7:0] dataLogic_cmdPush_fifo_io_pop_payload_id; + wire [4:0] dataLogic_cmdPush_fifo_io_occupancy; + wire [4:0] dataLogic_cmdPush_fifo_io_availability; + wire [14:0] _zz_cmdLogic_byteCount; + wire [10:0] _zz_cmdLogic_incrLen; + wire [10:0] _zz_cmdLogic_incrLen_1; + wire [2:0] _zz_cmdLogic_incrLen_2; + wire [31:0] _zz_dataLogic_cmdPush_payload_endAt; + wire [31:0] _zz_dataLogic_cmdPush_payload_endAt_1; + wire [14:0] _zz_dataLogic_cmdPush_payload_endAt_2; + wire [3:0] _zz_dataLogic_byteCounterNext; + wire [7:0] _zz_dataLogic_byteCounterNext_1; + reg [31:0] _zz_io_input_r_payload_data; + wire [0:0] _zz_io_input_r_payload_data_1; + wire cmdLogic_outputFork_valid; + wire cmdLogic_outputFork_ready; + wire [31:0] cmdLogic_outputFork_payload_addr; + wire [7:0] cmdLogic_outputFork_payload_id; + wire [3:0] cmdLogic_outputFork_payload_region; + wire [7:0] cmdLogic_outputFork_payload_len; + wire [2:0] cmdLogic_outputFork_payload_size; + wire [1:0] cmdLogic_outputFork_payload_burst; + wire [0:0] cmdLogic_outputFork_payload_lock; + wire [3:0] cmdLogic_outputFork_payload_cache; + wire [3:0] cmdLogic_outputFork_payload_qos; + wire [2:0] cmdLogic_outputFork_payload_prot; + wire cmdLogic_dataFork_valid; + wire cmdLogic_dataFork_ready; + wire [31:0] cmdLogic_dataFork_payload_addr; + wire [7:0] cmdLogic_dataFork_payload_id; + wire [3:0] cmdLogic_dataFork_payload_region; + wire [7:0] cmdLogic_dataFork_payload_len; + wire [2:0] cmdLogic_dataFork_payload_size; + wire [1:0] cmdLogic_dataFork_payload_burst; + wire [0:0] cmdLogic_dataFork_payload_lock; + wire [3:0] cmdLogic_dataFork_payload_cache; + wire [3:0] cmdLogic_dataFork_payload_qos; + wire [2:0] cmdLogic_dataFork_payload_prot; + reg io_input_ar_fork2_logic_linkEnable_0; + reg io_input_ar_fork2_logic_linkEnable_1; + wire when_Stream_l993; + wire when_Stream_l993_1; + wire cmdLogic_outputFork_fire; + wire cmdLogic_dataFork_fire; + wire [9:0] cmdLogic_byteCount; + wire [7:0] cmdLogic_incrLen; + wire when_Axi4Upsizer_l108; + wire dataLogic_cmdPush_valid; + wire dataLogic_cmdPush_ready; + wire [2:0] dataLogic_cmdPush_payload_startAt; + wire [2:0] dataLogic_cmdPush_payload_endAt; + wire [2:0] dataLogic_cmdPush_payload_size; + wire [7:0] dataLogic_cmdPush_payload_id; + reg [2:0] dataLogic_size; + reg dataLogic_busy; + reg [7:0] dataLogic_id; + reg [2:0] dataLogic_byteCounter; + reg [2:0] dataLogic_byteCounterLast; + wire [3:0] dataLogic_byteCounterNext; + wire readOnly_dataLogic_cmdPush_fifo_io_pop_fire; + wire io_input_r_fire; + + assign _zz_cmdLogic_byteCount = ({7'd0,io_input_ar_payload_len} <<< io_input_ar_payload_size); + assign _zz_cmdLogic_incrLen = ({1'b0,cmdLogic_byteCount} + _zz_cmdLogic_incrLen_1); + assign _zz_cmdLogic_incrLen_2 = io_input_ar_payload_addr[2 : 0]; + assign _zz_cmdLogic_incrLen_1 = {8'd0, _zz_cmdLogic_incrLen_2}; + assign _zz_dataLogic_cmdPush_payload_endAt = (cmdLogic_dataFork_payload_addr + _zz_dataLogic_cmdPush_payload_endAt_1); + assign _zz_dataLogic_cmdPush_payload_endAt_2 = ({7'd0,cmdLogic_dataFork_payload_len} <<< cmdLogic_dataFork_payload_size); + assign _zz_dataLogic_cmdPush_payload_endAt_1 = {17'd0, _zz_dataLogic_cmdPush_payload_endAt_2}; + assign _zz_dataLogic_byteCounterNext_1 = ({7'd0,1'b1} <<< dataLogic_size); + assign _zz_dataLogic_byteCounterNext = _zz_dataLogic_byteCounterNext_1[3:0]; + assign _zz_io_input_r_payload_data_1 = (dataLogic_byteCounter >>> 2'd2); + Asic32To64UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 dataLogic_cmdPush_fifo ( + .io_push_valid (dataLogic_cmdPush_valid ), //i + .io_push_ready (dataLogic_cmdPush_fifo_io_push_ready ), //o + .io_push_payload_startAt (dataLogic_cmdPush_payload_startAt[2:0] ), //i + .io_push_payload_endAt (dataLogic_cmdPush_payload_endAt[2:0] ), //i + .io_push_payload_size (dataLogic_cmdPush_payload_size[2:0] ), //i + .io_push_payload_id (dataLogic_cmdPush_payload_id[7:0] ), //i + .io_pop_valid (dataLogic_cmdPush_fifo_io_pop_valid ), //o + .io_pop_ready (dataLogic_cmdPush_fifo_io_pop_ready ), //i + .io_pop_payload_startAt (dataLogic_cmdPush_fifo_io_pop_payload_startAt[2:0]), //o + .io_pop_payload_endAt (dataLogic_cmdPush_fifo_io_pop_payload_endAt[2:0] ), //o + .io_pop_payload_size (dataLogic_cmdPush_fifo_io_pop_payload_size[2:0] ), //o + .io_pop_payload_id (dataLogic_cmdPush_fifo_io_pop_payload_id[7:0] ), //o + .io_flush (1'b0 ), //i + .io_occupancy (dataLogic_cmdPush_fifo_io_occupancy[4:0] ), //o + .io_availability (dataLogic_cmdPush_fifo_io_availability[4:0] ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_io_input_r_payload_data_1) + 1'b0 : _zz_io_input_r_payload_data = io_output_r_payload_data[31 : 0]; + default : _zz_io_input_r_payload_data = io_output_r_payload_data[63 : 32]; + endcase + end + + always @(*) begin + io_input_ar_ready = 1'b1; + if(when_Stream_l993) begin + io_input_ar_ready = 1'b0; + end + if(when_Stream_l993_1) begin + io_input_ar_ready = 1'b0; + end + end + + assign when_Stream_l993 = ((! cmdLogic_outputFork_ready) && io_input_ar_fork2_logic_linkEnable_0); + assign when_Stream_l993_1 = ((! cmdLogic_dataFork_ready) && io_input_ar_fork2_logic_linkEnable_1); + assign cmdLogic_outputFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_0); + assign cmdLogic_outputFork_payload_addr = io_input_ar_payload_addr; + assign cmdLogic_outputFork_payload_id = io_input_ar_payload_id; + assign cmdLogic_outputFork_payload_region = io_input_ar_payload_region; + assign cmdLogic_outputFork_payload_len = io_input_ar_payload_len; + assign cmdLogic_outputFork_payload_size = io_input_ar_payload_size; + assign cmdLogic_outputFork_payload_burst = io_input_ar_payload_burst; + assign cmdLogic_outputFork_payload_lock = io_input_ar_payload_lock; + assign cmdLogic_outputFork_payload_cache = io_input_ar_payload_cache; + assign cmdLogic_outputFork_payload_qos = io_input_ar_payload_qos; + assign cmdLogic_outputFork_payload_prot = io_input_ar_payload_prot; + assign cmdLogic_outputFork_fire = (cmdLogic_outputFork_valid && cmdLogic_outputFork_ready); + assign cmdLogic_dataFork_valid = (io_input_ar_valid && io_input_ar_fork2_logic_linkEnable_1); + assign cmdLogic_dataFork_payload_addr = io_input_ar_payload_addr; + assign cmdLogic_dataFork_payload_id = io_input_ar_payload_id; + assign cmdLogic_dataFork_payload_region = io_input_ar_payload_region; + assign cmdLogic_dataFork_payload_len = io_input_ar_payload_len; + assign cmdLogic_dataFork_payload_size = io_input_ar_payload_size; + assign cmdLogic_dataFork_payload_burst = io_input_ar_payload_burst; + assign cmdLogic_dataFork_payload_lock = io_input_ar_payload_lock; + assign cmdLogic_dataFork_payload_cache = io_input_ar_payload_cache; + assign cmdLogic_dataFork_payload_qos = io_input_ar_payload_qos; + assign cmdLogic_dataFork_payload_prot = io_input_ar_payload_prot; + assign cmdLogic_dataFork_fire = (cmdLogic_dataFork_valid && cmdLogic_dataFork_ready); + assign io_output_ar_valid = cmdLogic_outputFork_valid; + assign cmdLogic_outputFork_ready = io_output_ar_ready; + assign io_output_ar_payload_addr = cmdLogic_outputFork_payload_addr; + assign io_output_ar_payload_region = cmdLogic_outputFork_payload_region; + assign io_output_ar_payload_burst = cmdLogic_outputFork_payload_burst; + assign io_output_ar_payload_lock = cmdLogic_outputFork_payload_lock; + assign io_output_ar_payload_cache = cmdLogic_outputFork_payload_cache; + assign io_output_ar_payload_qos = cmdLogic_outputFork_payload_qos; + assign io_output_ar_payload_prot = cmdLogic_outputFork_payload_prot; + assign cmdLogic_byteCount = _zz_cmdLogic_byteCount[9:0]; + assign cmdLogic_incrLen = _zz_cmdLogic_incrLen[10 : 3]; + always @(*) begin + io_output_ar_payload_size = 3'b011; + if(when_Axi4Upsizer_l108) begin + io_output_ar_payload_size = io_input_ar_payload_size; + end + end + + assign io_output_ar_payload_len = cmdLogic_incrLen; + assign io_output_ar_payload_id = 8'h00; + assign when_Axi4Upsizer_l108 = (io_input_ar_payload_len == 8'h00); + assign dataLogic_cmdPush_valid = cmdLogic_dataFork_valid; + assign cmdLogic_dataFork_ready = dataLogic_cmdPush_ready; + assign dataLogic_cmdPush_payload_startAt = cmdLogic_dataFork_payload_addr[2:0]; + assign dataLogic_cmdPush_payload_endAt = _zz_dataLogic_cmdPush_payload_endAt[2:0]; + assign dataLogic_cmdPush_payload_size = cmdLogic_dataFork_payload_size; + assign dataLogic_cmdPush_payload_id = cmdLogic_dataFork_payload_id; + assign dataLogic_cmdPush_ready = dataLogic_cmdPush_fifo_io_push_ready; + assign dataLogic_byteCounterNext = ({1'b0,dataLogic_byteCounter} + _zz_dataLogic_byteCounterNext); + assign readOnly_dataLogic_cmdPush_fifo_io_pop_fire = (dataLogic_cmdPush_fifo_io_pop_valid && dataLogic_cmdPush_fifo_io_pop_ready); + assign dataLogic_cmdPush_fifo_io_pop_ready = (! dataLogic_busy); + assign io_input_r_fire = (io_input_r_valid && io_input_r_ready); + assign io_input_r_valid = (io_output_r_valid && dataLogic_busy); + assign io_input_r_payload_last = (io_output_r_payload_last && (dataLogic_byteCounter == dataLogic_byteCounterLast)); + assign io_input_r_payload_resp = io_output_r_payload_resp; + assign io_input_r_payload_data = _zz_io_input_r_payload_data; + assign io_input_r_payload_id = dataLogic_id; + assign io_output_r_ready = ((dataLogic_busy && io_input_r_ready) && (io_input_r_payload_last || dataLogic_byteCounterNext[3])); + always @(posedge clk or posedge reset) begin + if(reset) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; + io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; + dataLogic_busy <= 1'b0; + end else begin + if(cmdLogic_outputFork_fire) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b0; + end + if(cmdLogic_dataFork_fire) begin + io_input_ar_fork2_logic_linkEnable_1 <= 1'b0; + end + if(io_input_ar_ready) begin + io_input_ar_fork2_logic_linkEnable_0 <= 1'b1; + io_input_ar_fork2_logic_linkEnable_1 <= 1'b1; + end + if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin + dataLogic_busy <= 1'b1; + end + if(io_input_r_fire) begin + if(io_input_r_payload_last) begin + dataLogic_busy <= 1'b0; + end + end + end + end + + always @(posedge clk) begin + if(readOnly_dataLogic_cmdPush_fifo_io_pop_fire) begin + dataLogic_byteCounter <= dataLogic_cmdPush_fifo_io_pop_payload_startAt; + dataLogic_byteCounterLast <= dataLogic_cmdPush_fifo_io_pop_payload_endAt; + dataLogic_size <= dataLogic_cmdPush_fifo_io_pop_payload_size; + dataLogic_id <= dataLogic_cmdPush_fifo_io_pop_payload_id; + end + if(io_input_r_fire) begin + dataLogic_byteCounter <= dataLogic_byteCounterNext[2:0]; + end + end + + +endmodule + +module Asic32To64UpsizerStreamFifo_5b3f2212c953407c83e1cf8c9cc77ea9 ( + input io_push_valid, + output io_push_ready, + input [2:0] io_push_payload_startAt, + input [2:0] io_push_payload_endAt, + input [2:0] io_push_payload_size, + input [7:0] io_push_payload_id, + output io_pop_valid, + input io_pop_ready, + output [2:0] io_pop_payload_startAt, + output [2:0] io_pop_payload_endAt, + output [2:0] io_pop_payload_size, + output [7:0] io_pop_payload_id, + input io_flush, + output [4:0] io_occupancy, + output [4:0] io_availability, + input clk, + input reset +); + + reg [16:0] _zz_logic_ram_port0; + wire [3:0] _zz_logic_pushPtr_valueNext; + wire [0:0] _zz_logic_pushPtr_valueNext_1; + wire [3:0] _zz_logic_popPtr_valueNext; + wire [0:0] _zz_logic_popPtr_valueNext_1; + wire _zz__zz_logic_ram_port0; + wire _zz__zz_io_pop_payload_startAt; + wire [16:0] _zz__zz_logic_ram_port1; + wire [3:0] _zz_io_availability; + reg _zz_1; + reg logic_pushPtr_willIncrement; + reg logic_pushPtr_willClear; + reg [3:0] logic_pushPtr_valueNext; + reg [3:0] logic_pushPtr_value; + wire logic_pushPtr_willOverflowIfInc; + wire logic_pushPtr_willOverflow; + reg logic_popPtr_willIncrement; + reg logic_popPtr_willClear; + reg [3:0] logic_popPtr_valueNext; + reg [3:0] logic_popPtr_value; + wire logic_popPtr_willOverflowIfInc; + wire logic_popPtr_willOverflow; + wire logic_ptrMatch; + reg logic_risingOccupancy; + wire logic_pushing; + wire logic_popping; + wire logic_empty; + wire logic_full; + reg _zz_io_pop_valid; + wire [16:0] _zz_io_pop_payload_startAt; + wire when_Stream_l1123; + wire [3:0] logic_ptrDif; + reg [16:0] logic_ram [0:15]; + + assign _zz_logic_pushPtr_valueNext_1 = logic_pushPtr_willIncrement; + assign _zz_logic_pushPtr_valueNext = {3'd0, _zz_logic_pushPtr_valueNext_1}; + assign _zz_logic_popPtr_valueNext_1 = logic_popPtr_willIncrement; + assign _zz_logic_popPtr_valueNext = {3'd0, _zz_logic_popPtr_valueNext_1}; + assign _zz_io_availability = (logic_popPtr_value - logic_pushPtr_value); + assign _zz__zz_io_pop_payload_startAt = 1'b1; + assign _zz__zz_logic_ram_port1 = {io_push_payload_id,{io_push_payload_size,{io_push_payload_endAt,io_push_payload_startAt}}}; + always @(posedge clk) begin + if(_zz__zz_io_pop_payload_startAt) begin + _zz_logic_ram_port0 <= logic_ram[logic_popPtr_valueNext]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin + logic_ram[logic_pushPtr_value] <= _zz__zz_logic_ram_port1; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(logic_pushing) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willIncrement = 1'b0; + if(logic_pushing) begin + logic_pushPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_pushPtr_willClear = 1'b0; + if(io_flush) begin + logic_pushPtr_willClear = 1'b1; + end + end + + assign logic_pushPtr_willOverflowIfInc = (logic_pushPtr_value == 4'b1111); + assign logic_pushPtr_willOverflow = (logic_pushPtr_willOverflowIfInc && logic_pushPtr_willIncrement); + always @(*) begin + logic_pushPtr_valueNext = (logic_pushPtr_value + _zz_logic_pushPtr_valueNext); + if(logic_pushPtr_willClear) begin + logic_pushPtr_valueNext = 4'b0000; + end + end + + always @(*) begin + logic_popPtr_willIncrement = 1'b0; + if(logic_popping) begin + logic_popPtr_willIncrement = 1'b1; + end + end + + always @(*) begin + logic_popPtr_willClear = 1'b0; + if(io_flush) begin + logic_popPtr_willClear = 1'b1; + end + end + + assign logic_popPtr_willOverflowIfInc = (logic_popPtr_value == 4'b1111); + assign logic_popPtr_willOverflow = (logic_popPtr_willOverflowIfInc && logic_popPtr_willIncrement); + always @(*) begin + logic_popPtr_valueNext = (logic_popPtr_value + _zz_logic_popPtr_valueNext); + if(logic_popPtr_willClear) begin + logic_popPtr_valueNext = 4'b0000; + end + end + + assign logic_ptrMatch = (logic_pushPtr_value == logic_popPtr_value); + assign logic_pushing = (io_push_valid && io_push_ready); + assign logic_popping = (io_pop_valid && io_pop_ready); + assign logic_empty = (logic_ptrMatch && (! logic_risingOccupancy)); + assign logic_full = (logic_ptrMatch && logic_risingOccupancy); + assign io_push_ready = (! logic_full); + assign io_pop_valid = ((! logic_empty) && (! (_zz_io_pop_valid && (! logic_full)))); + assign _zz_io_pop_payload_startAt = _zz_logic_ram_port0; + assign io_pop_payload_startAt = _zz_io_pop_payload_startAt[2 : 0]; + assign io_pop_payload_endAt = _zz_io_pop_payload_startAt[5 : 3]; + assign io_pop_payload_size = _zz_io_pop_payload_startAt[8 : 6]; + assign io_pop_payload_id = _zz_io_pop_payload_startAt[16 : 9]; + assign when_Stream_l1123 = (logic_pushing != logic_popping); + assign logic_ptrDif = (logic_pushPtr_value - logic_popPtr_value); + assign io_occupancy = {(logic_risingOccupancy && logic_ptrMatch),logic_ptrDif}; + assign io_availability = {((! logic_risingOccupancy) && logic_ptrMatch),_zz_io_availability}; + always @(posedge clk or posedge reset) begin + if(reset) begin + logic_pushPtr_value <= 4'b0000; + logic_popPtr_value <= 4'b0000; + logic_risingOccupancy <= 1'b0; + _zz_io_pop_valid <= 1'b0; + end else begin + logic_pushPtr_value <= logic_pushPtr_valueNext; + logic_popPtr_value <= logic_popPtr_valueNext; + _zz_io_pop_valid <= (logic_popPtr_valueNext == logic_pushPtr_value); + if(when_Stream_l1123) begin + logic_risingOccupancy <= logic_pushing; + end + if(io_flush) begin + logic_risingOccupancy <= 1'b0; + end + end + end + + +endmodule + + +`resetall +`timescale 1ns/1ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +OOoBg4gI2nZAz8wwveQb2xYziCO/14ylivOE2CroC0KR1q446pg5ZHoTPlNXu9oR +FRdk+YQI93EEtwl0LJTuMb+sGUNIUS2ieLbzb7gpgkBuOgUljkWzXsN0p2S8f9nQ +QN9I/ZlxuRJ+sjdUPzEEEWHeUFIamGV/bFLJQRvloxvTvwLpmavqG6GhWi2vdXHo +7WqQVvDZRXw2M1o9dR9PdlpAkysf1TragnGQk5AkUZ3qOXFRHbxOhnJyTnaE1GyX +Oq59frbbD4+rLXSfc5EcBvIcpDJOgpRiCtikYUTFmw45b5M9gLaBYasEi8c7ZLIR +hQNrovA1RmOBbD4PGOXIrw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 752 ) +`pragma protect data_block +om+C6TrXX7WvV09MgL6R62R+Od59uPw5eeLNNbNww55GLUXwwj/XGluwdblYZx9I +X+OGjlllzxPGhddDes1uu0dNKh2ykfPsuWVHff2KPOJBKoYeNx6pVHSJR6EuePH0 +AhyaQM8gII6oK6SM94NjiC9BWcfDvsjfNZytp9D451ZvKE98e0NYabL8MIo9s2kV +hXffla5eL/f4PK7O6Y5XPFWrEpZtzAnWBDgKmEsiwAaDCKqGSY4iiwUewIaBv+no ++Ka4H3jnDmn/kGjkCfbajYK06RFHwFFJlgAzE5OFkMY8Ksmj63sVYM69D9UbM9DF +niOhc7FJg8UxSMZivgX9broAWkURRuJv8CeV37kSTWQY3ZEYK5YVCUjgwJEDCYju +ttWTXEpc3zXD52bxJep6OqjHO4n3brwnDjGeWrfb2IENd5VuXBspvMZ+2N3dGmpM +2nyNRZa7erdjUbB3k9+o0Efs02Jvj7TCsviSczk7axZYkJZI4mxPF+b8FStXCvEB +LXfZ7zKmlAcvi4QhCJ3anblnrJDeiGvv5UisphO/KeahF76MYUcZZi2tkiS7KcqN +BgGiZEgzvz6q/euENKIJAJI7Z+YoEOXDZfFoEW20WgSe2LbF5HK0npobYc8MHqIs +Pj1UIlLucUKcAg865RSblbpeLgNK5ryqdU+QOwi1pM8JFsgF48JfdVWMaFu9sWdV +zMNn55XZ4AvwOAnua8nN1fZ6mOpwJX4Ebii/zW5S/6Mm0kbhHkqZg78eXQEQMbJP +5YUFRgm2EkdKkxUmk2qwycEMEqLvXk/aOg48zpGcLAp9LwMjFRotYNW5+ygxGGQ9 +WR2CYo06vLomSI/uE7XlTHHUArxUtH385f1fq7V4QRutX19Wjq6GyG/YJWl2JURc +u+WqUFTAylQRC8Fhb+BPUoP6oW1YmiFwJ0LDM6xFkFWk7by/1wO0DdZV+slmdKR2 +1sxJAK6dd4yk223AytIzJlN7eZ9pmgJa3n4/X0QNDSY= +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +lvtXQ11Z9LNNq59Ajdesxcgo5CSVwrUQlGzmWsibhgsAsHyCjqyj0vMRSR+QiEty +/yyi7z21Q4K7YH9jOeDy5ci704W9tiZzbY6jJLUXKIB8tCJnB8DHWfmPTJjac1+X +kAprlwdHkFxurVjCyvzvpsDzl+7qd3dfEhaBAOQTrigUU88CdOFxwRcXpGn8arty +jpeOR3kDUSTf2tPHovV/i7635KJFX7o+tzJgPU4pQpgxBuHNN2b2rUy4eZxHS8/K +SkBE3iIjiOUYaJHZOgUGks3PvjFmmj3eD3ktt+v8nt/ozHPjJ7+uP8/p3i+qPyOY +4YYq/Ldon1lQeJanU4emrg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 800 ) +`pragma protect data_block +LXRln5CGH/X3ZcC9f1s9GTxumdb3ijnQQ2FPf5CLS40wU3FpMlOGzCsOTBaQ0U2F +9oguD9QGHXfbD1Nd7PairdinewSLKx8JR2NJDQobGByPc+ysqVmUtvuhRNKAl33p +T6XjMlhW+ErrSsLQLWyzVl/WuxdW9LxIu0sJtoA07ny3Tlv/mazOJBv/qiQeV4MN +ME3SEpILxBCTIfkZTacMxEgSQWExjpebTwhrH+qQ6BlH+G5OLRJkwgGf3zlGBAOv +WooRGb02wwE4zZT8LVq75rMiXDHrLTYLa33sLqoXQlIBMH8+EyVUyg803Ob8M3T3 +P0pOvZ3YinKmZt0udsR76q1filXw7Vr4pNnqfY6jN5Tcx4SfVVOrAgATj0mb6yO4 +PN5I8gqTmaiF2qTM3Z9OvVEH/15Q+L5BIfkaD7NrXvexgwjTCbQZAqOhro8gUp8I +0FU85AMYy3vh0GId10O0gj9uIqlBOCzpSPp4v+vxYL9gXe71r8jkBkx7xWspnrlV +reIqWJt6b5eVQ0Evqm0zoWTq1f3KG2QlOcv2XRxexmjrZJxN18uWjtHJT79Z9HdF +zD0dyC2++DANYrfY3k2Bdjq9ul3WjDfIF1IZmie5nqpY/Doo06O4BvzJma47Ridu +McqvFIpZnD8bO/fJpsHFSTGOJ/XgjTD6L/mAUMgNg/xywOohLinUAFv7btl1cos3 +11npbTSOQo68RlTNeyZWtZ+Jl7ymhhjlYDbUu/vXwSN4eZuWWwL7ZggynnqMSRC6 +mkr+GDI2YWg+2zYAGJ2dbgcgug8yKlwu7pGL1jXD2NIGOTpSB4Za71jBoqh7baly +3w+qb2Jpj3QpmzfCsMJb/QfVrtQ9pXl6uRnvN0hp+MM+hkRTZmW2QcHa0qMk5408 +UYZQGWsUBKVwB9lktWOt7QSXi7MVPzzHtwB0LM0jAYZGP9JXj5w3GXjKQt5lfdv8 +7fEoOfhB23IpJpo70B2ONKCH6eIA2BI9kvFO0JaafaohQixe6ZP0x6E1H9Uj1d8Z +uBMxCVtI9jJ+5v6FXlHl19YPtiRAPje2oBZ7f5kz7jg= +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +YZcxj4NiuiyaBjwj3+i08UfgElpJok6CAPrtf/VeNVjKQ4vA0nsIxPTauJCmLxEk +n2CsXLkWDAo0vTBJ27P2Gzis+Byuf3ie2/rrt4Nsk3r0oYiZI+/ne+066AsA5vmj +nqK12/q++uVjy1BnXRhJWwyJxZPo+9rnGQRERXZmgh+QZ6ejYS72L8ufrSK4hPmE +2/vPW+haIsw4iifrZaqfmJNT6OA24BG8ZnyU/hCNVUwzybiZ5NNgyzuo4U3x3eq/ +b3ZP5uRk7g57KmnXDVio+dAa5DNl+z4ImILcjLDJcqJ7TBRa26pECkiCFo/84A3K +87RH6WBz+a0EgK85kgWFBQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 5808 ) +`pragma protect data_block +cFcWPJSU3e2Rdd62+/WBbQ4M/VpTw2qhSBMfL8eYbNpdXnkifLxwuRR4FoMccpQw +e8cxhwO6YChEAaXawYmul06piurwYwL47Mztl2oLZ79DYbrxpVSfHMHkHrhJ5mKK +gVdWjF9ihtQ0I/uuaoD8MUo9+0t5a1YFFaMVzO4L7If7ZXR+qwx/Qbog7MTv0eGj +uJTkdSBLo3RUC1eGaDV6ewUTjtCxeVAtmeQLHVPMGXQo7dkXXuemALW8ZmUf/M/J +6xCWZdr7rAHAcf3VKTWZipGdIoKTAhEilZWZLXyyseviBUQ8V/TEKrhS7ei1SIXk +xoJdCLu3HWmHy3uptWwZl0difB+wdl/wAv6R/ngi21ZH7ibyk/pWrrriGn+Jblkz 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+033gGDVBLLjTa1FRhbPwsfM8oELuGAoxlyemGiQKg/kpSZypLUbq1rf6NccDfeEo +mvL1KQo4mQeD+4PMfADDtTDrgTo04Q0+dyYY9k22s2/rS7hLjbRym+kvsZLekG11 +buSVQbMAkZlhVW1Iu7gcQdM2bNT6RCmE75FMI7vn7/jztTgPV129EPmee5laQNXd +GHnBcJ/dJ0JVwoBSvi62xer/61Xr+fNVlUjuJauFn/PsjLJZZsIbQ6iC7gl7wFaW +Xa81QIjPslAzLVq2OOCBfjUzhTWXE4Sb/BAbmylYxQnml1NSS6vnaTbji+pntP68 +pUaliLDS/OOIza2PlYxHVG3zuH6b4+iQ1bFWeJS1kPYQSBb1smoVlSMeWIp/D32r +XIGWcCKsLzpdP2bMk3FfM8niIXjn77DyPNej9N+hS0TqKOdKLAHx0i0kTWpMwlH9 +nhhKvfPxjr/oXwPfBapV4sjOXrwB50W8t8cA650jPWnQLv8SfeqjIBcocy9teGlF +3R7DIDOlt31yWL22elg1zoEJh50nvSbyZAhYsplQnGsUE3C/XfRDjb6O7kpBtCQJ +AWyoJ0wbkimpYv02vSac0yzTuxMrhdKs3aXuWczN3I4sGuyO25iHqruyO2CG/0RD +dJejxndB1DFwJ7JVHy/JaRFh5qmxehOVLJBmaeqH7GkBWvbnQSwoei0LN9qL/LPK +9rcFAMy7AtD/fXqe+IXxtzdmEdteo8IMN+vhCm5L9gxtIU8wCvxBvhWOxYo12NIp +frxsi3IuIvxnuLg+RKGfOaBQF7v5uDNkYLHBmT31zx7Ak1UAWnFcnFPC2yfC/qrA +7ZrIJlCEoigiNr2Yi6A2Zs4MSx9fMWgimfamgGP6+/ujmEQQZuu2xl3emmmc+XOg +Tnv6aQPfcQ7mfgJ8XZH7x5SBf7anOZ5EkiAQBRPSuMY6LwjD2cv4zZRg+ZmidxEH +TQ6cTMB5V7I7JvKj1GKYi/YtmULWziSI/RrI6bO760k96jz6Y4ni6KgdfQkbMXya +EpbqL+YyQN3qYLcjxFuzboZMrv2GrYatoiADyg3ROQ5cujyrOkxuv3r8hk5xv5et +O4lyBPRrC0wjR+edwSiecQ0Y73esrIU1CuoVV72gdLWfad98Li7pUUiyIn0mcfAO +MHas/cZtOU0VGILzY6ExVkizMDHAbiIUghmu3lPyMHGRsrAP4RYZHHRlAOowi5Sb +o+h3D3eflkK5rPIB36kDtMzzuhq1JEXr3Zj5HARBXnO57KbuoOw3GfvdK8g498zS +axGgz0m4OwqkwYBsuNi9y1tfITOdtxvjue4/mxzHLUWdyBTahq2Gq9UO7sPPb2F2 +0DAmbSrScu9S/dnZ1KQHx6rAWz1hWzx7oP0MgzOLJ/moyFGi6ljVwuRlxJEFr277 +SE3wbrkWgw2fBZa322gBujMzWTxx+L4xLma2qcdyJ2JM0/mKTucy1315BvnQA9dn +pJ21mZyh6XH4g5HmwYOyEFicj4YlEWrDN5ptFUzPjlgIYcH7DIjZMDfBCtLhIS1p +EwMqO7MXO3MqRZs5E5PiKrduY04kF41aB7x+1PSbRO47WHAVMhnWeCS4QzUTPRaV +vKo9uVM51UKszmxhXVhij/gi17Hml4tPJe6FteD1jP3LswycfifeDBgw/SCmdbGe +yP9D7xd4rLXtN2TBcyRDjFc0K/5fzMvxlWYTxrz7fdh5aLusbBjIETYFL5y0qOOx +uNnfezwVGFr/7Bp5HXrGwDLHBlRYOu2HrFhkrvoprISX2qgSHeJFL0kHH+2+V6mK +w3kpDJsDZi+QXVeenKqcti1txxSg/MOtNZhGb2eieYo8lI4FZKtQCFA3dWoeGjuU +SpZTDNzo7pIHakf4QUqrYIE1gFn2sNoCbBlx9CDx3ks/PzCDu3uqakh2O093kWQC +/8RxJuzcN+TXoLzz/H0BsGC+1K+Fo8YwQnsLj0YoXSBrHV1hoNBaDwo+ZdQE0KwT +B9huJ2kaIWOG3pej56lMiEiB1W6sQzCYlyfJzt0WCnCRwPNmCa6LGnABzJIYNNhV +SW+ddECTo6TgtdAKH0/k/QalAUjFJJcSRoWO4pgiR2yl65NSOH8R4bt3eMnHohWQ +aNi/l+UX/thdnaAvCZWa5Pw/coPPjvmwvGStTXXrLeLCiliL/DvGgcKSocebaki9 +iF38kB5/CrVvCeg+3G5cRfnjEj9Wcg20C8gRX9wyARDWq8IH78NxBzucmaPZjZyd +eSq09wViYxsMHYxVeblHqgyyzpS0sa9sqrgbPKIW1NtWQLpC7GQJ0nBYGbcaV3p1 +B+H4racUuzHzTbLgEkCXxnL4Iq4+l8nrao+CAKw/iEV7ZrCclvXRoDtOu0CZqBRz +8a90qCPA0xTDBSCkFFqmR0gLN8dKIj/k6fMijBRDtzk6xXqF1XXdYt8vZPTK4oMv +hOtL0ou35/o4JzD2QI3GoZhK4tx48gE9HZm/6pdHfCdyr6Czt2c/ravHkJYAyt7N +dVWd4ZJSsnE9oGXWqqUf/m0Nwilt86ouFanggwNJQzqBH9nAs7z3a1Ou3ML0wOBp +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +mEtbV9EGXcpC/6yko1/E5fksxy4umj6Ln9zdp/k87D3GnzU6MtGj2lR4GCbisMd+ +Rbqmu++LZV+2wB32AtLnsLppKmsYhO9jjXRe4xPQK1niY8CuPx9Fr5cd2zq0iVnF +bFX+yY9CqzKEM9Mvztoxmllg6ROMAs03PPD458s652wcEEnPn5klZ2tYXy1JQEyI +wuK0EmtlFp4B+IrUHiZZJoJBxmxQCtz1uIZrR8PF4sBs4OO9W5NB6s4hrEzn7Jkj +sQlyyW4RgbyZlTqNt3mz8Zwu3iGowx4s4CGhhIpgPPWdlJWY0smeNKsbmJXvOn+j +9uRi9+ghgR+LTAxZo0Ibig== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 2048 ) +`pragma protect data_block +HUh4J+fK6YFhzi0NBDbJqMMdiOtZRe6d8QSG4h9yRGrUBaipIeawvKRtVUjxzOVk +Jrr8kMcAoGyqVG3ZA5rHQbVbOeS1eTWRktkUtgQJkbXJKY27q+jdqM6STe5Xyk/V +bUCeN7QwspaKVLlT+Z1OpcACekiWFgy7fiw79LHgI/wAeVv3w3YXmHvsC48YOuDq +XBKV7gOooz7/lzeIxEL61rgQfg7uOt/BwmbcqD0nzH6NRBrp6AA8vleKetSB8NMi +gRNcQ9ZHg1PxqCxNVVzBmtgFf0Cxn2FdzcyF0BfmBA78aD2dzze9hZT5orFv+/zV +fEQhjV2iAj84cfyH8tSIlnkWMMsYQX4fqdifZXOUtJ+45+uZQPkJ8idEnVj7k8be +zniyfaOum4sfspPnaa1fdpLwUMZQyOW7ZmKD0Ioistig9GqANK23zV43QKe/bexe +jmqhXDJANp4rJ2T23FciuAPkQGm0zeomzIgpjNFTtemGaDrHo2HYY+cpe92e14QB +0glxi1M35cP0FLbHXW4yFIjQswOFRLlY3/GbPvfn+9yJkzOjm4vhq0w40egknNfQ +2Np7SbqTtdRJDVnPZ2oo3UJkBCA7PM8kce1i3XmeIAFuN8m/TMKYV5WJQJiOTDyk +0XVcz6pahWl6rd2HwMLQgbpSejPudFTe3uLHS5Fi2aG2RTpHTYSCOIkNC+DovvB5 ++UzBIUJz4qx546ybA1OWuIWwmUl9BQnt8cxU6ARH+Sny7uRYL5X8RLR7G5qlVZGJ +gs61Eea2+hHgdnV/PJAx9HLDa0t6Tmwq4P8OD9OGH7PEPbPXY45/MDa9Ch3LX4Hh +HedkWuG3ryOYohdpMcmCr1zkojZ/DGaL7eqMKW7JprJxiXGZdoZ41aXt2eiCl74C +TVxPm+U4SSHQh3f0a78LWV7U4aSHb4SbAWaX4mUZE21RaF23DmqlUxuBYn/6+VLJ +SwZ8aH/eKwtPkXwaZ2gXtkGOMxbIgs/GKLRQ0k6sr/EMWEgYXpgY33LNzudM5u7q +XyWfoJMXciiY5uXUovD88q+1Ni3FUOD/brmf/3W3Hh3Db7zmkDcWvT1FDUDcGXep +5xdkPwBEmRaI8D4IYTVIr5kv+BsOFOQZWjLyShpJXPMRJ5g7qxSyUUhhKEgWkt5a +ZA79/VsXS+UQHfIPcWK38VPmkhnLopUe7Y2IoQiDxJJ8gkVfeNP8CvA8VRU2UMwy +SM+kjbARwKj/dLQ1GSYNOwEsTJ6/4M10Bc6kX6DCBxFjqs8dfN7LatGAvifFjmTt +Kdjb4at2888iGfE1UrrsE5NhETXXXdaCLYTk4n+vSvkH4aO4GaWq5el1NeZHvZ4+ +wFU0e8qENFYoZqM01NVm8ij5qtfSqEhuhtgEDhcYc9SXl7yoTgHQ7K/jG6dvfRx7 +p/LmrJj09+N+2ggcsnWOW7gWem7mLad7sAVHlxmYWWQCqU297iKmaHLaPBiqdw5z +/LXYK5ssju8oJaRyieEQFgD+kj6fZHoskYnyv/GA+PnGOkpyGyFaNZ+ZCoVfQWj/ +jGSosBOeflbi97GX9zcnz1kb6/XGWMZO0TQhRjQmLTECtusDlG1mDs0DVHXybjkF +N1fg1l4KuoOI5+sJkqPKAvq0LoOA+1hNUQ0IEMj51stxOiKdiIJV8P2TjFlZJYLs +YvQyBBeYej67sSKpFHPd2yrOtP44NNQAEpvjPt0mKhJXnzSN2qZvbKSBOgn4Sbk0 +9i4XJ0hXqI0JF23f/zw+aAlSGC6NiAIm554hbB94QmEyU3Ow4dojWO7jzkvqfjBR +ozkcMQfuqsBof3gEjovlJSAoHAvHK2w752D+xoLdSzT9iO+UlFCuzCAXblzpQCUO +Ud8xB1E4fgXx0HBegDqx4CRR6Levsch/Mldrxb0JqkgJ6Bkl+FxzmkjwaoYtwtZP +kCZly6WHPbc9D2tAJapm4P0FWFDsnBbF1ZmEz/aWKKkNVy+1P2RAUjChcjycAfue +3wygkO0ftd8oRoCRh2sfzZqJjip2nd0U3YeMhZMV9795zTA2S3v8nv3x0kScC7fK +fXCSZZtWr1J6P1pmcWOTd4f52+Ym5K30EDmu6aXC7tlnUYhBwP7zP4nhFy7ya+dy +eM3UvUd4oIPed/r5rvmF3uJycmC1ig9F6BCgKN2geT3+vi/bSD7RVlTua01tpcdT +dci8sQENmUG7hZ80aeZrZVmP8tWroI+a11/qAj6//drn9qo2/YnV1L4AWvtTnS71 +nbu8cx6B5LhuRMglPXNQWcPdcnqXG0Zu0WLNL5mbn/xjI6q1ksl9Ket0gyZiF3vv +u+c4jrQw4v+36b+nRby8L5rMDL4OdtLrg6ZJZu+nDIOpW4+XcKNDmS3GjgM1gBmI +Nniqq8O1a4Swei4JOAr6G0AJLDNZ6WZAd/bjUOFFg30a3+h9PwVuC34XI6XH1Y4b +nDDn6id74x0Fo82suxDTVUXcvLmO+YunWR/r6EOUmfFAVbww7vKsu6sGj0IVjifm +9sx7GJjNbunSQzLwcSQDMryZC/E/+uzBK+7Rfkynq5XTDPJlKTWxwsx8PmXB59DH +xR4MTfIS/h0JTnlxZfGAuHRoIccuaf3n3jI/OYEvyczsoV8PJKDSXtWsXeL5Sby8 +2jMXA2rVgYqb60AVjct58Qv2VCJ0FM2G7dxkENdAOwFb4yfKL+pynRvPYg6Q9UsA +1lGiJmNiNjrOEWcgXi92beZF2WZDdfs7ZIw/qwVgYuA= +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +J5uwiQrMgxLjAj13SAy3vsBmkypkUHuPQwyAno2NI+dh6ADhBeGoXkLbyWfXNO1S +b05RGEBtTRrRNY6f8sSoZPBYR58MJ73nuTvU++VlZj/tjtveso5nLIb3L9Vkcd9u +0AiQMLa2c0BwzGlJOtCwvWFRdnBcL99FI+19wu3C5WuQGCEmRoMY/ws1Iqm37Kqw +U1xX3Dwt8W6rsiXga2zZB25WuvJH7x4XHQfNqjaLhKknhS2JfB26tukpUQnAWPnW +dD5cGa9rs9jsi3/A7lx2vFtvkxyCF2QF4w0Gp/PVpiJE/shh4MsCHia43FXoq7AA ++ky0TMuOm0HojmlyU4c00Q== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 8624 ) +`pragma protect data_block +oZ0GTgaY1jFft2IB2hWTqNnQiodJUwzfVbr6akyrVbz3jFePptbD6OJF+iN40U5m +0daNATJHzAAhGlugA6j6S54r25yU4y/t7UJwm+H831ajTDW4z9BGSYJz0wMNw3ju +4JMlN5OQxPLh+7lN1i192UAOe1M++DSrXrfGhCwrZD5RZMDC1UiXGtimTv8/5oQw +Zmbe9WZeFxEX2A+HofUOuEdMMchLziAg1HE8FW2cG3LL4c4Ymco67/+jdqrtpFIz +zZymAyvBPZd4u77o16AitfasOtKfKhn+wk4u/BvRNFNcd4x4N2vNR/b+MOp2Oz3v +0mESKr9rFsQcz+nn58QRO87AqKETfMbvC+H2mgLRR4jfdTDjb5wd8a2OAFIwdZmj +Dx9HxKyGAkbs1hDz25qYZHEN86Uok2UN4m4Y3x9edwjdprSd7e8hwzD1Dbfbhte7 +akuJglUszDNYuDqmJSvmZT1yE9P9Z+BKj4krcs0wQ6bRmPOmTC+v5pm53HC46sms +lwiy2x2BjLpyWJXWWBpmd4tHBpXJwy3xhc+YECnyGwgeTP+IfjlyYuSBw1XhjRMz +xCRuQ8ERkhThmquMpedpOcQqNlY/eOSXsaAb49b9lZAzJoYkysUJEugj3acXr8sQ +ixUwQAYHoZUFuf148eU75Pe5g46di9pJ/tsT1Lgw3+sIDUhHFVi05vsHop5EqVVU +tSyEF51g9pnpKYtniZUSC1wblp0pWZPr46kjDMQQf+TTOReFg6U9LVNkmNt7wXkL +zSl61xQdDP2SzIlJ9NZ4LuWtPbCv2phM95WMSzZpwpibh/r1RU+0+SACJCJ/Xv8I +m1k8xKAP30qKGYbwKAeL2eTizUNqxHHeMsikd2d/pi58Qn1NvtwZXvfGrpFdM0Pg +GIyj5BUMTpyDBODwpwdqtZnoOhbN8E0nu5Y6j2kbKkb9jVh67+GZga6BzDZ4HVTX +RexVm+BO2zaGk64cV6WC021eEauuKZs1OU/57uF+NrIN3FQ5s6ST+JOzT+lTySpG +9KeAaDJd2WI78e5ewytrhbE5XPo8Voi/kInyy1NnNIR4rOYU6SOxd7V4Jl6xaaqJ +c7GLAnTCSZn1T37LB7gV7fUYOigOX86fxTc8xD4TXRibkNODXeKCjE4T1j6RL7+y +hYLDCmysyURiXv+EYiWhdFESEYFopkex9y2YN5d55noXxp+am6KfhTVSgzMRD8+1 +Iy/Z5lN6GqPvejjnHbuDkxgFdDc0WSxDGjayOyExTprybFJ/HLOLf3m7DsPYttHr +5+wMOhOryD+bpWuKdKS/J2W/73GlGVWJEaK1uhqJXDZyBD8TgGldEkJuqkAcMLC/ +h3EE3+nzwdU/DX95k9nA9qkceRyCseSBnoC6QKv9IAwlM7f4OZ6NZAtO4h9jXOYs +7TL+F+3bh2TsZvm2rvZohYLL2wvVhIeu0NeP+l9ypxV9JsHSb78svd1hSKEfyml+ +V42rWWi+RLlNptR9Go41mh0j/v3mH0duJWr+veqtiv8Qcctfz5rUO0Hq/i/yhMoe +i9fbCPultUKMjN6N0qUL6YPA06jmI5fKhan9cH+f4YQfgfLzRtIpn8tzdS/Keuh4 +FIDTB7MHeM+NopyfEjmU88OPSRzmEEQk0k1SJcxp1ltIf6xysYLxoLJxlHyWnREg +Kejg5ynZd6bLMSwtelBerOPj0vGSii3Lp/qKowh7vE0cbs8P3qFFaHPIv75Yg4py +sk40lb4tVOvJTCkNSLsAeLW6RvR9t4PD06GRfktXWEdOvaeiBiYacixD3tM5NXIS +EOr5Yb0YvhaLs+ha3SwR1jjVRFP53FL61Ut05WRQ2kG2/A4DTkdxuECDiYDcxtOI +rSsN338KzyPCyqMi5dmGVBpyNN9cR1FLrKhVMXUdiYgiD9kbtibhg7phh0+9BrvN +G9aXtEHmyZVl+4inaEkgw9QxBVq1myxtVAxiSzaf6sPtfhCQcdc8u6qZj+HTqp0s +rcOiAregtA9LPniFYNWtmKwKlnj2eDgupAQCxN0qYjfmCW96IQLBu4QsIifB755M +VCJDL7Z5F8GaooNNPO465dZV1jfNzKgg6InSrYYWQFPYWvaaMT6/FtEjlsYQy4WI +8lNe6PIcCnAJT5qcYFxWv29Eerv/lW1KPxGFA+cZ4qjwsTulVTaGgV3+OvtyF45i +HLhFRsByp4T/rlv05E3wbXXvhAnp5Mw+Hss3qKZaQYr5zpjZL5ooKh7haY94ig9t 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+6tchOOT/5XnWTj5UGmMHH6C+AD1EE+593b1qdhQv9DtD9gfF5xdqb2m0QbQc0Li3 +9iIrdCWC7cLalnsdn1m0hPZfA9dfqVfIQE19mO7YqQonV3uwLV6RBMvbvyoaIVRa +tSzwNYj5V9fc+J/1KU5XaY9V56XD6EjDa6RD/fyu5ZbpfLuvdavbswSDYnakHh5p +ctKeCrOK07oFPtSPCQjTc84eNRaw6gKaml8ZPtvuQwfJPsDnAJ4XeAqy7B+2A6Ij +NfLnGt54vskBkBnQz+VqemZBTAM+h5g6etoe0SdmVVOJviXT40oLyh3Hwd+jUPP+ +f4DfYwwqiW23WvEdEEKNEaTXfqc5gmmvGjcnqWFcLhScXIueeZcUa7HwtMTjSxtr +12a5UOwHEepebFzd6dMc6BkUnbBIqEKvGzZIJH7Kov12PrfzLk0FhiHMQVCrqmBg +xiq8i5zpt08Wxw8ZClp4v1USkVDR3yXcrAS4InvKa/ZxO7AWIUR1B5+w2mygbkxc +KMluz8sKuQWe8QJMxJ18haqRSXXFPK1sWwFQ3G2MDQtK0u5uzjaJWEzCixqIjEvG +aPiPoU6oKh4b0Tynsa/X6sibE8hPt121rb77zQSr27QLFSu2EEZZhk6GvtNMT88O +0o+fHPKo9UJVXTqCh/n0gjYLx5Fm9UR6hhUVKWS86LMqoq++UlK/VhlPifBer+W4 +Rm1U5WdsqmtVP1Af6Piq3YZhLxgOUZiOinlpT4LV2KkXdMlnEgAIUGH6RyTEtKF3 +JQ72fPPjsv3f4X4mm38soHmhIvf7hVJVcUKMFXuRan7qEpWiwsJSVHh/Mfkmowee +8MThc7HvPOj2OVeLWWTkW/UXxK2aD8xzlyr91BAm13PycbfjjHjKsv11sVm3ynK9 +F8T0B8oFaZfDshBGXENi4Ct/xPE1Cao+9ngrI5Y1SH1gNxWuP7GTmTW6hzcWHD5t +bw+tyV8tUbSIoZBMhwP2vD3nEVnBNrVeWB+rfth+c/3ZkyitXYkU2icVq646epIx +p4N+rop/Mffky/9U8fyyTHCU/bppSuCY/DmaVRhdwUdGKMbvd2ENS1hfK910Dmlc ++5UAJlPpTx9MF+GKbJD2RxBRyY+SEeeZgUULJJ1mvLGTy3JGK5r/QWzmzn2V3mXB +8HwpV9tIu102yT1nwE3sfQ1m10PL7sD/jE8edNkKN3tOHxCu9cQIESRxx+DZUMln +KiYY7MioiBAOwZWaOaPFm7Dl8qaPZAzMlWstkfGXxBoCTFmEk3MJs7PAt7ORmmSm +Qx0CirSeW7S+eMiDmoyaXqHDlWjoObqrP+qsP5NSEvHFIUJIP7lR6HyQSdiLUSN4 +MdmCeHep+eyraWvxVbJIUgJpUvjz1Ou1iiojiHU0aRai3RnXKQWviUZlkNpBfaJ1 +vXVL+tQwfkulj+wZ529A5yYc2d19GHkCJQL6kcFcxAxmnq8HHkImFM6Xa4cNrnUQ +UCjowezIh5WOMsxFgberDwfi5xD6fZPm+4JJabJvvMcczsJS2WGFi2KldZ55nwY1 +e+zh/AS+nb/aAWiWE88ty89HHATXGV2TOqRL7P1GRdWEGfrzsAwDqeYnQni0MH2Z +TuNXCZkvIe3JkIck6CgmAkSoxN5tBSgW6U4hRIBo+QedLrV5QWfJaCnPiEOm4qfA +HOQkgRa1KEh50CCCIEsiMfG6+uoAeKs/SbGeWEwBNFJ/VQNDzIdcBFkTeR5u+8cl +24sTpOrJW2oRN2PmwwHDlfBvq/Pr+9wBfSBy43cK42+7NkodyLIPoy/4ERTpXVme +b1sR6ZaWPlBfD24WkUrBHePuaSfFh3OXI1vQbdOYVL9FScYoF0AFNvg2WJR6Ngsz +4ju2zJNLaRif/4wHIJdsXXmb2wZHlM1y8o6MlXWuX81+P7wgaQtldH7VQOEtCXZy +JRA643/2XOamn2oxrSEQHN7PU03HKVI8j4TYzU2kVtQ9ZqqeoqWGBMo70wCI9hIo +sXPt7UbwQ0jr28hfJZ/7bCZKiC36MX+7cKP63GNnIAILn8IuUwaO1y9Y2ejHIfuF +2N7ma1YPhjWKMsI0HYW9jjTdmqQ/xaAVXRvbTfjAXPSH+FNT2MkIMCZYYM/Ti8WU +vxnBpd0gSLKzsFvnNCDLTv5bXHWdoOJ2RJVf95B+SCeVqHUaik/iEXPxQVDrUOW6 +LLD1dQXpRCWiTiL3Ju9RtCLK4LKXBDAOqyWeK/MNN6IvmOd083bo7vlpJw3ksy8p +fl/FzC6o2cFT+Z1Dt1I/HypGuYgCthj72G5zNuTWEPnf7+cZRDTIaN32fUuobpmF +VhZNJUPcPv5lrHc2E1y6XRFS0m3Ngzg5Z81M1Je9bFVVWYcXz1RDJ3hqCS3fVbti +8rzMdh/lpmaXB3JMGXaoTGdJN2cTpWLHIQS8CG+Rf+LHjUDS1gCDNq80F+ip3yB9 +HBcwyl3MqEWyhiyY7wHaREvaM7f4NpLubezNM9nuu2FkiXbIN3UCCnbLK+rk231E +/yX3yqBrWGYVQNDq2CP5yDdRpHJLzDwTwX30lKYfwcI= +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +jUjs/IOtuXb97xlmyLq5Edj4QcB1X4njm+CwasvqhiKDISF/uEFDJMVIj/u+M795 +kVf3cOwkzvRxZbOyaqa3d3dNrJpmCfLcCQe9XSPq6gw7Zx5h7mCBR8CgBosd/bPN +dJDcmWwSeM2dAAY1L8RWZaVAt0ECVzK/jKZ13nbpAbZzrtXkLSGEm7C2YEoVz0ZN +pBI0A7g9Sefz2Hy6Y0d8HdbJMKW7zm7KRME3k29eMtEmlE1qKdJfxIduXCGWs2Mb +qKWPodTwUcLeIzd872zib1vwIJdgR6giq/AJhdiN5IcJxFDvjjatsulWYSfE1iO/ +jiC1tGg4ec/+iJP41bbQRw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 15200 ) +`pragma protect data_block +KdNDALrSiDzN/aVTuRIcd3tYoSHmqNEwKAMOby6rJyhY62B0zOwd1/PkXsicwrji +SE6MbG0JEsXRHFgNneDXFDdMCoHDYrKL1s41Iw6Tt7cmuszErzY5umojyGFgO9o+ +ChLfS8W6rbLMWO85cc8UwpiiEBKiKa7WF5aM3fLymhss6eFjoqtkjNCFjM8EtcLI +fAMWzSX9mWKiJMRZeknZpLP21dsjYDmEzWQ4ZNGVdxMme6lCd1xiwkQXp1tUnNoV +KFaab2gLghoP/JNsOtimnPV44pv+O7vp4Pcju9puVpB8u2V5JU9bVvjJ11aD2aNN +ETQPGtEPu12ABXNGhX1uIGwYdmBczC58WF2owIn8NMHMp9oiyj7mMIpr6YkHqGJD +7VUemv/WRidINkyXxkaJ8ArHXixKdT0EM+okMDz9hlh0fTXtAnOpiNMv/dclAGMa +xkDmWg3tYj40QfFgGIdfOhbWfg/4qTvHIP1VN6VXEdjaBsc+AVUvyZ099ERutDz/ +dBntwwOAyI7IjNGQbe44QCvty1cH7inGi1HEQ0i6Ca0ibm44mJK5h3e7j459MXJf +WM+FZa3P7A/kV46TljSuL0jyGvfPHwVchF9X8UWiQeNSQlk4qUrJkLAfqSJBZPNb +unAQ3GYpPs3rnbLZ3lQoIWc5+CZEgUA22ndLe9PwgwC20cSO9huHDWmnZPFZlPt+ +W2JyZ49wxmQUUJ+AToZ6mBKJSGlfsLtaoSVu/60ctxuIq8ASnGm/8iY0G5V6GEFD +b11srFlGG4dSG9XjGxj6+MIwUKucL3XUvi54KE/xj4u47YJCXgQV4mtDT0bo80wg ++tcc4uup4/cow0j2PDTjwlDqvGE7iPwsFm0oIjidzpfEuFxldIbFzk6DcVgOeqlb +dubk9E+/d0exqS5g2IqKEUfrQjntIdrXjs9b274JhgtLXzG6RQbjG08tGUVKmsYS +DDtJEeeTNu+qXM8hyixPLxVd+ABocUUeNrdPY7bgHX/IrVhtrep3HTVTR9tNNsOG +EtJN0PKWBeCL8Osq9zCdzTw6a5/dQPx01lwwRxwW351oSCZI5zwG3Tuqrt3cYkDK +y7uIY2aZWDFhzyYpclXknK2LZZIJdTJf1yF3ICAJlMNM6e90lnkp5E+ciDC5aiBu +FJBgUaxeBCLW9E1RCdl71Uet6ERBkEgF+Nb7W85MCXfTao7deD4W74hXDF4ueJo6 +005qPsnfR+r7MTum+1oKdQJdNpAEBAvVdJ88/hdL1rUvhwvrjMtZm3dz7ICxOOrV +I/SopOYKdzs0oyDnbjqHBKi2BKw+EuIuZG+Xc3sdS8jVzA4esWizOXumOOkl5MM0 +5WxXI8JcXsMjWm982wD7qFkET9puyDe6lSVk/nV6rjVplTYyu4Fd7nCQfkMDjEH1 +GfXrq6+BNCeT4jf6H1UT448OQZCBlj+gLDphg5Mp0fhhVGT+Fl8C1qVRhsSwBWC0 +s5yCaB3L9deYB37hHsd4MNMKBlUZOvd4p5YU6Kda/CaL0J3q1wSd2SgTnCJl04Di +iKdFNCVJCOxmvhd88WS9XiTUGj7gnJnFKpzQcTmYLzFkijnmdwvuSaHynfvd7pJ1 +8J2tbICPqZb0OyUQOMbr5+VLS57DMYvNaNMS+1LuPXYxhAGYnNBx/0CRL1Rc7LQw +X51OdaxfFU5AUx9J8upmbM0iivAk5rb0UvqXyeWvcSD8f/w3fg9fNBD7b7hVW79N +4BnXYghP9LIfPs5C+cd7R+uyLUk0HFrk0+DJjcSM5Npe9mL/Ic+my+HLagqRLbIg +R5p4Vu8oP9el2xZ4es8M2rpnL3C5yYv0lzdFb3txGTJojETfOShLDGcTLZsCDwVG +hiCO7z3GmFcyOpzwDp+tNkZdrBJY/4xJIId2LmNErDNlgVBEaGYYj63Gw2E+RGhL +SPY52ZCmYs3fHbYrJmsxbkP+Jak+kXoUYMZt6LRl2DNRHHCisHo8t7hDy040HxnI +bmgxE6DyC9JXEHZgVC2PpD0ihO+kvwSAhDe/1R4CIRkyCH3iQ3N2lGc76QPi3ggY +1l+crSQ+wyajwOyEiR8G6A9fzE2hgBV+dCWKzV+BNQxHiEomZkzp9WGY5gdHcuYF +d/5yFzT5nxFAAc+KEMQE8nQRYxL8EbCWFjqE4xzWCP4IgQlzxSj2LYcJFh+jnxcW +4r/oLZKEZZGUSNzqKOfZ/37ZXzwAMRH9Az/qUHIyZB6n9L67MRuehiigYTef4c3N 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+Z7p+EsABfisuGs0LIq/k7u6Dut5q0sKGz+K6zY9qEo+P7sM4CdS7U6MhiYl8cHrD +VP/d2nINI5ZUgyrOkGO7v8CH8tZHvhl64GS9vCRqCjz90uXx3b+JHFTpsyMmxNIw +HXr9udJoC66LvvV2G8vJ+9HpDSNZyLUGb5p89I5iX2ZjYpL4W9PXO7ljA1ZRidw5 +T+JPhbMJQi6IpFAT7Z1/D5Jxx66lHSFNTYzQEbUmolovqljDQD63eAxuIQKUzXuU +v+ZZ0P79MM/C8B7lLIwI+B4jE6ku7AImY/hGyy0LdJPq9/t2/1Ro6GaHDEw61jhS +vpn935hkVpgOt90dnvwWPItfCvKMYL3p+c9EtndGwVKMKRKQIcDUW2qh49iWUYui +pgUCONn/LDxaT9o/eAyf+9t3aGdXQeorc3F0vW3MlV1PQ49z2q75UdDtzaSNJ9fy +gNYoCRXqFdUo5lFwlsJx6XsuoUU182nhFythlyCVSME7GLDY49jqTtCoJ+GExU9g +PMjXbKl1bfegqjJCIo0n/NAhks/2TT45mU0QanXQjLo7JirD/adXi0NZ6eLj7OWX +rMu110LC4+nLXG4i0DuK6jQmXnpmbVjetHKw80Ge/HdXrzpQRS8ZPvTJ7LsIxOOS +Bz6P7V+P8zixWcX3Bw2hNcV+yUTY5y6Y8+Mcq8pOPZw7836r1mRTY7P6k6gVLep3 +ixEW8sMUclEIiPr42EazjMzuG9D8Z2aq0vQbnzslpGBPoceSnQX2mP9Keej5ux1j +dXKNb/VMBLTOlPkQKJHz44Otj7Qw9J1L/QAwP3r4JQfuirSHMr+RUrFKovlIrMPt +cYUJrJCOB8eQTSb3JWbGKmbSNE47/t2QmggJgfZNyjPPluiIodKzyACxDWt2kv3J ++kabEukYi4GoNOZuTsuHk4M+9TCME9I94AcOmynSd+7naB5w+Ddn1XfGih+hq9pX +k8Ug1HLtvwkeCS29DXRLMnvMxKG/cGWN2Ks3y0OUG7VhVPkS4ciU83zciG7/wQcR +yM3R52pOdbOWOV7LtqAJR8WtGCge446nuuPQ3/h3Zrpoy6MTezJ8tu7MGUEvTz1z +Edo+r8wvmr5kt2lInDYQjXZlCEskNM2Dsd/WHZC7mkLUDqHFdL4nfSyRYZCRJFoq +MVV3nNQO2RMvJqPuY6rO2Y3tDhF33Ulc6uURsiQQQuPAqsBxF1Iq55TppHYsQ1Vx +Idul4Cnll6sri7+pCdFOOuV0gTogZgfqqE+QnN/vnceEj50chmKRZH/F1BKbDJoB +OEVr+eNXZWPl+e1NpalqJhVjn0Fi0WhqVXDqbePdzfaZDl5OUCDKbNCo1aZbCqqm +bDNiVvdM1nGmSJsXvPsSYhOphq7at8o8TgOOUbYt2cu3gEwPPC4jds9MmkbXpjBR +xzsqIbDENujeid6t0+N7VB4WS9+i0JeY+7Ly2yXTgfPuegAPkphLj3xVI+DcnlYR +FeGcZd2Qo3/T/fttiLIQMLMkyjl/x5aBdWtHnHL8ioNUjjyqQdNZeD7fRBuUndXA +vP+ZL0HpBJKBaGEL11A06Ke03BU5J+hWSc4tHJwwuuiqcpf/I/8CUZuV+FQJzPUn +NrNPXjGAGHBcgX1LO2GGznMRNacWqmt66ikfxQpGLWodXWgUi+/zHzt+1fct6Fwy +6Qdmex4CNIyXbiz2nzuVnm1LBTSTz6hyMfuXc9OyTG9sI4cXwaj0S7g+9srk/pYC +tDYgt2CQBlFh4f02XpbPAiboTD5xH0pp3ZU0QkUhfjYvLd1FiD5K/Kl4ouKHOtHr +QdFeqKuGzG9AD4lzR/MhSJyBUs+Gk9sE7ZIUgDXlioLh8zXgwxVfQGc26TzrESS/ +g3GKSh1HE0Swbri0vGi9THVkwCdmhvMrNJI4ymQGJ4mgF6od6fAM5J3AZsYsoml8 +rCa73dD4UrFQk6/r2SzW/0kpPd7VCDHYKPhsvj8H9GMOSyH3NxsWtXEIKEW+WmPT +tGk8cniZerhT96aolQYq2xx4kYyJRa8jMHmTDUH0Ar+EQ/MO3BLAW1vbxQ+DStco +CJPdFSS9J0sWfK9BoimaaXT8yYlI3rSzcI5RdvmiJw4J/v4EHAOlkCyRj0NVPC/6 +brg3rUxQF2qtKT7YzS+Kh3O8LWnVlwgMNJbUoF4+Q2xK6hH5bjt+M4xpoEjKoAOS +EmfUsZvCkIt80O73PoIvXOAZay4pp4ry1Ssgdc79+XhIWD9G1jlpDzQ+w4ExZvhK +8NWdZ1R5JeoRoh0pQEPte2BXbZ62oEiK+5et7zvbHgCwWvVHzp2sK0zSFvFIZ8Ti +Og9yOXDXBGDOVW1BDBdgiiyMsxJq/rOAi099VQoZsdCDgmCT51mjvjsQ9HTQV+Y9 +h/oAHVXaU72ogYVQA1kEhzoXAGWz5P11UPh/6HaNircqniVnxK133P5BE4CwE91E +aB29X8Ds8DvxwDB66BGnkiV8k9OkG/qhb+FbFd3gR7f1gUI5LDCaBg54p+5yMv20 +6K7bPREX7+mNd/mz8/JPLtWGsNaTk5mMcyXzztWkX1Jx0SD7vZhj59nXoWLqxzjE +sKC7t9D9vJbccjM+ZZOu0pX5QvGKDd9ve82mV+OR/EaSy8W7nb+yXL1/CFGUbl/+ +7mwehw+R0PULXjFYtFB+HlhwtyNMibnGSA3iaXq25io= +`pragma protect end_protected + +//pragma protect end + + +`resetall +`timescale 1ns/1ps +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +PmlpB/6YO0aYZmLonOSfv1AKI1gSH8MDYymmabRlHFrShbqvDGa8mxE4q7jVthDq +MeTpb7dntYmVLpQ3jrou9qzgE3VzCDgyllo3TuIcQpf8xbi/clZ9EKTPRNrkLHXj +Jn2QVUXy1p5jRGkj8FP9VCUZbrPJDbUrwkO2Q2VtHlAdHQAM6Z7U9pJ6k+4Lt6z1 +rqGgvu8nZroCzTOKDA9a17sB/IvYRCebzdw86ug8kfwFO6z9joWnFo8nHyg56sAc +aAcfkjyAi9uRiIQ3EUPJmFFtDYsOMqGzh3SmruIKWWPaL4HbH8ef7gp6ZFGqR+Wb +scvgrPSCW0tEJhX8tcsUCA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 9184 ) +`pragma protect data_block +FGHQV6qyvL9P2mdzMtBf6ysGowZyPSEb8mK2B/uwInbUMlQwqOl1LKarMIzLcVVN +pNXodSwWPs+yWcpFZo1A0q7pR8/KYA9ErUAfBLveXS3xtwJk/69qmW1J86sXrDb9 +EN4a2OGoQhCvs9FITpUsknvW1uSvMAXAgD4mSNXIsLV+HK2T1fKojXZadDHED4s5 +jPKZCPyAzVgfSIYTAPwui22k+hYubEUCNX1nXIqb8gF/2XTI/SW+4xvaRfFTiqw9 +BRJFIE4801ZSr7w05i0MOWzf3ITw7xa0itEPexfmE5ONII12ATMOBzi/9rfKgd42 +CitshmLHG85XD4ioUN1PAlpKWiq+KkqusFB5ApyLjwE1/4t2uQyS/RaCHhf6/p9B +9+v/nueQSjZFT7/LvfUoBEo2zFeiH6g922aX3BGWyXcloUzjn/yMQUBCQ5o9uJLe +18Ghi2Xhxqve/9uMUk247v2rmlwhla/LtkCH3DjnEawWLoK7Yw5V8VB81bug7S7M +uohJ09epc6KDVq5uputtQjBFmHQZ6x43bqNV8/hoAulTXbBwmMIdmsvqpPKZcncO +BwBJ6nxG2FxUoTUazAGsAMybFDRBQ0j5N0OUC4bR6FqeFJUYpGBm+MyNeiJe00UO +8a+yN1RwfwjiNvKy7PmiXw5b7SJxbU+2jA7uhGYy4sGqn+6ikxh/nVbzub50l3+9 +h6ma1i4wCxHu9WHqq46tNj48u8mrMxS2F+Q4VRAby7qGF1u2W+8D68Pe7RJyTtVj +IyKXly5CziAtte/wXJKLh8FQ2N9ZGzO/7/LQMwghsFeNYhg594eF/5EhPtco0SrB +O0o9JJrlsff6becYm7XFmqDAYrEbxjEBjDrthom31OGTz1vSA/kXMNlK5kMjrOyA +nfnOBCNrCB3+ZL4WftGEt9+XM0kMj4y1Y0s/RW+W0zBgUrspNWO5jjX41XDaXPun +4L+Ahmwo0POtjtt8skB8gbkJFk8wY7VwowKfOrHuuH5GQAA50Tiv07qoiLF5rjia +o4L55vE4AZdKaQu2fSaJYFVjzrd1JJyw9EgeatCyPJSJXbBUJB2nyq+2PzjmWzcH +2L9jC3tZdby1D1mPxmeHt1/9NlMiKiYx9TgSA/L8NsCans476eYXfHFk580Ziuj8 ++7QXXtQATbCyShZONTC1EVYO3ZoAg8aLr5Dxy7WAkjFms3t5uwb6eWc/hE32jGDG +yOnMTP7/iI+PT5p9ye2OK9mbB8qbwj3jWSHIqlwnxA+INAQEkqRzID+hxSrmlmE7 +QrXaq7R+23tjt+PPaD6Df4l2dLdac2Q7erlNhQB5nfKVy/AYv2E+UvGeUfUAwXEZ +P0XgkAYXQ1VDQYuX6tKM2a3oTikRkwSG6KXJ+QjOFsntVcLheqqF6c/Vlhs7Wr5p +0wOGmHXc4QFK0RZR9A2rZDi2DqMAgIaMUVc/rT+od8rQuxbfLApsWxwdgYblQbuK +fGUM6PtsNnFVaVcAwKk69lOXa2k19j96JPVv49Nzxvz9FQyeDepegxy2GpRv/lmG +qHNnzgZB+NUb8MwObhkCr3CIf6980czBxhNPi5yAlhsvZPmoBm5wj8jWjiT8m0f9 +KVU3SORhubl4A24EzPwkJe7FepJZc8bfD0qs6n5kMSJnGDWvJd1ge2+hvnoStOlc +hwj1U4ZkjCH4MJk61c+UpJx+/Z3pVPPZDQ4TvEdbiTrmUCJUQcRwgIQsdWowKEgX +rDZik46C++xB03FEcKKwIDqxLHJK6Geovzq7QYTlKk8JMjb13MgK5aw6uJ++ipDB +5Cxzgm/Z+x9L3WHRUP7wvH86ek3CqDc65sXgy6wn1uqWJt/8msa+0af6Y7Pf3fvn +lI8UD2ppQCsYviH0cpVD8TBVzjIZwhOzBY2r7g3y51gT97XjgNcNkzW2ao2IqNGn +a0neMxRjP3TShgNzGCMuYF+383wGaeZPxqttmfTcwTO3ydF57ep4wVGXe1HLmxBl +RBklFk+iqdG/gK82PlLL02JCF+jO4yJ0Y7akEC4oofDnljC+ikO4wc8hiLPqedvd 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+m2Pok8sWnEbUfDM9NIIhdfa6sY1+SjnaYHhkVRfTv6iJHKlj6uhymFpsB/P7K+CM ++91tWd/Lzr+xyxlVnWfAE+HV6DNkb0UTxe/Rs6zU5YHyaQQJMZu/ro/3yplkDsRy +eNCLBLSq1/eFLQrhaQucfZ7poWhs+MWPDy/JxUoVm7WEToY6kTvyAR9PcmHG0TSB +hopnFs1xaXvszjf13aHnTqynHR34uEP/zg08oU9Y5bOSWPZff7RNaZVSiGGjZpzy +uwNYxJ2TPZBXJdJyrLPg3PNrisSgbdOTwsexYGzxRwl+xfho9VwsubNNrcSC40M3 +KPDR07bwuPeF0BN4SBc/VFlvVbLyUIk7yswPIyV21xX7k6KPXSsQADAj0AmD++xZ +CHkrtBCSQqsY1X1NB2c0GGbsthCNd4VJs6Xwv7llLw2rTEZ0JAeNnLRRfDoBWc6t +Yk1+afgRXlRY0y68j6kyPKnc7mIR//wYpHR0aD8IRLlXMZn+iQgDZpXx2uv6bUGf +atdlwLT5HqtdqT/G+Tt6+WxbbxfKckTtcqw/CRam+A2qFORh2ldV3MIK8hs9jFv5 +z+Kn6NjUOjmaaojA3RfFYOTzsKPK2Xa6uTUrM+iimSnopzg9ZhhUHcf5xbWdivou +ylwioEUBQ5No8QnTY1k+t9Kvm6aA5iZbpn7jjhLLz4P1ZodaLZzvnehS86XFCirP +cfPd5i/2gw8mv1NoQJLDS+wyZSVBqyvyHG2RMKLvUF7jdRDN1kA6O3UGz+Cxek/7 +PCONO5vBroIQ48YmlePbS/mWxId0Fk485w4TzkD8kv7b6oYEUsMWsS75HWYF2+Q4 +79RFjsCz+53ZR5QEMLE1AAeoCLn810C/hxS7s7E+dDV+M8gmar2Oi1WS65FmWYqf +rtVAtVxpEH3muphkjuUauwPN22VB92Qu1JYl8hoStt6b0I82LpRP4JurLlk5WnE2 +a8Uz+Gif0lfod3awons4qVIydRqPWhs4jKwgKt4fpneRFd/Qsf4PCdXCUgOTp/dg +AeTHgspdmHEyilg3oo+NYd+dBbxqRjph7VqzxKJAa0qA5fqgKWZon3UXdhrAxwVe +YQYsU6P0Dpi++qFWHrD7hMMp8pxq8bTm5cnowhjFKZyMCu5N3/cAjd/DUYyiNuh9 +zYDywjCHDRbCS5nfyPCVySVt4BpT0yfcdq4eNT+rIfwMSxcWp6HANTtEvYU50EP9 +eBq8yaBrFHiFvrcG0us6XD0jf0JNC7FgfEmQSQULag+eMLkw5a8ID3zj3DF28j8e +1y3LHZ0odZRUJBmkOiM/4CzweW913iZ5BI4mHqirrOdQghXvhdPcRgAN8YVPb/JN +KrLu3NSv+OYZ9MfJfTnjyRnt4J9tzQnSJd26m4ibeOJxrXi0fITXtO0h0G6xMRr6 +BagAt86k0XxGcgKR5wbzjkqjqSVELaBJ7YjDub8tuYWVQuvC0KyfE34pVVHGgtds +2ydWDkBvtPDVsbq7UYiRglDXzo7NV1Hbd+2XucJLjb7gEUHqoNFTgJYAg7QhtaYx +FpLlKbe9a1NiEcb2L8sVNX710Rujp1d1tYODQcMo/ffOnSMir0UkusCbcfVDm0AK +PPhKrtrJ42vG86YnV/CfeNobuSJbv4ERE5EyL452EG/5GVz/j11IELBAIT/h0Kci +qB0tlwR4Ub0EezVlXznI8Kq9u6KgsjfV0bfV8fbzUnZDp2F8FQ3CqUx684gznDeY +M/zHw9vWJTEz+qxDYhXAW5CAnEsNHaoO0sp0pvUXROjORaa2V3LzR0zTDS6Pt1vR +OLRC3XycBX0xG5OeIK5q7exLAaG2g6OUko6fwnxV/PnRaH3o+gs+UvW+1E68YfVA +zgpSBOdANw+bEY8UHclUSdn7D27heLi2uAGfmJsR23LkxBR1vylMfd6QWkV+7pFg +wsThh+eO9vgDcf3/01iN52iGWRA9HtquG8Dkbl0LaW+KZslEHAv9hjKCkK/Rhpz6 +RNgrQgjJC0ErECLjkgoIfeFjroBOSmhlYKogIAFpUruS0kTRnjUxZ7PXlHrr8cfg +7loKXmU3NorEezi1B+SgabLkJKPV0L2/Px0LsvsE+MAjqM1fBqCb+GWI9zlEGKMv +hB+EfCw7C0bqVHiK0esOCbhBRd+azsd2gMQy/VkrvLkhyWtvfw//IOO3ngHbz8HK +mck2JQRiKcWB5gWkib1JK1Vp9MWllvVVWiv1q3ucs2G8p03F4VFfv7yd+ERtCauV +2EyrRHQsVLGSBuBRJeECDAJAKoMEF4gekzax9jAyOx2sGqfmwEDb1jL5G/+u1jtU +9Qk4dHKgULI8m05kPzk/PkWwDBQMV9S3FfWjKkrm8xR9ft52kBzAlzs0NzP1O5sz +6ZG1wZdJd9qR5QE4Lm3gaxPvccjdjlGoZH24mwloYWAG2mgXb4hutcoRBINLlkOo +c3Isz3kUwDcdTNryYiDmxkLECtp8g8bNrabmdI1goigD2qwcCqktvWZl8SxtFcnV +WspkIpJhdVSfmzKexGLmdg== +`pragma protect end_protected + +//pragma protect end + + +`resetall +`timescale 1ns/1ps +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +nUxQKBNOPAXm4SMK2ufDYCaxH6chMgD/G9EkTxUt+C4Nt0uAomJL0bJYD4mF8lOC +r95tiqs1UL9IxPtBQ7/tBv0W/JFRZJ/wPbPiqsu4V9ZtWkRNwuwhOdkOe7peQbYK +zj/GKqe/6NnDKvo2Xqr8SF+tE+6MaDB0XilqCHc+dyO0o3AqDAhL7mynjFjvo2j7 +F0v0ToZFohVnUNWznEKxKGU+H0NlmNfYSoUlYleeUiwQo0B/drPTh3EFxzaaGSSm +pPi3nW/4vKGCaEpyX/VJFfaWzNLoaHeq0OqPZ7aGQpV50GLpDMglFlYSca6t4OZR +MdwaEqtceeAjFhWd1AnrWg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 7296 ) +`pragma protect data_block +Q6fip9AYrrc6csSM4j0nGbidOqnpUvFllvtr90ruMh3QiH6wgCa3Y1I6FB++ylFh +hIfnz0EzOo0+SG0Wc+s9BtsY+Q1dCChpha1qQ+FWmJwH0ylGnHU/vZF2G+coVnb/ +mnQLB03/zpjBEay172RecdOeH2x7ztWgIzA+bfJDtvnJ8tOYBmwP57I4zENEkq9V +YU834CcpTWctHvMPn9p5bdRWIMD5YGFGw6gENULNdAr1ISPBcDLCwwwDCrccHqo7 +B+7rlFPC/C2v6y6GiZDH8YBP2HfT5BcPJRdo+9HhGDIvUFgdbwiJLAsrctiEFHxo +y/kL3BEz4/CSFMIMIlcpwnBM/JRxCRuNBS3pHTJ0NzxOfP9KyLOduKFzGq5/5XYE +KbWo5Ww+/881aF6xY1qA0bUhMLx4aoU+4JA1Ny8jl/UU63kCqTDtDSg8LvR0bbFa +CHIiDjDyCvsQiIRSD/yOTuAn1/m5ZCYHLTRQo6ZtFb6ov+jrgbPThCEKNmVWJqoJ +3OPNjVnHf4JCP6EOCW4dvJ8jDecKctTqcEQuNgqHQcwggqlUfzM7JKRxyQQMHtCT +ELDN5DUETXncy1HO9hTCODvRAVJ6/gwOZ1/FEzPAnR0Atvq6YyOmPDe8fWO0wRRo +fJ2mCimbWcnDnYRYtUtlBex5f7joH9hc9beZiOJmwnf5Nfds0OvNSs2xlT2hxJEn +OcS371snjjJ+60l+b+qt45RbdwLVWzhEUm7FtaYRqX9b8L0wRYa9EKI6TedvhM6E +A2IhdD90G9eV6mcOQnvoLS4wJFJgHru5Xa/K56U8b7Vef5Sv3Jt4x2Zby1x6Mycq +s3C5qj0yNolPaJaM13SgMyZKf/OXD49EXPRhwQQJeV7/3V44GEjIbCJ49Q0Wskuf +n9jyn00Q9FGxrJReoBKodFy0A85lmBnNqX5Ni70pRh+lUOTnALFX+0veYpFf4CpI +W3vM+z0+WT4lr0zChxnFXDFhWAlkJjtOn8fcMMtMoyg5Jb/8C9oM8FSS6b4+Tqjv +saf8ujF7F+BDbOzswjqZP6cvj/WuIUPiW9MdWmg0FcEIuNFzMQfYciXi4pCc65cF +vgzZcLmiwLxZjQn51VvMjqPgK/gtmLqdLamWVBjIl5DTm0LxwjPsbkssQ/M5yvYV +nUo+Q7QbcnWQkV9R4D4mlLuU28An4OcdJeFRgpq7D3/97Z2IjqsrU3vDV+LDsdn/ +FR2cbyLD2ipf0jsGZbhhNxmfkTvYyYoGdklMGCfNVJDzlW3+AyYJAmE9jcfi5G63 +AgHw4X8gOvXCyoYDameE56H2kfwxlOvENcET3WJXMI7XnrnbG5TZ51ukUxKOOCwg +ui+NMT496RJdKcaVZa+N5hXzVPNY11joE0bjXYJXo7PZF5dqfsKXms/Y56SHhpbi +GuNgVUzlNcCPuil4WTkcZfWIEHFB7mQtQ9ydazrIzSQUCmGJ+xeQmdUE9+XdTsN0 +21a9b2Ayq4tV4oxqExHScUON6RVY8qD9bKNdGR+cK6NLTsN//sikvcAJfNFnukzq +MzKq1C8QnNJ+0k7KHejyqYqsr6CKdpdoE3sWlJ4JxPABHKGZXV2qJDbsM+/bakhT +vlyKWGEJ0Afl3hQDdvOYX1vhzT1CtIkQHAWJ5r7KX94grHVWdJ9H5jnrdC+hyEcx +Qqg6XMT/oYXYPf1DfuZQPjm1XXCJXYIveMxivbNmY2Yt3ZWrSWBwVsaIz2fzQKVS +tMoT65j2DbBjuAzlxB1+XrowwxBIZzRqv6Gfc2KzGBZ9jHstPkfSIwevgy+etgPS +3HQwTXpmvLI09d1tMVEMLr6CaJ27LGp83T0cgC2pHHj5MOAdM8Z/t1hxQ1S/xT7X +MIsf+InTh4cEBYXf/fUZag1Tt8BVsirYvbnC/kqtN9sHvT115rFFScIaIzgOr84k ++qK+i2BueTRhV4iCxx12D8eqLNSKPAUMAYHNmFsECekHujATkh/AIL7e7srYTBH3 +mUHPUrSUb3mqpighjRgH3WDKQ3x92alyN5GxP0vAdNsApilCgjB+8sT5AzY55NsQ +WEriVOpUZ9/29nmdDX9S3E/AYb6g3J5cnGlsBkIm02pOFgY2mWjbLJOO3Lt9dDnI +N5qxM+qSbcoVzFIYnznPwyTC0vlrEMiHSgMNHFWYmUyEjtWPr6CHA4k0s5PH6pUW +lIFt0JpCYIupXMLmYOb9RitMKwqox1ltblTjVapDi3DthT58hetpJhdXFdVLSX82 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+Ap7oWVHmy2RSlDtGolQQpvBSvHOmolAP/5IuaPaXN5eyKRkfBk/YeYNtTaiBbNh9 +Ps8hFQjFw/TvZumIZVHY7NT3U5tHvI2ggrjlMkgHrDWGbPtZWVwWdmQwu1EFQUqq +MlI/TXlQZqXa5NC90NDGgBV1Fi9LWQb8KBRQGQI78U+NmnyiMThG6Iy9ROYAe+gW +Q5hTOtvg/PNxLniPcx6ak5ASFxKxwAggikXJnUexFVurxAGKZdiBxIUvdShZwmx/ +iutX1fZy232qr8OGxrv7ekQT3d//R3S94ezYaA9aKGWerGftBpORepKbrEtow10O +Sac1eo2+m4wBx19voN6mxnknfaVqYkkQydwXmWOeN+msSbbCsHOCpxVfWrznj9+A +VEF2g1vF8iYJRtWU9lzUBxSEk51Bra8DbMmvySFSvT0Sc1kz8wAYtGcQmkXkYLjh +AAeDMJkC5DGT9cO87uNe+yZjbtaoMlwTDlMzC6Pg6zjKlG672zB/kV6ay60jqT9Q +Usxy+cqV7FYQct90gsJlVgjx6tpYc2BHoJVz8srifZQygKdLcaMfSalT5NgqKEz8 +Yo5OTpILb1IfcWeM3GH8QI4SAVCRtVyoj8UxBZOMXXXyBp4Av7C9mRqW4YxX0GG7 +4XH60qtENX+q9eqIYQpQ0xqBlyNGJHtML+n07pwhb6G+RD4ZuWSrhfnIBxcc2jm1 +UwdRohaGn5ptVXFoUwzz5Pu41QWk6N2ZUfCosSz2vOojOQo2csahEBd+xhJL7uwV +`pragma protect end_protected + +//pragma protect end + + +`resetall +`timescale 1ns/1ps +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +MItf4LQolnfNNZYJvjTV4ETejF9FWX+Iw4l1AlQF8c/u5UZCDVmqg2Z2l3n+esxQ +tbWXCpsG/kio6VnHwWXHXsEhunA/mY2EAnxUsfL3KKUd4+4eAhtjJdq6aYmG1IAn +eLYlsFV5MOuibkR5Bk4JLcZMSNn6d1XdMUxIAvwj0O5grxxtVAj13Bcun1IXhnp2 +s8I7f+zNaUtQMTYUZNSicjSk7p8QVxCfaTAmwZK5E7qQMcaFvHjPEtG5nv9ne7PD +mQnlHeodgRtKy1OFs3ajfiit9bQRYdPfmBBJurC1Gn53Z+6x9PiMb6wTheXN42U1 +6PnKOGnFskNUTm9yXBibqA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 8176 ) +`pragma protect data_block +AkpifhCv11FqdyW3SLOja2cvQGwIgr+vEkQ5XQrx9WBU4WbQPBi5r02VYk/j86Cl +Zkx7XpMYvsHTVC5SL/PRA98jiWoEr4FUfL3DbCS3KygzmxwjF2e64U2t1E2zCwhw +7ytcZfB1ap+8OW18VvA1Tc291fOGATSh1Yp1QZ0NosjhYdplXxqFEniRM96FTvgw +B3IbQCWH/VG9lTlKGDlcYw84ZuplhWzz+238XKfs0qkaxng4sfwrfTJtMAnzAiY/ +/hEyuT8MDXHDrkCQhhqloZ102sGTeQkwy2mD/gihtzC9O72YsoyplYAFo6F0fib6 +UWUPm348phjE1gkyqR5XLDF1wYQMxm/O5suT3ESAJW7/Fj2sPyjMTxTFbyI8g0Ml +AuLsZyVg8JuhriK5yNXQLmUBSHloM76A2p2lc20WT7CtuZSH1u7L5F8GxHAd2Zqs +/SQQ1hYKHwIahZ8Tm+Qu4WxNKDUJ3w604WFft7qbcS9jZJzqPWFXPdC3n6c/5BB4 +1839ZDZSsa5W7FcFram5/SoQeQ09cXuBl++N7i626NgBOFJ+bQKd/PMlYIG3QaqZ +292V4BnTUVmBcQcfg/Gz2Sm75fgLLHioLwY/XkeQ/o3K4r4psWeLYIrdSbKSC9Os +A3lWV1dibtocr58kUrVJCdTiKq5rMheVpcBDL8gNsOS5GO/HmA/i0YlG8gWa6QBq +NiDe7hW+a+b6EhrCjvYwkgCaHJObadzlmj4MYF+qxqNS5yXyEX+C8aNBxGgYdpnp +Uehl0Z2Oq5TcjY2woT8dV7GY4PNiiZ5c2yI11DpqG5aOnoAWPKvILntlPdrOZytE +tjohqRRc7Q7SXnsluCWFq8tEL7aiLO1LmwGVNDICm/kpq8PzDVmKxBFNoSbaFkvl +ISBglcWPl3IUkIgG5LuGVsrzbISi72kZyobOpXzfCI3UT66OC4OXGC0S+utjtDlT +9D6dbZIsw5XYRP47RlLV9aJxVXzsr7KaeEiaelHqrUQ0mfakVTy0I6atSSKnkhDE +G8yNnXFLfCaFjTpDjoGjfMO5qdxZhhuItrGRPz2VS7z9XWJC86iTNPfh0Q40e1iy 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+7BfgRWW2nskofgHrs2IjAnI1woh2JsrTHrNeSLkT2n5PpxxH8CRjngtESwuYzm/E +r0tSU6Qv105J2YO3F1FSpFMCZFecoU4pe54oGw5HC4AEOk6gvKy4QNBrtmiIx/Or +jJFDqXZ4CA/CZc9iekajccH0WmoenaOja+19Sb3y6JP63N/ior+F6yb/YHtjF2Mh +cVkcaeFwE3ro8hotEbpZeDlFSjk942EQ8TZyO27VLaHTjs93+mcWmvzzoP5Tuvkn ++E66nQ3z5RvdAPexC9tJ46SXXHNn0h4p8Ff2rpGe3PYJk5uToH280bqoaD7YMset +iOhcJ+mUZQ5G3NMaDqDndUIQUREYfLP0BdC1jp+9OgNuPyExnaWiIj8xH7744+yA +GrSFEBkHueSXFUfBsQFa4FrR68nKXqPN/D8jOwDHPjQq8G9ZMyREqbuPF80HFcsn +65/3JZoJbTUWa4BahXkC2VIS3sbwXRkWapsn0wssAabb0DoRzpAZcuxO7q3m0NSG +ay8mqcynY+uS6TuSsEqIfQAtMgPUaayWe2vCZpyW0y7RaNGWSthsT+CzOx6Src5H ++PaoVftVEpM8UHfkHegJ+luUdT9jYph/BNld9XPSSmSNF6FFD6O5velOfySxQrRe +XV5HGUNqWwdi3HeS7AQU+Wtz2Dpoj50EiZbTk4VdsKxaB4wTeQUhhM2SWKEg97R5 +cFLBQ/uKT+Gn21yss6HoBD4BhakqbFBxFlwCC2cEsvzYeO1Eq1lHugI9RzTU6iF3 +2JIZvvebu3N/AfzDyk3ob1TO+CYgNknzgonXN1FAf+vXspLscFVnUY6AlTUi2zf3 +Ok2e6DLX/JEa3eb+YV/YzSCVCsOKjQh7q0wVtn3HFeZHCS52Fctn2CgHF6RZi0wr ++FgadPPX3Vg5MUPmQt9u/5d76jpcj5HYCyEBv8DTFMRV76v2M1ucLrEXMRaSHtjX +26FCC6I8GSYNnxrfwCQpXVcXfO0gG7y7Jk9eT8I4kNzyPAifyyvWJTAP1VfkVXGw +5dPtXyPKVuGKfa+Ie4kSgso4wyFuqY4DcSK/9eETXhdCJ0JcJiAa3SC6mNSQJbSW +EdMjVjOjxDOmI2tMzNVrCarF700Sd7EelcK6Q9Fq0g3/6lYWeq+XLav5Yj2aAuEB +Yftoo8DW41HDqmpgZj/tUg== +`pragma protect end_protected + +//pragma protect end + + +`resetall +`timescale 1ns/1ps +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +IbSG7Grboq2nZ104ab+a/+lBKvy3RnVPf91eIPRpwQOtsDLKLPZ1ylPWfu5llh+u +0HiEpTDTBNXfL5Z/Bw0JVPbF658H8g4lvM2q35TW/+HM4h3PPwAG+H8j7XJ46HjA +QUI5/vpzx1W069wbVAKK9JZGH/SBrS0FKlV7pupYYQoUWwKULicdTyUn2enKQF1T +B/+KU8whV5QuENrwXYZ4JGl/WkO/WhC8xWW3G6NwnoxUenpB3Gzg/KsaekaN2GhI +FD3esESRqJsvtSUJRBOwm+QdjdhIm+pkvJq5eptgpqANXyyO6YVIJ54bKK4cCmbY +UuWQyYsM4xa1ficMoB6TIA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 7280 ) +`pragma protect data_block +naLN5qhzy4XXLyb6zLajhcevS11hu/SfzYR7GfnloyPaUYlRclKMhyZ9F1AZraFl +BuymX3VA5Tv7D02ejw4vpgo+LCyJxGhxIE/esj+Hl5mTk/5s+dHeGIYwCi7DH9N0 +e0H9wNHRryN0kKnj4LVtJPuI65dRfU6N2p6aIIoBGj+fJva041sfAcE0StR0ijbV +pmzOxPNeIuaylF5Hwbs28IHMNnmJUj/2EjzStsIxaozgzwvHkGv0ldUgqSBfVla8 +9fEOsq9yjC179N5onPmsDD62CmaSgUoGzKl14irUndtToyHC+6+NjkSP7jABqQgU ++dE6c5sKAJM5EpxOHZZOQXEhAciZ+8zqwIPzsotXAb0AxDcW1dc7S9QJLEpPi4jA +Mbg0f0w18K7IVTpG5/Yt7iIMxaKaPuw8ez65cf6CdhVP2IdSzFvS9/MOieSiM16x +yRFmQQkzUfdPoWwH+uRPjZgqy8N+Hr11bbla1nUTL2E3C0w2tIi9U6R8iAbE2A3F +94CckZZor6nzBvidleuD+F2Vai2V/4Uh3YX145Pp4+r1KhnnT4ZMFbXb+n8I8fRn +dg9rpH0wotOJ9eREBeDWZe/lGQ838d/njGilvK1azurlR3e3jZowtlU/q/2d8m7G +aCRUD/EVda8+w6LkvG5dkr5XT5i3n/3J4FKu3PjR4TuNkdYFGacaUdUvfoPxZK3+ +HY85O2imphxYTpRA4CF6ZhyR6NbFqav/8W22kIlxRGF1anClIgfMBw4wz4TUz3WN +1awPPgmYRVu8+CgRUxnBAYQnwmYnGn4bc+oIDukt+0fuO+dPLb5NvEILB3l8xi6k +7er4AQRx9JNGIUG/rnCdiy2anaJHuVnqCT5RMp7yLnQ9wL4X1N8nwGH9Lmr5y5W3 +4xmgBieqOCr5QqpVpB32IELxPms5LdQnzfMYy9xOshbCzGUOXJnOtdcV2St8JvTM +oXQgClYReYYDS32cbn6umLVlsK1jMqJtObLsXbKaqejsXJjopFirb2sMrd8my9hf +cfiTKUxWCO/fDJ5I1hMt+aWtnEe4Vyg5AqHc22nNClXGi4TcqzBkpVDoGpsYpFw/ +uRowYonwzb/bk2hfprJeujLzq2RY58AW2Wf8oBJhccybdV5kM7XMY9ci5ssldMSx +VT1UIoUlZ7pqDPFxyX8QubuPMSOZFeKPW19U5jJBP9AGpdCK8pCo71jpc0EJ4/uv +S2RlRm9jtarabKm1/jOx7ArDfJkCot/0Uc4JUx7qmhdpDtuCUANuiyn5sdM448aT +dBdotDopJjVVY+0q+0bBsvlFuAwDBSZJLjFILGfrjvVA0uU2v+7ffVvmPCbgt963 +Q7jwxcMQSb5+68YTyRyg9bfvfWeirDNJawCCuWlO6ZCDT2cW/vWKtg1W0wHXcnC/ +c8WY60Kfu8ryx1x8KmbD38LEsbMBIZW8mdVkgQWQ1ffK+O9mHOawHim3ut5UdoE3 +4laCqnJrfpfXlF4dBmPc5yI2t17cxbQoTpRMH28FbmCLE1Kcfo52qV2BZfRvliyF +2Rr7gyNU6lrkcJh4Mj6//LsD0AjnGCbZcY+xMFjXxDjJrNGqY5fPZmkejFYYe1vP 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+4BuOtpQvmasMkKJnxlu2BaqtwY+DyWQXwBzMyEnRXOH6FDy8QeJxJUpqeM9prSNA +BuAI4hskQ3FVPOdKSkQsR8oXj5wd95zGJg9uNZ7UlMvOk3ETTZxDe4Wrklvyioce +jRsQ2X7FkXuIE811AxrJO8g17XY9ut2J3XcmgGx6MfKOo2M1TbKMtw+rsYLAmyw8 +L9dchPSFZWMXaNQ5HCaF/Cib7FQNRlN5LYJBPpB5aacaOTXRnPCxpXbgloNnRvx5 +GhRGJnidgGz6j/9NEXUtVwxbs1z70Ws8yZRklauH18BkfSpH0zxzsk0e6AF8AHUq +AwjZP0IN7INFYHxB3+wjnmsYiIzsnxLwJk5EFbn0x63fJlJR3QsmOr7MwlvVw62+ +PakhGAa6UEOJB6Vn/DrKUpjbcy8gENGF6Lphk/KdM7vPMq9M3aiwyxCZkPiiRVVD +dhQG2BL+O+cf+YwNbYAOucjg5mrv85xosabr1YGizfR+1Dom3145p08UMfNMISms +QYgW451lGwAmCp/ptuh9mNQfLnzdW4VaylD2Lw78uPDHJ940z8X7+cB7T1yZIWEv +T4asMzupr2E0onu3V45UAFgRn8Y0imrRtYWivEVJuP2l2E/iUDIda316gQZtvFUc +hWJDd0fUBGuP6i4P/zj2H1kAicfEHggPUXoIqWayvAR1ce2MqbXiXSw+VNPHVDEk +ICf38xQLoX1HtpP3MSi8O6NGbsid6SHMxvFhRA/9Mrc7UvrChV8YqXqpOh1OYwQS +9SiHPSHW8HIPycU7Li+PcbO+HBUT66sD6ltCqhABPGvbx6/oBa2CN3YJrqMGxqkA +cUP6bvLK6fAZaSJbE9fxDTjfWbwjg2igQfRl+wkNmL6+WYCJt9KF9Q/isAZcTu/9 +kAMgNqLKVQDOxrZFJmR3cq1h0KCf6rJhewzMy/plJpuF4vp5vkD9f6q7lIdQ8Dzz +c/MvFZUj8cP1EBylfgR/97CHoM/NlVxevqqg1Yl+baQuewXjv44/eZUqpELEQwIl +j31BBrurg9cszfLYyMQT/y6Inrvc2bb7uirGCBF/5F/w32BYbIrkxqOmCJegiZg3 +6v1NlPRhI8xl7xS9ww2wPyAxZCo1egXaF9Wc2/hu4VtRekd6gfeXg9daeEwyXGVJ +/IanHZ1piGfaFSNrlyBDqz0KejB15cv68+/lYpoA8WjLbUTZLUlyWdZmgsMeVSLZ +PVMijZ83AFATFqTwWFJ3kXccC9TBwbpvxMOj/3wVvGiicXf9JUbZSpsiziSLlw8x +gkwU/yEeYYRXzKxRkgJRGFGpvNp+K6NSIdtNIkbtCh2WWfOZmGTHWtJPafdAJ63l +idCzh7Cs/Ia1F0Zfso1pCV9eXWzbv461WF/guS/PpAEKdZsGGPqBHbVn22vMOOlO +CekHm9Ynk6ZijLlCKqZl5DF9WVcmo3pOgqb6vmII08tqKWAgilF/7GCau0xYzUQO +90rXqbiYFm57pebSvY/taA00LPhVKG/TH7l3n+9OXmb1wfAsIdlA9RBDRiAA9MhG +pFmDBeSg68kQITM/wq9ljX4BxhkEuLLr1OUMTXdE69+5DgTON89WA8eZdh+Km2zm +lUy8AoJhm8bYcZytZaSRn3fjlGqx9zgRyjrh2lBgW/4q0/RaGz6AcH4g4/lF+Tm8 +ybMq1Nww2vaUl4fYC/QncZq5OiXem+GmXfFL6NTZWinBMvHC3umZCO7XJHDHUbb8 +Q4vBrga2xKnfv3fIQ/n4tKv1ns0rl4KUw3oS67HQhIHgTcOgBjecDiQ8y91svu/+ +dzvqvF6PMOD9c+YcONSA1moJ1PEtT4qGK8+oVfU/tU1U53b7m8vn9PDr/N/nC+kE +o75kx2YNABiIngmou+yFw0ZRDcijDwzpD75lYw+yy5dKi+rmXdiqGY5VgLgzZ3tF +KjRloh4BS4wIq0dNhblYSSuKj9S7kGeoQlstd1tbvLoS6S4CzrbdRwL0LlRicQau +6GywrhpkJpPMVypS7xEVPGvPK1bGfp+y1i9lJ77YmzWbAzrl0a84DCGgAjAF0ZtT +jObPhfdXNOEvo8YYwaCRscnU1xHaZWUuX/F96ej6bR0sGdM4sGyySYOH0gMJQAQ5 ++ft06ZZ/rRFAovTbZa8tV/LrZNspwjkjILRD2rw9jkKKP1BuDFLusATMDXAzeySk +05gSIfnpHz566yR7/yurZljJ1Owfm1FHHGZCLD6ecwoaKcvpSlXTiTnUvSDmel+i +iaJNNOIqcOAoP4PZ9DB1HgWqvc77FR2qlM35zH5IoSWg1VVN9f5ZS+wPwo8zRXru +H+ywdu++A8khD6Z6ukzkrKiDAbwjGxzwOqPayzImo/g= +`pragma protect end_protected + +//pragma protect end + + +`resetall +`timescale 1ns/1ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +Xm1S9sj1JuCixXxxRRYRKD14QoS3afZKjplPN6ZSLQnAvIon2j7qx5mq8XGsgaSS +IEzaBn837INyfSUXRKCDbOHB6vgrTaXMb6v0UzxxzPWS+b1IVkFQr8FAS35BRCmT +NbIAI/Yorvx0WO3MSnUTRRpDBG8iOn/eVIjECdf9yJE/4mpgec+WdTcvzPWMSgUN +AC41MmhJ+dYzesMt9m+NxO6FhP6/22rXjdUpKCdKZCyCQFtmRGfykI7AbREfU4zh +oGDWnkWlKck0HShR7nAecXqLfG7+Gq5YF7MGzZ2f7KqpVXIzMVxQ015P2LWLKD0Q +W1FNsNnFrHW1pzexa7KCDQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 688 ) +`pragma protect data_block +d9NgTXPSU17ADKmxgIGRfmNOqDVkC3xL8aQNJSfELvwqHjM12d0BwF921Y4NSrAB +2hny08w3bwVwZmMrG4mWIOg4TJhZFU8abxx16JZIuWDoFZArp2nzhXyunUk20E18 +DjbINy2UJjOconqd57OAgrFbkfE1sjygBNKBfNiWruHnc9ACTZgjNP4kMMKYnP4Q ++C7F9/Xpq93riPzugPgorK6JMDDO0j484pDigDe2pslBOviHjuiG1PusCsYQjS4k +8xyUzI+IMaFD1o2IH2CaHTBym+SFlLR4MF6uh+o2fsJ8sDM4MRnxJqfeQlsbmGsM +JEiYRkbaUze/Ftjp4hhnVIQwlkRQnqhKk2wI3RrFo3wNUKHuEZ9Jt+zFEI8VBUxU +xG5JozZ1GvO3bl3emvy0eqcjgNDycd+VzaGXIFIfkPyFI6t7a+VoPPWd5L5OY+E8 +CxORS71knWP3SH21cw/7DBok2mmAPRx6gM4RSmpLWGBILWNMdDEig5Cap21OX7kW +rNGUsqAyTBZZcRbvvubH7ON7IFuJqyGi7KCvM8q0j7GoWeJ66fcn0otjGNjPz3VJ +m2oVkFMjqkHqzDURgMpzkkAY7P9tpeLJEnt/ETbNwEp/epgl5QwjjNrig/HP37yK +t/hyIpWkFjWEjE2Es8U5/qbIaeYOGB3dHbMO+5cV6r8NfqB2hY3HivwDXVpI7pyl +vswOsuKJk9+V0f0jzzr2T2IFXBzer5qGpQhtGTugdfzMu+VsQMEDZWYh9+Ui0PSk +fQ25ZrSBkxXSck2Esed9zLN7WZvAEIeH84e9uGqHV73TJaW8pm6B9uc6S1kz8h2f +JVb0WcSJCfMoycYsEStOZgOpE1mZjhqG24gnM8NYZ1TlgrGwh9Z4kqhhlooetldC +cHL/fnhdSq7YRzoZsgU1lg== +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +YCP7u1cObVZvbCw+OVJy7l9oTBWleoq9pu7Q1OQPRSS0YTyAEOS46qp9gwzKKhwN +0zR5GV65ytGjNdr4ypFsh/u1ryyP+Xi25y1v0IaneY13gDBicykWGwlQqUcNiJM5 +hpa+wkVEQE+opumFfZGNlYO6XWC6VPewxzGFLG0jgTqLSxKckpAMOhtJRe9QDDID +1Ogm7c98iqLCmdne915Er6r79LaO2eiQ4skhTnXdhNl4fSnifNNJAOHRzuLqb3Or +nv8PDAzc22u35tJPGB2x/4lyeoh4L4sOlbn1xCyk/GoTqJaaB+cKDb6CkcwK6BMD +W/DKlLnHCsJtQqRpnPB8OA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 6880 ) +`pragma protect data_block +tIJMLPz+Es2zE44XNEZaphc3xNIDE0DWrwDXZwanlE4+DEu0gwUKVHaIHCHiYaP/ ++iL7I0zAyRuQCAYC7iplK/3+YeKHiT4Rf8qdVORZqU8NFdayBFfx5par1YcSopM3 +bwf7Sl+ysL7y7Z12IStzoXWEGzwTE8jL43T4Oy4/u8lej7XbKcPuNubOiSKyctvA +2bWWOqRFB3kwb9WZzgQnEXqu/cYVnTtMg40x/46cEFJ42tIQ3hpv4APDzvHQLVzn +cER4PuwnsgjGp49n4m/qHNx9BSP/cod1d8P658Uwq7z8WRnxYqRmFu62VLtKSOjc +j+4XUh6EbulwKRRG5BKG4e6ke9CK83GQjZvygRfGW7aSBNccDfvAtWBU8Fdfmclq +NNgvvyUfsi8DPNX2Vk9qSwGzq8yJxXZWHs6Me71b+bH66amBd11yUslxiophwCRk +oM5WRdtZDJs6D6ochsv62c5qqJftPE9CrhzHOOKc4qFDOeg29Vup3LAdf/v31Qxi +8GO9U84yOmDDbniVOPBuVTntcb2ftAFJDfJQx/XPcVY9vqs2e98imCJsi1fL4eBd +KVwMT2ut6Uwle5BGNMsAvvUPMud7ujCNRKpjDJ9GN/cQKzP9/wWJkTMQ+K4qkGRw +VJ7K074M/b6spLgoopn4Yi1jh9bhn7lOr+/zKB0wsI3RtPlabUV3VNdnqggZ2mwa +Za3UOitMGGujkSFoJyTWA5GqHGK5TpRgk01hTOgLdxYgwWFci96Spj8CHok+1ZZb +nKbPIIRLM98EPTl+1QgrWGwBmLoPjq1NqIteySNzRcCd9wcmQ+0lTFM1la/lMwed +sbEueU28y6ClLbFDfqyLnlHr7LASyc11OAeXl8H9QV59b6wkUL32R6YegLwXUPCU +u1Cmv34bNPMhtoWePJ1BmJS62YxMeuy/OYNeVugzJiz0fU7D4GbAN8063xaoAlzV +YqihWNDLMAITg0SA+2Uc8yZVapOQ3EQqlBgiO1qRKmyQhCM2FqJ8R/J2SjNppicZ +fImEqq2DMC/TthwdWwtFhtR/zVFXIbibvusZP3U+UlXkBgAu0tOYl9N7IDylXJUL +4jsJrL9i8mTBrOOnaCM3ruEagjLBcyCAIhKgrJRJLxYLUVVI59kfZdOAHu9hANzz +XadvsYv2SgrJEWvb7pM6cYSoy61wvaI/dCa+m2MFaCef/Xuj+cD2GFsXKJCJV30j +ZMjm+EBMpgrzPkk0wzwV8eIT35yipmZPuMpVqMQJb4VLapzIhqXotEL7VbLwVbov +IdWy7gV8zblmMkzmb1cer7UgFu3c5Uelk/l+ynKmqFsdYeoBsNpJj/tXTJzyHn3e +PFMxvO4wX5UalH1uK++ygjja04oZt378+eEeRbikMwWm+EWvQQqCXGD1il0cj7X+ +d1sf0WR7sMIyMzL8ZMY/EfqNAUYDHgHTGohRaMg248Cz2gcb8KLSitxnga/VWu+2 +AtAEjB6C0sWfzPLaM2HwW4CAo3RAIOftC8ltT9pqjWsmrfvZhNEuTvbS92bgDyz4 +wCKX8HQdWemibAot+dQYI2WimGhq6WEYrfvQKPCZnYyLGWFTJUETgiN5+1K1H0JP ++gO9yWE7MnRDfXEm4pxTvLvVtu/AUSIgdOPkekHEElbMmBRpOQukIkduyraCUz+Q +wyRb0j1lkFckUK8egEdcJ5Ot6RPLx840zHkapofON8QHlB8oKJfQ1Ii5Fr3PN2BZ +I6yk2IsDQZpJgxm5gS/norXnz6CX8ABOe9gYhcSNMfOYXKEIsxkHxy+K1x5HkQAj +TyEagU56d2T4runPfI/Upgx3JztvPS0ui7/5yHikqgwnHHwcZiFhgELkTzDhSkJ4 +D51SlOQH+wdXreBpu5+uBqPMHlYxuXOiWIL9kagYYABDd39MDkx9OvoXmZ8d8ks2 +Ijs17qWnZ+MxpdurVAwQleVwXg5JHJi3tN2oCYgSB0EJ1jCujzHJ28GSjkvsTzzf +KytGWm4SH9RbhKZtmUtDOY2DGeuvtlH/ournvYWEfmnyNwbICGApeLRJ1VSaggY2 +NfuVA2trp/4+r0Zjfch7AsmmXArJy1bJK+GhKOky3Bu+KdWp3j+txXg0bG4haiWm +viedcLoQAY464HWysJHol292x+48kkiCN9zk6RvpHGhJFv9TbSIrIIlpiUiIt6KX +MOPKy/RmE8W88CpzolWB9ACo3G/rXfbQX5rkPdBvnV0vRxXLC5vYs+SDPqg5y7sm +4zCr/661kfV7F0lLZIA7rMSbdkjBNEWYoHKfOqIqBVJPmEBRbamge3i9fZuDi4y1 +aSmZrCWiCVzLM0mziv8TLtiIz0b07zkwWjiM1CTi9hJC4aXQJYbDYYa1yjW87+3a +9iX0oHuPCyEvlBw082EvB2eSvAUGPS0vCDwJivS/UgZdjt+GURMkKACDzue97pwW +tSho4itjdiYd+SOcCJPkgnPRtKaro9x10/ZEI7x7ALeiwdVT0SzprgND0cVxR7r1 +9AM99RPBMDtSW2b+hcC+qIz9Q1qWkj0CQYQe6JujGz3eVJh+TMwGC4cwHRjpDv/L +Eo44UsmeldvE6e0eQ0rpcdXV6NuhFKCPZXo3k72HLhwaqjbMBV7CnwixRtLduu1+ +2x2EVTsnC2uug26ad3J3UnrRptxJq82oDuoEoqHvlgiWA4kM7GISVOORTnOBUl/y +CRF3KEwkM3YiZto2S+bMhavRcf71iXCDV8k2epbQB1ySCITZjVTlw8cJOHTI2XLp +zoqKgaf/UcVOmlJDksVSPrYkljR8aWdrB8Zc7RcHnC1EHmAS5Htcy9reWKTBQma2 +V0WtbSPahWImh1Bv3gGy+S9tjzb8I96MYJmQVGIRMfniGNZnSK9Xl26WGToTzuw2 +3QghJbF5bQ5HwMScxOnYI84MfKW56i2dvPLcFfqhGSYbXVdw6NfTo2lN63W8OXI3 +RhY6h2LlZZqPCVKyuWxvLEeyyHXaadgtLf4F4BlgYJD3Xul83gEwBlqQNDl8wlNK +crUkavtDEy7UgijAQuQ99CTMywVN2dmKWXGvwR54mYSsGGWwxXW6TMpHD0LJ8/zc +biPWx25+B26M7T7nfhkSzJ6riQFWj2VlhWORPJ3gKHrck9pL42Sv36gcLrb3XC9U +Gg29nVbQy7fHdkpXEogpNBlExgrwdyD653G9k2Y3xrFSObjjsSs5ANWqadEWm/Gr +j/PZfhGtopF89H81j8vUTWufCEzV4nsWsoVaHTGcHSUWFUwxC102CUmO6qAbJXca +4I1xe3SRrE2uu60LG9pAm3lxfszi7ObXfy2icZYctgNOLrz8fFuM6Qf/6O3vdEhy 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+WODE0xHvYv47l2Bxuupl5rs4E6CkBwxzY/CVY9FmifLcNdf5PsIcnx9zaxOA6iIo +NlEn4zFRz9DzC1X31AcUTxlF/rTNO+4vjkgFMHW+dM/BRX8FK7PiPBvQXornhQRQ +pP4dwx7wwomhAc7ywgzmODI4bhJHJj5w+1fRTE7aGhH4A2/u0shgz+EHQ1cPQukf +AZEURX0ay7ckNC47IIbeQ5vNRqxEdvv5CmxHbF983tEXmIwizM5lhP0WZ7/23hWC +2wVU6fGY7Bq0RP+23KCLp3cCPLLzBCC1csCY1i4pXVLr9Vtzi2E885/kt94wPuEm +Oq0DJ3wjzHvO03tiQvbo729zMY4AMBoH/Cyq7c2U8ZvPuB4NN+tdHMZRRYUlWqpf +yjZV7u+3sTqvzmLKjl98KyOcyHhj+0lxuqu9skR87lC/whL8c8ydlAj8tsjdNFGZ +XyOLphHHwpYsb2VxT85BlWHjmmNYzUqLl324bjtlnXHXvLpL5Xp359KxJgBx3w+N +dxXOSmpWi8X6XUSExPTGVDt0qfmWmxmedG+V9zvH5p9tHopBskZaosC6gqQoM9lj +Wq94fNIuRsTDqluCOCn50/IGsM79dakdbEoPsvInlM26XQMbOGQnfa1JfvE/qaT/ +Hb+U0VFpTG109vWMB9I3uE2IM3QFqOxurdpyGzWmGExAAdJEgquuxaUKchtRo0/h +swzA091pG9w8snK80AnIuTUE6WD1JJ0YM0q3Fj4i3Ucwhi7wzKaZLcei9C4KH8ak +RBErex4h7NxRySZGdmyj9r32hSUqeF9pdGE+AyXhCY9loV/0+IPQEBRw7dyS+kqu +k1oDCjQPIXNZSteVg2NEq9Ara+Nr5i8qBNEwCcbJfze3RwRRUJHfHUYZZv5Bw/Ma +UcqJGYuFA0TQxK2fwwr32E+9qtHQB6KabDjkfXkxos34RSOE4PuUwRP+Jlnp9LJj +P2uBo+YOxrlPfKLgavKoB+66pJqqBFxpkN2UjAls4A++BpHqrrD3GinOHtejw6LT +S2jcAZTRRhYfI2g/A6k3ew== +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +UHE03qwRSxH7Y3SoeZzOc2GpMslhCPTTv2Gw5RwahMzvF3iwatslvcgDdd8fI2BD +Dlu1c84ye8ZtLWKjSb7N3GsBoo3WL36AoYpYmyVW+heegZ8mZ46dNYCnxJYxoED7 +IvzgWWoOU2Bm2YgFxPOT2mKantYJ/ATXd8bVM09X+TEBE0e71DYDwhKvq3zCRpBI +PRftlHhH8DbF/MWedexxU6i66X/9S2mAQwPN4YRBCOf/c7OJ/Ole/Zpf+Dnwo9qX +aJp6T1LTtodRLhqdPlIWFk0iFCi1UWfs2NSsVGEcn05HspdOy/Fp5sIeXIK72cob +oDG+vayEozPxF4e7YU1aAw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 7968 ) +`pragma protect data_block +45VSHw6COPRciAp4YlIWeDNBlQFLxnoaBL7tEnrZqsDFxRJbl/F47dG5u/ha5AyD +xPbkq3jFeg3hEfPkniIXtKce2gZuH0X/X47X091eDfUgjgAJ18QpbQHNVovaB6+J +gKlnY6U28bOx4J8kuMnn69Ghg/4Uz9X/v5rVNiN5kDhYBs+nIO7aq1J3DvF0t6qA +AtRQOBAcFt0N7HHLvM0HP7NtjuyEk0LVFgvLnisDko7YC7HI0jKBgYG3YtVb9p0h +lgW89Uki861E0g5j7eKUfCHPQubEtpWo+x0QnI8BIecVowCTHC7ibLqBKbU/FbIG +EqtoCQ90d73V4sF0jRI6zT1Rvg9rNQSNg1xAOPB1oE8KJF/A9LyvPxPrCbvb5arT +luHxhRlMXtAfqwlUTh2BosyFNDSF3sKP9wR3VZeXh/ea5l8jOKdtHpDFQJIDLYrM +UhJRlsBM/cj2BXD1uMn5W8cUi+DlRcDrq9M0/UG0QCek+hGRRa5h9fcM82L2bVNC +CJHanBqB5f3Q3ysiPu3BOy7H/j9SFrerpYXVuFLUoy2oYnv8qf18UP6IsRJy4XDc +F02jGCHEpqn2itSCAmkorsQ9B2EiNL7qJnR2w8YoWbuz1qPL0LGoHmwAgHMJEW7z +BAp0+OBwj5FYAKteI3f12CTEriE1CxjzzUBHrCGyHBfpKe+BSmt1dFzsmYufK03b +xRGl6rwHv5qfNTvL6cZunfmLx9KLo0dopahxryVi4eCU9RMmSGdVEuthAG49NSAV +JU1nFyXQg5A2H2+pzRxwS953RYWH8zyNlVzpEu3coScuJRpB3sCLYq34eEWYpC0M +Z/KiZEist+kCNa/eWtXpZFu9BMgd/QPRFuxI5LBMBImlXnkIN/LiwhQmNyV2xwxl +CZSoA5eaaTs1EozVmqN2NzReiua9M8Q++n2oR6qtQw7L2kzlLO/ANTZ2jpFL4I8G +9fXFNqF9s+x55pe0HPpDh6H3AAQv1V4Ki0X/JsDvpH75c3gOgJegLqjN5+e0MF4Y +yThx1l1zYcicQEXi8c+o93bLr3kWTP/2Tcf5UawXoSVylz8bi57eKYdegbhyHivC +sWapRNixUIfGKJUZCO1lChL/IUJt5tjowYqsLGgthxvH5qc/db3MbuPaYctMRjkC +T+4YahLXYAW4pT6LZzFacA2LqzSzvtYDg5V8rSPVvorDy0DaTuJfTByHmCN6QEk+ +NMB7a8mAtDBA/jfXNGmKzyL8Wufx4sOP+G1Vk2Hju/9CR0QRcDPwt9/8o2ZdEif7 +OZ7qKBMJp9qJbfmX9iGIc2n9QAHdJlq+SnHnkACQ+fbV+R0sde0eGVsAMT3GHJty +CiJGg85E2Zz1ZeWlKz2K8M10rb0U52Uh2u5qa2t/OJTzlklkK2BHxuruKrQ8+XO6 +pQQnOI3+V0RfeEuIMki3uxUKsznJ5ev155bwBh66CR73jRKvXFECTv9MeZAnw507 +qjBYQDVqxznDWgqi/Vgs9cVudB+72DrN0CLd6X6gjEkxiYQBaED8ODVUgbdiarbX +mwJeiwOUQoN9No03iLVNA8psLMl6vPjyGtRaRU2b9noWZqhhi3bgLO17R9dRRHFN +k3UEjELluVBeIgkgLsPFIGTaklBvDliqw5rTcmByX4klp0B1D2CPYN6W/jgwDt1s +x95lWRZn81DRHcnl7+SE6SR3zpVkBXpyc64vb2eU8SEXiKbDA4ht5tbx1oY8HL+D +lhVMhbTQnqes8Qut54qshmrlbm6D90gqOOVRz7CExPEsdXb7x0s46Is3RMJx0fAD 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+0CIIGfg5CvVm6rNRz9S9zJS20Om8ZrbkfL5hmXoDL2nq4C11r5d2m3Yyqrpl9hqE +7dRmAp9EHx+rGT77Rr5z1h+jXtFWwqhn5hvn+BmCFYUQGo3JL1bDnk7E6g4gHy0m +OgKHiCFwUHWYiLhR9afzNPuYKfydhjxTfz/fOPli2WJxK4O6mG4J3vXGJ7JBRTWv +xb+pr0HqR5huMNvVLLzvxUq9uEg0+IhY5sZj8cNV+NYnYPgBK9XIQYgDLu+9d91Q +UK7z8oo1M2ieR1EHxEEqz1Je/byjkjzXh1QTclKaPYJCqSzdG0ei3gs3RQHYqcri +ibwKPMEx/zwiRHhJ8js90S+Utw/inYdTDbBXhf/2jANGbWH53M+L+zwLU9JPUgzf +SKUqZomlgwzYoitnSwX3OWGLZQzC8KDDAh2tr9j+s8a4NwsPZtoMRibp8gl4jVwM +VQp3c19CrrLraOhkbCSCM5M03WSaUNHCu3X0hC6nRJUd+OI+vnHluU+wQ745UlPZ +mQySnl/aW9rjBoXpjGhDzfdmUOQ2X3MPnGyVYKZ/0THt01o4Yse9w4RbX8S0iTd/ ++fIma28pu0HIj4CytbffI5DCdRI9BP/A5j7nNnp/xZYfmU2J0U7N5+X8z+YZDGdr +KgyYIMwuVSWTgWA80mtGmlauVjBRFoM9QrFB5PlIQzuK9TzsMlzqbbt9CpYhwxd8 +20GJ62/I4tfnyAtSesj3Vxsmh2CcP8jncGmsswSacE5PjQ0OBbM0JRQzuqNS5fLr +cVpGYGEG5fOCPUmBdaXsR6ck36TM0W5yIX8cyKHjoGe7X6FtrNvTYzgxjhprlXdt +z+9H7hh4/n5TuFXCD/m3VxukTolCF4eThGusLF50AcvHh9LIpefTtYIKTDHyLK2I +7FPJZ/MCytqRTwcKxk3gdI2PM/hnHX3yS0IAmzjhYVhbKC6HulkPO4bKmaP1aEcB +iIftyAbivNxeZb37AmrSU9ongkc0rxk/63IKi/AJY5Mq0Op1RkJpt6TGQmfmgrbI +txdPUJ8EbETX/kEN1zDsEc9TNTkI9GTqPzpFtMbW9wL0Grce22pW+0c9teCkFqyZ +WCG5wKnmiQpeAVv1VHpYwdEOzjJv0UbAyfG8kRoSOC/TgG1aFA4o+/XW0wpw8Xhw +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +Z0bYUsBqE8947zdgGWPpqFrvmEzhq04RKLUN28rQ1wkTNc3p6zFpUJeEKPaQ9Q5V +tCYl0NaYT5qvQhZvCzl+x/jJ8wBpv9J3+d7GNb7nnUIy/NMuLGEslilaFQlBW3Jx +JcuDPbbVPZh2va/NooKz+kXCo82BfGYEKaWptjDHUpp3QHpOXlNpyho/A0yFqBSM +AejUEZks6PR4s5Chf6BKcUmh7/XmEjgEZW9NnltYPxumu4dD/IWfrOuVW8f8xwYR +Z97hT01NAlA3daomFvT8ZWfWFTypxCaR6SyOEXBxs3X3UloqjzT2lLIga9ZeNxnJ +dpGd3a3KAPmgul1Fz5Mtwg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 816 ) +`pragma protect data_block +Pf/yNaDaWKTTpcOJbNx90t35XxwYm/d9wJOyWLKd5c80p1TKmFatZvMBgclEa4wm +8M2luNdoyRCXtgCXi50UFmvDCdnKyfDg4RmdAGBqvP+DQXzbgq0r8Hcu3R2c3wRN +dTOMqbGACK9r8AnAP6JVOPyWpeKNQ6fdAs0PxUHD/zDAy3eIY8xzpFkIH0QIw5Vd +zg3YQ3fLlhg/CMJOliQARr+M0e286QIKm3zg4VEiVvBGJWAVCaM35O9a9Zk+yH6l +or2juNa5ufSiR0AWyOVS6UPlrT5E3bIcuwEhZa9K8mocpS8sd99uS3QYwilx6wTX +xpw3po/K6CcTc2xSIRZuGtIoDL7Nxa2aWlsl/pc2iho2+Y/HYDZThrmd7tw0XvFJ +PtsreaARZHeJ7ANRzyrlQMdPmAvHCT4CjKIiyVKvcbgFUw7D2hMP/688qBFJwEPf +OCQsn9Np7TGUpNWt6QG2R6M66lkyfaWYNx3vhn2qGO40/el4dpXgD1AlrDUgBuRu +ZpBP0qIOOvsxghto0MOUaTuj3+Q/4iCLSc0dJ6d5o2j8sxz0klLbzDJySqdohJrA +41mUZUvEZ4JN/flYe1TRCCHEdSk8h+KkvQfDqqJp/QDS7siyLQzm1JyvTKhFo8xu +9buiNusDvnLILyoCW98w5kFDRf+zHhWKN73zOeHGQKfR0aO7fX3pxXLsEwLhK54b +Wir5u7+9pv3n3v7469KZUa6zWzkjWcFjOHxaYA6DuURi4Smns05T0Y0rMtc8FSbF +iUZCA5mPFRKviK+6VE2SsjuGkMCA2zm8qz9z6Vgh9t9Njkr2HoPnzquYQg3c58Kl +iGHWXfuurDXwM/EkFVUF85ojRFGfXLF7sD1V5UNJYnKp4aQBM/8+TZkMB7aADvGS +/pmGmD4xlwLYjDOWgp/7091/kTLRZSLPoq1OEcfO6Z5VqaAnDiL61UTbl3/DLjMh +cH/jr8xaYKd9boxsCL5d/mSuu+iFFlVTYcZLhaoa8P4MYLRW2eaOjjuciNYperOb +CgHc+0M97uB37gtHJWr/eMavucWdrh9vHieFTjsQ/ov7ZK9++h/m3x0K9faH7SvB +`pragma protect end_protected + +//pragma protect end + + +`resetall +`timescale 1ns/1ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +YgWaHP1VVrn8q56faPuNrQinWLe/8n2gJ9/4MU4MDUiGnK0PUfYovpXAmNkrRzRs +VtwlC6Jj7InRw6kd0R+Y+eTMlcbioFK/qAxJSWfvQxCOPX8d7BT5wuWQFVsUoS+M +oh+4OFFo4X9aa0mI7PEcrjEhR0n13PG73T68EVWvHz7FFgytscWtG8kwqOSOXmav +jLPII6xmu7YPzZm/HiNsnMvvViuwT5aJb2CnGBw6n76GIMmghRK9Q0a/Qiylcaxx +teyYIGLKW29sOz3rZ/ENSLo010LeR2MXNKrLgL+PIW6y4v/FQ362XfI1qYw2kVQm +jpzkoevv37iwQEH6GlMwgg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 480 ) +`pragma protect data_block +Dd6JpxWofdheIkHFwrjiQ2TUBTsSrHi5N4DZxL5ImyVO0a8v8bX+ETlfPNZUE+8r +SwuVh8rOFSay7+0pb14JXUqp+DkrtVuid+Hu0E/AF2LxkH8xuI4mtxHP4wpCkof+ +XA15pr/1OIO2oas5XoAkb3d4JYntYFFoODk4+Ry6tArSi0pQCUAbp2xlJccIS+7g ++yQ1oXZ31XRzEQ5dk0k3B51+5qfFF+dKhPCH/Df5via4wF9ZESfu2YPZlRfXdmiL +yy9HzqqqDPfcuBtnGBqdYg7E+a8JV3eJr31WINkRjB466nVEkWlBw8tBpYiaDqZo +u0czdrGrPhk/G0pUqGMW9g8fhtSf8+oKfEhbK/gLqlQ78J4aXdv53kni1ylyInQ3 +wV2jwkio/Mz4dx3QJbRxdjGpui22vVZ2a5YkBVEL4E2xARB/u4I0mhdtWP5+FIhJ +TeOjuvTS4qw9jLUgJTmvsHnAjDsfwZzqa+7FQRfiR63Y073cnUHmB0H9CT2EuM8S +Wb0yYNeBSqFL2A2zJNIj6ruwaUeT90eIoNB2hglHXBAkRfqiZM0hdbbuk/CcAjuz +XD31yYRsEQXfcMmJ9P647dvYwdzECtBFUlP/DaczaapgIKvsnSArzKsq6691veHZ +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +mUjzSHf+uYPqL1n4IVyPVci4v0CrLYmPDHLV4awO61biHqpmrq1JTFqZBQseHQkH +6cJcU4LYtSNM3V7yBbMqQgr+2S6WRbMzWLDk7oaYThKqu4qR52i/o1CLubg6qn1I +ZFZY4okKZs8sbexheNKJFEH4N3Wx6tgv6nV7d6h7M2htuzLclk8xDgldmWT/3b+p +G1LAS8Dq6Ll9eTtFx1t7AYLaCpaSUJfGQejrDqvXmTyUs09j8PYV+q84M8ow856B +r6VT7J4TsQhul/FwXdFtG3r6+gx0T6HnCq6M0DDmeoz7gLnekNXKa5FMEstTWXIl +ctxitcmi7/Z40dajl21emA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 816 ) +`pragma protect data_block +VLstfW6D5LEE7ZexczR1r7H5DG8rlhP4PiND05BP4I4l0Z+YIQHuCADYxsh6LEn4 +hfTsh68yilbNO1RYyv5EU2gjhG1upfVQG11+GG4wJ+ebrmO38+XL7NE4vKSi/uq1 +/FlhR19oRl1Xje3fr8W9zaMTqhu4zTBn09eWOORepwS4fMkhXDRdfK0Lcj6cfR32 +DajYlFXlce2ky2kjndjmYy4p+Ii2I3SMM253IdlwVcL/vDCxsPGhRjM1BbXXs3Rl +Fg0A1IZPwQbTFdpIK1uNMjbEGfX1Rd1Axz2dzVQIpouDD7GKfL7fcDbknBi8ax72 +z5dSqevuYtuAYkXME8N35J8kSEm+PDHri4PAQn+PTZ7SlAAdwGoCshfev9Wh0FuA +6dBHNnp1Xolo5hgBnLEpwk86eMfpCEmS2SOKT+PtQzbH/9ybtCy9cxyeQa94puNB +pqLt2Yz6ZADpH7a1qHCSWk0R0KsH3G28FWaDVmx3hMo3v1hO69SSL8MaDkY9VaSy +LeByRe8Ocunna3yDiT+ak3nldI6eEkox1A7a7fzP0wr/izyUB1nnoDUKTBTpUjQs +imcM6DvZ12xUdevxNNDoT35XfdHilBxnXNUHukbkfKKa9DgELM763LGt50La05JD +2DRS5asmgZUt3P6om/SMA5wupzfyGwJ1sD64NGeXn+9UY+o3kmQb1PFd3ojnGCSs +Yk09kJiIMVT/Fvaz5kh7T3Fwq4fW54zRwQvkbBzHW0g4v3hQ14CKOY5ay57C1KPA +Xd/gjm3erxvE5KRquwl9qBbPG5HXLdKGYsBkeHO2syi4KI8RepNnQMko2IFoQf3U +Dj4vIBHKC/ghUO9ivy4/445hL4JU9HiC1bFkmP2Ojg6j5gR++CI92d6VcPwzsR7+ +5Pan2unlYw3kppVlIX9wgI8lfRtiM5zHhTFf7akTXgwmzfV+L4QWrKzkjoNu56Lm +znT7+JDPsManGGeE+DsdMT6vcBDhrOC0AI82jEGnniFeT6Ftj/Mw9J+x9J8c3/z2 +LME6fkFQf6gsTUIeBwvpixHwCM2oIjWDkASPIl9AXmSnqjAWrFqtI7TuJfWIkx7I +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +Ye1kA25/n0nWVEkXGZy9SyuUjU4Y6TvdjEyZxdHOYyJqvaDK62VmGBEQpH39t1uf +G8L8coe+k7Rady+4qr3L1go2bL3nKa6Zs0iyCYjP+pJkLJCd8FNBNVuiXjHTLmaA +iCbjJ2285yoEhYQ48PIBTgBPoG68Vwof5V2YLee39KzlRpYFRuoW4j5BotITbxop +M9I7g2lHQpoxnmuMjZUaCRZOpg9YTqzaJ9bGFkZj/vOS+iLMgBpS8FDmw0+JzJgy +murJ26ZaRXJi9Kd6iHqxOXbae4vBRW9ICST2GFrNJ80p3zPkYroT+xnxhhHDUHEM +CifzZu0QanpCfZ2ZIgURxA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1984 ) +`pragma protect data_block +Garu6n66/nHyqmePOZzFG3PDA8QRaG7IaDod4zrXzSsO6ogd5o2PVUPNh5VMNGy9 +77oznQYEYGBW9IuZ9nDC/aq3FUmblLd4hWpjknTruUObUXBgYXaE6zMd3KjLtiM/ +4HMFuoRnCWnZyu3P7Dg3/DTIzYgrY25ZiQvg32jyrQBc7JVQX/Y/E9XSYLCAbBVL +oMLOlqe2q4buUzSavBhEQxxg+mbrCBeF0D+HkAv64VjUwYTLcq3cmDHG2FPNTcAt +4q16s7PqBBLVN0zu5nDAjR1odHpOwf9+2aNSHbAnCOf9vIs6plPeaJ2dTcGMnzbK +A5f0/sGUSCm6rerxL+40kvFbQNZwTBe5oCNzi50Qo3p+tlJJpUfWIE5Adfxd+5El +xm8NVIZsarHxpOQCmEJoAekwXHtguYTU/JAdEjvQeqV6yttJ21Cw/xpCXCdayaIc +w6rPPRuNOi4jGbQOlrqGkXDjaNXicd1qbCvv1pKKg/gG7bxQ140/0q0DMpRXbhL1 +82sVECjdRMV+eMCmK6hxiPDwgzUqCXGPZLwXrbnTZJ7jX6cJwpVEMXGI4IsKAqju +2BwaPCYMXPw6PxIDLs1j478nZUi7oBJGYOOT2sMI17gE5y6VHQFR9o1wPVU7QASv +/np7nqSaSEOdq3ayYfKG5YFEKesSD/5vEJS5OQqcVIqiERMhmo5ek+IugLUgDcpM +YKz8V3KZMPR+yrc59mMTBV6omcWLEB8RsejTADaKvILD3uOjHW/dWZcNe2d6e2cy +bkRCVUgodXyLhoZMiwcEovjMdfclnV+xESfrCRfBgKsyf5gIqq61T1FbHB0YEfb7 +1yEc9Kyl2Ysnj5J2UuoPhMwHx8yIwpKkCj8B9oTig0SlacnFmVs3gek9gm2LZ3Jc +zo2OPHngZcEwvgZK6/2dn+uK8ZzMQ0UDsDvuJ0kBG75cn7fdNMuVhcTJXQC6qyHZ +QHtyBoqt8Rcxj5wSb7yZRtcjINE0SIOeBzjTIAO8W14D7iWr9ASUKE/eEoXi+DJB +AEYJrIaAE/b5EcxHDXxmemU/KfB4mXbqifqCoJwd/bYxgrv0QaFsLcEvpvEgHGU3 +rg4digLRvmw330qRA7Vl2+XXE4VpcCAn7zYyk1/e1kqY3Auogqvv05f291LQ/PqH +coKVN1Jb9PwuZHxREjU2Ef/N8Vjne+33IiSVPP8V6BYUaeNTK2X9yd/r9VrknpGW +OwGqdheLqFABvI/5/pXuBh6qGxsZu/O6nHZtNCGIz+A9jF8sJ4FYvcWIQB1ZGHSU +aWeUO6EQrGl5iXv6L2n3IzhAlibOo5LUx4LlGtmAgSF1fcGw8/g59TjYE/XF0RIX +MuKrd6LkKTzcQwP0i1dsZV8POnyjddy0bDlKe136KYMAoBEJaGpTxl3fTFAwdnJo +lKypD9As61wWh/RvfvEzFepl74afSLx0hp20ap18naHyaTNX8iSbnRhderywFXGg +tNbBqygju/E8tSi6bAtMg8UxnKIiHRqZTfXvXeXywzxg+6Zu3IMJjB7ejZ+wROAy +W2qqvT2xIAKnTESeVYdebjIaF4Akjhn55d+fCKjLCcjtiYSEvH+8/YwEq1NsCe2v +BqPUcQnpIhQQ3h1+q3xgQxu9izSvSoMfnzcA0XJbnLEvjLXL/LNkEPygUO1vXpBd +ovxP89b2JvD5Yj8TlnrPd2zVXpGLizuYbiTkL+eMAIkWqGCeuxFjPdyFnu/ecPoT +v4xeadWKjrntjRyty43Ir8w55U9lL8t4uXf6pNvAnpkklklowO/KXOGYT/VsStj1 +k2hSgN8ODWKbf44Zvqq2OyMFjqg8Pll/Iz3UgvbGll4c9mdwvTsZS00etus7U9BK +X7o+9rt1SSr4jf4JfYpl6M07nDaFwFGpwO/G1oJ++sx6C/iiInH8tvIw2m63aPob +DagCnY9qhhMIsvfWQl99bHuRiajikI81oQGPCZda3m/guOv3aEzat9njTPuk20SG +RL4TSWqHRiL7aJm9QG57LjyeCSXKS6A97pbPXnNDaoWRkxpXTbM1EG2WQVxidS1P +tCgpf/HR8z39GbDT6O7uEirisfd6YS0r0PRYEGEKzSOIfH/sX0RU7SRiDz2t/EPA +BI+rdXHZWziUI/CqkUJnnEXjkIx78TvcJrgbyY//FENn8hw1K7ylBbHzIWrtbYRP +kyIFCE2HDgHg4oNEX3RzyZbeJgsPiz3gq9ZCH1A44K+YFDJeN1oadbFQ3ulpu1Bu +5ASwlCWwro6xmU7lnN4ICbg9lFnzd+XCmKSpzh7nM3OSDdReJ+lIxOiS5WQjVGyt +C07oNXUo/+fnvTG3hyoimK48X/3LLef1LKIl781mNlwEvrkmRDhKFtSYTFikH9GC +qreMKzZkYV6jV+/QN8t38WsgH6ggI0W3hBG3Ss689xQV6ZURLAAswSyqACD8IJGU +EZ0Mya4MZgvCLnwJAJvIYFxaaVgkNXMQPBa+KMtZ+w+dsNiJmT+OS1N7s8mMNd7C +whNLkDItqcD+DQp4eLUa1y7SDWaKBT1zn8ZnYFaVu2fvBlkSC9i/V7xudCy7s6Dz +CZls/n+CDakWQp2eZ9rs+hD1GrR+dlDoactpTFszWYY3ujiDcs+oB+PlKiCziGzD +2CXrv4rMXPfj86GCN4+2Pg== +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +gsiyAh/zL1xUwpmprr6NAQQaIGczBGjhcuuUGvpHL8hMBxgMPcIMpvp8WS1ajEHn +py5FCDlR4mW8uXNvTts5kgng4OG96+DdQ4XdXqST/b20UGq4PinSXtk1LOUv7TFw +yYAQKVWJda29Ami/BKJegEbhdCks1D69roeJH1DSwVfXs4+eMQrjc7MbTbY1mpoi ++36fJivaA7U/YlJiaS+2qIhWoSM5Fyzla5dhoW23p2f9pCfJOwY9bYe6tjCBi/92 +qgy3zls0rjtKupkAlBZ6bW8ESkTjiRN/IyOih61JTRjJXR1AGRDFnndbdKW2JBRX +DDpVDAdIo0PQsrjeXscc0A== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1120 ) +`pragma protect data_block +oJzELbB5LZeNsNweu5uYWTTwjiMIVGEKkku/Cry+UEzxU3xbxPijNdpqwF1CUnIu +gyeQXm4W/aABy84cGADozOtQl9tYT+8iEZDzwxiL3TduRCLut952DiLthKX7tDiz +K/Sfo/5K8SoG+5gMrxRT+PS/OgH99ThFjftnZaeUDUL2YAVcGoD4l/tmXQMaYC1s +0Czgtprrh9KgH8U1OZPWXeGSCQ/Wcvby4cJ6waaHQd1XX9mgmkyX/DoGVWjHksfl +ON/V2l80YzUA7kz2S03VWrm4E0gsaemi9zjfxMffXLvxxFfUfh27bbeGbwIrV2P/ +e9ACpAixlZbLiy4SPN/TE/N/fx9mmqVCzM5nL5Hx1Y+zloPNKumf+FN8/LHE3vTI +X1HR4/qS0EV9dA01WpmmGNaHi6RZ7hoh80NoK+5VYpuJHrnzM5+ypXOqpKkAjzxA +PyB5y6AMGk75Zjm05EOdWq1bscTch9pxEYwmpnwNrD9SeE6QZK3cSzn6BWR7cGYa +Vh2bY6lwovJVl6uxaJms1dMTnny+SrkIitPqD8Z05k7gsEIdH8UjJnhvlhP9Vzg0 +vJx1pS8CW75PYm/7u0U4o8iVOebmW6uHmra+CbWEHrdv08OZ+VZdJhY33uao+Hhm +fKI7YBd4PCnbc9GiFI5j0hxpSxw70bDx4nkVZU1E27kM3unKmi3SkIE7cC7zFQUq +1OSt/GgzDEU9BzLXWd8ghruhmr/a9kORV7mPvMts9jKCMgXxS8LmXeyAwgw8GJYV +6fjbL0qWyPd4UQTGmBZOpQJKadU7ru9JPIrr+1w2kPg+jMqzH8+ctqwHsbx8lqzz +re+6w3Hin7b45rVm3ABrbdS1JwelNH4xoTy0X/oroQFQglbZ0vJPk4X8TLDsz1vK +OnDEtNKwlLg1QZLW+lEXBoSUk5LXQWQEgxmC5YU/svO/VqGARYosvV+pF8aA3pwa +HZkpdtk6kNHxhQO4OlV6Tq9+kp8XrvNYEjtTkwKCzqSuJqNL5cGqKCHMzfz0lmI4 +2Hg9HDZv4KxkbAx/5QFoSCAE7sO5sUxRed2562cljCUP1B7HSg5Otgw73Fz1UupU +MIIkAlf4wy8MNnM8pU/YiYqabOUUadN/Vs7mOg3Jnj/UfGRrKxAnYw1YGQTKAI4A +qu4GPVqmPP0dYEi8h06AD28jO4wlSHGwb894S1YlipYskzfVg4PD88UduuEmPkwk +ob9Zgj3JPMAErReBxRpJGxDLrK2CMpTdWGlYONQVoSkdKvTj5C1JEtymuUM4IgP2 +/DfWb2DbudqukHzzwVjXUdiXgul0T/LseZLKviSckTQar+nVfwHYH+9YNK+QzQ2E +QhYCBCm2tTG7f2xI7wjqUfEG3hedAoqoYGoq7GWaNHiW0sMK/WPVl9C464c34HWo +RLafYBMUzzXknRsFej2hOrLiGD4VHJFlUPXDEjiyQ194rUWtmjDJ9x+0cfOTPczJ +N17QQBmIYiQGeSX9Q/1rDg== +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +E8dXbDShY+3zW/pawy6A7D9NWDBtkXfCt/ri36z9YJa8KqfJdswpb2811maQtonI +mB3I6Qx3vugXgBL+SuJDYWmPAuuK0s4V7CfYmd1uFx+gIl0nQmwrz7zGXxGxS1IC +Vo7cclA1Ux8nkd5kAV/a7XqDP9d1xr2IqDWp4sIwfXVYSpJ3b3Uv+AvVC5PLbSpW +WLZrBDJ+ktUNqvP25HjEDcwmdyKx+IYXtSdF2F0OTxq+KvyMkkhCjJDno9MKfPla +WDec0k3Tua9WFgnQXwkfgJtsFE7azzWpPTAIYYyNo/vsq82JL9wksdOpMC1Q6/Nc +ldjaRkUQ34XjBHxGGe3nUw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 16432 ) +`pragma protect data_block +p6S9Mf9ezb5qk5YXeBF0LIfOw6RxpYgFZJx5NiE5aVzqjzLHCcAfDzR+wfDEMRnH +ugRW4ejCNXHLZ3kxkHGU7cPkawbGSlG/aHdksosyhU87kn9tY5IkMzUexUHcZ9Up +dE38e6Q8nKLcRJGOycCeInYlFvAHnuYfS323Hm3KWbmRPxZaa5Um7Y5lJeZtwcgr +53fckM/1BVxrst1Ml1lVrWuBZtRn5Myc+w3rvgatUHSxt53UkyFuefOxAjgZTXxB +AywmGpNk0BBWrLp2FbWx41HfBbT1T/WtnO5kEmNMHVuMcd3e55a4R7cCOAoclg5F +ObBPt8bCZKm773oRVCyY/9peEAr4ANfBoAWQpE0WrVFmNVRQH041+hTn3up8PVxd +ul/r4suz4eKLKpP6oYaExd2bALNTQIo4zV06NWtwK8iWRzk+XGN3JE9UFFmJcuGS +thyc0zET0dcPIzGGkKNDUEC6xtQ05cMiWGLvFsNjUZMExsKJC3luxBXHLhIyrgXa +MabHH+q5qC6qD6sicrxUx6K8HN7dD9CznT9B2Fe1HQtkkGDDxZz7XTmlE/gty9c9 ++7W/0icmzGCHzGaFr4UAPleM3vYmyBEgqx0xioFPBglmKnJGll/vk9lZZHktXJdo +l878DiRwpkrITmWOt+8tmYV82pYRrnz9ELSRE1eNiI9jC3XVDG1aWw+CzrM4nFKa +xV8wao2DAK8/Jx49uox1u5eE6swZ84AWBj2VGZYWawarhrBR0OdOtQ0YwMkrHMS7 +fqifOvJreMXHEJKVi9CO4M5QlmAUZtg04f85hunzEcc/ugjlCUc5XVqJLR1NGNED +zTh6stxoAwdedJNkPje8JJVCvO97QpfrEjgY+cCYCgroNSbKUzX4n2hOayfQ2dF7 +37GKvw2hj7gQURLrogK/WLaumnfV1GHZA2hSSV9AT7p/50uC4t8QgQd5dT6VzngC +QGGE2Ey4UcAi00q5oPwoft+aE/Rih4qA61D3ab5NUHg4VKKfjS75aLwv1mO9MUtm +Yfl8TuuN1XTno9Ar/UN/8Gqgjucp52YVrzBwt2D6dhCPdH12yM/+SXr6wxb6ab8C +q3nF4jBxOKh/lL7FiqWp0ksvXBqgySjbIEmny+fQIP6eb8/IFnG99L858Disp4dq +2zqVT3t4p4H/jdcVGtE4JNl0Q0ySD78eMmf/RWA9u8TleGSjIF+uUbHJZzmpUoRL +ZzqlAHnaYcOdgD3TnA5K3B+TKq3ELgQVUyPk2a8fWGeQYOLQ1409zW+5Y5Ceqb5u +mJWsNUqzdWT6oz/XX3tAbkbQHG9Xdo0TY6nkWGOVeWmHW84qsEGNPttSKc5x1IEW +ckNnU+2bU9sYh4FWMb8wi5HemLyP8hoKJRyVnZAK2aLfylFcJn8YsODkggcyfzTW +XRQhGbwcGwDhvOXSimKvE9eNGB7q/cPfl1j+rM0PNwXN7rzCAwAydG7B/4/uYkzo +vVxUuQa0P9VxtovXYVDXvoukQae2ui5nYB4MKDBhJ0INfkIHsM6KnuU28hwZ8g9k +krUq7Ow+HSpCy5S4V2UIg6Tb99REHIQvdURLbDWKEN8RTvz9Ywm4Xlu/QoHkiXE0 +0QFSnJHC4jNW8Zvdziz1ew3VnmO2aXB1hcyTk7jLAlImJ8v8/mPfrkQZy1KScjih +UJ2Wdel8L5K+0WvLMSTL4zVOMKSiPN3uC6pJei8dxbSoyQkZYtqzBPlI0aGHwmc+ +SdveDfiYOOG9PB2q6GpTP77afyGlrnPxAeEZoRrAq7Pk5CTR5CL8ptFGjx4yZNZ5 +UtM7WwoE7BMkiaLXfJH1vI9uXA7tty3lGl+5X37+9XUG0qwZ6GsCfzD2LjBsrIzw +1bAld9npILQK9iJk5qcdzq9RnozBbCo2VwtxSTuEKTfWixXHi2kruXy8c6JrRMah +DOouewRO5ecNGhjyNFKTuMYMmQx6dXBYJt9saekpPCG4ZCDPAbWzP+qARAU3Oax0 +TIOtkYqEQ0AnL3I2YfZ8/w54ZukM6qzwU60eTv4LH3TGXE6OU6Wt/Vv9tFH2gn9o +he7jtpbE3a4I+eSSTOhvgK6Ulax0GMag/e4sDhSuyVOA/bgMGzx3CMwDHt/mYcJ6 +dqBFGoLirgSUkLpHr0czzVnW0yn8MPPmB+xgAjcKxTg1MD1V3eM4QoY4pwQmNOyG +GMTwTxdMOEFshm+0ej9Atg4zV+Rf7gtvUdbe0a2yRNnntGFfYKT+VizdazH1Pwlb +ZTEjaXdjMpJL8Qja0y71hGiIiFM3L6SYY+Yi64hy9maMT1/i3k+Vwz6wF41bbqcT +dbWrtUvOgmMpZKI8O1B+7Hpc9orW6ADHGK9qzqKnl1S1gq1oCtXDKovVr2+YEIsP +qdOz9TMgvNw5CRbScgQ/H20QZgkW+Tua834vUfFYkVS9UTTCCXFJj9I5aY7dBiR/ +EgLmvs9M3VzQ2nrVbmC07wewOmVdBy954jdqhE62P7a/HW+3dMFMTaEGt/lZRdTH +fZ34JL8jmMleq4WKyKv+yXPpaFnloKKBL5gc8eAQ1fmHIdU1t/1CcA21d20hgaN1 +Eap/h2H7Iv7tVFF1Sd8xqAecwGSuV0XEIX19x/AjhfsYJArboigxKwnosVMwcGS8 +/xIExsYrogtH1Nn0ygcpLDulm6BUG8ZiclfArGQImcV1hr4oOEz+BdU1XiEPMbpW +BNjL5X2OpqjtQ7ZdiCsX+zWWisGwpoWvV49es9VXk5seVj4WX1vyBej7NAL6AqFd +MjWWvt3feLtkm3PvWfG/jZHPt77U9WXX9Gezn6WE1BQJ4PZtuXbdlu+EuG8p8AOV +2QceQHI9nd517VAVOW9O6ytx93SSBrx3LEM6311/LeIibk2P/ZTXPLH2jCVlZC1F +fV+XW+nZm1JaZl/BZNzIaEIgqfphflTz8bXWs8Kihuhr3XhzTyiuNlffgspj+aSu +1we4AxaWpPTU9ihO+LNZMJyOHZQ0n6z8miBpkhuzDmw68OZ91lKExvVqXNr3keH2 +hhMJ1NQz2ASXC3JBKC6R6+T2F+TwkYZLoV1LMGrozgXCmeudleOdTSJ7xlPG+6Gq +b8bzZxHmpO9H5oTcNKbT4H5UncaB9PqqHfQu1amfH4/PpCimd+SKK1xKWT3IOJ0h +2jMDyzwr+a+9OBbz2zSa4WMVH/fI8gBPdOowx5dPTpsqRusasJl45lui4rVuYi8V +DdveIIhbjvTVbHb8Nvaw3oXo+fhY12KWqGQ13yYtlsEtXDhn1a8pOUlC7qVITVzU +uP5CcCMTM1tEoWrsx69CKw8KyMKJ3ngObqXr8uhog3uYlg7aMGDhumLKDiDgSat4 +rX9fJzrfq0uOeNxrKHBpujI8JKC2herwd9RDdNc8/BN0+csXNP/cpxpOplEWzCFd +6p+XIvtZJmSDTmZtRw98hSMZP8X3TLjbLAq3bBEIaES4mOVxzZS+APkDwi/tkFDY +4MBYv+htxg/OL+fxw2ZXded/mcNwBCDkBd5BTe/u29COA+Ky/KTdAa0Z7hWGhrMB +JT6FHJw8gzvuf6Ruq8quvu0526zF698y4yJgf5oaZNdvTS2Lu8o7NpVEWXUf8WzC +zjpXiRrNi1a2/O0zLcEQYN4Al4a3OgnbtgTu4tLUIAF4IP+bdglD4XMUIy7ucbxQ +BuOQ8sLRYci6HvmUv79DJcnMAacA0V9XGQT9Huk2J6ChtWfKq1x+nj+y1pG28flF +3ISmc2FNxbjOsppQW67GvEaaHG8XUtnQPtD6iqY/cFHPHXj7sLMa5f30n3RUKUNE +4IClRNMMdGW4tQIFShbIOehosQ2m81eNghHLY4M+66Ms8pdq1GncCN7qtzKKLYLc +GKQyqZbTUxeEWOZY1reAFpir7FpYdey22kylJJNqwJx804f9uHfq3pHISD/Be7hD +rIrbj/cMzkbMnyLZ3sMUdqQhdUIGz6kHbsKsS4BcT4J/qyi4XUQ0QBTU6H6ONnnf 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+ErGfjn45+d6nswjjpbPyY/ZIFy1d6t8BbFfxmwWg3XjK7nlJ9zEEx19Zz2Do/oN1 +Tbvd2SLQzL+kQWow3swT/MjT0Rb9IwrnY3ypHC36aGvBLxHpno3I7SI8YUTRjqSC +N4xLn1LF2g5Gy9iOa4flAPnJ/5B/d4V64mSwDhnc2ugFZbKTMJkCpMCNalTNi5z2 +63e/xbgEYxXA4AGl3GkRGdMhcvUjP+KptST0VoUJ1dHTdGHijz3xYHlDdL/U5iWa +qPBuGrFW+vkfV+PGlmEy4sUqutymcQtDtf19LfOMU4JvhWRhZ01G+okSktAfp87C +60ziQE+sp7a/ZaE5vtXem5MwNnGiIkdawDM+jBSN6ymiUa6fXyfcjbzmf9tjPcuX +XBfZB08SN1+dEXlx54/K+wFDd0XqMxV8lUzEl3DhDxdkrEh+H9xjmXA16ZA9CIq8 +62b2Yx+9XHMwGXc456g/pEQUJnV31ZaY4ryID7/DdIuz/pnSngRjInee4wX+yPBJ +xaygQLbPyWZcZatffnit7Vk/1462BHm3H4iCh8tD+3bfmIQRhM5IwmfLule1mKG3 +relaH0qVbYolDQtzr0i9zMna0IpwlFmwGrymbwF2qnF6sS1b9hyxx6KMcRr97IbC +7UX6SDa+dNlURyGvMEH6CSQI9/XAotZu8dCHsgCYdPzTbf8chfX2uRHd9YHwSho6 +Hab/EoDWK+koqq3OjamyHB1CdGofU5zfRwVfs6G0o/mTmOvP5R90S1t6spUGcxD7 +KAlZ1PIEMrla8r6dhUUU4ji3wWI8CV2eCg0GZ0DpPJUsU90QNwCQeE4pqnl7ezis +DsiSjd2bTrsyYa44Ws0LdhYKOBQQpdXFKKbi1duomWvP+q47IMrRIXvyUegpY7i5 +7FZoGGdDPNFejUlm/pfFT8fbndFPVh9rds+jnOPKz5XjvwPW8T1aPMvHgs2F0N4d +/TvwTGBO+/GyA8mwbOnQ5ubFLymfR3gusgerQXvb0zxdHXk9oFWuPLXcYhd7ahH8 +6PpnKAXLf2ciC3L96pQVOAQ61ftumQnVDn2CGri34renIhoDdhH7GAgmgu+xKEsC +xUMyRtLETiT2j2fQhXMwDpqXwscYbqhQTarcgJrO/jCtHRFsb38S5APRmwk78Fn1 +cTXANzrRQzcf4z37QLcKa5DyCmz4hNTleYLoWPklVnwk7Pou7rIzxhB5E6xNzWWf +eayQ7013x0gFJZ4xQ3EtyUDKkJ827FxQU+QVZoWmkLjt53i5Z9Anv9pUlX+izgob +gHQEb+1BUeh0ZPtmCznkeMTFwfXn0l7QPIpkLdAhg5AS9IqMjA/Fp9gYKsip38oa +IGSCGpm3L69u/xCAfuto3vuBwWzq8Ola3cUkPyGtPMVIAm29fv6eSYmN3lkvZXC9 +qMFtoF7ldm185oxHFQ/1GgHyZSZtd+A2ktHqsI1j6KbpfmfXrol/k8Wdq9fgsqNh +JfDWBw53z/+mJNnKiUHZApPlQuKLCLBBCF7gCDn/JYPCq7Iq4w2zQQtZznvd5vT0 +s8bq7r6++3voNP5PuAta9iizBrXyu3Afp7qWDhaIntBIb80ODjO54HNNMvFOpyWW +JrB+SYBjCtxcWMvEIi4nPKAODhLb0fauMUxB52DipQErQHgZWDcf5Hz67LrqbJ+x +UQb8j9q9yMJAYTbuZf6DZ+4khR+spi1m6C9dfvmh5K3Yv+X1USclvA64qaodpF/s +VEjSupWQoTrZH+IcThHFP6/+gwJcGC2Hg3dmoZSLT+fy6CiZfr4IweUHFdr+0kUH +MYXN653lENH5fe9bV3HqaLH0uQoCDwJL3qqe0In8pDbN4fVISPnOAewpF5J98558 +v+AMTj2UvIMIipCOCrq6Bc3LG2Zl3RbxFULNIQQ0PHsJyYVdJM4hs/C4wSYG8qrh +qoF4PacFlmo4sf2CtrqcawPMNaLjwSYTavBxubdGUS8XWFiIwGtA6neZgpu39gdP +BCT2pAWPYr5Q1AI0IUU/uGgLgUDR+IDvTqf6/Oc8pJqrbiuUpZOhY/AI3DfOXwnV +oqjcZ9MO+sbgaWL1ah34oMik+Hizaf9jY6Gg6htx7Y5MtjKUbOQ4SsSognoTmjdn +mCCyV4J7DdGHgR/VUkoghbU/qTN5rKqSJdNIYQsJZOj4U2EsS7uQn1ukE+arouDv +PaxNj5CyszH8+UUnjiP5VPxl+lLny0vlfYn8B1+3RNtQHrE1NC3AhGG0zhzetnTA +UHGCPkCudAhYRsfYnF0++r2eIjwst4ojWQEhLh3U8FxIEsVoXCarYvp6bt/ldkfO +BLZJMmAcZRO64umdvzTJ13A3esrnaxoy3ueZFNvUtPbRZUfxS17tk+vmkPAKgGSg +JZj5lV+5240xqCT9sebEKQasb0idjeDTkDyOL1J7k07eSPrn7zRd2u/st2FqvRTI +nImshMgENidTWbSi521415tdtxbVsRZhelHi9RkhlFPrJ8lfdu31tQizIm94lMd8 +LcgEM82AjktEp1f9tdHXk/tVM1S2O7acH0d3R6aoCb226xT5Q8lzRleFwXXZnUKd +ZHPg+aKAUszd2jux4LDCxg== +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +l8pSZBuUsKv4mAjlYxaEkiVDG+rJC2E24ChAvazlVAUEO33jqkTqU9mRgJBkqPoX +NHPGUDldGPqKjTPawC+OSftjFiM8lMJzjAkfksW+XarV7lA5cu+qu7v2XbxDukoK ++uhYE4/EAf/rzRsh5USNikDLA+f31pWUZVpinXRjhv/X5UQe+9w9Hm77jKdn2Uwx +V0emfy78QX+lPds+RYQJOL/zv1iBbf5zGLRrdNyKznh5Q4hQem73AFfkn91wDKYZ +OzN+WxeSeYfSzmJ3fSs83IeIOJNsgFhF5z9clPfWlGUh0CkmBV+8OGu+/3+pOfhv +DiIQj8Jx3VxwINYa+WqsqA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 42304 ) +`pragma protect data_block +qQ6LZII2teZC7M9biVeS/s4BIfyoFyRdHbSsz1i5I2cIYWMRQg9JIUFh5wFo2gYh +nryE1wWICKrHtjOOxAiWfek6kWGep5CdYiN1IPqiWeIBBWJUfZYj1dFWY94iuPr7 +MhhvWzhoreki2JUlutxW3U78BDfBycv4rcaMTHa2U+QjeB0x4RkPpQdVKevm/E4D +QrlKM+EY8H2MbzJkMUp+qQQ1ZRiPAawwv1NWKqHY+U2uTht08ekD/MXrUk+fT381 +mqLnzFuMgy8NnSBG3V6lGw+R9YQrjZnNT7aCVsApWTSmCu/lcXOT6IXL/K5+I30d +zkc2/4HOFETY/LSl5yg1dpOKLBgWDME9RuUZCr4xVDdVSTDwsfwQGY2X4echNYyu +6sYJoAxJAK35veIbYcfjsYPgqs0pcQPtywGCPZD37hbj83ZckadcFMzOTh+DTBUZ +2gc/SzeSmb04Wy7EADxsxmnK3ykiGx7n128hDcUyF/9kMQfZXmJniQPXxKYxwqcN +22I7vpOQ6TGu9JLXo1JS1sSsmLNntDrhfERlUn9Ibk/iOYwnaZEFvhcK34WuJKki +aGnd02EZe+xAz/zqi3sCmAL6XKddckG/zrK6lfpjQBKwEE58Xd7Osl5TTTrbkQAr +vxulzMo0LgaEzg1j9pc02oHnqgVglM9ev1DOWMWGZn30kUgd6D9tw+8OCFSDd++3 +rmC4SqJNzsAc88sGvTxlNFMUJsnQfPlK/oJ9yUrTh/2TkLhr42qqfT/7u5o8bPDP +jojX2ey2fXIVTTYOCvS0w29e7HztnenwMiWhwzvcdauwpxZyYFWFXYlhI7+CMxN0 +JIB32KtSPFwg5n9fitRxxA2hlsYHo1NRFhquWoY3Gj/NfWIujSXsmTFsbNfRxx16 +SqoTkcGp2X3+ALQRIEaWjC2mgrhIVTkxeS22VpBzXfZjWvdzudqOP5ksceTgphE6 +b3mE8coDLrtaiMtfBPc52ONAO1Q4snxHoFXmZTD+BtL8bVA0AN1Gy5G+5EQn/x03 +UfhORbTVXeGK0rusj0J38+cFSvcd7OhKevfMvYekSfUVlzfPGVKu/RZ7tOeMJiBd +0jfEYla8qMz1xIJHdCqDAUFr86ca3hR18RgQHQ6E5rYVIQm7ZSd0Qy+QQiwwzA12 +GkcoQ8KkJrpLNvm7qp6Supitk3IuQErxUmw5t7xYCW10aEhzkpdv+r60BC3KuCMv +fTNBODtxYFLEaWW0UnD4JIhNISV2jcGc6sHXWOyg+8otpEpryMtyEKGM84cNEOot +AKvjYj2UE1auOOPPH2rQUMcoKQrT6N+zTFDEyujCG5tMIaIo3pPmuL745KCgLrbO +J91oicPbOAcvpYQTGzoLL+WpnsB/RZeEyRdVSpAk7FZugCS0CYqbo0qM+Vm25uS8 +IKyUlR6qSoJMaHCLvbXXOkCnrdEIuMeA5syQwRJbKWfm6Xld2e1BEcWQjtwpkB/A +AW7Zcbm8vcZXcSxA3QVK0Ayt6uAks8sz8QMVcwvToO7dWOzroROsnRtzA6N9u+ke +hCpFFKw1pnN5Fs5NVRlSprAqVbL4dH5IWFKFKeJMnL9791iFGhzZPmhvfR5mOmmX +vwqyDF+cK/+S1USMIYxjs6gTattAulHhwyYpHf7jvtdJsGzQ+WubGbCmEvjp5qaT +ZuL5+y7gcFX0d0MYjy5WJj57s6bvQ4pkN4Od8HNT7ZOnt6YIxcxu4q+T6vqAc4EA +cpjL0/TtcPoCtBTjr0QquXethL+Xj4yN7vjSzBeqT6na76PSHlgzLMbf3GWBQNFk +yQKOIhybyNJguc6UhWlFCiXvaZtRJFILfx+Ks65BwLdhvjJlNFupdV6iaW7Y7SCe +ks065N5ShAwJRgAraWJWSqs7rjh/OlHsLgxy76Zskp8AbKluTQhWrxjOPDOKUYCf +bxT+XZ+hzy0evmNQ5iuu54V1WBcKiruo747uCplcOY2kQ7tdoKRHvMgYZX/0nXDp +zOkIy4w0l4rRtxms4YAlqj/0lzrdRgXHu+beG3TOe7dNvPc9BMIKpZj0BYjvfoUl +Os1HxKgYQ70vmFHe0hNsBCnicCsR0wrscMIpCBKLXqjITunV/t7k8ZefiuX6HFLU +afnq2/1gxJNIzB6Pbjg8Oeo7R8BovoJwYvtDGiexh8tApMAGrgkHM+a/Z+BlEe62 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+Z2DCoIBBwUX3XLh4CuZF79QZUphP1OG3IPg8U/Jat4LbuTfVnZMre61y2FsIR1cE +iyCGOzKUevybI2DFU/tF7Luy6S7J+9kXivnQCWtMrecfJzw5gu9f3s4mcb1K0bsH +Ua69Z0r6FAKlIkzzNaWg/ZsYscx5/zYBlzrweCH3dwcsDysE10mVjxGtwu2CNIn4 +bJp0CmQVsVMi35qSaQpTXL34HjsW62saWnkNmqc5WgGTx4yII/tO89iabkuec6NE +blHhRvn/ZP8D2PbmKX5P4rObyOOy1IL8DuKzleofyj8X0bQa8CCAKVvQVYT/gKpe +PMWnhe4LYj3eKcpIcHzcIMg5dEPeaBssaw1DryqcxWTES3sHpedG1w5rWUA2uPcJ +fdlRLtnVTZPXtes4PwpysIPrmzzufEor5OroVe9hfQ9im2/78KhI4YnBNG8WSUMf +HLnOhP28RVlb01Er5SNeFxp6X8sXV/ZFtzoIgl67Ha+2BtySCEs+cJ35YZAm8hfC +Fypkhtw8BkFDdJ4xqCCQa0oCTKK7bvGpK0551PB4yaPKzWEhOY6G+v4I0rkxvZ9F +OFRppwfiPKX08ZFDnMxP8yZZ9q7YkiOfxjrTntnmXkvnxCwrmofxCxu/c4zch2r6 +BeVr//bMhQ+EijV0eqvldt3BebFaBT6N69unpyj8nq/ALSCcISx1Wdk8YfgZt8/l +ATsuFiRRYiYSRUvJqPNwFj3wrJMRi4DR5CCDm/Kh8B2Lii4Fe5OOR7dVLEBeBDKV +Zm9a2Hjbr6CXNuFIrjZSCS96QOIO8mZ/+HPDCYyV2M5wlQ1B1VGYLKQ/8hCOUln2 +hsSiLjGbF8DpBWH8p/PqY0vxrD4Tf5lOwtVcpSPleW/yjMZJZFgbI+jsteL4v62k +3zC13lVTJmjzuPgVwsvG/YRGwqCJkCs2O6oP55vp5qFayYD6fiOtJr46e4JHHkj+ +Oj/W5CkDUngBsJelV6xnQYh/ldmJdMIUV+eSEwqHPYuAl8PqOw6w0gwukwr3Sh3q +RA5GoidObmZKJBd/ip61yUPwxjuHC4qgwTETxjlnGdHmwf8Ys/4dpjEtrY29hHLt +zbwP1NjdbYCUCy1kl/WLc9rYenJ+8ZNT6ezTd8SbEvSisWGIbIZgdA2n66gbn+i0 +pogCJRtLTglHL7aWST64bPI2zIZ0Z7OhZ0pHSHt3iBV1rwj6Lbn2Hq9bbmhOIibE +hhyHcThyJYdnWfYxaVNMyG+j206k9Q/Mhq8B7ZRvjN9DoGTnKPk69BWVoVLJr21M +0D1NoLC32I3P3iIUtLQDXtpOBpvle4DfYZUA3b/RGa48opRNnhbiAOLr1QdsQWCv +jCu70c85SFzhuDwzMuCfFVj6AJ73lBgnXIfi7twihnWw+Fnit0SfEspYXwawG8MQ ++tA14oerWdyR8zJfVs7ojnH11O1rR7gd21fad8ysxU4D6Vvastg30+XWUDpZ8FPR +bSW714OKlfkUJcv3t5GHwprizK/jpEWRd2CiILQXTUjD10zVaPl7HvsbC/jLg63t +dHfjRLq3kEjPNqdreqkvXlJI+6BMHo6nxecILT0mrayu/avwigYlFcc/YnMiACXR +zd67IL2r6syblSg3mJ9hqcPjYe3fuBn05Fmnn6kx3z36ZRIk3gStUh7s5IxEIAso +H9CN+2cBfGa43IEFH36wPON7ySe0ethWtSr71vA/LYNWfrOOuS+UytSIiJv7PdSU +ryNYYi7+AoCLVUCr5hPsmNktrzp7YdzAz+9A3Ffep9OsekbgSOm0kFlI5gvxbrKE +vDxY2S3kjNkU3fQwdXV2YEj+gmtzMVAxWWZfcdLy1s8mojHqEDEizq71VutmlxEd +Aas5PpIBzqXqK/13Sq9PPHHWJeoaPv6iPdhjN93ixu2KWAbBYdNt9YbyVarEGayr +imQpWYNbnMhPRNXtVil13XXzZl/PUHBcKQSg9hGEn8uPPqQvcjwfCVX5MD0qu6H9 +cvuSTqi9aNlHfyNDOm0r05dtkVRstXoWbjXRrI8FdUMqP6yHrprHKF/a9WgqMcpx +qMpzkpvd//ZEjKMPoTicFo6rulap2/gHww5p3r6djDcNFfmGqB6RGwD9o12B2+71 +7OjC2+Z7Ai7T+CmfOuStooBVgfxuybBA/trKV7rVww3KetP+KltippsiMOukOhAU +2Jo0TBtYcAFFvZlVh4QgW47ATVcRCpqpqDMNMy2Wn3nnahQ8d7Q0IV9XXZZiD/0W +7ioaIclYcAI1WFspHWROoAzjOFYr6n01a5RoIm6rRVuZ9Ao/RXDyemlqVrdskeAd +6iq/aAnOrcpFtwKqFf5CHHp0OJmYB4LrI6ZImtwWpLGYW7Hg0Z32VG2rg1AUrI5/ +2L7DtE7dWHkPk6WSylj1ZQ== +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +T3JVVv4olTqmMR7B97zmjDKAAUqT1HR3dA4mr7nZg7imRVPYr+xDs+3/lhQy92FC +czhXcdpkyt1b33Rs5P083o4weI51X3sRyi3HEkwCUu1XaupRk6Sw6k0Y36TQtWFJ +tUgv8wnSw1+0UdCO2a87/+reXVlx8SyGA8iDp48yhsqPZMA+RPnemFIyVfrmY6RK +MSstWf9ubliJLYM7oRKCEJzl2BQhLR2vQlKzYLAL5JvvsA11Syrps3oZMNq3TQy4 +HNGfGBSOgs26G/gi0Rdm6hP/gylYErMpf2WA72ULhWtBnZnyNGg9+l2l9kwdrWJE +G+hqYrrJLNDYKubNop7Lug== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 13344 ) +`pragma protect data_block +UfeheRgBRxdnaqiFTvEeC0Q/KuH9TVOzWZxM4U24sjhn2RQRPREHerSOK/3qaI+x +rfDb0OaF4D3GaMmC4S41VrXRwQmIRu52ShkWonVwf2z3h4z3BDOk7s17R8tzX7l+ +imJotpd8E+lOr30U0BIWTBbWIT4aZJ2hUMAxkCa6/g0otZNqObQenri5RJhQvnGA +HjVhegbZQdLVWuGH8Y85Vgi/+IJ9k04gvp8SpV+dgp4DF+bTcVVqMbz8CCC31kTD +210mJOvXnxhbyhikFen55GPZzqrg65Lu6Hj6zEidaqJNKcml9lmq3bajxYmcezEz +8yvSkxpytQMgHTgZl1oHypPxovxUd+l1rD5zJShPIXMnY2jybKvXS8l7l0B1EF8U +IKZnzYJPNb6HEQ81PxXaD5CexMQqth1iJXDbUuuA+sujmc93z0Rj1aByZAEf59Ms +9uQhUHBFCMEpHndl26JaBW8z3ApFpWVRfo66UwvQ/PUCvZcNv2GVKEm9wsO2yjPf +ZNuEK+NAAxP2vWruAuu5wW4pqk+Qhp0z68wgv9yI4j+KVwXs5weTTyWJsh5j8XAs +iYNYd5OaR17O2IEfKQ/XDSZlJzGjQt68XkM+VzHnULQ+jz3dxFCqL2uysExdEl+m +nj3uY4mSrPTrSPHVIrPqikhVtWfJ3QG+wGlbKbhKt6Glre3gJl6tw1HA/qY4ZB3w +YtmIrA0hx/zWKWAkJ8hrhegk2BWKj4NKtGfgu52HcOvZ1oENtJjSqI3YMyqZkKd2 +MZC7VtCAPqjuXBfPwJN5WYM8b2586IXgx1GFMQ5HCUzau39L4jxkPKVZkVqbE+IX +yDuzNa+TTlOCKiGnTLYNcsx7UFwc/Yv/jQdRXZmxL1VRSBNJEDJP4HR2jwA93Kwc +p5t320sj/7hVJiujQTQJChZhJYRjCGPZ/rh2dBTCGB0oRqSFbQTM/0OuaHrNcKke +OF1XwTBuV9BkhPwWGNK6QI1f1ulz04qxZe8YI/kHDgvqOzDtqiIH8kC3CVqU8L6y +QaDNWc94W6461Gq19w5tWWdvaBUon1Hfo8sdVP3mM08XOqNb7DSbDxPPSQIIvtqq +IlcVs6UWz7Kkp4wCy8J/sGMHDBi9vIoxk61pv79Hgo8fxhe7swnk2MBaHgRhPWI9 +MgZPOt08DEPbQS3hYX0MJ4MSoHh/zUQ5xrPdzz+JHiN76CrATpfTI87lY4ARbw3x +8TpW7HhRQtea+sjBb5QXh9Yr+ZPXQtTZmVczMZ3mpR3WC9GQLbinGdyYGM3SUEYz +pbU0f5B9teKsPQNJXJ8Y9TTG3zbC34aHnD+g2Ep+L3pG4l5ooRwfWCm0hKjRNblt +R+/5xE9hp/OmLB5wFp0Eiid4P1DuH7oojKrDpw6J1rJzJQfRIjc0B56lVw+/5t9L +Igsp6utF7TN9fNe1/T2A5zyYjt0bE/75pzacvTe/eeMpkgoQWWmzWd4/hFlhW57a +YAfG9eyIW+cAvyn4BYCEfDiXOFXBhGCfjPeDSvWZEfsAxx1hDcu4I73RjKh9JBvM +Cx05eWJzBlpo1e0A1SHLucd535MWvd8WcelDI+F5t9CpPykwNLGUxsSEmzmg8mNC +pSMLE++Gb6K5b4Rr89/vvavX639U8/4TDPVdlCZ9BNiTGiIPn8rFCKhu7l57I3MJ +TqIC0ktGVcbyHMCrQSzUNcaKRdLZPimq0/tUImFW/WPPzXnxibjE1W73cFbTixpd +2kX+cwGfQATGdpN0sNyRPxGQMYbptdeXGB0mFwKFE+3FiY4VQXNVtugYvDS7hHqQ +BEtUqbERIcNZ/rXKBCO14NcdU6ZjBvGG5Ejzidrzesjg1+9bswF9O1qLPftKR22S +1SUti6ef8ZDrAp+iBRrwOnTbo7xotdqeVDrTLQLXLnk3RNKX0aXzFAUGcf2ByLUe +RUHxiIlYeKCHZgoakR5Fo6JftG+2OJ+R8HA86fygLlQZsCJTB3gUdn3SwuxM4/Oa +sETP8If/9bkAv6IEUIY4EhTR6iQOVfe6wCLaNn6V74XSOWkVFtl179M8SxS41AFn +l/i3mCxCQeR1+bQJVOtvXq1o9wpxJf4qm62D1/a4sMDnXaVXgemMrbGfwnKpB+wl +j8cUf9lHJKGJX91RFQbA00vBHf/Piotl+urWuwf1tUFY7kAHFKy3r3AmjKW2XpOY +dQfAqh0D3pAUovMmlPWhrlesXeRaJ/JRcAA2UqO4r5+UFdNmPzaNjM6uUakjmaxQ +fRZGzF8RFz+ZSy5KGQyXRmc2O/twrKvfRlDPPwbAqijQqiLDG8DdzOxvvnBxdp8F +tByinA4/3jpoeAhESfMGUF1upkLaWAbuU0U+dpDudMxHXhVHiV1/NCyPxGsvp6SG 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+vPHSOFdwU+WJ2rBrR78kV5Hdx+QcmbRMIOaVytbvWGGumu/Susso8EUUlSha7lVv +iQCG3yYU/UwWojBb20kEO7ZtySUgTE1GeX7GnsDomVg88bAxwweNiA6ajGDE31KA ++sthyYTjFc8BFGJMvZNP3Myk2LA6xBE7fGawPqaQaA7KLkUNu/eUwXg/3YAwgHEL +q854mENUOoVigUL80r7cIwhaMYdhNnrfFL7dbhLrIkAHx3Y80GitH0A04fQGYgJa +mRhpLpJrag4s8Defe8rLwxBIupfTS9+rWQXY5JBdVUFyO11GnEWGogFvvGR/7ATu +EpFMXh2f8JljpqrNl3CLFojZEx6kEhBFDmJV5yCGR3ceHMCD33uu02S9fuTmuQz0 +Uyr9Q/5xAbctKJzjbsbT1fv4y69259A4sRYw/PtWsJUdeH3U8rjEeQIw3yOkQi5s +KO3rqLh22T1mYp5ozTH7cTsz29xPYiEixqUZZE/NRVIuGP+k/NKd4WQdtuCfwyDn +O/QbxsdFpr36SF30z4C4EXOxSPWf+Skfn5c3Gqf5pjYcsE6rJgisDzYpppiq5x6c +iMfcxuAKmI1vAgrM6vKwN13j58icozNHRLjpmrSgq0UcAkvShLy2fQgsgSnE/Zkj +9bJ39ZYmx/WYeTOU66n5n/RXxXVVwm4A1j9AyuG+xoeIt6GDTRroDMZArIyvtCUO +Mduj6RjgxY0Ju1F596J2v9l0Auiwdwq6g/iNXz/J2IwZL/j0pMxVc6W11Zk1t1Xi +S7fW3xD/KFWvNPDeb0+wP6tLLaZp4vBnlckmkh2r49/+6glg1GvPsCK0zdseKbQZ +CpvUnz9gRxONxasd8iDMx4XP+cZU/qt24Yf1N7jT+SRhnVBpNw8hD2ARxNHUY5b9 +4EjQoZcw3C6NYSpZzbqqqUtftIhJAeewARw+Q5c+BBLtGTuUd7RagbKBSOouSNX1 +259lwPs2AJiCss77mpd3sJxhXrGBDGaSb5DNpftM3UAmMsWaY1vowGwkulWJmP86 +jp2VbN9GCK4IoGSO6iVNb7o+x7w+cwaOBfFXFg4LVUGLbqT/LSi0O4+y2mTPoZi1 +SruCYP5KmzAqToixBjl5l8vrDUB/paxNnDSOCp3nlPW6B7572K2DNCEYUpEreYAW +iKuOiiM9a/ikJau1sCFhL9PJ65WqdLWeMSH/6jf7peNsv2lK35ucMksieRK2jfHc +NWdrGetAMlcB2rVu0xiERh87SWP8ArnjLJomTpMV6aKuTB3gxhUkExfWbUQDQtA5 +EYCy+NPSfAPaLVSu6c/WsnFW+VwydK60bL+kZI/Lw+uRAGwF1RW05jYpAREDhvWm +C2sVIAXnjZ6bAHaLVt5WpJSmhoFoIrXOvX/2f22cdUcPxmi5r3N+am35jyICj7TZ ++foK8hpnT4uQF5gqaMw2UYhNNDribdOn8W4e1CL6p8ubP42dgvvPECvWRI8/jIhT +bHWKZAMhjeBxSBCiFi3GczMfg82lcwFBNrHUDrHBWhqwjlk5SRmgsDgnGmDBaRdn +OhaJ8qX8XkUMEXsUaTDC3VeXK6Vcw41JaOG5pgCceRjsGE3KOM9SJkOt8gl3qjV2 +4f8PfPgRSCkcOdRDkiDIQh9TDg4CK3Rkb8wYVziLfZHgbdLVrlJ5PM2lp4OGvArm +bU9dk4oCzdHAoEIys79FsuDVOLSdBJP24p3MQLLZN6P2XNSZ0WcL6ejN6XxGk+2N +aR6iwBUPpta4J7LNXNMeH4iEFgj/IfbtHg70zFk5ju0gt5AUyKRZz0wYHm6u13Ui +okhzQUM2WzLAsdXyYehTUxz2LJhJSYDg0r+d1TPTrXauzh/p6vMwZlh5ucaHAPuH +MqIJIgobWRKECbX0m3m4cLyNU8CBb+4H+26eIskpaShxtGpbWCSBjVNA6faG+lB9 +LdONLxhGhir1KpFPgt/O9N0FT37KiW4zHFroj1G8fHAmaAe/jLKCLb6j44P9psF8 +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +Lz6FbX/pVyGiIjjEfPgmiw9+t39Y8KY/9do6W/TSCEeKEEctN2g6bJQE8v5nII51 +HQbGd/vhbqxxBCE+F7odeXY2yLF1W+2PypPquLqJYyk7NUpJl/WduF/X7kY6MeYK +Pk/pHOnHR5bHZpq4LdjlBHexIla4ytk1fbeAUNpGqFXfdxUKHuhg11fsCHtiL9Dq +e1yEAbHO7lBU/2M6Qm7hP579EJ0mRY+Ig1KTH78gvnGxybc7j7db0iL8puxUVdPP +onAP5LlxeZuF4UycDVI368UfvPX6c7VtYauZ3+gl64CbFKm4PNUwhsB5RV8Vh/Jy +YgUU6BkJ4rwDsAJ9lWzKTg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1312 ) +`pragma protect data_block +Nu8my/ZeIqCKlm3k1LIhDfNqSTp8cd3KJe/bSS0MRXyvIthmdoUEvoeqsfQOFVfD +pp2eufeN3GoCh7J+3r+Phu01vJQLR8Xj6d1wgx5lyrvjCOUmFvFFalaBgF+3uAxT +A8NiL81w4ArWYfTqfTtii2tDTvcptbZSgg7pBn4ylCLXwufQOJfvBLB0Bk8cG5wv +sXg2J3jZyB0MrvgS2aXEE/bN2JWct+PKBKNfUUlbYEJmBe7gw3VUPrBto9CLOHX5 +nMPOUKtz4xRZDz8X6YB/FmBQjGMfR8Mxn/2IeGbmZG1jK6vKjjSIfoz9sPybFavN +V/vmHsbaTqB7PJLQZuW/Nk/v8ghiZ/WTOiljvFdHiDbUpLL7O/DBnNiHNZrIKqRS +xKp0D/r+mFHW9Y8qeD0YAFMfTe5ikm9fd/BQacaCJVt9T3I9ls/TF5vhS5INrLMj +TMW7Me8IpXpfzrxVHdSvuSScdayADuCD241qJ9XSStRV16lXAZsOPUYG58D8dPg/ +mbQaWZ2bUBKEUDilERYH/PUxcScQUFgRuP5GamoUxzCbKo/LzMFG+sYYtLHn836z +FjHPD8lkfHlbl9mgHF4VVJQw/Rs0Qv69p7xpGLFtOU9bV1y01u0vXio9VsggoKUn +/caeofCscxAH/MOVM4qTcB9cjPQavBQ0pjmsLKpR4C+GWaFRvRs30H2VKUxSUmRo +77yhZZGA5j4kgb3WsTVlsMfH2tPhoooQqfbSbFnDGMNg1SAmwfRv8NPOLDF4Kr0j +0JGbxMmioiKfQaHZBjj85xUhl+ro2mepDdna1r1zgyK/Zjr3DHJuvE8wTukFernn +JGeGkSkcV5kO9WR+DYc6Mec+osrCWn3D5EI+fzUKSgGRJjy/mYecaY8SQ4k5McYX +0GIQoHqm6Quv0auLsYnoi/9m+NV/lwaEMP2TMJ/rOVLXlY8sXy8VU5/bD/QVc4L0 +0W0wdxYz9G7gdh2HxLIRIhzq85ig6azxlLndlLJweSmcf9OxT9eA6GxAAjw9Mx6c +PfPz8iYqjG261x7sxJOwH0RkRouIXOmzKNVB16BfaJuXZjHZH02Fw0LCxbT/pbVv ++jbFg+TtbMv3guRyAMcLNwbUVe+8UBEYeaN6uc5pQUfTMtRoHbE80j8NY/jpbudU +m7ApSKt5ICdBSZ/wCHKTA+Re//Cz2BOJ/8u3ltlL8CVRrJ1Y7F8AGVHRpNuX+aXR +nKnpMJfEZw9z/6m8EkLWOa1fiuGYQHg/PLDRPiokyTMWzKbZSzZjmLoZs2dSs97V +X3MgZ1M8JYK/yBEFrnqjFp0I+cMuLaoPVk8Md/yglRpWDeH/rtRUSLZOOvPAYviX +yUceuOLEJcCTs6/lZt6zd79nj7gTp7x6t0kdxyYOP01LjRy7MmQOYaSj2ivIzRIZ +dLlQPtincVC2IuAfhrkLrZHUWk+M6eJy4FSI2FnB/4JZydYWbFgmJcKP46SV4/Sv +zh5cYPsnhA10nthWftm7tqucJ92upyvJUUh4IniyzEMuOWtAdv3I72mCd4e91SRo +su1u1tF6rXt2Y9nU/xZV5cX+xe8V/+tzX0OgsQXyp5nSNY+Sj0fXKJGJ6hw/EUoP +pJqW+FV2bVzlf5V2CS+ztVOS+tV1R3u6k5YtJJYY5qydjUfnZQsl2EhXxK3f5C69 +Dk0JiYoUCdkDWyWI9q+XIYEH0mKzhCDcKA2QDwTcULObaug3TwQW8wV7oDWL4O8b +ojats1eBZvP5jP8UkR9o5w== +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +TTxOuiZPb3z5XXLY5O7KZo9Sci79nGV1/MfaMohoe0ccAJaqk1GLzchKYcHE/uM8 +mq+Lgt+Lq5ExtX3mWQnmAaV5bf2YjuSduyCMYjYr/WfeFQBrvYNKJLOCq59+YxLz +R1Ad/3JrTQChewzV7VLmOrTi4b6Bi+rDUv/eCPyQZ3m2f4PErw7ca6P7QWDC58DQ +xpUxlnB0Do5YE6IOORhfzH2J+kWMIsNbu5b5aZ6GQN6SQfJD01HlPvwLe/Qd3aVe +PSqjzgzb2QHjnBWsZPDaphU2PQu357OnnEpf3tDzZxPLGgdN4cAJCd98mmfu6wAI +dGHx48AfKfxh4sbfr2V0bA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1024 ) +`pragma protect data_block +fJNRvOMBPIBRM0scZqncFSaKb9GwamqRassaxCczcSmNF8lcC+CosRzsWGqDDmoh +V3WvSyIsxrrqzsK405YwAg8C9eKJaCdieD9xRWROdJaM8lW4+KOdCYRRwSfNmPwb +Frh1AHi3c/YSX6Zp1iEyyQoiZlnCOgvfrQTUYSZjRMFqklJnLqQpBZOLRkw5X6JF +P/K0VFKoc2rsqnlDPvAzO2+mWAlcnec1pYEM1RElbmT7UpF31swFtOUruI/xU5Gx +y+Nc/Tz4c2rF45s1N8IydbP1VI8IyEzJ0efHLlujJ43Z2Yc9syMX0bzDX+rXHSFA +d+zaFPINa3yszIawwhLSqQlS2oDFwi/oRL1a/xBQiMHn6Bx1ldYGW579tQpqmY+T +dHHBJsV5UwMUv3mujvW2HF9J7XnIZUah3GG86n2VXJdZRMnYeA4ZZxfZdYlBccHV +3rAduoBxGe3tof66Pv9gMhN5pMe+w8a3njKo/CwLLCwK0WUMCphlGGoanAmvtGZf +tRu3d6q4eW1ACzG+qPfSsQK3ngH0Ts998DWee1VntgJr2h30KqUIJooJ0fwGIa8k +ILZKXUR0msmcyh1ti8Di7FlsiuPodnRaUCgXxVirmYalnCYT8kGASRzJYW7OzkHQ +xTZsFbSTactBcHjpvFZSv/qSK3BXR2BMGQtRmTUhVft+O1sLoycki1yTwjoFU2zg +JuenKFxnJmUl1Ac8R78Ikx2Fbn0EEFA4UEHoYRDm9mRwsdFpNEwf/WoZmA6CVYgh +pw/2DFRbirJYlv+QDz4E7xr4srHJfkbnUGr5T8kS6PTt90zGl7U3dvynTPMIAyz4 +GyAar2RCSSQKRe5qlWfVwZ2KIrtRWljAvHrq3KOcvll2vzKP9/Xfceqarm9UrydI +41HrB9c4GR5rkIjau5iSSkL7xo1VdUOqfc+l76NataG0KaZhSLL/UGhEfxw9j3qD +ebumDLu85CVO+eeB+xpMUOp1kG9jCIuUWlc2QJY2PSatE4vf7d9WZv3MjE+dCWna +9Zt9YawSS4nXGo5Fh1U3/KEdkMVIwZzEEq+48YTFNaEwxjeMmkWNB3LA7tB4aq2x +dyRdJRzn2ZFnpi+e+5sh1zyUUb/VtKgp67mGY7QYiD8s0Ld16MyjVFbg/8cJ217m +jwOaR8MzRR0YANi2hOfeKppvM2Ev1+fEM1Lce5AdoSSEcNuW2Mq1DJg7QL5TT+m6 +Uu+6EuhTWF8eArIXCX/MGms+//DSUYcn3+fjKqnyoiPMAeN4fN7X0qvfDFnuI5wB +P9IQQZrLuaA2YQbnaMCA5JrlclN/C/hGHQhh1VFOEB648lSTs/nnRr7kaMDRpVmx +xGA1BK7JL3oGZnE4JdvgSw== +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +nkhAcPFy5CVC81K2XeH27Rc3XAcv7GTNij0DpNy/tGyGNqkfm8/I1LfCR4iJsPE8 +U6wXF59KtCx1ze1dlOrt4lb/rddSlMcjclAf/22Pk/Ic3DCXCY0Ma9YAKx/HDotN +1dAaTDyDrmMf0i4h8jArjVEkdRRMYvXcwIYMQLgdoUxnytiSl/z/kA+HNl9nfVla +F0F/7dY9wlvF2XLOT6OONbt4VXzzSKlXn8yTOKl5QXjp7NZg+R6xKHy8uv95jz7W +GAMfUNRgH0a3b/wnyq6xyxtaUxFg4EqRSmIB3/vuUWN6CTQhUgnUCMIr4vYn5G/S +ow6ZCwubW4TjcOE5DpOfdA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 17296 ) +`pragma protect data_block +Hdm6Faz9e16HFoSKmVivS8fV05dlV+LAzpIs6QDXyT9Y0Qi5oHgeb9r+PINXpgZo +KKUvkxr0RGfRoWE1tmxx1AXjU4aujlITqfm8eUr5YnHni6ny4wLXbYJemzd4Im/j +xoyaeleBgWEciGAYXNXIOVWi/ULg1ADkemz4F9opZrFpeT0xfPmSiVux9EalFf3s +J5MgOhOa5F3orX1Tc77ZKLMWc5DSJ5usMhkEz/xlR8NpzRdsMugaToGEWz8kki6G +zCjIppz9+iSbc63Sst0osVlQ8dkJVK+31yiiWwyufq73nsbKbEHtSOr6BLpgFSyE +QnnMyRVld0OnanTgECcKVbmcH/IU0Wqs/t5f8je7ccAfsZhILP49aQfocO7uPff1 +vQk7Xq1LPp3xWZuJ2SILGg2qzr8uOnZ6yFL+by/Xfw53vKIYNcedWOJTMx4OYjT7 +Xa2Qsy7qMs7gv1U2YGPW6Gm4f+b5C7wT9OGZnERTLX1cCqdE30tC8J1oMGJx84qF +xuNpnRv4xLSoSYdH73xu28yh1y/LAq573bwdjfxYG0+lpt6bPFiJiOT0HyRm/Cdc +gdaV47Ou/SP8/Z4LJQWaQy0D21AeVrT8WbxHBxy9+5pv8ogp0f+hQdp7+NPNuNMa +e5S78E62uhfaietO4AGAZTrN12usLW3OhT6O5p9Pfik4APPFyLJUd/TWqlzNy/mw +OUoi4AI+3PMR/zt5yKD6twD5FzryerMVh9qZkeiHXKrrgFLotgodz58m2si+nyrp +vg+Tu3jNSvq0A3TzzW8q3mNuWLV9l5O+ib6sEOw8ccFBBgWMv8I79Uv62uJH7AGX +RldIx5M612GtsxtCya2P8o+7Ds0b+9TmvLK7obcrDqD9/wumPpIWnVdtbjSu15Gb ++4+78Wuu0GivmcG33J+A3XUqwSnSqf6IbCwxYzuCeiSmChWqdAL1Q6f47J9Yo3HT +n0nND6OW/hjkzhtsuUJlA96yRoeU2lfX+Y6k4OOkScrDbick6fdfSpcMaDNkpFHf +ESC80xu7N/BooRPEj1XIO4vQ1dm3wGrFQ/JvO4VSPPrfXIoUVApqEYOJUD0zTp6T +xwhboEAQ4NPPavhznP3khd0scrq0m8fkzs2Ab7aORQLseuwSoNL2ks2egcOCAA4R +uXgMDfS/DN5Fyee/nsrPScKnaiBFawPPTDJ4RtltMvY7ttmdrwqtKqIufid2Tc9q +El274rdFSSxB2pHbGgg2L2M/JzNSFhEBxGwx9vuc92KYV724m/9Lp8qIvYsmDQ/D +YUIG0gYxeHLMHiGZjTdFQsvGGQ3D/pWLltTe0qmpedymXZyfs88oIygeMH299UJe +QsqZE+JHMLHPzueZDfNwCJVLRsWQMrKcKW/BNPqz3sCiNG+zCQBwoFJ1JLo5pAVd +q085F+QC98XvrqI1oiTv4fn2/4XZDljuQ3BN3ptVO5i2Iqkd8EdU+BFksCQJ5VZh +O9PAnZmtq+ak+AIVqwv7KQEDF3lYTQf2mY+0mWHVo/1uG7uOqiKVlDmZaGt7mNSn +AqA0vrN3NtwAIdslnA6IGbkBOjHi0NB0V0Rb2fDBf3CPgVOIRohgRzNt4/j10wBG +F9LyAUcXUMHnYwJ8PJecMoEfvPhMrQIznBBt81kNWNwxwUKjPQdNM4WNxon5Rgrc +Wl/CfwI3BJeMgs3o0OzWlZzeKBBGXDVrltQYL7M38PKo13VZ/LIR5oAjzRr4BrTq +bCHCaDU5OXlXQVwct4fj/mZIq+MxUWN7lDZvOEFbf/S1313YynEuf4vJTPfmhIe/ +Nl3fkMfM1nX3wZUNmPGf2Hw8KhMAn8698LnILSlCsNE+8dyjb1GcaTTR4KDYBBTQ +gO5JxfAhX4b/Ty9rtxhRf+RXkcxHqpeMjSQBCQy40stLQTRgCsVbHtOWwfZfSlyR +FTJ8VoVaauZ/eYTHhVBFU16hHKMErZRKhPZ0iQvad0Qj528ge66J5n7v/oG/xbV+ +L09vhKuL5jjyhRncmmQiPnpWfSAl/vRek+Gv2AkE2crDujkcCxZvsMRcz+3SqAOl ++cpZ3JqjBsgiIIKVWkfBXD4BBbDROKXDXMouA/8P3mLi/ZHrbw9YLrUP6OkLEC3R +pzzCROPR2/deBg0nm1Ptf2Oj7pj2IjLF8L2zJUZAKkF/xI407kfUfUQG31WaSjCu +0PkGhwgojIuFBYFrPej1SZqfrZmgyWL1Rx54OlajRTrylMy/BF77z8eJApIWsoDe +fD/pSz295Cpouvrkh0H/ijJ5s7LQ8xAYk5/PG3ojyHx7uDj7hpM7OeOZFpDm1Fqy +GMG4m+5fF2Y9qFV1Bbh/0A21k9xjf2YmNZU4IpDXNrmbnH+sLDojGNwdYFhaC2YU +Xk+9fJFKfUa6PPeZyct36Zo/dGhX8zbX+LPeV0cUr3FJxq+hXKfpVVqHr+dhKufM +gWkPjjSrq2KM3CYfNSADNazT0WLg+eB+7iJtbf7AFnkRHKhltFSKJHZtJC9hAfjF +zF5grQJCFFv7gyJleq/cijbiGdOLSP1ANQuFq8BK+m1U0GHVbFS51Lc3FNOHlK60 +dAq5Zg/TH1wnvgCeyYO14aOHzwO6Z9yZqwWHhKmoCQjkTlojv+LYZTdCjeeilCGV +YuAKJ/iAyxF5vQNHxkSUODbJRkNVgoOANyMc3CEp7ji5+UWgQyTnXAEUd+1QfIaz +hFm39jg9WA93rtLyi36uGhc4J+CwneqPASelJ+TnJpbtipU+znJhNE6hUBc2uC86 ++GrOw2qhUSJ51/JwVimYcssSlpQSZa3ha63OuHf5oBQjM0E9KzUDIbTVSe3ry90Y +RaCt5Vm9CnPk/N6CjJqwMZt1QOwcB/Ed6aXATRyDYOwNdyOEx02evUMS+s7YdnNh +7nv5sOf5/YzF5xO1EDFt3UxaGlx+FjtmM733xRnGaV6s1iIwM6NVlgm1o+c7UCM/ ++RQ/N+ju6ooFAnA2MDD8CaF7XqqekOhDVxSvNWzU6SMdvGIGc0rOxCWGA+kKUzva +q8MkVh8T66BiRFGM5l01QO6Zf7yFQulCl9n8kyngC8UTh+p58na52kQzgeyTTSgI +hoG1wpqqgjGjvuoj4PHqKcIw2XLfoETsnH71a+lBOBnzfulp03FX0vQXRAxRGrY7 +H6757ORt8rNgcGdMI53C1SD2sT3q68QyV935xbzKCchXFDOzKedQnqA8dxos4rBC +wZTyqDxMeCd21pXXu9I6ERUxP0elhshoA5qyd2vIWAg8FF3Hz6t1pr95RjeX8uN+ +QKdD/bYzSxJDuu5yLXPd8TeSMt8sfowxB4n/+JUlJx929KHDm3zCqZZc77Lx3o+C +AjNN9+Fj1aPWaRYCEwUjM6zSbMNNAasfqxkU4dbYvXNn/Mc4nzXxySKnggpMtI1M +eLuDNv+42YA2EzpDoeyPHAUn+NI/waRTns0hTEHAG3Ngu/aflW+zh/RXTAnlGfpA +ugjmpYEpGtVsoW2UWMrBlZKQZUt3YObaKL2HzHLuVMstgyuhpdwvrTtKCA7sbU8M +KznMfXtyadntP/oFLXTSSJU0xn9NSNuJSsKuN4GwxRw5lSm1HhVvuCOw3khW9gCG +nDBY2uKUZhOtlIjll3Tb/R4XncJWcEU3TbVNu+PD7bC3gIP13c6b7vlQJcxt93p1 +VNE/uZiwa5wEmgEnHm6yGFQCplwajPFxgxct5Bf7LLuuzvx47WzWQlgoc1CKVkbG +Wz4ah/j+5OzPQYBT2Pt44HuMGiTx9HWwoei0tslh3mv4HjZGvhaDuHkLFtnE2/Ev +r6fpe4jkpn0NTa7LTxLb4P3MQ0E3VLQAuatNy+u3gD7BxpRhuEh1J9Cjg7BGMGbV +kUMHiyGjysFjDeFfLnrmu8fPrJAkCxnszGxa1o+ABPAAlMQlQbbehO8gk1L/Cq+5 +iV5NFSGsEdMcZV4fGW/DjWf3UEk84DyCfzgq6Xj401AQxvbWWIqh0HJ3gTvd+/EY +Ju6ppl/iNkO8EIZX3Rj1VvtNshXUhEU2dNtY/oN3CQBnfcHRInJ3BQJDwjaD/Wja +HwWbBfWDFPqrWqndJiD9GcYx6NCn9wpLrja6GwaTewbNj8m96ONsLQFbxtq4Irpc +8x9EOvtH3vZxEYTmoWtD6a0ONtvKlhOXiYTt31mPhwyh9JY5/hZhPWEMPM52n4WB +LlPXYn/BZXmdGS93XnwMJbjI9+CDID5ojJfKg+krWWS46++3cm0iH+ka0cCm3Y2J +15IHiImkWKD7eL4DzqVCzyEVGAmWtD3jA1swSUgVNbkLowkij5MDvO+0VvfMJfHz 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+Bw9TluP6D3LzVBnYRNH5CxHcH/XJRZK46yA37DXByKmc4naBcO3tDXQf120yGlhK +Id91U8U7MLMA3/D7u7No05nbzi1OxxJPWOrAWnGHrl+tV8ZE1gGBL3mkmCws6KtP +uZqQB7CrPXH0I7x7uQXus5x+bJagi/cBsllosvJisPMrzi68Ms3LirjgDhsCkaE2 +uCboBWO0ylwya45Ze37WLs89dt1hLARcWBfJEJIkqPMIRNc88mn/yDg5CQ+f7oqm +SsMHeqXQXwJZBGMFM4b9h27oaIbXHq609EAhaEkZP8kOmG/G3A/QQgld4KcVPN87 +TZPnkThZB5v8e+VVGM7XNhS65hqOlSGf+DZJCC4IdBaIDHROoYazaWS9HM/hBQnw +H8wOWnFrC4MWaG0mBxD0uQ+QWZDwqWoGFcv6WSrO9YL6tMjUKj4/i5zpj9aDcK8Q +najlHPaxFYrmd8eFI4atl5tkKauovlbhghbH/oVmNlE4jqzIPPv+6iUjo6+whOnD +plQ8PYg8UJCzE68e/KYi5aRzwIKPiO1st19mJ2tndPIXOZOQgSo562f+/GlE0TSi +zRVLMai+hPVVdGLFSx3AaNFL3zChcIP/4wtUYxZozP7Ed8/7RfdmRj1OxpnfGhW+ ++eY+QcoOElsCKruQa2LYKCKnbdSiKBxqQwZSGHZr1wvmiV4XBq02mLsHYj9s0o/O +r1ckDLwBQXQG6/e0tRko+QJXKqp2GtH8darXNEtGVk7zIa6Fp1LBgIVnjqQTv4Jd +k3KAyJ2256YXBdgVCO9xhqK0pNYBs7RcBpAwM6wj8FTIiUQ15NinhAGp4FbD/0nt +5DRM+tvEFOdN6AARAgNsKYgkyxYVPyvhZpz81qeIUquMhws8ho9L38or6+1bdBAv +jNKeKs+wYHbZS77zUX3IDJOOUGwEcpDe0z4iD5F8d5epwy/92EPBrlm8Y2a/A29Q +gKc3HI7o9NERsY5LU5GqNOPkZOggWM8CKolEz6yfMiae0BKw39OOZjM3kfwGavcL +rztEqZH8ywuxHz8eZUIi8q8bhG3dSzQngpS9pPxsvDGBtQ4o3Cl6yE0ygj0xQjxv +1CPRtktW/RZyjI9Lo7pv5MYuRaXLvRquZCF6+8oNAhTQrJvTX6apLv/Bl1ynvUKi +OzzpuOA7GD9hVKdjvuyGcxUS2T1OvRUOhBVtTdd2OZwsjparhKjzzIL3y5C041+9 +VlqAQ8sa6xqs0wdNVSOSi+PsI3JOyiJ2sq0jSS0+Me7H1+4A0ai4vqg1mlLDlXMS +mI2p/DzOaXQDRxN9ml1m31aF8wcH/2i7DZ82duiR9qtMtXE1jxs7RAiDhcyvYT5p +8wmgYJkjXGxwPRqLBPCYvKKGBOqGNdV/NUXJCf7KjrBEGBtofb70jHL9M0jYGwN0 +mZCPisKC25QKt9ZLPcRm8msR0ti2k2E2nsmGoKDkZvnNVMLdEA0u45CebRCBUqo9 +3xqLdTW94QpNI4XAu0pA9lIzRAzez2/0NJozrOuzScbX612KP41p+6Ym/smba7AM +3erST3vHpCcGvh9wgioPlKIVpC6iFgWbShmPNRAVecWPYnHwnw7LSLcOkQdvLHCm +U9UUvO5nXKBQZhfE0z/zlhL2URvV6j6y7+ZmssBdIczagHw+SLyAa9TclrlGDpgW +AEJd17gWkzAyZBowgYcvXfp+htKbv68O0mxm/iVNiF288D5SN2QgwCIs2yd8/08W +d8uIT/4YuDmVdaMwq5spcsJXYwpLzzckgBAAUlfZpduUd5XDas/ePTt71MExSc9h +okedq2hcbraL2xgf+Ml6+H0fzEgsNoyydAIacFfuzWcqa/vPLLdYSBAEp8a3mjtc +Yxp57kJH/2DExO0WaqY6sBKDgFvcNwLgJaKaQU5DyxArrqZNk/HLMAc7iKTBNYoi +/ITm9NqxLJ7iaoboVaMu313skoRTQAexCgfCbi3bHnu+09pKdqrYw6Xu5WcIg+JN +Vj0kessoTtgm44DT/jjmujG98CSvI1jG1l4RlhRe2vjMi3BZ6Uz4eF/xAwp1okhi +MRwj3HG2ymVg9IoMWnKG3DZO1KXZTTM4IwTZVuYEKcNdvZlyZ4in9c06sIeFViPq +JP1Spd7XDu3CI0s7SGstRwwcG9VB+q1PJlDuKPq3IG9hdoolGf6Gt/OaCo0UtAuo +iXFUVNFcDW1tXTqlwttSHiF5T/w3Ma9Q7Y0zRidtqU4b87/FjOHlj4S9x+c9u6x8 +WhueGU+1B6GkpkbsduV1JiaTXKCo+f5/DMJ/vxAL75SlmtrUB2rGlKNzK6Fmwupl +0n3XT3IOAN0hloJqBFOH3UyRFQjT0XVI/vPrqBLghtHguFx/eV2ADwYOnEOOkPjU +9FsRNevix+td71QaHz7yvWs8/57YXMU8YI64KITyvXu2WNJts6G0tyB/TcBAL8NV +eM99LElCOhN0M9qbaWYR+A== +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +GI9zPoGKbJfy2uLvVqFFpipF7/f2E0S5JCwnjimYOsXWBfeTRJgBk40QuB7U6ppk +RnRJbZv2OAchR7CcU493ey11kvcRu+CeNfDt8W/FwNevjEwgx6j+pAQG62JczJDr +o/PnmspeWHplQXZHafFrk5KYU72ihYx7h/trZ2z6PscwC7iwkq6yxBspn/mTNfsI ++8dxS8+L4CJWMqe4N2/a8p/cEuapk+wDl7ZL/KiR+F+DZA56sm8QfQ0Lk6Q9Qeqj +hYmgKytI9gqPfVFnHs93nZ3nXu7PLVu/OVCtpZX5R1lTa6klr+sE+NzL6Ni4yPGd +1AlzNXunjlmbzVno8FSMaA== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1824 ) +`pragma protect data_block +AXQ5Qa2OI464gGZ360Rr67vUd7TzolMvE+xgiKUVzC2VBgolXmsO1t90yfbP46dR +mh/jrH57yGnxqv8UUrBPLk0/tQadu3ezS3iYP7B7ktnIA3yhLj2dPmuUEivQgWGS +b4dwjQtWTDyGelChU66CogT4DFpaFJ32LDUqN9NOqRJYV5bILduoCjJpfBIJa4Cn +Hlz/tlSkwP3YgJJkc7yFXLgByqFqxKPaiZreu+P5ozbXvd+twLrBhF206HDosMYb +udnkVPMAEm3NIFM2W3/+jh2Pb+9NAbP/k1E+roMpISqIWGCyv0x5LIYyluqNNTTN +7t1YBLRi/tEXV9xPLl+0Uirdu2zkM9J4NnNjI4B6LgaQJyx90Fg3pELvZdQkcypk +ygl7L8ZLWnx3arcpBsWMexpBi3TbTtpS7wkwwPefAnWbI3IWGs5KJzT8ZUr8ko2s +Z6R9fKPFT6gw9tOoqkh04G7rJUqhWjfQwb3cBF42g4CdydwsqdnbBNAX+iu/umog +DbgYl8xXTu4tEiVGaeaWoU/fsskxQxN6WUp987ytSz+jSXZgqerOXbRRA4d9Fwnv +PlWzegeuPbjszIrWU6yQp4l2RhmG4zoe7UycyaCLW+6Bnrskysq077hnNLEHBFj1 +08LjWRFkaDr8KLcClHN6z0rUydt6EfeTMZhd2Ihnx79VronjC7aOq7jB91m1S+3s +iU4/5apxus6iK0sleXQZSWxkM2Ho6iqN65kd2OSDz+YnAfGP7K/GJJse0ZcI4Nz3 +5moYCZJayoxX3e/voS2oMqGaWjySs6qHcj6YHBWwtsAgwyllH9DsECMMfOWMsaDd +aHUYqLDz7jrPIbPWOoV92R1lr5oFBPU6JPv4AxngJ/Kr9/+ia+BPuKs7Lx61AboO +T/VjoctK5L4M79s3Lfy6YYS0jvFTqtZiuN7zLoME74gkSOXL0JnkuzpmiWaG+/AY +734rCDkTkiHlI7eP1wF1aREUg1+h0HcvzytBhFm4XfIkGpq+9Q+YqOEeIrahRSlJ +2ngxaIOlA6pp3242SqSaW0ihctnACi/UoxtA2HklHWNQl2WgMcWDsEqhA6n4Q5r2 +nGtDk6bbvwnjftokgIwekinx9e9T6wi1r2c5cLbIMF0DnXLwYvD6AGDqkuGg2FN1 +24my4mwnzCOVSUfr6XmE8oMo6BLParwh1fZC5zYowPRJSRXCT20L0o7uOpaAnwZr +oK0g0z6vzG3SAJlkEGQXdWw8V4ULn7ZtDYFHdRb3PAQXTOaHr8WjvSeT6DePCS8h +P3yxFBcR/mLUtA48SCUx04qH4l90Gi0taDVLC0Gu0/sBbrACFfURGqwneJ2oB4ER +fBHYiaONCWPS3EJ7btcoPjLxmebdX942OvVkjN1fDTLyY1ni81K3o5wPA0jOhGXD +U8PU+xldQjDAQFYYzJ99bnrhfKyQTxquYLUPZnqYy1d34kMC0swCLWhDGYucZqt3 ++RXetjN+bBSRknxd8O69HsJYIe814Uf9Hpc2GHUAbMaGzN9ixylh4i6qxgbCKxQk +UBgrK0xsILH75KnZP/OQLq0C+QWtHxQyOCllILP69QlRp8+EcQWnfh1F2BbnOisv +Y/pDX6rJ/qb4FvJnneIa0lzPR9NQMqyHgJrauuphCXA74HgRxvKgSBa2WpTmKEWk +wnL1Hx15qR8MqbS6kyvPww4FD7SJ2A+p61v8x9lmiK6tCsnBQZrNk/wNUWqk/jQm +BhVfPc8vFfkVdcR8+Bo2qo08qSVW8jp9ZbQ9Cr0c1QgeKm1u8T3ig3qZaevnehf6 +z7QpXCZHUY4FXSPKMUTPqPj6ETUbZi6qozi/CBKAsTG41/Ps+Wsix2X3IA0VdzwV +Azw53vScURpLzk25Hh+rm3AlOTnFQe3frjklqNekflvJ+6gHbx3xCHVqKP2RpwMB +5URU8WKvZXkso1j5oYxw51If+rOZDq7sNchOW5RJvnqY5s3FzyxtSVufn2JDLNWZ +h/EjUx3Of5U5psZAHYm6R5cN9fdkknxKN2XuuA56Nk3Kh+dS34/0w8cdRi4vgjYZ +bz5Geod3rcyu9gtNtE6qAUnaY8OT6vAkibllrQvZMbffuMOucpe0RI6ReI1mTh69 +EbN2m4fMLQyYvPWQ2xYaiatxeDG2ptL+PUF7Wcbfo4i3788cg5hO3Vug32Nv22YN +b2UIkqKqLpGGmCUI8QyrYlPzidzFMpJnIMDe02tMAOD+eV5T+o5zX/OFa1x3xKVQ +RHuTIbeWKNyN9pXUyeHaos/evAe6KkA71793lBLaIru2totmPZuqiNw0ZcWlPPgP +3yZC03I1kVMuVAcuOp9HWtTQTH5ymzpEwpzSJ9kq1rVMT/pvaRRnRa5So7Fh9xml +wjnrDkbbzTuGM7mqUEKXfmidtgnfA3bzq1I87BY/IGE6n8jHwMvBRwdEjnLdfj9k +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +FriMp8xwFwm0LMCvekNwlbVBo1AZgDrmVtXw5xoD88CNjKwH072pbhCEvnL8vRnl +vwGDwLxlRtlWQ4sJTitZ35eQEa1/sG6RQZQgx3YRT8HTCrZEOstluUKNA65H7R5F +RrDJXRVBFyM87875G2KnKbK1qciEHc7doXhzDW8cxk4WNln7mBb59Q8+4ulz7Jfb +6CzMT/u92j/YQMXR8AhnC6Pja8wdJWzpF6niWmDVnN5I/Cn5/moWgLPZcQGs5uX0 +EE61iFIk4nVjslZ2wvRuE2KADoIXbCvvM3dB0EI94cVmNvXbWccVsGk6CSLHTYe0 +AJXHTXUxbjKoGNyhUhGkLQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 41984 ) +`pragma protect data_block +JNjowIfsT2PtKwZSqh31spktaerSsONTTAwEjy3H6YNY2/rvCMy7Z1McdBBZM9K8 +4DGBOhpqLlYoul0cZLw02zLTFNumYLtIouMgePR4fj7782eYQuX7+vhemoWeIX7L +sdVpb0P+t12x4i3ph4BHmuHAwZrnfxfcz/38L0wkCzlnbT5ijPg4W5R09jbmOLRy +0U7myUXnbMhP3omnzh8cWV5MmRtg9dqQdLGCCuQlTRmffNwKhxs39uhcCVp64/oQ +7tOXWFgR4cRYs7zNCVtrBPTdDcjFO8dXSYyLqyYaEc8gmSFhSjMbzw1z7HTjJh74 +oHL/YUcqEVI3ZF87eh65KzwOXdsk4ni/hdI74CKS8vL+NCKafK7VhzfX7D45sRAU +8nzN4Kapit2hNwrpMmX5krUcziv2tBVteJ/fO6nRqU8RAHfZHITh+a9xH/KpZ57a +7uodaE7uM81gvcnvCy7PQ/2m4Pj1ej0n0yCOO22Gg1iuP8AIx4hzryQce4UbqR49 +M6FCFKhwl7SIG/GH1B3ZZ0j3mP3Lt4WIyTYh6Lhlz7H8x3wrQ0MYECsChRbr4ky5 +SCoCCUnT11N5btkcj+nrQEu//OACUjkYt4qJUZe8gO7llGR9eG/T12cnh/g+iN4R +do02kRKWo6Tde5fRM19uRHvtXHlH2IIIt6tQh0ceJQzX8HADIPgAASHdHCluRYnK +Nq34VVJ1roK4pK69ecqvfeymIPqCay1NCYUs+JlZcG2S3O0yZfGcNT37m0caga4S +Aao77wX6RlHdl5zBgSpiXZYqO2K+bL8XUUgzFVOu8Rd/eoK/PEagQBbrD6P1cauq +v1ZEAGpPeDm3zBbgz1Ukxa7sGohJlvjzr3MVChXdYQ2x0Wi5tmqSBUaiHLA+qtL9 +l13WeEXGsvgaI6X1MHzbOv/BC50PvHB0hMum5fzYgQoGEtt0hgCTTAmIZec5qc/q +0qoEt8Smr4elvH3eUz1EESxvEs+8BnymD8WR29hNTmhqHC124yd5exRszPWkQJXJ +BO02EPTwam6FxxjIttPd/3zwiFSMyoHAQbgdiB4hSZOdu/yuN8NJG63Ffus1Tndd +kyiFmIHVk1QwxeRa+vdfbJWAKuQmnUfY9d1CPeO5pUhG47JBK49XSCQRGklDrx/J +XXffrSFKfp3GbBk9TPhl14SCxCjk3ZKjRZYSKUT8LJxk156didFzni3D3nGvNAUE +r6Wn+R620kauXkypjBYgFfMLwTr/gK1A2SfPlg2taGs/esG6WJqNX75xdR4FXmdx +N4Uf2WaAUH/MxIggTtcx6J28uVGRGNY2wTNLviemtACjUAmbmcwxMnSZTewyIaab +YL687d9OdQyYfJxrXry4wQdd22vRiQDy0ecAowNYRsvLIIfQen1OLm4a9qV+iuh7 +zV2zaJdAsarydyHbrn6zwkNhEDrZHB/mWZOuwtWD2PPUjO+hThIoYDf4F91CiY9u +H5lHBIdKodPKpZovm8aCaQi+hQmlIC1sdJzDhhj8AO75WGTM4uTG0CyZCHg6+rTg +bF+5MRublv1HOJvMH26iHs9h2o44iAGQEPyPgiRIXxAnfGLKbJtxxCxESj47EbD2 +hM+eXxgv8bi7BPNcP6IOtChFzi9GawFpE/zwkjEMdx4qMaWYbqnmsTT7PF3Prygd +0xirj17+HrxoIBDKB+U4m7ZFRWJeY+elTMfolgn3RDNPWkiBNyx0YYQQhvRGJzDu +58Yj1lQYrjKZOFkJqJA4eb5aGiRxMGFfVjDV0g0MtJ2c5OqsLAk4UoNa1us/xo6z +pzgUlDXoPB1wEu3YVmAnv3A52DlgRxbDAAQhN/un1yebO8bvxQU8mQMwdyg8s0f6 +dc0P65NZIEVpXJ2T4/UvwkKL7ScO3eYraUJ0yxkkuV44BrB8q4QUH3QE+piooS0Z +oX1h8XbMXLvIiBEOBF9KqdZYO0XjpQhIZ9idF7pUkJ4oaH+kaWnE4DhdRehX0Eqn +TlTAVF78PGjMx0dBp3MQsP2slAxac7/x5ciIlX6JCqzHu86ue2GNcERRDVfDzrQ9 +J5OXnP/M0Y+f3gDfRu6c2knzOv2uTppYxf5VLgggvivkAsJApNyFLvV/fNcKSUL8 +MFe3R6whm9WTi7F2ux67pv86Loqqmy7BrCCkpHjuwaznClDtonSu3Ae1cXnUvoyZ +5is7MJjmCK+lPqAIh/uwITmxgNvNLDEN4I/bYI/dMgo7P959ZAwZXyjEDCfWjtl8 +xECu1CGLDDaxtLcBEjG6V2/0/bu6oGGY+qLJ6dzdRKhHsVxIPzQB98FgjvuN+i4U +Jf/SEoPgiUFFE3yvRj+tQdAe8t+gpFcbtS7nMFPa73gF5vSHCEZ379Kc7cm5hKjT +k5YX1S91S1LpA/2/sEWIFNBFGs0+lynwk17smQlbmyFbRcmWhgr24VOR9T2CS6Jv +k1/k1kT6nd6qNn2QRHsGSQUryVQa4wXKZezi70y0vDdpd7JQTbJy4dPTUGJfJ/jf +DadsedN6eyRUmDTmZ85lRo/goB8+kTS1WaC2wSXcG3B5JEK9oOam/aVIyymUhDQS +hgv/Cdq45UFwopRPlrTJVk+Ons5vOepNriWqBZH4wSjV0yqq4HeIFTlb0xRHiJsx +mH3ZjYvN9Tyhs0xmqI3yM+kDY7Er8HLKcrpF0iJKoHhUn4ZuT49iBdedG0Vg+YUW +PgvWrjqMgwlBJKKl/KjqVGlMPTf1ghpnW/LFqn5LD2tFONdldCtLBFDGlloPIGsB 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+BcP0CfU3NSM+RVlxKADO+laD4mdirWTbDal9S0t+QCuMD66EsH42lRH0iuHOVBPh +zjKK7+G6RTR2Mlrh2lVLGLOrh59DRg9X26Pn97R3sAjG1eZR8hc9q2Qkh2/Fq2Uw +mGgL5fBBPX9LRg+30MaQaPCh+CcgI7ZUAT8GiMa/CdsptVmYgeEUdPmjq2wYMX+N +wbULr1S0t/AStBUKi4vHNusVvyFqu1iXU0kLqfnqe6+VKsC/RqEf8EYj4DbSe614 +o0j5WXACGqHUV636HECh3Fz1bzk5XjtZXXya07FaqXD438AeZZi8W8htmLGwLhZy +CxNo0cpzQHaB8eJSW6T+jdDmqBh6U5TibXiGTtxMoNXBGW81ccMrAPxicN5PttPH +09OqFQMaA2jLznr0U2APkBaZfwdhLgBoAig8ckBiYr0NRJ2UZgHMM6Yqr1cLKT70 +9tBkxDd76ygnGWqnTpDz+pMTylRHJ9mxlqFFdApFI3RzT/vCXPYM+p8SBjzPJ4Jm +xcofzZw2Y2OCnvssMYsnvPv22mAsGvtvyD0KBkOdD/KJ6HVZc7B8NUcB5oEGNuEA +wiwicMF/nAJT0ZtVE9fvXSH17rOQZLBNR7DQ8TfqB4sFcVHSHMocfrtIml1bjIQv +OOiTF5ElzJEqf7x304cbcVI6R8jGljdEn5SwS/M5r/KKI8UzzlwgcCXrOafNDdDH +3nOPkZtKBa59HrqBzN50oZS8stfKIs6YJnWhwdZ/hqW4mLKFRNFY5uHMNNQtpfqM +bUhMBCwpUQsgdbxyTNdtQfDOYXhYfTFMlQgkieC+IWxLmImeLf5Po4Yr1Dn0FiCJ +gluYUOMATIsZ0DVHt+ZeOP35QaviTP1g1YQF6u8oATiVTMc3HOTY6vYW9xz2haqG +W98E5fULykkuUkVkI4ckBkQ2N0wPknrmFBg6S2sdMe1GDxPHtaMobg9i4cNfdqu1 +xzaniNSG7VcNnWNNltPlH90SvkbKjExUiPqYBQpju6Bp6dJvpKOFfKgHSSxETsTE +YlWtN2yjCaS60D8GCJG7x2lpZwa+WheFcGxZAbxaZ0rwEaNMbJES0bjzFq+3udm/ +JIjLl7NQvPhiEYkOeANgDAttvvxKMmHeEsAC/ZgY2bROOXLLqUovMKtCtK0C3s7p +TlDcNkMVNy9AkGgbTCDlzy4kwM0KXJOeqPACOUsIB4GQIYoh1l8scM2+IOR41qk2 +capoS4mT1SDiIw6wnHFKM8AM3QbDFwKnlW4AZOAlsBvpd9bajpHMr4PnnPOdgtCJ +ImE+zKnLgMskFFyOQutUnkm5EcjMmDYOhoBf/+ov3cLgxfex3VQ38NhcOf4XxRbC +2dfB7dbXY8Hdz84+/HjMzdyur8HQBLLujnAPds3T2JZJSporm9btl+xlwbVOlv0/ +yBeHJ2+0Uo1pdsdayy7R8VUgOf526yeto30uv2plnBihlvfuEmSquVdktWGsJfuh +dK6QPavx+SBgoXHmlZjXlCRRfYi6tNHjpJmx8/cpQQjiZDcnVfKrlKWyza/83fyB +NFy+j1JyCkvkFPNWYwj7aRqo08gpXrZoRSHN1xlCQUuib2Kk9eohU9PoY5g3Kn9V ++EyuusDToBNpF5prWD4JQhBDbwTRr0iWdd5baeXaYZ4g3SW4Dk1Pq2O2K+I9+ISb +5Mic4crU5GZYwqvWk9L8gzftmTE+0qcJrfmy0SOgo96pBEAjswzdNj5Y+Cni16Oi +6uUpMofWOh04+pargm7AV8bctIj4CijKcUJbHo4jnYxPw+VzjUaw9oy+Mq6mwrXC +vs50jCyrPhe2nUczZn8Fv35mH9PG9OsGW54d0lf5iR27ctPOk48mBZeISk6+LAHF +Lk33lADqkiH4fgHir0S/uxNK6wdBqqSDxVceNJD+0ReKrLDDgF4ZcTytfziPIKJU +2qgc+bWiPJEvVqosEkJBS32lLK6SPjiBONmPrLTsE/DYKkYrcfmEpmYCDuEC4ywg +ZPPjCeSAjCj7Yj7Ky3+JMOKFdN98vY0YZN7NDlX3VZ5IE0W95iQMi7TCUdY7D8bd +/ED1TactGMNlMDykPOx/aUB2snslA2NqC7rHMrrXLIo9pps+WjqQSKpJt3bUkM7f +OAuM4URSePUqyQ+NXT3yKsiGrmsE0HivaratDGSj6RfM2MhoYscx3+GDLle+52GL +FEXYXAwFIU+KrjvgzXGj28luy8ZPXDex9B15ORmH5oLUEEMcmz/gTuki+BojjHga +6210vAxd5rKEVjo5bMQbJXQwpSMUronxaHlhbFKWtXPFhtIvM0aS3varaPxrJ0mk +mncXBZiL7nYGmKLyjBybCQu6ZDVT2ROHW54fZeRne9g= +`pragma protect end_protected + +//pragma protect end + + +`timescale 1ns / 1ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +MTh6YEb8fd47amN2cKNawaQawHld8lPdghxaCndTGXumotjbHWt413hSK/NgcsEo +Gnt8Whe7lgFMcFazYmT08o77uaPY9mP8ImzOr6doHD6yp21HOzTAKEHU93tMh13D +H7s4W/dTurxPSDUL0ipbZxO2VZAj35Pme2xieR4PHJUM7jBgdbYEn+Y/ioiS2oFl +KywnU98yjp1OAHaQ+EEa9TUS25IEaVNIOaiFbTaJX6GYvqIgtv1piLkwfSU3PyRz +bvLUm4CsqqlbZrnuxrc7aAru9jx1Yw+hae1UzJQEJRnJ0xdmSx2wjq6SvVT60BfU +tM7iyI/3vbP39OroA7oiyQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 27872 ) +`pragma protect data_block +yEFH9TMGaoqsZtm+eXDLw4g797WYufoCS6kxNzsb7PdM0sF/jwquUBGpjjNmJbHb +HZXjotlyenEI3Q1Ywatqdfzm/FtafBQLgtn2FigpJi5zeQ2y56edjPZdaVL1cOWK +hYU35erakUi8qgU5Ku72vG/8waL85moGfQ2GNmm7eJTwrlejtb7PcMu7vgPKUQ27 +qL3ywQzzTgZAmyMJ13MGU+MA6oGFDX6T03tbO0ToPLUcp2cUzLYefW6LyJsHI/7r +buaEEy58FNW28Z2xJHJ7gi0OgAUvMkkdbKx5XCePm3dwc8WVJTk/yjoUjdpUKZo1 +0TiCEVvrzuGzKp83TKq7hp+3QbrFWrjpqAq8Sg6W+DwGTgAeYC8rnHcSZ34i8rOv +7smiFfL4TdR5A/y7a99uGueqFWKG1cGJC30s5BCWlix9xdCngV+YZUQWZdznNQqB +24WoYosejqDQB81nKf4UZ78nCflmqO4Rk8xQphf9NZZPq6KsEcOoicz3vx0+YadT +iHwWpun714FM2IIU56FA3zX3rXErT1IHi2NffVN8yJeOhX32CzKiu1gDUmQuqbMR +ldDOxi7QQsfLGCZRjjhl/wB5WncMUoDWtwfFQStbg7nHIA9mNcDypd3E02OP6W6E +8IEs61k5LayOVUpMG/oycbC2/tzFsqnP+X13V+APgjEieKDlkO5pcYao7lMwGPf6 +Njm/tMaDABHFTWMcCp5St9ZtAF2sfsv9LesfYHpk0D7xEowxmor38lcb2xmQ7+ac +rahsh7Rg84O0LR6NlXjXrAhg6bYFuf6wmIQjb+oFKQPYBvumCcqolBqjqYMDdpp3 +9dpbBgg9L8LhMNsKvNtw4+Sep0jDW1Umd1/cTBxCCoqbq/2ZzfqyXzDoMgUpwFYM +KauE1n6AjxOnVjfw0ZNGVwujLYKejAXgqpcpKyECzgV9ZCNg0JtWkr288qoeF0zB +DFeZw6i77LEv7H+TU0GfT2XIFjur3JHlzDsVhCwpjBaOnMVNzqWYfCShpG6f/ZUu +HlgZtFSj9XUDCVHwMZfb/bGABdOBQJYpo7ZASh7gxzoP89r59hpedN1ig5eVtEQ2 +l0Ft0d84sqsTnNqEg1v0MlkZbLQCxCoPIjkc2Gh+TH+sn0J6frFsvcklKXOpi7A2 +eMEh5kGr9X+H68S11VS20RCKxaHF1YNeCCh4rS57+t3X8+iWtKpBTkWKuanOHfUO +0mrtUTzrSZcyUzDREipLYGXa/ddZIZhL5Yhn8CdoMBi7wETvp12mI/IHLoY3LRcM +Z00O0qH/4sqj6xSSFtieBVUteeD6g+755hbT+FB8+C0X1lT/3i0oowL7uWCEEm+O +x1DEEcC0yYKXtjSXmsWMFdDmuvoUDN1mDdf9GJ948mMAMwlSwn22u1WIBthhdz0C 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+pQyB9H/NewWIlJfkFvRRTcQML0tGWBXX6YYFjFFg4jR8nzqNtBJBsZpgDZWeu9s1 +2RhG9nSdRCSuBnEdpdYHb6rqQ7drZuh7l56oG87WP1qbxFoMZ925doy9ckqZodwN +A6oO6Trmud3/MsO3DQ9iCL+3B6NQ78tONz3OH7jEpBxWHghYdwsZ95LbR8OBS2z0 +SepqYBx9nB0kbIdOhdndRP1BsdXmhvcnr8s9MFnkA/JppbFDWpxdbGKORg5gK7o+ +Byo2kXWhSue0NLb6QjBKH3HCB35sL+Iy/SM8jNm/ilMtDZOR29E/b8eeLx7ixyH/ +Erw+ati706ubXvkoAXC/n/hRH51apQOvjUystgKFOpg6wNAJfF1Q+ORi9uR0qWe8 +i5qqL0BPXg4l0yU9f+hWRjY8VifxwmpSmV1QG/hz5N98ABYiu87B0gxIdq5Eu8E5 ++CfYDNFor2vNSA8y9rGX6RYsSIoxQScM45zidYtzoJvq29vRVfIC6cGCNCTHtGyZ +bq4KjOmLNBd6e3o4KIelH4ycG6L2c2M/aTz67Ws0Aj8Tykfy8hHl/NpFegOsV4u6 +QVuYUUT+Ufs8wqFjiQbAeTiH7L98dJN9MficHE0zUAETI0jiYCUxj+Ya4oLskx/E +dEre09z5iKDrLM2tyHbXVMeDE0E79jV+rAW+328DPyjgmfLLxSoNuRHKidBYzpQ2 +kxp451ur7XSI22aV+c4Rgjv8s2kBmXt5g1LwGEVHY8CZaqQYrQXaX2y/OmcP9IRC +kCwIZFe9prhAICWTcTLlA75IcYSKrks35Hs0nHJ7wpvj1hzOqRs7Qp4zD7NGjtKt +xQ3WxeqEQpoHVr7okvuNySeS5rCmG+24Vj/1QKGs9tSC30EkuaDqX/pKIh7Ahla+ +NkaBrBAuzQL65ftqqcqcrKkw4ayoMH8grg8hXb0lFTO+0QwrMvCTe6KFA7ujFPU8 +ZURAbjEygRzdLZ/Xv2HHJ6SJ7IQxtuYKOXNlXFwJdRd0B94qqJcs2VivvIZpDMw5 +3r/Lg8Rb1xOX25SKgL9WBrDHmhiYjw9rnRcwiOYM0s0OP58u/i/zcddMC7C7ZYz1 +g+R+C5z+0wQQbuOUqU8RPJ8AP4DNZdi0o6V2aivhocnuH/Bm6LcfdwS96pBH/uur +dPxsKgKewGUl4uj9UOJrNuKimz7qoUOD8bdIYuES+3wh3dcGRLlIa/uALpVKnBXD +b1rG3fea6munFwr3G76O3khv4jSdn7LFZt0tv9Zjjq4s6b2fJIIjNQVRyeqE3e0v +a3KUWalg22N4bYRMYTD8COWmaszxOOfKINahj5oklukATfYb8ya+ZuIuYyOU6DOB +yUerLTCE4ISOQRie3zqkPQNDpAQJrtzt3CCegh3LaNUWKK1k1cQOl6KFBN9z5COn +C2Z07OYh9goCmKDJerUYfbrwfGFMd7y5l15Xs7mGydMBc9IJXeB9q3EL8EWf/iKe +v95d+d2yzbYZmypGMD/pdCJ3H5JKg+mZgC/0nfXnT+Bu+gHL3+ynQ1+5kA5/4sVP +tUWnifc6tbMHEa2j7e6UUNtPriEI5wGTeLBjBeXB8fOVNEdZtN2s4p+zcXJ4Cx1W +tXZH3HXoxEPbHrgQEKvKVFWrcLSHZPLvhAoYOZoQI/+RMnR9qVVRacBTwXiNhqcn +HGhU8FSTK2DowTm110M+dgi5yhVmhnguyrWx9boMk8O0h6pITJU38aMFnPIoNYis +xaY2Ku+IlpBVsm8x6ggOj19977q1U+Km8QSFiYRU2zvYP3qQxyKM2Pi5TDodINqf +ynoUDmY99F/OTVBMLLme/7q7NbnGHohS8ekiEpXiIxy8f1SkzOwWLu3Ii5oX8tBd +wAM+yozXmOaId2eFqTexhnSx7EPkRC5anQRGXsJYTJh2dnJqgRFWtRhZhyr8Dwar +CSNIXmIfflCmV0ZxO2JOWYYpdI1I35pzscvDYhJ6SsDLMWzk6Rc3MxecziG1JBqL +J1XAp3596rLeP+7MTnGpgI6q3+OUSiYRLKRFqoO1qsLzVCuH4LJrMlov2pRFl5qm +O3IVCLxI0FIxw4HQb0Xpcr8WnqstBWoBoU1CcUecCkhrFgCDWSWPZL/PTVeLVv4N +vmNurotg9dTeV1wgziZfLpahgoeqfyH94zySTHZb5vZvI6HTVWK8+TnsMy4h3ABW +eQCTxksLsuutyiNSNMcXHE+dtkeeX4CiDIdeIud10yDV/wOSRxLkpUllxZT3avMz +ssD12W4Jt82Mn5bShg7BookbbAFFA2RKiOLhvYO89wOy8jcVerZc/jJmAkcayUf2 +v54ll13dkUiHlzVVA7t0N2/M179RbeuhIDOWncw20lWh8TdfTUfqANleqARUOn4b +4bgMvrMyP6jt0fU2Zw4P0HKn90YGO7GXhcyVgi1Dp6OPuGbeiAs6wQhlMpTp9Ao0 +J9S2JNRoPu+EffjBhfOxCYxuF+qlp3fIKbBPxEofbMCDBlLJTzQNi8qQ3kisvs2K +UshK2bRjbGCbCzDuwc1aPF/xa3x1OA121Fj65VHfL98TzbRr93wb1Aq1q1w49PeP +IvBaR2pzuKWRRReBvx+J7j7eXqcgMNx3MJZN95nEqmB1/CJ30Qn090FxPM+3+xZL +Y/9G23qsiowrEfgjvkV5Y2aSdtHQJ3FELwIH4mvevhSOiaFahZIyl/b7bzngKYSW +aWTI50Qv3bAyo3e3Ozz/iQm0CN2jUSpqYDqBnGQ5ynahyls2fB9OOxKLWHrrCC2m +ndUN/C4Acg9sTqGeSGwVeChLM/tF663M3VhsQj93Z6gjMBHmFR+r9yTUkp0UyHWP +mcJSOINBj3Fc1kvgUS9cj9zksl5eiG6AG95RAxXBxrKAa8YbfXgZScu4uneKaW30 +Se/uC/k3OWxtvw4vZoIclWFJVqdH24CsV+hzWy3bjjjjqG0fH1plN4xGsNF1gqxt +OYwVWW2m2CefkW4AM5+AbeTlykXquMQOcuYKlX4Z5GV1rg0NjfT0BF5oAKFdxyLO +NwtXHGOza+AzqMhl9yo5/0WCBGmkiviUzJJI2mDMHwM0ExKgb0O4Sy5CuGnomgAO ++xLD57vjb+s9pSMs6JCmw5/5wnGxY5yPXztxc9UGT2s= +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +GgbHzgThm+pxY8qJAenj6M1nMg+PiGn8p88tojq6cijNwxinCZAmPODaDelUBiV/ +7pt9zFVTV7grht3KSqQVNS0NNFR2RViANJyed9qeVdSo+i1niQsqbPxS+dVMrEAH +GLcA4c87U2QITQVVg7mqbwa39eel3uSw5jIs/cPWgUVZwOX65uNekkTj2RtXHhFd +d0pI3dQoLqLefXHWCbn9KLkxN0XEZfWthZgyZS3VmSWHt8u7zaOvBv47vhah3n+9 +KhPDKZWleg/lH12jwGNtIA+ITKMLpp85nyYO2opdw1uFpHhBC1eWGDzHbnzEyKPz +1lNcyRWK+pqU/AY4z4Ujwg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 880 ) +`pragma protect data_block +a2PDY7wD+DHw8OF9GdySBvuAv9crSSeitt71UCe4rRD8aRaQ7B7JOb87rVKNaP+Y +P/pNSHeTA0LgZbqqvIaFxo2MZorvxVDPD9t+dcY2+NwzC+guE60XPM7TRfEWjuoe +mCDMlV1FgD1JBxxH98/PCJ9FdWIitffatZK/6h0zBd1y20gPL4NCldEah/0dlzsE +ZYlSpoKDOkf4ffYl6KkI7rK5zPl/obVTsYxOGLgnsUf6KPLFF8wfh092jhr35joP +zJPi36aMCfqrd+EVpO1Ba+4f2HgslYMGhgxzSfiDw5+qDox8mLHJrH6YiIkPecqY +DWXyb9xcF53f08/oAFMiYMqaYQZqy0QHCrNw79H6/E15d6BdVnG7SVmAlaJXlAQM +RB0LmInhsRXkwvijDTY656LDiQHUezuR6a8w3gyVo/IODO1LU8C2HZj4/NLID8GP +/VQhkQDYOCWzMwG4flLhavf8TGaLmmcsLpB30ad2uGLu5GkPCWLw/xu3pPbHtZSH +QvuUOUfXPzCXwqDLBvLC0Q3vQktfghuGVwl+G5IUeoz+79V0RJxBwiugsA+9kSPc +adazmz2dYTZQg3XuS5fEwjW/PpvmI4AO5L/to3aLL7ScLIXVnAFG/RqthmRn8UA1 +UBBmFSbYLWoZD9+yYC5Z27zL4cpg3aO6/320kboJd09lPyT9dqU7J0sepyAHbSBe +8I/h4S3KDUpk0ZY3p1dq/+WbAAJbFbysshRIobC36fJEPf61smM2n8MSfy33wg0J +Zf7Ox2L7sy2gRSdjOQdz4ewzRS6FowglhyPo5GJOkEVER5oLRxLwmFtNNZ1Z5kgg +/YQ2hAsi7TZWcksSfpM38VL3yRExRkYApK1//eUdZLGG3B0XNL3kMCvO/w7/UyDv +KyZYuYh3rOMk9HN0unGrAYYK1rq4HRc7d+p04AtPql6+UFkj4u7mNkP6Obll0+Xt +RtzuEQvQ0hZvTswe99AhgjofpEIG/YObN9S/FEHmYwBf5CzOg442K4otNJ9USGp6 +xEXuVj4EGsrgId2plsBHWdHiUVPZacoxWIRIEpW3Qy5PXHqYMv4rwxPJAciabt3r +gKxplQKOCbzsgNb+UbbiNSVMtBIAYwgkdUZarHuethhgz5M+fEa+AqiLzEkj5N+5 +3W39ohLhggzKXrAnuVk7fg== +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +module `IP_MODULE_NAME(sdhc)#( + parameter VERSION = 32'h10, + parameter DATA_BUFFER_DEPTH = 512, + parameter ADMA_DATA_WIDTH = 32, + parameter FAMILY = "TITANIUM" +) +( +input sd_rst, +input sd_base_clk, +output wire sd_int, +input sd_wp, +input sd_cd_n, +input s_axi_aclk, +input [9:0] s_axi_awaddr, +input s_axi_awvalid, +output wire s_axi_awready, +input [31:0] s_axi_wdata, +input [3:0] s_axi_wstrb, +input s_axi_wvalid, +output wire s_axi_wready, +output wire [1:0] s_axi_bresp, +output wire s_axi_bvalid, +input s_axi_bready, +input [9:0] s_axi_araddr, +input s_axi_arvalid, +output wire s_axi_arready, +output wire [1:0] s_axi_rresp, +output wire [31:0] s_axi_rdata, +output wire s_axi_rvalid, +input s_axi_rready, +input m_axi_clk, +output wire m_axi_awvalid, +output wire [31:0] m_axi_awaddr, +output wire [7:0] m_axi_awlen, +output wire [2:0] m_axi_awsize, +output wire [1:0] m_axi_awburst, +output wire [2:0] m_axi_awprot, +output wire [1:0] m_axi_awlock, +output wire [3:0] m_axi_awcache, +input m_axi_awready, +output wire [ADMA_DATA_WIDTH-1:0] m_axi_wdata, +output wire [ADMA_DATA_WIDTH/8-1:0] m_axi_wstrb, +output wire m_axi_wlast, +output wire m_axi_wvalid, +input m_axi_wready, +input [1:0] m_axi_bresp, +input m_axi_bvalid, +output wire m_axi_bready, +output wire m_axi_arvalid, +output wire [31:0] m_axi_araddr, +output wire [7:0] m_axi_arlen, +output wire [2:0] m_axi_arsize, +output wire [1:0] m_axi_arburst, +output wire [2:0] m_axi_arprot, +output wire [1:0] m_axi_arlock, +output wire [3:0] m_axi_arcache, +input m_axi_arready, +input m_axi_rvalid, +input [ADMA_DATA_WIDTH-1:0] m_axi_rdata, +input m_axi_rlast, +input [1:0] m_axi_rresp, +output wire m_axi_rready, +output wire sd_clk_hi, +output wire sd_clk_lo, +input sd_cmd_i, +output wire sd_cmd_o, +output wire sd_cmd_oe, +input [3:0] sd_dat_i, +output wire [3:0] sd_dat_o, +output wire sd_dat_oe +); +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +At8NDOCc4kD0cT6FYsAsqOLQpaMw3bVfTTiE5FP1gKwP5J3rADYscuAA9znbPvis +MBOXI5NN1IOCBhY8docHxSOtWyofhmco6KiZiSxlTAMnmzRtihgtqcUXsQWTNJTE +7whQH53NWjSMVPv2SQrHMa1RpUZnyo5STupbfD+3UW/HzNlYy+PEUQwYAxlOnG2M +LOVENWcTIh7UmStLPYTtgneJd8aOpL+baFyO2aNiHXosS76QIqvTKZQ17Q03p5K3 +i8PCPzCbmM0BxPP9kfJ10GKVxW69hi9fUcUUgGpKsloUh/zrI9OINMKLSkzf1fVU +lCxpq+G9vTz3hl52Jvm2Hw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 47504 ) +`pragma protect data_block +6DtJMbz4Ibm2QCuJndBEjY814wOQN1ovsm0I1k/eQ5F6nXmL+8tc6Dg5H5R4TyKZ +q9fOUov9KWzcH+lSAAaN/zzJYb8+4MPvp+PEgjpW1X4DgO69hTRPHwcr5cAdpFGO +zjd8bfu036TONJBBYTZzmJAkxyj2p0KU3zkIpovpC9js6bioz5OgKp5u3XMI8a+1 +BjG+bSDznAAeOMwjYNQhDyLCmyJ0dscHZu/ntQ6a/yXr9eoQ1BV1Yp7+jXu6ouCt +lypRiID+AVbz2gyP3k+PRJts2jYpffgbwCPB85AkZnua3gXlfPWAUKvYub6//sSu +TBSd82JFbBrZEZA+rg9vuzt3RmM7/cO8VfqwOcQUYP5AX5m/+4DbQcSJUJxwLGAs +njVZQ/SNcmsAdAlo9d67Z9nM9jTfdNi1QZP2oJUs0/9heUXixobakPHNc9FdtgFD +5ZHvf54jmPdw5Ko296Xf1eGabMBwGP1O69p/vyHha8zR80v72e+tNuCiNy89ERMo +wp4awRnxntoidrwrJi3lCHd7NXiORFtkmY8Zac8rMBCQ2rHig5/Jlfn3ny/8Plea +lyTGc0FkW851f5MMMMmk9fIZG9hha8nCxTHzWzlW/Gdudz6+mYEfTugrI/OWVGOr +E7XfR0Runql4ANKLVNCzzjCYWBScPSo7bI1Y4IqlHStO6y+L19DZ4Q4dd8H+g8r4 +858IUd/SFT+0PbeiKb4biad+kULqoLLCYndauDNBSwP8cCtl8YTQx4O5Pz8ne5rs +Oks9WQU3PYs5/INVUBoNE7mQaaKK+gjYbcKhaXskEKpMCopy+9QA4k855XdL38DU +oZFMr2PT/EG2w8+5Qntd/ZGQILdijMnL0GJ7pyu0b46VLj8gI/Ofb6bSNCwHASWX +/b9SxX4EhMZ1uj8ZR+rmy0CJWvm0IFdocVofbEKlqKK4cptZ3msiO31/vpph/qEz +xqnc4vBChtqGRAj0rtWEP+4btqdFohKKvxpWCiFkq1J7g6c5xKzTiYzgdBbxyJkP +aS0ep6AZMeQGBftpKhNeBNQMW4Xb6OqrO3z5K5KOFxVWsY8fTxHOVV+u7pNPZfZS +eGPsGdUjFA5YSNXonGVcSnSeTEwMnHmUnyMgzM0QU9li4jlLpUu+ExqP1ajaf511 +a19zjSgBkzGBnkx02D1mIDyrSLl+7hYpXF+e5RiPblCpRAAGeX3Grh+LvrfChIqv +3pDO1BTNUJJ4fCsZiqjUB9HiQmY9q1ln8MNWjPdUQKJ8menPjblIzrXowXAdVvJS +zYwnv0FcTgRYVuh5cZrtZfUMJn0WaDlF9jOt2fxUxdppOCxshB2HRnHQGX0gG64x +wVKdXpo3TSFyNPKqD4d6O1EKY6BQh8VafJa+ot7DyqQJQvG1BR3pGKTVfDs08uzZ +eIrrmLy2/9AxFRCZxJe0eV8V/FDOWIkN4kjVZZNhzjLP7/HG9nZai0JP/PyTCq8b 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++cAwTefgxlO2Ys0zxAB7ODOlHKXIJnvZ7rklRfFnjP8QeJmIKlFTh4Jvx0/DTLeZ +W6sVvCutnmuiWDdUFrA1oWiazw/uCqkzH7Rj3Eb7CAwOqBoVbxDc6orfPX8VGAVp +zRcIK8vogYaHJYuBMvQ/sDiaa8Glvra3X8rkSpU6P4QNrBQictrzfG4bnYpEsSem +oi336Begi1f5QKzw401WCNleCpAeW8Ucaf0rfvq0r4oE0L6bTmHZlWNDM9HIsRQ5 +a1ya9EL1ZZ/lQvicqN6iPuDmmgSZXQkfMgs/bGS5aZNovI+e1ikwg0eNGPQ6KLKI +y7hRgl27yEn5oSREP4DJ3PTm0Krjth7UXtIC9YEPN/t7lYQo5SR7Ija/Cjh6TtKd +fL62mXIe0C4p+XSMgrEY+xsUjl9afNj81r4OCuEREawF+fzzBhVeXe5Dq+9WoLMY +CX93+f3Z/PkhLou79EzgGo5I6Q+7GSCoLcM3PqgwiP7bJXrJJu6vvRvQhX6WDON4 +pTW7/SzlNwaBW9ANSpNWU1gcewMA9B+q7FhIX4ZcAH67X5CbjE8s3C6z5dbtRjKm +W6UyMssNqc3EtxO+nNdPHAB2VjV/AafNUV14JTwsdwazAhVZJI3/R09yh8hvSeD6 +2O8mCkPZynCnhaVKef/dcgDC2ybA5lutfe/Rks7y0tqCXGGo2yyyYSWRtYiHRyw5 +bf4pj6QZCoQm8LL51juApyAf4R+/DKGLQ8Vf/c7gFOv4TxO726MkgK7ctAIrTRLR +TYbXSvSl6iuRjPFMGSW4xSzUE/oCMnfyP9tIqxesvZuCIkQnq979KcMfV/dUezVj +M9n6LH+r4gkqHQ+eKdZs/IVxJNwpl7Jm1KJsLCfJJx/5VpA3dLarnJjFTq0fFrjz +2+sE2AwBf9kIkCMKQ8BIXRBQ6qcUnqwWXHJNSioclDwTEES/wVzsJZ/OqMlJZC0X +vio/89cf3nIywv9dv1QwUhV6VWr/DuPHQqShdDPTEoiXVbKhMHRZh9V9bJudqYjc +dUesm7cBg8hYWfJhnJWFw2fac33z3PGefVWtlSwE83XdqjEncckNOWy+JrZeD9je +VevFKbCGmKxoe6pybqA9ALo/YiV8zhT+OK7y8GbvhB7p+F4pT4nz+i+uLdxY5MQL +yWaEamEUT5srUIJLYDVWSstc5Re3E4B9eps456KQ1F1/94ZSI+IzkSlQni+my7yh +tfPYn1abp6Zqos6hJnAxT2SzLWmpW/UK5R2//Fikj6Prllx5p7WfmpUVeGCZ+yiK +9O6wCavH/bHeK3yN4mglLtLmZXG1yK7HX2dUYZh5Hq80j8krVqKHInh8fKAANGXO +cdujBcyDE9KWNo5R5KQb86mqfk2IRkf4VbG82YQ/PD88UMsS/7UwxbMXsgODFRUI +LRsGgRJbin9b05Sr0uYov/VDT9UmJmK/miBAhw0IeyEPcrTzcAqfktVSlgKUYyXk +ZBJkEqu01joWzFKvajIGOlqBvLaWRfBlOMpVsWHtKmugiWyGYq6+8790hPsMNqOU +56N43wh/wDk3gHFFQP0r6Ui3jashTlXfTOR3iRUwG/wrVQLg+PzPAaMK2hYH6o54 +V+H8i/vDn7SiXbN5UIukBhuYAeaDe5d9uyrZP2nIYKzpVlyFF+g8yGKOAcQuO783 +3bhAyNCzaqo1l0CL26ZvQO16iXDP4AWUyAKqIgnf12RfwQJy1AhPZGMtpPSyMzCw +/jr0Iu6xgJUNa05E2z2jnZlLnCnHFCE02840u1XmTR8mA27sXSgQzSiGhmr8l6yi +flXW5ac30LeVj/xE4Mqknx+lh4ctydk9bRt+fNJ5gvYUgl2zLnJomFz0Rkwpw7ZL +BEwAP2+Hnp8jYq42TbatUIKRXu9cGhkYePwFZJcbi/Ybp9TH/z7fkXT8taVpgkSl +m3S9Mn3qoZphBjmo9ht/UPU0cWNjcRcUmhENZl3Vab/zf1ZLltgRGU2+7W1cnVd2 +z5tJA/WNDw/Bg0bIpE5vSmf4YcTVnjWvBibFO1w0Zd7+tgX3PCUnQb6HVGoVPP8D +yZ1bzRGIYGDrPj45oRyvuQW9Z4s6Kw6ZcGDFtS11rucRdhbgWilKnPijcUFJrmfv +8U4mVsBdNuiyzUt2PjyVr1jhjsH56S3dN8h8F6F6/cWYF+5BmiGUaFMeinOx9Jqy +cg07i6Iccdj4X/oO+R0i7ziX3dWOlsqIkE9HXIkGG7bDyoM86yJX6cogsqCn0AX2 +Xz76Jty+69/QBGD7s/OgBgW/C1O7AfYf1Inv4eSJ4IC/cxPKU+rYZwdK+gmXdCTU +fdVn7uoqFQDmDOuKCFUyVnYHjfgPiGsBkC1FnklTs9k= +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +J7KosW2ykKi5EFdAMLz/gyhLImwj2gD50cyEdEtO9kZx69ZgsPaqC2N/Cju0QOVu +OHSsUW3EwVk2dnUxhFc96WyyvuSeNjGSIjL+g0hg7h7U19HwGkjyDWXxI0FszAgU +8MtLn0zyRn7rDX4WKBW6e0eKZyxA+4TEGoEs79gD5JEm5GGH/XXqYNlNZhIY7AnO +PM3n/egkRGqxUxmVys4D/HKwWQJqiijl51581+v420/SeIz8g33QCnsj+FVv8FQY +rG0UviGcyHwANSYYV758eDBgsPuT0uRiqdzQaml7Lr1tI9riDfjD2N92Ga/lsJ2Q +1vT8YIB5wgEhiEjyQJNk8A== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 2848 ) +`pragma protect data_block +ApxS0ov/xgjlDiDohm1kcyal7qO0JfHd7W1FXJZHw0gORD2rAIYiL865p8Htsfc1 +hVQtAzpQhmgZn2DvNj7XrLJkMxtf+zUJIx/g7lTELO6oCW0VuhgpGmWS+PKB/AHL +VYS1dcgI7YlztIjcw2Bpnt95fwMvB+dikPCkLZNtzZi+9CTcLpYNzqjA7unRpwv7 +vNS+iRBUQRHHBlxRRQtXW0T8kbRVEzEEgeV8CZ52nBLY/J9iN+uuvDL+inJEMb+s +nvWRAHQyPzLTrpTW7utm+FWRxBwvbT+PAmXrLf7gaJvFDQRbSq4qs6ADjKtFTDg/ ++AKAZNu2/emGZFaXxXwmALRK7yEYrbofI6HxezIDEgnvuBbuZXXSqH8lsI0h3eGA +PPlLRxnBBpU2UjNWefnRqUOdmkAxlMyLAtxjDDjhXF+yY5lQ5tRqZQiR2DfWxXTD +UeGyEfduJZvwERdkTVlTX8thCbPHmeVNHNAcsQBZJgCIq5hYp+y4O6z8rqKOtzX/ +9+0cRd4h3BPgMJNQbD7xBBf6Eui54SBvh6l/p9Zez760ITfu2jwHWVnCa9nvFqlS +20ki8PY4KHcauwYPHuccDIYsEiMVSv7SE9VM0dz5vzRLPADoGNKOpX12E0QO7PNr +Ve9Ld+QKeL3KeVk5l1Dm67uh2Dli5986Sp+axX3mtzqqUWv2bsyoTgm5/jIzbQTy +I2/LfwalvomI6yBPDWdEyTqislROQTj0YI4DOpITzZXV2tjeU1pAny7HBezc2Ywv +D31lq5KKzxiop3IIwf9eatZLTiD/SBsRzx+L9NdT/MramZwtE7FdDwrTwnCW3CO5 +T7phr6Kckvhj23cPJEHaOBx6Hr+y5w8eI/YvA7tVZAkMq9Ja+4O+J0atNuYc/4EE +/wq9wjB6sJDjsfBleR7u+SrWgX2LwacK+MBLSfQGgBgKbQRroRzAd8qAZgKmojtt +Mxlq7pNhxmJsRsKtNbIoGuc0epuFstBuTzqn2lA/YA+04orsjM2NW08gkjQZBY9s +w353o77r4l00jLIB/lrk4UlZ5w9HwbIyFyEG9y8kC6wr1J1fAjeJq8UfCFWoPhdE +lyTzH4E7JEArLElcUurHDLizruJUx9mD/mxs76xF2jvOg39WAxNBfijtt1boqJsA +dSuVj1yfDbY7SzJbrJ0zVD6aKRqr5Vpt2MeFCfVRsvpDdsb9abmZqpF7K/QZ/gl/ +2mVCrj/LYwePiDVlkpbtbzq5yr/y1FGgBn3i+TOo8Mgc2rK/GCqDIuRQMbi12fzg +Inw9B440YGaXcApJW+az2IPgyPeXaFQU0HSPDYr2svR3coZZ9dxmgrTLC344qvhY +bYVamm/WQhRAWeY+N2COlJPrBgoMr1lL5HLhMcpIfVdGc/5wDzdw2+fN/wEL2VKD +6feFMM/Vr+/Pjo3K450YgnqWFDfe6AcpDZqB64d+4b3BduUxiFcAxwzwowXLAQ2h +CuXHyVcX8ndmk5G7fgaL+Kg6Bc3Upl1SBBFs/NcexH3aWF7DIhEjKdIleBLPDGO7 +RrX9wR8PzLLFwbh2FO8sAvU2lh1syoZmpCqcN1+rK93CmeV3EJSN6Q/8+gaKySQR +GZvEM3dof6jIAGaLYKpe4LsmYnLfPydBpiiiFYTEDJXqho66gwyqZI5wxdV1zWWf +Af51a20NbmBUtnTGeag1Wiq/rwQ9eMfprNTZ2bTAxTVJCU1ZaTi249Xx3IZs8x22 +58Euw6ivKFj+p/gvE/orHoIZKFcFl315ZgKkn5uBVJYdhCrDiLzMKZxHl7PMlTJ9 +s79g2J+SA+KyIGyIT9Bgz7+JNpVlcQky4DGS8nyggJWbQ7yoBG+f0tmmMO7V6vIh +XE7x71gom5tY49p7Bdz0NK1XNOW+/YONEKlh4Bi9/MDqYk5VhGRb+4wHvwLCu56S +HYgtuZvqrFnpzCVxq1zBepFDOcGDuT2dx+klu+FfIBhNGIZR1PtvV27jP6e8Sw8O +PB7iHac7aApHhvibH0PkUTVb+VFoBZBb2jwkkknpxlARMLcjv5vIP1XkemRWMiYu +Hy6OrvjlaiNw+kJzmxh+jr2TxFhDYZX8xzDqjSNPI2MnP9JXWm2VqnAEi5NY8/qP +u3uS3zQ4FqMupGJz/jSzyF+vmHzD9OQZtIDKkrtYbkaXaPd5gGgr50f0OIpWwgaq +QQ3Q31jaNFkRgQgDoqanT5glDd/sHTdPgNKWdKhBb41BKDCO5W7KEOaV/W5EPlHf +K6uHYF6HST+fwotOJXVd5d/jmVnXXU//wHxpQa1sH0Si55jeEu4flRICfAxlbBMx +nu8CngFhOihbvXooeYmNrLk/Qb4l088PCbNXnjCyfw6p7Y7gkRejRxanXNBY/0mp ++Uz+fnw8lUiSDcioh9E0ISH1MFCAJQuKI0wCe4l8oUzIqDQ6hUKKgvjvF3HKlu4p +LhSDQeUts6ZNX3CXkIM4igj++o3L0J5Mn/0Y6gksZAUjfzs/SPZtzfvm6/Lm0eVY +JkpBjjDtTtof2yaciBNWPToV3AqMIQv/nODrkJDUuAPpazs9jmiWAXAucoK9FkjT +sWXKDpUDTHdkAGDKL/jiDyRTmdRe+SVX+nsAgJk6ziifNVGkMdoEtjI64Cpp6cEl +tfcfI1XPcSqIE+LRttHIl4PEVJlFGz4jpQcA07FMJc2nyRCzHWpFVA/Oag/zbI7c +WQ9GWIlI2/YzW3VbFyjuJCj2M5MatZBlkqZ863vH6XCWvqAtRO1zAs9bs34WwXPR +xwVPw6TBwsWOWoWvdWfCGbk/HysKEx3gx9b/nKcyE0xxV7QuOg8Tz3+EbKPz0mfb +N8ZJNOfNYhwO6F5C4aBL53HEwzoPzkMGL6d9uKsnHmaKFfymafClWB3fPwoIITol ++DXFS2X2oPPB49LLncsAxvkxoXWB4xwtezM9r2H4vOBtzDTHCL9UQJ/N6H4ZOoYX +SEyNCXNyaHBq41P+EEWTi4lAjUSxv8N2lE/7HBFnbKKMiaivlFZ57AkwHjhR+v2j +nyanQp2AF7c0Cb+XH8Ku9BsUZSKLtoDcGv09ZsIXYcZ4I6HutNLtRM1/NNvhrumx +LZY5GA20F+E3ATrbx7lWEwei1M6jdBuJMiUl7cW99ceL8JckKYUwLq0JTaDKyG2C +4vhDfTtuk8eI2NuKtCV7pCx68nUMMGbc699cGnnrLDTRZl66l0RyPkfxQWKWCtPd +QeZX7zGSm+w6ihwmvRyjB3kz+nymnKe1aTGGABCV7oNdX/5x2iJkoRgq0PTChqNj +Q40HXwizoKUTO0f7P+2SXTLJc6lKQmzHCvvJu6Wt7AR8X2wPlAxCqqHKC+73zY3o +skilQ4PglGzfWixxzE7XbuPhl0vhEukGAMIoGH5iyh7L1WvtCObK2sKCZdE9+MSp +GfCqpX72BfSF4xFFn0IT+AIOsi9AGSrMreXPko9Lue1WiYcELcEsxpHuYZX9I6IF +iA0aqOaO6yZ15oCXDF39cotuYBNeudW9/Jvl6njbAvOEMRbRz134g3fg7ceMZbDD +7NzCaIaSljBFLMS0SVieFxaCM4upKoqI+OMmePMHgZdtNWJqmDO9duysrzre8SPh +r25XGHo7ujT3L/WVz/xeEwbLYOxBrqltcNKtIVal6R4OeIVlUSopJZyvcELBOHhG +kFH2sMU3oZrPGTGF7xN0Kg9L1fD5pn6TlU56B0PJnWEK9FbKA9hDKX/YF/ErHzMw +M5zE+dXaUaAZlIWPUSsnsf9x0ybL4BBU5XMjQrr8rYjQoZGnZxZncHI3JM0kgqxz +o2AWhMH0WmP0QLXwjMSvXA== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +Qd0gHlsfc/XIgslwDiE9K9yr3xlKZY7dRCEA4nolcKqvt+nIsq3FL92/SaoeJGIo +CKSXu7GbU3S4jqPDe0b6FxNbar2owJoFHYDQnYxbcO647ljaPpBiv6x03zTZQgpB +M5+cIbxDDXPyUwmRJLwZAuQE/U8ywGMFDSApNib2YZPLO6URh/xvjhMIO4/ityTH +GRv9t3xhHHvyPfGB2Oa10v7Y98IptlsmWMPEg/cI/gRKKUNcEiTJqTmMFYUELkF+ +5iWuLPjdOzB9CLSbubxWA7at8ubRp5/EFs8cAmvD+yzglC9Txz5rkR+x3ryQkXzr +7HxEV+XcVvxiezPBQv4Sog== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 2528 ) +`pragma protect data_block +XiV3gfci+H3rlSdIMWTxzJU8cLPDqoapCBHln6HDS8BmHn/Fwma0HpaXbMxwsDc7 +m8P265VvSuSMBdnIc1kZNyhKrr0lmSQgF1Z6+4PdX7502xF1ztSIj0FALgQfGnC7 +6emIbDmkjYr0FDhelXSc3r5hh7YsHqGr0AQgUEOT1QykJleSgdfrdZnz9PrL3FXQ +5jBZheIV5/d+P+j1A9CifQ1oFaU02dQ6sOEnFwiPSqGG3c0KPn3RptdK+dP9SYR7 +e3PkVS08nBuXUyC1wO4/qmL1XAsR16kE5nyxbp0ssSmf+WKvDnsyhS2Lm/S5DE3D +hFBouoZKBO41OqKEaOPqE0hHmY8rZ+UDiZ6FpSfPSypgzwRBKCVLHHecjUSnZClU +pb6PdrJqrlZqvAMw6snEDn84vJCY1DtbZ5tkLVbzobw4d/7MXoxjfkMwBdwVWymg +Wgpu2XZ2g48IvQnd22tr3bS4G9OG2ex3fPbaOMKY/LwaaXb6F91XLsjziVWmPR6v +ODOmlrKyknnsMJNwEl8yboPzyk1liTeCxnDRS0iCxPC7St5kY0A6neB9EGyXnFKw +wj19sKpeGx44YvT1UklpZlO/6f6VgPnfCfqosldhCfofKVHA+N3nHWOyr5efrYDP +UiGGLimJOJMUlMjgwh/Q6AHGU7/lGLv+TODXQH3kGwwtdtGQMvAQmCL3hMmnUW5w +xuQYu3a4bpXhPPeg7JgWUWTJCuzUcyBvuRLofPtQqhDJEh9fJuIQKUBq4O4Z9Xua +ItGcNR5Gho1oFm90LS/1+zuQB0XMBqrK+9P5zi97CJULS9Zirgs5EGB5S8tK19zo +OHNycDnFRJ9KpXgwPY+aV4lLZ2cKqd1EVMcf/BbyrMvb7Vj8NZmeJvDJAZFZUsiu +9Vu3jVLUdcoO+0KZCAaUoxunJOFgo+d0n6hGTjMrOCzUsDfFF1VBiEGDBeOOngt3 +Kaz5MN8saN6kFL1WlLGpe8BjMckUuVqjHDYiHuC6O3vNc5YwsFkllDKcAG9RPJT8 +HWFOcQarm6eAv8F50dCks+NAcbfTHoOTXYCjlPMAUzoRPUlc1H4YiyMzali+dzsu +i7u2dK8kpsYzQ40WqkLcA3OV7MD2Ip9sk9vyBzxxi8QZIBuDPBcSIOEHLPz3MFzu +38MeoxDozztBTzGKQzP09wtnb2+s56lfOywWoaHZiHvqoAlCRvF5zdQlI+qNo5ZG +W3gzFcY1UxuaOB7Lg4p+MRD0lWTA4J4vGiIzgY9S6hd4siLlXycmbKkxUrXTaeC8 +PdmFfxe5Oy2iHgW//s0IZ+D/Q0Zgt1E4Y8rmtnpfzKga2nu/J/gSUlqYFgPju/PV +Hy+U0l239VYXVjxpC/7EUwO4ayGLktCPuOqYK8pS/jh5KP/oZxIJa4TKmoJNN8h+ +KOeIHI0mEc2BPYEgl0j/E3E1XnG5lxkzgYzwVQlrIzPJsbOYrCUfG4ZzcV4svFGn +7/4kIHufTWI1pSnfmTs/dYzHnECbqNL3JVFG3JsWjuuhygksP54i2hwEl9zBm6CM +p+7bm8mJlvKRuOJnPscDPDCb7nW6MhejY3vtzgE5aNpw7yjMj/KkJ3zUxqa8/XNU +3oT1vgEil5feall45YeNCKHVgvBSNAPR2a2nQmtXC5H1rXLrobUgagCBKAykwVjb +eE7QV6dF4pwIyo+ZPV8uWotR/OuKJWpiWU2cTqN2rlekqPkWpdWa3ZeDgLW8j6xe +hJ/j3fLpSd5avKz9n+NIBMewwfGlFH7BB5KzBoDQZJCxFwFrStcmy7/2lc61881s +kGLl2mJCpOV9o7oKEyy4Q2D74cQg7CV6aEIcRIyDtf/DHiNc2uauEqyCcEK43CC4 +i7kQUvgFpirRDW8lvjicOQtBaw8txUa6vIA7LsnS7/ylS/y7qmExQ/qGGKVuL6jZ +M4NLWr1cgfE9Nb2gCK0RkZHDRG6iHjzvV66HwQM0p0hf+cxXXERTG+v4aSEqfx8V +4mbRZoeJj8O3wyRhSyl22CUnwTMv8CK2AAbqF5p5w1POPlWtWbrljIV3B3BRnAYa +u1Yv9L7RMc4zGNyeMkgIYF2IarqIkuh32m2TxJ2ifPAkbgu1mRx9OOCTENSdQCCX +6OF2Se1lCm4ylS4ov9MxitQDLJdSmyGDcoaxFdAilZBvbtz9LJE+kwr2qZdszndI +JaiQ26Ft4E6pCpe238BB4woF+rD0Ds18ySy88oxlKnOmKj0kY7UTwSyqB3EEbcNi +r17JbUFPO+0ktu8z5BhdtYeaOPuN9bx0U+H5SDeDUZzjlMrBn8BmZvfAhIg5ov75 +LuiHG2sdy/fuhFsz0dTZ+3fYncTPK/jepV+ZtbRaNNoCPJQx87MUquWxQTh4I9ee +cmxMGg9viRysyfyTTzkucX04i/vAfY1QnJKAfrF4nHoCp+hUUslqL3MpleLKwHBO +WYFiyIXH5TYqlsD4GihlrWY7NJ3iYT1KAjerkmAxMzf+RfANhejoiEpmXh3ERZoD +Ma5gUzFeDlJA6mQxIWXjktbQpcArWhLoXsovpZXJrW4QNPoSem0FCYlpnYL+ue9e +ZOANFYeDntpubIwE0u1QNsUjXOtYErl4fPP/vi5Z8aKoftwHdXA/xJqB7EJxhHai +28JI8dfYPKKPnRQtTIhxGFy/EbtjmFq4Iym7SOuDjGGFwfn/T6XkBbx+vMPvfnO4 +0wZHtufixei9ROJLrwFY0ZBoMcs3BW5dl4y23gB1kkI/4yrSU29D/Ml5RVl53eOC +D7a/X+oC6fhBsA488tIotPnZb5OVjuTVottdPygmW+rU3JZPQ4AHxymiLSP+9c+Q +FoeuCM1em+TGHFQFls2oUUjUGH5mUt+KTJdgU71nOLMl2GWGsUYErMWOwAqY1VBT +iIKBinugO7LV9e6AGqyB4ZDage6nytueroSwfpeae6/CcIANB10p67UistI7fofA +BAsNhDzoJBMsoiHuB1SnTMR15id3BDMv2IknKs22typ00DodzNEpwOcVgkceZTZV +M2lYksxFuOgjraBhFHPGHUtqnnlD/v6KXlJAU0m9Rp1GMaH4AY84mvsgBqCW4RRC +aIhbp/+oVBcW2CT0301R8orpUOpoHhYaurgjf9hcgL2tc/flNxUX5rkHwbjse04J +rENenqhYdRa4UdyvL7g2UXVWJV1VrOiNb/0zSw9E3NM1TQZ9M9z5o9LAXjDI20PI +quHHlk7sPJX9txbZyKKsY0SObguCB2uUt/civinqGKQxSys1+w7xakkxV3T6WXH8 +auGT6bqHySMGFcdBrb/g2Bi7bdcW1ACoSBIkpBT7OE0UDiZK5w8nR0B/iQFgV6BM +fLIndYjxwQRbuIRY2ea3aiNt0EdG4wO4b3Nrqx6rdek= +`pragma protect end_protected + +//pragma protect end + + +`timescale 1 ns / 1 ns +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +DOiPrSoOsOWFMnUIePF5KkkuP9M9CD3sIOJUMse5YjGpsWljrKw3wVgiaNNbbKIA +tZZ89fOVGIkVEtqDKovfN9hhA0AvJ8mf4/+brMg7PR5hv4fEfoTvaSiSOjxminpj +hDAU9j9J0EeKG8IbY8UBCawYm3GdcS+QXpoDDPl8pGbWFzEtgpqHwLPNdotkODuL +Cy/jYYjISPMG6+XBTCDGPlB5wHTuXk4r+btUx0HJQC86NboLhzI5xocnTZkES5xw +eOtqkXEjljvu/nu/NhhumVFQWtjfe6VAKlLnz9mcqkTlGcJBfXBEcJuVurHCods7 +hizyF/UB7hJKgVj5ZWx4uQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 13568 ) +`pragma protect data_block +Vj8vE3xLVzvw27QQ44bZ2zywreLuPxzb3fPXfP14qyoFQM3H+xA9qigVzMNWUD4N +ORBewg3/lJILIjWK5K0RcF/it1gdkXzzp2leuIQM0hT0eLiBdJwsRhuIbqpf0hHO +Hl7rgQWznqwcU4x2VEuzNj4SmOvP1qrymLItkEL4BuhLora2iGN5wCqJicpy5R/P +JMevjx1kDWakIzoChrsznItkUg1bEJUih0/3Py1PLWvVI+WaJ8Njc4HWGDpDeJ80 +SSYIHHEBFckS1DQSOXqHr9FdhqAk/qNxojOrb3+mBRcibwmpgivfH9ftYpStzC5G +xo2a+ftIH2AWV4/SabJIYwNrRlN9l4ThLouwSwT6u5cimsAegrLrOC9XFSqTcqnQ +x5eqmpE2pItMPml1YbxIqjyLCND/ATjJ6eGJuuLU6pOz6lWhbayLPn+jGrJdk0se +J3Q8iJLOAa2GpxHyfdsIyItbpg/ZR7DjGDocjQfU0vnqRSvPGCpjkToiW80LHokw +raxMIEHkwQK1OHsICbp7KqWi7DD49dYTehT4K7JZeCtViSTe3USPrpwLJo1Ab0m7 +iKIzW0j5fM70z62o893Rr8JFQB10jlGPe8OxwPCdU413oMz0m0MUG+DgXfHideUa +6f3Y47Dg9w+hc52jaMGIAo+Xe6GMbyTxZ1WxpuBGMHorD2aXFJUep6DXS3DD2wTk +/0NQV8mLPGtCzuo6JGIihEmj5duwZVi7zuP+EtEm1t2VLm0ULg4U44JC904TjwCi +kRLNsd3gERmejv54N0AklYGq/fQbm6ulMZTmbMVIwXQVbwY/wbbHzddNTBncvFJW +6c6EVY83ul30bHj+lUOsqe011Php02GE3dpi39ZS+78IiFKH5Eb8f4IFJ4p1gr0x +F5xoqZn7qpHg3/hYsAlErv+kR6WIQh4CEKrHhbPkby+eyytZcG7rWLkfcElddCkm +FbWxAqfg/7qjL2J9IkznKnXXOTn/kRFEFKvoAlxEgv9/oWMP8nAI9+tyOIyJEga2 +FEjIJF5BUk7/6Nt7vOaP1eO7cT411punsp4ikUV2V+KyIJcGsW1dbuKbn56qqyvH +EsvLtOxkGKoIptwTyyg8SgLHoUwR2xxRebgCDpWZqkpvLnkvZZP94NLZVLOOsODM +WEeym1J7aTWYlXllJ/m1kUp+vu2yKB9gbHPvztJgjpKAMqXuzcStpiKdWfpS57VO +eBmUklDDhDkiTwT8uDxeJr+ZCBnzdCitqHWpk+V3eU8lwetbyvmQd7o7QcF2tOyp +tg3rnIO6HT1+BMWWUZCrrZa2OGNqIUboW5bfyt3PIatq0zXoemDPsJgyt0KNlm7N +l323wCUit/DO7dvHf0MGwFB9eLpFyiESZng4uZWDRXVhttCC/JJuua1FC1PF/kQv +L/uT3YmB1RqQ3oGju4aJbEoUBNKK6bH9Uymr3d0L32aG12iag/yvDHodmJQuctU8 +BYMmW6rszqpzH9RJLYGzYZPpWn38F2LkHGAHEKvdqvFPW18SvuqBkcMaBoCkDSNG +lzCXOVVRDFgnLu3wTds5l4NfnpZYIIhctTvbI6EbhGzK6TBJYUW3Ps41MsQ9IXSR +R9rY+atzWV227rlA0elsVDOI+fLECkW6eegEWMDNqYHJmTMnELgEC6wCx3tKzvfo +YtC+iq5cbSfpXQlBBfCC49x0kRRX0Y3Z1KYa09v8a308f+ZNYpbnrnmpdHvAKKXr +IoiBNgzsRMk9NWbGF02UiD0cABomDRCLmXY+0I8d1i/oAa/7mV/ypnaga6WSevOb +HyhoP3Ow618+KEJr8iMHFi8445w377jsKgMbnaw03iSGMc5UPqnfVhAlQ2V/GEqU +GH2k7KkkczOHl7P39lAGP7oT9/o6Y2U0v6fz+SDhx6cYcCRBYgtjL2C7LC7ZEGO7 +Y7rPwvmsE4fswMVo+SHJjiedzPUW0RNsXzRYxAOIBXyQZHG0BOoaibQVdw7hSa/Q ++kIkEI0t5roGDi9SURd1c9o9rSbMjQuv+S1JhfnZiLG4HbrHArem9X6sfhTPmCHh +lD9CFM98GDWloeK6p2rpobGD5J5uwRDEpMKKRcWmLH0RNg1kwY+Dtru5rjUcURuI +W8TkCMgnk7br9+wQG9pSvge/FoGs99zDtb86OgZVEBrz0q7pY0wnQG0x1Qai7D/y +MJRg2lsn1lJnLUiU68Nqm6PXRbKYxVUuEqiW3CeHW/ZzWl6sowZS2ovm6U6L3dWb +bTtpHo9LOWriodHi4Kx+ymcr0Gcww21xwAbPCzRmunhC/qWbwDfcFEAUe+8GpkdT +H7wOA4HUuHytgoPDiY4p072aNuUuJGd+rbbTCVw6MMy4lg3yx5KW7KAHAEigBD/l +NG0fgEI14rxnLRdG89o04b7irZ6gJHV3Y/Df/CILd8xM4JpHCsA0caIjapDvDStG +E8C2APF3fxW5vb58BqgRloHNOebMgxCDVNvT5/eckj0AurBwEsz9qvXGwTrYjaur +1QgRfeqD26CG2GBLWUfmshCevm3WwLP7AFz2zevUmPp3dOMJyTzRnPAw5rUsqK0B ++wqxTtAVBGpzzUpo4XX6ZecR39GSV5xmpZwpZyscvtX9fAvHCX4gP/tDgNqbrF/t +Y1zNR5VY1F60OYLzNmjC8sKIX9A++gwKlCLWch106gIUdnUFCYPJBNLRt9k1u3ms +o7JO5X5geg6rSQfTUb/LTerqZ5IFWRNal8e0bw/BjeuRV6OjWIcVNmPTRu7kKU/3 +S7pJAonfBAr3WD7+oUtQpOubgZOiyLiEmGchAWgym30TkEiIaHytrdEp43TNzNK7 +c5sExHzhdc/CQznIyH07MGKO54Pk4SN3StEbPqUTKttLL5+9AI3ztA6v8c6H2S8j +EKPWgdbMzWylkI4mcCYv96zMyAk649IdaTRdR1WJu3UuAy0Nj8EYInvJ70kmWNnh +DazBFlSQlzc6ZfcNiYNtDItAh/dU0BwojEHG4V+K3mvgiBMyfR8YbMayxD/zdtb8 +95OG+98xV1YJBvMq5+v0O3Sa3L7G5DHD4rHVJUHiyy8LmhSEvEjsuU94ATX7s8Ih +7TCqglgT1TktpzhkBZNAAFXe8+hCVEsZTHP0TchXacAhb81V7cCGju2OnaHuioRP +qxf1wy0nm8AzscOPw0IZ9pqDO01Y5RZXX9v59oUsKPWT3+DxDR0cmcyYeuPHWoaJ +hxtd9KYHJPknCXW0X89JohcsQyey9cW4Wz3l70+uty2dC/BkOzHjMIuwlHFPIM3V +fz/Xf3eANU120acvI1PGolOCREyY/7CKu+nN3SNL5RwgG+xVV4+NcNT2b3LaCNd5 +UmE8ST9+49eQIPxjvARZq0cqT61di/kNxTFkM29Whn/IyVY9twb+vcEA8OtZyFKu +v+4qxW5TJ24t9pOsDidpkvivIViJpIGJPKR2M99si5Eu61Xh3Hjq2nwnGN9EJPUO +LMylEgSjxuhYqU822jnBKiWGBV4lTs5Ar7TwYtv6pL5G2rLeBvFpRKNcdMgFa8CQ +zH9YpBUCv3GpPT3q9D2fOZJfM0szdxvxI/b9TPrDdkky5HNjK5/ahdHPdhbroxRs +HksYmCz9rOVW6O/CFJwuvA0KWMSgc0hBXrm02owI3Wh3zaKA6BpY/BQ4qZ5OIXNF +R5/nYsG6wc4SViqmgsgnEZIOmHIxm+zzh33kHCNL1q0FBHDhgP+DUMKy+p4wdZVs +PjZc71t+3WeuCFiN7hpwPZsXOsqZWnbhdbLk9Bl9wkbdR61pW6b6AiR/NzikBbuL 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+FWpGHJMBKkGYumEfq3QUkx8FolOiUsx363e4iloH6K1I78+nzKdMru+jn3aEUmxY +wupdht4Wvzt4Qx+5e6NFbc4MhxLHgPE+/8509jT3hPAKypGcySfLkxOpiSkoTIUs +JQ0lI7fNIcqjMLb9wp0tYtqeJvAc8CMHHd1fkV1tvy5/2jlHk6vifZohEuHB3taD +XSdWHaNlMP1qdsi8NmgMS8xSCg51XnHhZuR+K1WRQdhqa4OiY1ZlxeYTXVtDHJ0p +ufLl5i98YD+dYTPM1SK+/JH1IPjtt37nJW7Mz7ZcQuWBn/oZZC3+61tivpRYu4mc +8YYYa1szyhl3L5zvhHKNO6gY3MZBv5WT0uLLhr3wQHkGHsn9+EtDhCrCaONdkT5r +6mGZzfRBOe6B7h3Gwc6AVPODxE2SSS4G8PtMvfDFD4yTPYF/E5OBd5VJ+u9SGGoJ +Bn6sYRxBiZdEBlMLysmtAznaPistaVRigrAeaa03xqNLNkMXL0S3EaQe5KdY7uz6 +t0PcQrNDUoZtYmRu21JUlQ1jih6+/r+oNw0d6WpP2lpW1DoRchC1W8hQK4+WFoHf +Q6TIeO5imAISW5fOiFftw1xgLcfKgnReP8Yt1+ULq9XfMxQWMJx2c8U0upF8nmfQ +om431jc6z7kUiYmPZ7bmWhvrOnzXyogJMA7Tkx+E9IXAgb3E7gvqknomjLyiS6Bi +m/pWWB3lVhBJJSKpJIqN3+ksko28L2oFHeJv0vf1nLP8H0BDUvKsvMD+D4WB9Xe5 +4zyTYXLX7cmkJBF7BLAK/WUnyy22wI/ZOc/gojq2pb1r1p8Evvg/K60+m0KHcZK0 +lhOuros4TEutHVos2cTkcsn82LCeRyESZ8Zkw56EDZ0= +`pragma protect end_protected + +//pragma protect end + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Ti375C529_devkit/ip/gSDHC/gSDHC_define.vh b/Ti375C529_devkit/ip/gSDHC/gSDHC_define.vh new file mode 100644 index 0000000..a261877 --- /dev/null +++ b/Ti375C529_devkit/ip/gSDHC/gSDHC_define.vh @@ -0,0 +1,47 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 6.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam DATA_BUFFER_DEPTH = 512; +localparam ADMA_DATA_WIDTH = 128; diff --git a/Ti375C529_devkit/ip/gSDHC/gSDHC_tmpl.v b/Ti375C529_devkit/ip/gSDHC/gSDHC_tmpl.v new file mode 100644 index 0000000..84b81fc --- /dev/null +++ b/Ti375C529_devkit/ip/gSDHC/gSDHC_tmpl.v @@ -0,0 +1,111 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 6.0 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +gSDHC u_gSDHC +( + .sd_rst ( sd_rst ), + .sd_base_clk ( sd_base_clk ), + .sd_int ( sd_int ), + .sd_cd_n ( sd_cd_n ), + .sd_wp ( sd_wp ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_aclk ( s_axi_aclk ), + .s_axi_awready ( s_axi_awready ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_wready ( s_axi_wready ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_bready ( s_axi_bready ), + .s_axi_arready ( s_axi_arready ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rready ( s_axi_rready ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_clk ( m_axi_clk ), + .m_axi_awlen ( m_axi_awlen ), + .m_axi_awready ( m_axi_awready ), + .m_axi_awsize ( m_axi_awsize ), + .m_axi_awcache ( m_axi_awcache ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awprot ( m_axi_awprot ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wready ( m_axi_wready ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_bready ( m_axi_bready ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlen ( m_axi_arlen ), + .m_axi_arsize ( m_axi_arsize ), + .m_axi_arburst ( m_axi_arburst ), + .m_axi_arprot ( m_axi_arprot ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arcache ( m_axi_arcache ), + .m_axi_arready ( m_axi_arready ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_rready ( m_axi_rready ), + .sd_clk_hi ( sd_clk_hi ), + .sd_clk_lo ( sd_clk_lo ), + .sd_cmd_i ( sd_cmd_i ), + .sd_cmd_o ( sd_cmd_o ), + .sd_cmd_oe ( sd_cmd_oe ), + .sd_dat_i ( sd_dat_i ), + .sd_dat_o ( sd_dat_o ), + .sd_dat_oe ( sd_dat_oe ), + .m_axi_awburst ( m_axi_awburst ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_rdata ( m_axi_rdata ), + .s_axi_wstrb ( s_axi_wstrb ) +); diff --git a/Ti375C529_devkit/ip/gSDHC/gSDHC_tmpl.vhd b/Ti375C529_devkit/ip/gSDHC/gSDHC_tmpl.vhd new file mode 100644 index 0000000..98a4d2b --- /dev/null +++ b/Ti375C529_devkit/ip/gSDHC/gSDHC_tmpl.vhd @@ -0,0 +1,177 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +component gSDHC is +port ( + sd_rst : in std_logic; + sd_base_clk : in std_logic; + sd_int : out std_logic; + sd_cd_n : in std_logic; + sd_wp : in std_logic; + s_axi_awaddr : in std_logic_vector(9 downto 0); + s_axi_aclk : in std_logic; + s_axi_awready : out std_logic; + s_axi_awvalid : in std_logic; + s_axi_wdata : in std_logic_vector(31 downto 0); + s_axi_wready : out std_logic; + s_axi_wvalid : in std_logic; + s_axi_bresp : out std_logic_vector(1 downto 0); + s_axi_bvalid : out std_logic; + s_axi_araddr : in std_logic_vector(9 downto 0); + s_axi_bready : in std_logic; + s_axi_arready : out std_logic; + s_axi_arvalid : in std_logic; + s_axi_rresp : out std_logic_vector(1 downto 0); + s_axi_rdata : out std_logic_vector(31 downto 0); + s_axi_rvalid : out std_logic; + s_axi_rready : in std_logic; + m_axi_awaddr : out std_logic_vector(31 downto 0); + m_axi_awvalid : out std_logic; + m_axi_clk : in std_logic; + m_axi_awlen : out std_logic_vector(7 downto 0); + m_axi_awready : in std_logic; + m_axi_awsize : out std_logic_vector(2 downto 0); + m_axi_awcache : out std_logic_vector(3 downto 0); + m_axi_awlock : out std_logic_vector(1 downto 0); + m_axi_awprot : out std_logic_vector(2 downto 0); + m_axi_wlast : out std_logic; + m_axi_wvalid : out std_logic; + m_axi_wready : in std_logic; + m_axi_bresp : in std_logic_vector(1 downto 0); + m_axi_bvalid : in std_logic; + m_axi_bready : out std_logic; + m_axi_arvalid : out std_logic; + m_axi_araddr : out std_logic_vector(31 downto 0); + m_axi_arlen : out std_logic_vector(7 downto 0); + m_axi_arsize : out std_logic_vector(2 downto 0); + m_axi_arburst : out std_logic_vector(1 downto 0); + m_axi_arprot : out std_logic_vector(2 downto 0); + m_axi_arlock : out std_logic_vector(1 downto 0); + m_axi_arcache : out std_logic_vector(3 downto 0); + m_axi_arready : in std_logic; + m_axi_rvalid : in std_logic; + m_axi_rlast : in std_logic; + m_axi_rresp : in std_logic_vector(1 downto 0); + m_axi_rready : out std_logic; + sd_clk_hi : out std_logic; + sd_clk_lo : out std_logic; + sd_cmd_i : in std_logic; + sd_cmd_o : out std_logic; + sd_cmd_oe : out std_logic; + sd_dat_i : in std_logic_vector(3 downto 0); + sd_dat_o : out std_logic_vector(3 downto 0); + sd_dat_oe : out std_logic; + m_axi_awburst : out std_logic_vector(1 downto 0); + m_axi_wdata : out std_logic_vector(127 downto 0); + m_axi_wstrb : out std_logic_vector(15 downto 0); + m_axi_rdata : in std_logic_vector(127 downto 0); + s_axi_wstrb : in std_logic_vector(3 downto 0) +); +end component gSDHC; + +---------------------- End COMPONENT Declaration ------------ +------------- Begin Cut here for INSTANTIATION Template ----- +u_gSDHC : gSDHC +port map ( + sd_rst => sd_rst, + sd_base_clk => sd_base_clk, + sd_int => sd_int, + sd_cd_n => sd_cd_n, + sd_wp => sd_wp, + s_axi_awaddr => s_axi_awaddr, + s_axi_aclk => s_axi_aclk, + s_axi_awready => s_axi_awready, + s_axi_awvalid => s_axi_awvalid, + s_axi_wdata => s_axi_wdata, + s_axi_wready => s_axi_wready, + s_axi_wvalid => s_axi_wvalid, + s_axi_bresp => s_axi_bresp, + s_axi_bvalid => s_axi_bvalid, + s_axi_araddr => s_axi_araddr, + s_axi_bready => s_axi_bready, + s_axi_arready => s_axi_arready, + s_axi_arvalid => s_axi_arvalid, + s_axi_rresp => s_axi_rresp, + s_axi_rdata => s_axi_rdata, + s_axi_rvalid => s_axi_rvalid, + s_axi_rready => s_axi_rready, + m_axi_awaddr => m_axi_awaddr, + m_axi_awvalid => m_axi_awvalid, + m_axi_clk => m_axi_clk, + m_axi_awlen => m_axi_awlen, + m_axi_awready => m_axi_awready, + m_axi_awsize => m_axi_awsize, + m_axi_awcache => m_axi_awcache, + m_axi_awlock => m_axi_awlock, + m_axi_awprot => m_axi_awprot, + m_axi_wlast => m_axi_wlast, + m_axi_wvalid => m_axi_wvalid, + m_axi_wready => m_axi_wready, + m_axi_bresp => m_axi_bresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_bready => m_axi_bready, + m_axi_arvalid => m_axi_arvalid, + m_axi_araddr => m_axi_araddr, + m_axi_arlen => m_axi_arlen, + m_axi_arsize => m_axi_arsize, + m_axi_arburst => m_axi_arburst, + m_axi_arprot => m_axi_arprot, + m_axi_arlock => m_axi_arlock, + m_axi_arcache => m_axi_arcache, + m_axi_arready => m_axi_arready, + m_axi_rvalid => m_axi_rvalid, + m_axi_rlast => m_axi_rlast, + m_axi_rresp => m_axi_rresp, + m_axi_rready => m_axi_rready, + sd_clk_hi => sd_clk_hi, + sd_clk_lo => sd_clk_lo, + sd_cmd_i => sd_cmd_i, + sd_cmd_o => sd_cmd_o, + sd_cmd_oe => sd_cmd_oe, + sd_dat_i => sd_dat_i, + sd_dat_o => sd_dat_o, + sd_dat_oe => sd_dat_oe, + m_axi_awburst => m_axi_awburst, + m_axi_wdata => m_axi_wdata, + m_axi_wstrb => m_axi_wstrb, + m_axi_rdata => m_axi_rdata, + s_axi_wstrb => s_axi_wstrb +); + +------------------------ End INSTANTIATION Template --------- diff --git a/Ti375C529_devkit/ip/gSDHC/ipm/component.pickle b/Ti375C529_devkit/ip/gSDHC/ipm/component.pickle new file mode 100644 index 0000000..d292d37 Binary files /dev/null and b/Ti375C529_devkit/ip/gSDHC/ipm/component.pickle differ diff --git a/Ti375C529_devkit/ip/gSDHC/ipm/graph.pickle b/Ti375C529_devkit/ip/gSDHC/ipm/graph.pickle new file mode 100644 index 0000000..6ca87a2 Binary files /dev/null and b/Ti375C529_devkit/ip/gSDHC/ipm/graph.pickle differ diff --git a/Ti375C529_devkit/ip/gSDHC/settings.json b/Ti375C529_devkit/ip/gSDHC/settings.json new file mode 100644 index 0000000..114b4b5 --- /dev/null +++ b/Ti375C529_devkit/ip/gSDHC/settings.json @@ -0,0 +1,31 @@ +{ + "args": [ + "-o", + "gSDHC", + "--base_path", + "/projects/SSE/llching/repo/efx_IP_master/efx_IP/efx_hard_soc/fpga/Ti375C529_devkit/ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "memory_controller", + "name": "efx_sd_host_controller", + "version": "6.0" + } + ], + "conf": { + "DATA_BUFFER_DEPTH": "512", + "ADMA_DATA_WIDTH": "128" + }, + "output": { + "external_script_reference_design": [], + "external_source_source": [ + "gSDHC/gSDHC_define.vh", + "gSDHC/gSDHC.v", + "gSDHC/gSDHC_tmpl.v", + "gSDHC/gSDHC_tmpl.vhd" + ] + }, + "ooc_synthesis": {}, + "sw_version": "2025.2.272", + "generated_date": "2025-10-16T09:29:16.536987+00:00" +} \ No newline at end of file diff --git a/Ti375C529_devkit/ip/gTSE/gTSE.sv b/Ti375C529_devkit/ip/gTSE/gTSE.sv new file mode 100644 index 0000000..7673519 --- /dev/null +++ b/Ti375C529_devkit/ip/gTSE/gTSE.sv @@ -0,0 +1,9374 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2026.1.132 +// IP Version: 7.3 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2026 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _7bbe2a96a6f546f79c19bc5e36554e32 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module gTSE +( + input mac_reset, + input proto_reset, + output rx_mac_aclk, + input tx_mac_aclk, + output [2:0] eth_speed, + input rx_axis_clk, + output rx_axis_mac_tuser, + output rx_axis_mac_tlast, + output rx_axis_mac_tvalid, + input rx_axis_mac_tready, + input tx_axis_clk, + input tx_axis_mac_tvalid, + input tx_axis_mac_tlast, + input tx_axis_mac_tuser, + output tx_axis_mac_tready, + output [3:0] rgmii_txd_HI, + output [3:0] rgmii_txd_LO, + output rgmii_tx_ctl_HI, + output rgmii_tx_ctl_LO, + output rgmii_txc_HI, + output rgmii_txc_LO, + input [3:0] rgmii_rxd_HI, + input [3:0] rgmii_rxd_LO, + input rgmii_rx_ctl_HI, + input rgmii_rx_ctl_LO, + input rgmii_rxc, + input s_axi_aclk, + output [7:0] rx_axis_mac_tdata, + input [7:0] tx_axis_mac_tdata, + input [0:0] tx_axis_mac_tstrb, + output [0:0] rx_axis_mac_tstrb, + output MdoEn, + output Mdo, + input Mdi, + output Mdc, + input [9:0] s_axi_araddr, + output s_axi_arready, + input s_axi_arvalid, + input [9:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_awvalid, + input s_axi_bready, + output [1:0] s_axi_bresp, + output s_axi_bvalid, + output [31:0] s_axi_rdata, + input s_axi_rready, + output [1:0] s_axi_rresp, + output s_axi_rvalid, + input [31:0] s_axi_wdata, + output s_axi_wready, + input s_axi_wvalid +); +`IP_MODULE_NAME(efx_mac1gbe) +#( + .VERSION (16), + .TXFIFO_EN (1'b1), + .RXFIFO_EN (1'b1), + .TXFIFO_DTH (4096), + .RXFIFO_DTH (4096), + .PHY_INTF_MODE (0), + .AXIS_DW (8), + .RGMII_RXC_EDGE (1'b1), + .RGMII_TXC_DLY (1'b1), + .INTER_PACKET_GAP (6'd12), + .MTU_FRAME_LENGTH (16'd1518), + .MAC_SOURCE_ADDRESS (48'd0), + .ENABLE_BROADCAST_FILTERING (1'b1), + .LOOPBACK_EN (1'b1), + .APBIF (1'b0), + .FAMILY ("TITANIUM") +) +u_efx_mac1gbe +( + .mac_reset ( mac_reset ), + .proto_reset ( proto_reset ), + .rx_mac_aclk ( rx_mac_aclk ), + .tx_mac_aclk ( tx_mac_aclk ), + .eth_speed ( eth_speed ), + .rx_axis_clk ( rx_axis_clk ), + .rx_axis_mac_tuser ( rx_axis_mac_tuser ), + .rx_axis_mac_tlast ( rx_axis_mac_tlast ), + .rx_axis_mac_tvalid ( rx_axis_mac_tvalid ), + .rx_axis_mac_tready ( rx_axis_mac_tready ), + .tx_axis_clk ( tx_axis_clk ), + .tx_axis_mac_tvalid ( tx_axis_mac_tvalid ), + .tx_axis_mac_tlast ( tx_axis_mac_tlast ), + .tx_axis_mac_tuser ( tx_axis_mac_tuser ), + .tx_axis_mac_tready ( tx_axis_mac_tready ), + .rgmii_txd_HI ( rgmii_txd_HI ), + .rgmii_txd_LO ( rgmii_txd_LO ), + .rgmii_tx_ctl_HI ( rgmii_tx_ctl_HI ), + .rgmii_tx_ctl_LO ( rgmii_tx_ctl_LO ), + .rgmii_txc_HI ( rgmii_txc_HI ), + .rgmii_txc_LO ( rgmii_txc_LO ), + .rgmii_rxd_HI ( rgmii_rxd_HI ), + .rgmii_rxd_LO ( rgmii_rxd_LO ), + .rgmii_rx_ctl_HI ( rgmii_rx_ctl_HI ), + .rgmii_rx_ctl_LO ( rgmii_rx_ctl_LO ), + .rgmii_rxc ( rgmii_rxc ), + .s_axi_aclk ( s_axi_aclk ), + .rx_axis_mac_tdata ( rx_axis_mac_tdata ), + .tx_axis_mac_tdata ( tx_axis_mac_tdata ), + .tx_axis_mac_tstrb ( tx_axis_mac_tstrb ), + .rx_axis_mac_tstrb ( rx_axis_mac_tstrb ), + .MdoEn ( MdoEn ), + .Mdo ( Mdo ), + .Mdi ( Mdi ), + .Mdc ( Mdc ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arready ( s_axi_arready ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awready ( s_axi_awready ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rready ( s_axi_rready ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_wready ( s_axi_wready ), + .s_axi_wvalid ( s_axi_wvalid ) +); +endmodule + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_top) # ( + parameter FAMILY = "TRION", // New Param + parameter SYNC_CLK = 0, + parameter BYPASS_RESET_SYNC = 0, // New Param + parameter SYNC_STAGE = 2, // New Param + parameter MODE = "STANDARD", + parameter DEPTH = 512, // Reverted (Equivalent to WDATA_DEPTH) + parameter DATA_WIDTH = 32, // Reverted (Equivalent to WDATA_WIDTH) + parameter PIPELINE_REG = 1, // Reverted (By default is ON) + parameter OPTIONAL_FLAGS = 1, // Reverted + parameter OUTPUT_REG = 0, + parameter PROGRAMMABLE_FULL = "STATIC_DUAL", // Set to "NONE" if not require this feature + parameter PROG_FULL_ASSERT = 27, + parameter PROG_FULL_NEGATE = 23, + parameter PROGRAMMABLE_EMPTY = "STATIC_DUAL", // Set to "NONE" if not require this feature + parameter PROG_EMPTY_ASSERT = 5, + parameter PROG_EMPTY_NEGATE = 7, + parameter ALMOST_FLAG = OPTIONAL_FLAGS, + parameter HANDSHAKE_FLAG = OPTIONAL_FLAGS, + parameter ASYM_WIDTH_RATIO = 4, + parameter WADDR_WIDTH = depth2width(DEPTH), + parameter RDATA_WIDTH = rdwidthcompute(ASYM_WIDTH_RATIO,DATA_WIDTH), + parameter RD_DEPTH = rddepthcompute(DEPTH,DATA_WIDTH,RDATA_WIDTH), + parameter RADDR_WIDTH = depth2width(RD_DEPTH), + parameter ENDIANESS = 0, + parameter OVERFLOW_PROTECT = 1, + parameter UNDERFLOW_PROTECT = 1, + parameter RAM_STYLE = "block_ram" + +)( + input wire a_rst_i, + input wire a_wr_rst_i, + input wire a_rd_rst_i, + input wire clk_i, + input wire wr_clk_i, + input wire rd_clk_i, + input wire wr_en_i, + input wire rd_en_i, + input wire [DATA_WIDTH-1:0] wdata, + output wire almost_full_o, + output wire prog_full_o, + output wire full_o, + output wire overflow_o, + output wire wr_ack_o, + output wire [WADDR_WIDTH :0] datacount_o, + output wire [WADDR_WIDTH :0] wr_datacount_o, + output wire empty_o, + output wire almost_empty_o, + output wire prog_empty_o, + output wire underflow_o, + output wire rd_valid_o, + output wire [RDATA_WIDTH-1:0] rdata, + output wire [RADDR_WIDTH :0] rd_datacount_o, + output wire rst_busy +); + +localparam WR_DEPTH = DEPTH; +localparam WDATA_WIDTH = DATA_WIDTH; +localparam RAM_MUX_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? 32 : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? 16 : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH) ? 1 : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? 2 : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? 4 : + (RDATA_WIDTH <= WDATA_WIDTH*8) ? 8 : + (RDATA_WIDTH <= WDATA_WIDTH*16) ? 16 : 32; + +wire wr_rst_int; +wire rd_rst_int; +wire wr_en_int; +wire rd_en_int; +wire [WADDR_WIDTH-1:0] waddr; +wire [RADDR_WIDTH-1:0] raddr; +wire wr_clk_int; +wire rd_clk_int; +wire [WADDR_WIDTH :0] wr_datacount_int; +wire [RADDR_WIDTH :0] rd_datacount_int; + +generate + if (ASYM_WIDTH_RATIO == 4) begin + if (SYNC_CLK) begin + assign wr_clk_int = clk_i; + assign rd_clk_int = clk_i; + assign datacount_o = wr_datacount_int; + assign wr_datacount_o = {(WADDR_WIDTH+1){1'b0}}; + assign rd_datacount_o = {(RADDR_WIDTH+1){1'b0}}; + end + else begin + assign wr_clk_int = wr_clk_i; + assign rd_clk_int = rd_clk_i; + assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; + assign wr_datacount_o = wr_datacount_int; + assign rd_datacount_o = rd_datacount_int; + end + end + else begin + assign datacount_o = {(WADDR_WIDTH+1){1'b0}}; + assign wr_datacount_o = wr_datacount_int; + assign rd_datacount_o = rd_datacount_int; + if (SYNC_CLK) begin + assign wr_clk_int = clk_i; + assign rd_clk_int = clk_i; + end + else begin + assign wr_clk_int = wr_clk_i; + assign rd_clk_int = rd_clk_i; + end + end + + if (!SYNC_CLK) begin + //(* async_reg = "true" *) reg [1:0] wr_rst; + //(* async_reg = "true" *) reg [1:0] rd_rst; + // + //always @ (posedge wr_clk_int or posedge a_rst_i) begin + // if (a_rst_i) + // wr_rst <= 2'b11; + // else + // wr_rst <= {wr_rst[0],1'b0}; + //end + // + //always @ (posedge rd_clk_int or posedge a_rst_i) begin + // if (a_rst_i) + // rd_rst <= 2'b11; + // else + // rd_rst <= {rd_rst[0],1'b0}; + //end + + + if (BYPASS_RESET_SYNC) begin + assign wr_rst_int = a_wr_rst_i; + assign rd_rst_int = a_rd_rst_i; + assign rst_busy = 1'b0; + end + else begin + `IP_MODULE_NAME(efx_resetsync) #( + .ACTIVE_LOW (0) + ) efx_resetsync_wr_rst ( + .clk (wr_clk_int), + .reset (a_rst_i), + .d_o (wr_rst_int) + ); + + `IP_MODULE_NAME(efx_resetsync) #( + .ACTIVE_LOW (0) + ) efx_resetsync_rd_rst ( + .clk (rd_clk_int), + .reset (a_rst_i), + .d_o (rd_rst_int) + ); + assign rst_busy = wr_rst_int | rd_rst_int; + end + + end + else begin + //(* async_reg = "true" *) reg [1:0] a_rst; + // + //always @ (posedge clk_i or posedge a_rst_i) begin + // if (a_rst_i) + // a_rst <= 2'b11; + // else + // a_rst <= {a_rst[0],1'b0}; + //end + wire a_rst; + + `IP_MODULE_NAME(efx_resetsync) #( + .ACTIVE_LOW (0) + ) efx_resetsync_a_rst ( + .clk (clk_i), + .reset (a_rst_i), + .d_o (a_rst) + ); + + if (BYPASS_RESET_SYNC) begin + assign wr_rst_int = a_rst_i; + assign rd_rst_int = a_rst_i; + assign rst_busy = 1'b0; + end + else begin + assign wr_rst_int = a_rst; + assign rd_rst_int = a_rst; + assign rst_busy = wr_rst_int | rd_rst_int; + end + end +endgenerate + +`IP_MODULE_NAME(efx_fifo_ram) # ( + .FAMILY (FAMILY), + .WR_DEPTH (WR_DEPTH), + .RD_DEPTH (RD_DEPTH), + .WDATA_WIDTH (WDATA_WIDTH), + .RDATA_WIDTH (RDATA_WIDTH), + .WADDR_WIDTH (WADDR_WIDTH), + .RADDR_WIDTH (RADDR_WIDTH), + .OUTPUT_REG (OUTPUT_REG), + .RAM_MUX_RATIO (RAM_MUX_RATIO), + .ENDIANESS (ENDIANESS), + .RAM_STYLE (RAM_STYLE) +) xefx_fifo_ram ( + .wdata (wdata), + .waddr (waddr), + .raddr (raddr), + .we (wr_en_int), + .re (rd_en_int), + .wclk (wr_clk_int), + .rclk (rd_clk_int), + .rdata (rdata) +); + +`IP_MODULE_NAME(efx_fifo_ctl) # ( + .SYNC_CLK (SYNC_CLK), + .SYNC_STAGE (SYNC_STAGE), + .MODE (MODE), + .WR_DEPTH (WR_DEPTH), + .WADDR_WIDTH (WADDR_WIDTH), + .RADDR_WIDTH (RADDR_WIDTH), + .ASYM_WIDTH_RATIO (ASYM_WIDTH_RATIO), + .RAM_MUX_RATIO (RAM_MUX_RATIO), + .PIPELINE_REG (PIPELINE_REG), + .ALMOST_FLAG (ALMOST_FLAG), + .PROGRAMMABLE_FULL (PROGRAMMABLE_FULL), + .PROG_FULL_ASSERT (PROG_FULL_ASSERT), + .PROG_FULL_NEGATE (PROG_FULL_NEGATE), + .PROGRAMMABLE_EMPTY (PROGRAMMABLE_EMPTY), + .PROG_EMPTY_ASSERT (PROG_EMPTY_ASSERT), + .PROG_EMPTY_NEGATE (PROG_EMPTY_NEGATE), + .OUTPUT_REG (OUTPUT_REG), + .HANDSHAKE_FLAG (HANDSHAKE_FLAG), + .OVERFLOW_PROTECT (OVERFLOW_PROTECT), + .UNDERFLOW_PROTECT (UNDERFLOW_PROTECT) +) xefx_fifo_ctl ( + .wr_rst (wr_rst_int), + .rd_rst (rd_rst_int), + .wclk (wr_clk_int), + .rclk (rd_clk_int), + .we (wr_en_i), + .re (rd_en_i), + .wr_full (full_o), + .wr_ack (wr_ack_o), + .rd_empty (empty_o), + .wr_almost_full (almost_full_o), + .rd_almost_empty (almost_empty_o), + .wr_prog_full (prog_full_o), + .rd_prog_empty (prog_empty_o), + .wr_en_int (wr_en_int), + .rd_en_int (rd_en_int), + .waddr (waddr), + .raddr (raddr), + .wr_datacount (wr_datacount_int), + .rd_datacount (rd_datacount_int), + .rd_vld (rd_valid_o), + .wr_overflow (overflow_o), + .rd_underflow (underflow_o) +); + +function integer depth2width; +input [31:0] depth; +begin : fnDepth2Width + if (depth > 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian + parameter RAM_STYLE = "block_ram" +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + always @ (posedge wclk) begin + for (i=0; i 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / pipe_reg.v +// / / .' / +// __/ /.' / Description: +// __ \ / Parallel Pipelining Shift Register +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_datasync) #( + parameter STAGE = 32, + parameter WIDTH = 4 +) ( + input wire clk_i, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + +(* async_reg = "true" *) reg [WIDTH-1:0] pipe_reg [STAGE-1:0]; +integer i; + +always @(posedge clk_i) begin + for (i=STAGE-1; i>0; i = i - 1) begin + pipe_reg[i] <= pipe_reg[i-1]; + end + pipe_reg[0] <= d_i; +end +assign d_o = pipe_reg[STAGE-1]; + + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_resetsync) #( + parameter ASYNC_STAGE = 2, + parameter ACTIVE_LOW = 1 +) ( + input wire clk, + input wire reset, + output wire d_o +); + + +generate + if (ACTIVE_LOW == 1) begin: active_low + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (1), + .RST_VALUE (0) + ) efx_resetsync_active_low ( + .clk (clk), + .reset_n (reset), + .d_i (1'b1), + .d_o (d_o) + ); + end + else begin: active_high + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (0), + .RST_VALUE (1) + ) efx_resetsync_active_high ( + .clk (clk), + .reset_n (reset), + .d_i (1'b0), + .d_o (d_o) + ); + end +endgenerate + +endmodule + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_asyncreg) #( + parameter ASYNC_STAGE = 2, + parameter WIDTH = 4, + parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset + parameter RST_VALUE = 0, + parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance +) ( + input wire clk, + input wire reset_n, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + + + + + + + + + + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect author = "author-a" , author_info = "author-a-details" +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V +o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE +El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY +kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc +/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 +uYJaS5tuGEuFInBHa7oO8g== +`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 +fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa +rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq +PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL +DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w +K3OoKmk3zFeArSsql8B4/Q== +`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 ) +`pragma protect key_block +RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M +GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l +6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI= +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf +RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk +1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw +Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz +eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0 +2HflB1HYKxojQCcZU7qUgQ== +`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx +Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB +rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr +XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD +e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod +B2Zpo2FQ//YDRSAaEa9ksQ== +`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze +vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 +ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 +06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP +fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN +ZoPzFCMjGk5ZmMyIlytNCw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 ) +`pragma protect data_block +0d33xo/2RnBYy8BD6jq1J42m9u/75PA0owNvxlnr0TDOq7sF8XT6xouctVD1XQW2 +Ylwj0urY+dCJZku0aGRpcvb3H/nTlKVdEZOEl4QqB1gNGz/3mz75A3eudu5zgHEr +MaagjyQfDnoIqLWi1r5uTZrlS298IvNcGAJ+xXzpmkFmfG4Tk/5Jf2GPAPVtjREI +01kt8Go4CL1WNxBKcwm0xCiCchxvZ2oEtpERiC+7LUalgTJapIVoLFpvFv98229k +egvgF1KHNj0rAKedSG2Xo58TyA4iZXJJDdtgCxiKgu3Rimjno7l+ekApwmvx8n+p +yHkRGqetWfRhyE4A5q03RzOeSdA6NbCqijB3NPw/p58brAbA35rrjYpGIZXtZ4mU +De3As8VtD64nS2PRuf4/a2lIcDbwMjNTfMpN7iJfVBJ0/48tLHdetx592TLXenkF +GvAZ2yxoyBYzKctj4Keo+19Xp1UjVd3fr2MR3A7nmxLRKDA+upDxQ7ql8+pR7Moh +0b53/4Ri3Mkl+7EC1KXJNt2VbkZmcT7OAFIoPpibmcXS2R6DNVrhSKzfc2+TRM9r +mwRrJy9/R5RR+WGfw1S57Ho3wBPf4belj+Tfd7yhnwOVRXkTMq5M1BiigrGeeQ3q +z/hc1Kg8b/R+g7lnU0pqASnExPQW/DIMfH1RX75U68CAgaBAH22Vcbkoibp8sxyO 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+qIAT3WP49EeM+CQCp3D6Vxzm7Picq+RtwtbAXnnSQtvPcaSprODI089a0iR46Pp/ +4DLMUOLS+01HozXF1589YdqYep05No/Fp4eP2RdQxicYxK8d/OcvG7E8F1URVmAa +XdZxVa9caM3xYMWDZaiaOo6IZ+YM5VeZ4KxUblS1L1IlOnGOOZ3AiaLsHOh55ryc +Ei7EaFpheCmlTJyxUg8TdA== +`pragma protect end_protected + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ctl) # ( + parameter SYNC_CLK = 1, + parameter SYNC_STAGE = 2, + parameter MODE = "STANDARD", + parameter WR_DEPTH = 512, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter ASYM_WIDTH_RATIO = 4, + parameter RAM_MUX_RATIO = 1, + parameter PIPELINE_REG = 1, + parameter ALMOST_FLAG = 1, + parameter PROGRAMMABLE_FULL = "NONE", + parameter PROG_FULL_ASSERT = 0, + parameter PROG_FULL_NEGATE = 0, + parameter PROGRAMMABLE_EMPTY = "NONE", + parameter PROG_EMPTY_ASSERT = 0, + parameter PROG_EMPTY_NEGATE = 0, + parameter OUTPUT_REG = 0, + parameter HANDSHAKE_FLAG = 1, + parameter OVERFLOW_PROTECT = 0, + parameter UNDERFLOW_PROTECT = 0 +)( + input wire wr_rst, + input wire rd_rst, + input wire wclk, + input wire rclk, + input wire we, + input wire re, + output wire wr_full, + output reg wr_ack, + output wire wr_almost_full, + output wire rd_empty, + output wire rd_almost_empty, + output wire wr_prog_full, + output wire rd_prog_empty, + output wire wr_en_int, + output wire rd_en_int, + output wire [WADDR_WIDTH-1:0] waddr, + output wire [RADDR_WIDTH-1:0] raddr, + output wire [WADDR_WIDTH:0] wr_datacount, + output wire [RADDR_WIDTH:0] rd_datacount, + output wire rd_vld, + output reg wr_overflow, + output reg rd_underflow +); + +reg [WADDR_WIDTH:0] waddr_cntr; +reg [WADDR_WIDTH:0] waddr_cntr_r; +reg [RADDR_WIDTH:0] raddr_cntr; +reg rd_valid; + +wire [WADDR_WIDTH:0] waddr_int; +wire [RADDR_WIDTH:0] raddr_int; +wire rd_empty_int; +wire [WADDR_WIDTH:0] wr_datacount_int; +wire [RADDR_WIDTH:0] rd_datacount_int; + +assign waddr = waddr_cntr[WADDR_WIDTH-1:0]; +// NIC +wire [RADDR_WIDTH:0] ram_raddr; +assign raddr = (MODE == "FWFT") ? ram_raddr[RADDR_WIDTH-1:0] : raddr_cntr[RADDR_WIDTH-1:0]; +//assign raddr = raddr_cntr[RADDR_WIDTH-1:0]; +//assign wr_en_int = we & ~wr_full; +assign wr_en_int = OVERFLOW_PROTECT ? we & ~wr_full : we; + +assign wr_datacount = wr_datacount_int; +assign rd_datacount = ASYM_WIDTH_RATIO == 4 && SYNC_CLK ? wr_datacount_int : rd_datacount_int; + + +generate + if (MODE == "FWFT") begin + // NIC + //assign rd_en_int = (~rd_empty_int & rd_empty) | (re & ~rd_empty_int); + //assign rd_empty = rd_empty_fwft; + + assign rd_en_int = 1'b1; + //assign rd_empty = rd_empty_int; + + //always @ (posedge rclk or posedge rd_rst) begin + // if (rd_rst) begin + // init_set <= 1'b1; + // end + // else if (~init_set & rd_empty) begin + // init_set <= 1'b1; + // end + // else if (~rd_empty_int) begin + // init_set <= 1'b0; + // end + // else if (rd_empty) begin + // init_set <= 1'b1; + // end + //end + // NIC + //always @ (posedge rclk or posedge rd_rst) begin + // if (rd_rst) begin + // rd_empty_fwft <= 1'b1; + // end + // else if (rd_en_int) begin + // rd_empty_fwft <= 1'b0; + // end + // else if (re) begin + // rd_empty_fwft <= 1'b1; + // end + //end + + //if (FAMILY == "TRION") begin + if (OUTPUT_REG) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid <= 1'b0; + end + else begin + rd_valid <= ~rd_empty; + end + end + assign rd_vld = rd_valid; + end + else begin + assign rd_vld = ~rd_empty; + end + + assign rd_empty = rd_empty_int; + end + else begin + assign rd_en_int = UNDERFLOW_PROTECT ? re & ~rd_empty_int : re; + assign rd_empty = rd_empty_int; + + if (OUTPUT_REG) begin + reg rd_valid_r; + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid_r <= 'h0; + rd_valid <= 'h0; + end + else begin + {rd_valid,rd_valid_r} <= {rd_valid_r,rd_en_int}; + end + end + assign rd_vld = rd_valid; + end + else begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_valid <= 'h0; + end + else begin + rd_valid <= rd_en_int; + end + end + assign rd_vld = rd_valid; + end + end + + if (ALMOST_FLAG) begin + assign wr_almost_full = wr_datacount >= WR_DEPTH-1; + assign rd_almost_empty = rd_datacount <= 'd1; + end + else begin + assign wr_almost_full = 1'b0; + assign rd_almost_empty = 1'b0; + end + + if (PROGRAMMABLE_FULL == "STATIC_SINGLE") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + // NIC + //wr_ack <= wr_en_int & ~wr_overflow; + wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; + end + end + end + + if (OVERFLOW_PROTECT) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else begin + wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; + end + end + end + + if (UNDERFLOW_PROTECT) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else begin + rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + // NIC + else if (ASYM_WIDTH_RATIO == 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - raddr_int; + assign rd_datacount_int = waddr_int - raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + // NIC + //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_r <= 'h0; + end + else begin + waddr_cntr_r <= waddr_cntr; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + end + // NIC + //else if (rd_en_int) begin + else begin + //raddr_cntr <= raddr_cntr + 1'b1; + //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); + raddr_cntr <= ram_raddr; + end +end +// NIC +assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); + + +generate + if (SYNC_CLK) begin : sync_clk + if (MODE == "FWFT") begin + assign waddr_int = waddr_cntr_r; + assign raddr_int = raddr_cntr; + end + else begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr; + end + end + else begin : async_clk + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx mac_reset, + proto_reset => proto_reset, + rx_mac_aclk => rx_mac_aclk, + tx_mac_aclk => tx_mac_aclk, + eth_speed => eth_speed, + rx_axis_clk => rx_axis_clk, + rx_axis_mac_tuser => rx_axis_mac_tuser, + rx_axis_mac_tlast => rx_axis_mac_tlast, + rx_axis_mac_tvalid => rx_axis_mac_tvalid, + rx_axis_mac_tready => rx_axis_mac_tready, + tx_axis_clk => tx_axis_clk, + tx_axis_mac_tvalid => tx_axis_mac_tvalid, + tx_axis_mac_tlast => tx_axis_mac_tlast, + tx_axis_mac_tuser => tx_axis_mac_tuser, + tx_axis_mac_tready => tx_axis_mac_tready, + rgmii_txd_HI => rgmii_txd_HI, + rgmii_txd_LO => rgmii_txd_LO, + rgmii_tx_ctl_HI => rgmii_tx_ctl_HI, + rgmii_tx_ctl_LO => rgmii_tx_ctl_LO, + rgmii_txc_HI => rgmii_txc_HI, + rgmii_txc_LO => rgmii_txc_LO, + rgmii_rxd_HI => rgmii_rxd_HI, + rgmii_rxd_LO => rgmii_rxd_LO, + rgmii_rx_ctl_HI => rgmii_rx_ctl_HI, + rgmii_rx_ctl_LO => rgmii_rx_ctl_LO, + rgmii_rxc => rgmii_rxc, + s_axi_aclk => s_axi_aclk, + rx_axis_mac_tdata => rx_axis_mac_tdata, + tx_axis_mac_tdata => tx_axis_mac_tdata, + tx_axis_mac_tstrb => tx_axis_mac_tstrb, + rx_axis_mac_tstrb => rx_axis_mac_tstrb, + MdoEn => MdoEn, + Mdo => Mdo, + Mdi => Mdi, + Mdc => Mdc, + s_axi_araddr => s_axi_araddr, + s_axi_arready => s_axi_arready, + s_axi_arvalid => s_axi_arvalid, + s_axi_awaddr => s_axi_awaddr, + s_axi_awready => s_axi_awready, + s_axi_awvalid => s_axi_awvalid, + s_axi_bready => s_axi_bready, + s_axi_bresp => s_axi_bresp, + s_axi_bvalid => s_axi_bvalid, + s_axi_rdata => s_axi_rdata, + s_axi_rready => s_axi_rready, + s_axi_rresp => s_axi_rresp, + s_axi_rvalid => s_axi_rvalid, + s_axi_wdata => s_axi_wdata, + s_axi_wready => s_axi_wready, + s_axi_wvalid => s_axi_wvalid +); + +------------------------ End INSTANTIATION Template --------- diff --git a/Ti375C529_devkit/ip/gTSE/ipm/component.pickle b/Ti375C529_devkit/ip/gTSE/ipm/component.pickle new file mode 100644 index 0000000..26ca13f Binary files /dev/null and b/Ti375C529_devkit/ip/gTSE/ipm/component.pickle differ diff --git a/Ti375C529_devkit/ip/gTSE/ipm/graph.pickle b/Ti375C529_devkit/ip/gTSE/ipm/graph.pickle new file mode 100644 index 0000000..659a69b Binary files /dev/null and b/Ti375C529_devkit/ip/gTSE/ipm/graph.pickle differ diff --git a/Ti375C529_devkit/ip/gTSE/settings.json b/Ti375C529_devkit/ip/gTSE/settings.json new file mode 100644 index 0000000..ae9734f --- /dev/null +++ b/Ti375C529_devkit/ip/gTSE/settings.json @@ -0,0 +1,46 @@ +{ + "args": [ + "-o", + "gTSE", + "--base_path", + "ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "ethernet", + "name": "efx_tsemac", + "version": "7.3" + } + ], + "conf": { + "VERSION": "16", + "TXFIFO_EN": "1'b1", + "RXFIFO_EN": "1'b1", + "TXFIFO_DTH": "4096", + "RXFIFO_DTH": "4096", + "PHY_INTF_MODE": "0", + "AXIS_DW": "8", + "RGMII_RXC_EDGE": "1'b1", + "RGMII_TXC_DLY": "1'b1", + "INTER_PACKET_GAP": "6'd12", + "MTU_FRAME_LENGTH": "16'd1518", + "MAC_SOURCE_ADDRESS": "48'd0", + "ENABLE_BROADCAST_FILTERING": "1'b1", + "LOOPBACK_EN": "1'b1", + "APBIF": "1'b0", + "ONCHIP_PHY": "1'b0" + }, + "output": { + "external_testbench_modelsim": [], + "external_source_source": [], + "external_testbench_testbench": [], + "external_testbench_ncsim": [], + "external_testbench_synopsys": [], + "external_testbench_aldec": [], + "external_example_example": [], + "external_example_2": [] + }, + "ooc_synthesis": {}, + "sw_version": "2026.1.132", + "external_path_option": "RELATIVE_PATH" +} \ No newline at end of file diff --git a/Ti375C529_devkit/ip/gTSE_1to2_switch/axi_interconnect.vh b/Ti375C529_devkit/ip/gTSE_1to2_switch/axi_interconnect.vh new file mode 100644 index 0000000..4163a66 --- /dev/null +++ b/Ti375C529_devkit/ip/gTSE_1to2_switch/axi_interconnect.vh @@ -0,0 +1,2 @@ +localparam M_BASE_ADDR = {32'h41000000,32'h40000000,32'h30000000,32'h20000000,32'h11100000,32'h11000000,32'h200,32'h0}; +localparam M_ADDR_WIDTH = {32'd20,32'd24,32'd28,32'd28,32'd20,32'd12,32'd8,32'd9}; \ No newline at end of file diff --git a/Ti375C529_devkit/ip/gTSE_1to2_switch/gTSE_1to2_switch.v b/Ti375C529_devkit/ip/gTSE_1to2_switch/gTSE_1to2_switch.v new file mode 100644 index 0000000..e8ebeb1 --- /dev/null +++ b/Ti375C529_devkit/ip/gTSE_1to2_switch/gTSE_1to2_switch.v @@ -0,0 +1,1281 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2026.1.132 +// IP Version: 5.6 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2026 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _3abf8808e52e459c824b41829c7669da +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module gTSE_1to2_switch +( + input rst_n, + input clk, + input [0:0] s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [1:0] s_axi_awlock, + output [0:0] s_axi_awready, + input [0:0] s_axi_arvalid, + input [31:0] s_axi_araddr, + input [1:0] s_axi_arlock, + output [0:0] s_axi_arready, + input [0:0] s_axi_wvalid, + input [0:0] s_axi_wlast, + input [7:0] s_axi_wid, + input [0:0] s_axi_bready, + output [1:0] s_axi_bresp, + input [0:0] s_axi_rready, + output [7:0] s_axi_bid, + output [7:0] s_axi_rid, + input [31:0] s_axi_wdata, + output [31:0] s_axi_rdata, + output [1:0] s_axi_rresp, + output [0:0] s_axi_bvalid, + output [0:0] s_axi_rvalid, + output [0:0] s_axi_rlast, + input [3:0] s_axi_wstrb, + output [1:0] m_axi_awvalid, + output [63:0] m_axi_awaddr, + output [3:0] m_axi_awlock, + input [1:0] m_axi_awready, + output [1:0] m_axi_arvalid, + output [63:0] m_axi_araddr, + output [3:0] m_axi_arlock, + input [1:0] m_axi_arready, + output [1:0] m_axi_wvalid, + output [1:0] m_axi_wlast, + output [1:0] m_axi_bready, + input [3:0] m_axi_bresp, + output [1:0] m_axi_rready, + input [15:0] m_axi_bid, + input [15:0] m_axi_rid, + output [63:0] m_axi_wdata, + input [63:0] m_axi_rdata, + input [3:0] m_axi_rresp, + input [1:0] m_axi_bvalid, + input [1:0] m_axi_rvalid, + input [1:0] m_axi_rlast, + output [7:0] m_axi_wstrb, + input [1:0] m_axi_wready, + output [0:0] s_axi_wready +); +`IP_MODULE_NAME(efx_axi_interconnect) +#( + .ARB_MODE ("ROUND_ROBIN_1"), + .S_PORTS (1), + .DATA_WIDTH (32), + .ADDR_WIDTH (32), + .M_PORTS (2), + .ID_WIDTH (8), + .USER_WIDTH (3), + .PROTOCOL ("AXI4_LITE") +) +u_efx_axi_interconnect +( + .rst_n ( rst_n ), + .clk ( clk ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awlock ( s_axi_awlock ), + .s_axi_awready ( s_axi_awready ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arlock ( s_axi_arlock ), + .s_axi_arready ( s_axi_arready ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_wlast ( s_axi_wlast ), + .s_axi_wid ( s_axi_wid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_rready ( s_axi_rready ), + .s_axi_bid ( s_axi_bid ), + .s_axi_rid ( s_axi_rid ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rlast ( s_axi_rlast ), + .s_axi_wstrb ( s_axi_wstrb ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awready ( m_axi_awready ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arready ( m_axi_arready ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_bready ( m_axi_bready ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_rready ( m_axi_rready ), + .m_axi_bid ( m_axi_bid ), + .m_axi_rid ( m_axi_rid ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_rdata ( m_axi_rdata ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_wready ( m_axi_wready ), + .s_axi_wready ( s_axi_wready ) +); +endmodule + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +BSiclTfEX07oDTPwvSfmqSh37gsGawnAkFDdQtfz2b2aPAbkkOIevgA5jmAEpk8Z +jmjFoTAnEUNBHxHADHQl29GtYYLQLcTt1dvsb1L8xXXbyd41mZnW9qxR1yEXo2Km +PmHE4/laDDFnEAn08I7oinDvTWN/plGfuIWWaEXC4z7ls9W1O5jNY2gj1ZC0oyT4 +iwzQ3cMmgvMMfqkgA6T8wMNFL1jvPdUxnuGh8qa0Q5zso+v2lpzszj4ytZLI8JZz +ZeX/ipjz/4hUHkihXJPjFD+MetXdYJTpzRO3ZbxTOlyD1Ln8yDvo0qNPrgbzN9qq +YropxHtLb22q5bZxY+vKMw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 9552 ) +`pragma protect data_block ++Vo70GbdNusghssxCh548dyMR2SkpjbMNAhuQNohK03MZPtslM2VcFXDSMs/E4I3 +A0tJBsXs6xJPmnI2dRa4m1jbkpAyspc0YB55NAgJLYdmR9j6FyHXqlpTZEcftxHN +U0jtFOoa18GEMGSCMB1hS59vfrr8WKoVGK2KMx8ZvAuWlQ0YHQjLkE8WQjVMM55l +aP/cENky21pfv/q9aoe1Ku3NLdbDqb8Mf/xcXYVJFJaMRBTujuRBZkvEBDhdz78t +J6irEqM5Esiu61ol7FyudRxQ9CyuB9hXVb40puIOcvjK6w4R5IFdJtzamLms4rEo +ttyRNF4nJVzvrjJErNRuCjJeWgYZGt7SXTDXpHvc/U8J03YrUq//wH9tuvfylFAb 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+ypjiz0EYl6ooJdV6MS/XDrcnyFXRJMglD0hrUl1fPv9TiFOxNMHpTBhfhWz0nBmR +thX4XZpDQ4FQVfIBroQGJCK3GhiVzvJN95ATiPQtFgjyG/x3nSLf/bFXtUyo1L2z +RwF9eeZ6fo+kcN0UJp4FC3fwSvkZKocysKX/WzYdz7jVPo+03TpnbkyFMqorl0xD +bXhDl6XYUHZQCYHVhUXKcEZHOI2zSxWqNUvlSHXEc91pIEoXCvTi7QiaYSZHIm30 +YDkGla/3BGsmsllvK17YhlIl+B3INu8+TG18NyhGxe5t6c221BHB9CVP49nZWvq5 +xSXZLb2EaG+OsoEU1jshlGGdUFaaeZjuBF4Wv4cG/Kd21TMqtDl7tuOxWslTY3BA +h0K+XtKRSjnfR01WLA+/XQe4S25S6tcbR5AJSYT3xcLFDUw4ghn4/qQklNNEr57f +mD470LuP9+f5Ud307Xx4F6AM71/FGZrha/rJxjluETxdHCy5bAx/oXWQo31VURq7 +3q6UCh0ymGPD837xKYyUYceQRZff4/xlTF/OEQdZPNtbBVE8IsHMp2mfFfSDxq+C +axB5ar3/7/HrmzJElpSIOoSceJQXYo0L9scIrPSF8jNRRB2TxDReT/yjiQsCkww1 +fGF62e7DC0HnyHPBQrRlj9JQC34pW2K2ZTTgQYZhrhwQwTzaoIHBb45KPMMUuBHp +v82gEe/pW9K++sUDQK/W7wgO1NeiS5NHJmtaqv/uH5AOxE1XMLrXPsYiw7p2QJOq +1bmbF7c4TMfs9iT1KNHz2p1mqo4wOo0tHgDdPmL8PXLMm7POrz0rKoBS6lDTid35 +`pragma protect end_protected + +//pragma protect end + + +module `IP_MODULE_NAME(efx_axi_interconnect) #( + parameter PROTOCOL = "AXI4", + parameter ARB_MODE = "PRIORITY", + parameter S_PORTS = 1, + parameter M_PORTS = 8, + parameter ID_WIDTH = 8, + parameter DATA_WIDTH = 32, + parameter USER_WIDTH = 3, + parameter ADDR_WIDTH = 32, + parameter M_REGIONS = 1, + parameter M_CONNECT_READ = {M_PORTS{{S_PORTS{1'b1}}}}, + parameter M_CONNECT_WRITE = {M_PORTS{{S_PORTS{1'b1}}}}, + parameter STRB_WIDTH = DATA_WIDTH/8 +) ( + input wire clk, + input wire rst_n, + input wire [S_PORTS-1:0] s_axi_awvalid, + input wire [S_PORTS*ADDR_WIDTH-1:0] s_axi_awaddr, + input wire [S_PORTS*3-1:0] s_axi_awprot, + input wire [S_PORTS*ID_WIDTH-1:0] s_axi_awid, + input wire [S_PORTS*2-1:0] s_axi_awburst, + input wire [S_PORTS*8-1:0] s_axi_awlen, + input wire [S_PORTS*3-1:0] s_axi_awsize, + input wire [S_PORTS*4-1:0] s_axi_awcache, + input wire [S_PORTS*4-1:0] s_axi_awqos, + input wire [S_PORTS*USER_WIDTH-1:0] s_axi_awuser, + input wire [S_PORTS*2-1:0] s_axi_awlock, + output reg [S_PORTS-1:0] s_axi_awready, + input wire [S_PORTS-1:0] s_axi_wvalid, + input wire [S_PORTS*DATA_WIDTH-1:0] s_axi_wdata, + input wire [S_PORTS*STRB_WIDTH-1:0] s_axi_wstrb, + input wire [S_PORTS-1:0] s_axi_wlast, + input wire [S_PORTS*USER_WIDTH-1:0] s_axi_wuser, + input wire [S_PORTS*ID_WIDTH-1:0] s_axi_wid, + output wire [S_PORTS-1:0] s_axi_wready, + input wire [S_PORTS-1:0] s_axi_bready, + output wire [S_PORTS*2-1:0] s_axi_bresp, + output reg [S_PORTS-1:0] s_axi_bvalid, + output wire [S_PORTS*ID_WIDTH-1:0] s_axi_bid, + output wire [S_PORTS*USER_WIDTH-1:0] s_axi_buser, + input wire [S_PORTS-1:0] s_axi_arvalid, + input wire [S_PORTS*ADDR_WIDTH-1:0] s_axi_araddr, + input wire [S_PORTS*3-1:0] s_axi_arprot, + input wire [S_PORTS*ID_WIDTH-1:0] s_axi_arid, + input wire [S_PORTS*2-1:0] s_axi_arburst, + input wire [S_PORTS*8-1:0] s_axi_arlen, + input wire [S_PORTS*3-1:0] s_axi_arsize, + input wire [S_PORTS*4-1:0] s_axi_arcache, + input wire [S_PORTS*4-1:0] s_axi_arqos, + input wire [S_PORTS*USER_WIDTH-1:0] s_axi_aruser, + input wire [S_PORTS*2-1:0] s_axi_arlock, + output reg [S_PORTS-1:0] s_axi_arready, + input wire [S_PORTS-1:0] s_axi_rready, + output wire [S_PORTS*ID_WIDTH-1:0] s_axi_rid, + output wire [S_PORTS*DATA_WIDTH-1:0] s_axi_rdata, + output wire [S_PORTS*2-1:0] s_axi_rresp, + output wire [S_PORTS-1:0] s_axi_rvalid, + output wire [S_PORTS-1:0] s_axi_rlast, + output wire [S_PORTS*USER_WIDTH-1:0] s_axi_ruser, + output reg [M_PORTS-1:0] m_axi_awvalid, + output wire [M_PORTS*ID_WIDTH-1:0] m_axi_awid, + output wire [M_PORTS*2-1:0] m_axi_awburst, + output wire [M_PORTS*8-1:0] m_axi_awlen, + output wire [M_PORTS*3-1:0] m_axi_awsize, + output wire [M_PORTS*4-1:0] m_axi_awcache, + output wire [M_PORTS*4-1:0] m_axi_awqos, + output wire [M_PORTS*4-1:0] m_axi_awregion, + output wire [M_PORTS*USER_WIDTH-1:0] m_axi_awuser, + output wire [M_PORTS*ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [M_PORTS*3-1:0] m_axi_awprot, + output wire [M_PORTS*2-1:0] m_axi_awlock, + input wire [M_PORTS-1:0] m_axi_awready, + output wire [M_PORTS*DATA_WIDTH-1:0] m_axi_wdata, + output wire [M_PORTS*STRB_WIDTH-1:0] m_axi_wstrb, + output wire [M_PORTS-1:0] m_axi_wvalid, + output wire [M_PORTS-1:0] m_axi_wlast, + output wire [M_PORTS*USER_WIDTH-1:0] m_axi_wuser, + output wire [M_PORTS*ID_WIDTH-1:0] m_axi_wid, + input wire [M_PORTS-1:0] m_axi_wready, + input wire [M_PORTS*2-1:0] m_axi_bresp, + input wire [M_PORTS-1:0] m_axi_bvalid, + input wire [M_PORTS*ID_WIDTH-1:0] m_axi_bid, + input wire [M_PORTS*USER_WIDTH-1:0] m_axi_buser, + output reg [M_PORTS-1:0] m_axi_bready, + output reg [M_PORTS-1:0] m_axi_arvalid, + output wire [M_PORTS*ID_WIDTH-1:0] m_axi_arid, + output wire [M_PORTS*2-1:0] m_axi_arburst, + output wire [M_PORTS*8-1:0] m_axi_arlen, + output wire [M_PORTS*3-1:0] m_axi_arsize, + output wire [M_PORTS*4-1:0] m_axi_arcache, + output wire [M_PORTS*4-1:0] m_axi_arqos, + output wire [M_PORTS*4-1:0] m_axi_arregion, + output wire [M_PORTS*USER_WIDTH-1:0] m_axi_aruser, + output wire [M_PORTS*ADDR_WIDTH-1:0] m_axi_araddr, + output wire [M_PORTS*3-1:0] m_axi_arprot, + output wire [M_PORTS*2-1:0] m_axi_arlock, + input wire [M_PORTS-1:0] m_axi_arready, + input wire [M_PORTS*ID_WIDTH-1:0] m_axi_rid, + input wire [M_PORTS*DATA_WIDTH-1:0] m_axi_rdata, + input wire [M_PORTS*2-1:0] m_axi_rresp, + input wire [M_PORTS-1:0] m_axi_rvalid, + input wire [M_PORTS-1:0] m_axi_rlast, + input wire [M_PORTS*USER_WIDTH-1:0] m_axi_ruser, + output wire [M_PORTS-1:0] m_axi_rready +); +`include "axi_interconnect.vh" +parameter S_PORTS_WIDTH = clog2(S_PORTS); +parameter M_PORTS_WIDTH = clog2(M_PORTS); +parameter M_BASE_ADDR_INT = M_BASE_ADDR ? M_BASE_ADDR : calcBaseAddrs(0); +parameter IDLE = 0, + PORT_GRANT = 1, + ADDR_DECODE = 2, + WR_FORWARD = 3, + WR_RESPONSE = 4, + RD_REQUEST = 5, + RD_RETURN = 6, + DRP_REQUEST = 7, + DRP_WAIT = 8, + END_WAIT = 9; +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +h798DEoPCCw6eC93sfxnz8ZJ5DmYibE3rGjjhE+YK5a3RIfjyfpuQmm+Qi6hiWsS +h21ZC3p98i4VCoRgq9ttjdMjEUVk6R1INC59AvJ35jeq6cjGdiMiIPwnlnHEAIqa +kQUAn5DZG6XDT0Q74iMGbdiR7Uqpt242DlxQT/RPahxewbF7bTMwF22aKiwUymVQ +WL77YlV9D3RHdY6gVwH+r4vNibfPRFoNglrFWdWkXgAM3QCILfTmCmNOrDP+tU67 +Sp1AnVUQDUfoMreLqPv9PxJK3wnCugVdw08bgxzbxycLpfzcQbzXtVTNLzpE9m/C +m4DQ47zqQmz4Zj4f/JVRfg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 25024 ) +`pragma protect data_block +YwM6jjCriz1M+FDJXSN2LeXck/ZAaH8JuIXMxJq2uSTQniMJPx1HUHKK0h6e+ADy +nOpy4Npr3RCHDdf751Af8iOf0C8dZcMs3a1GYK43f9lfLJ4Am1BOEiaKGIMLoNoP +3/ezGIbxr0ugu0861FRZvKAC9ByuIi2/kp4W3oQ7m7vZVqigNx/Z+Lw30JD+Tdof +nd9fbmhRCCJW3RaeEuI7sGkqxIGkRp9Ypju2a3+UmaW00MJNt8bCRmHGNKebapN2 +4iVEq1eRDz+FLHYVirgJupc+ujLQGmDcYUtfEv75/zbfhbnSF2Tzy4KWhMa/eqDt +JdYj2al2m3yH2PEUGOEg/lmK4ufxcT7uAskU+0OCNTLvSk3xxzqGDoUTwqKX5Ln0 +JIDW8HetHVJZFTLmXuKbPHS6O+HyLuJ7Zxymn+Fjne6idZqUL/nzh8AJkD5MeD46 +devUK2qciMx2VyWCOynEzLIDQuLhf4HjJnSRV9ZjArs+ihs/aN5AaI98MfMmwjWS +KFKPxBp0tjRn2JUO0XR81ueXaQ9p/dLA1gbRJm7u3ADC4VBKoZXEWjeKWQe3/n1Q +mbN+x2KwcKG8XtTQY0BO2biWZo3QqJH1PH6ghVrcaM0KAEj3eBYyVZNVRgEB9Zrw +RRFhPPGhGTYcaC0TDtPS2EToJT5P23Ql13VFSHg3/OojCJpJcY0k1dryK52hqUyY +DiWhs5ZXPNHotTcdv5rTTZ/yPkW4CMHMJsuqWMpMzkQfRWTLiLfPZCs059UxzGNu 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+Yg3bb+MZBoJSx1bubJg+o5E3BkL40S/fAkj6c2uWPgCdl3r5BRCx1ucpBt0L7X2D +/l6T3GJAxPypfc4TzBOOQqOCDujGOV5ODMj1vMgngzz7owxpOiGCTjiHCvy49kqE +IqgNCgdBxm6ouv9UyqJKrMQrLiyUG1ZZknZxjWnvv9ISJ4AjuhkypSbY3v+ngPOK +hwivM16i4BPI2dfzEb0PIb7g2Y9jcOzteqjm5n3oypdyR+zpDT+hvqA3BPi25W0B +JPYxtbm4M1TPfEmgrkNbchX/D0U91Stwyv+qf4JqYYdaQXNdd449kc+NEnwTYsrq +imyaZXGkE+l6ED8peKJutbb1ccZHoZh+/itLOVb5jLrfCXLeDI2LUxittjCamfW5 +lt+O642jvKoWfacQoGHaq/AIPlwNqftmR49MtYZZMsDzfB+T4+2WoI60nL+OmMcu +GL3mI8jrE/W3gbgmLujiGP/0Ma1zJd1rqZufxTlCa61cMnpkieSrmehFshtQ2ONG +nsHziIMfVHv/ubGOxOvWWA6ESxhyq4Bb7YE6fnyfk4YwwpVD/QDv/+P9eOklQa1I +cQRQmNo/vwzwS1nfA0mc3wtdW3m0qIjV/PaogQuODlY1TLbydqB4H+lhbwXvhHZ5 +60YjPDLerHojlSKgOWBz35r7fbZqJOCKnTC6LE/2BzjB7GewxnTJsjWRJmkLaHmF +i6BmBm4m78KsKEJZgToH/UJ++X5fhUQ+SG+hz+h0i7xxyC/cnU/PigQ3vZ/SUkN6 +7zg/hdWRcuGmho0aVNUfw1w5Wdd1RwXdUYbYfG8RWeYIqQ6OWqhjLOK/B+Yy3r/n +JNwvRqtuUZFoPNH2FzMv2pdxZm5CvcOuJOMBcvVpgxktn57SwIk367E1srFwQw/j +VhTvV5MqNhAZpXfPbkZ0rQ== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +RwZLaWoAKLBm11tcUo3zg7WK2hPcNJvetUS0HcngH1N+uqVkxItkonJwS2nHozet +PZ4e0pcL7oMHU+YSSKFGF0HZtDLJ6ggz9Tjk65W4OruIfJxIuyYdw9nbusKhaJTz +khXz5VPO6s2gfnVif+az5zjoe7kudgxlxU7jmvaX9sbur5cFMS2KnJogDMLJcl1s +ZlLL+9F5h5+8PKCF6eoiFm6TtkD7MrBiDjMDu9eLqZ5t8VgWYRMKduwEQ9J2M3t/ +JcbjL7GG+1h3LkL6WEKxF8zVIpKiu3k7UC98wKI8mhEpZ8bChW07nVCr4PHLn2IX +BU9Qy5kOLqe8sKbl6LYs7g== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1312 ) +`pragma protect data_block +p0bIW99zYvQA4u0XRWnQ90s6MugNpXe6l31pFNyBhuxQU67mS/BBRtYtc25nySM/ +yHwfDVEt2eeSh2xZ2Kv1d8VWucKTg8lXrK+ooXsXcYiy61IB12mnjuKPa/FUxFS4 +JM2AiESAcF0ks9YGnHz5atWTSPAnEYKTqIrZDoYqJkbgClLiRdrZY+N2hC5jdZeW +cR1EkHw0PZqw6S2eCHL5hUi6ryPKMkre1oH3Xdag2DJT8qQxbuNqhhrm/L+8L8lX +f5F3asZ05yCB1pnJRqVPESYDajoN8u1lWD18RYsWX60ld2PcwCxsHkPOyoBvAV1u +PgCYq2l6s5FitBJR9RvIIWQXgYcJnkvvctXAE4sHkA/8YmzJKAUlmADFxObHh7nH +B9Tr9F5MMMItWtOlRVOB7r7GpKZ4CIu9H0pG8rHeitdTJzb//0sRPwO4Ifpq00gF +PYpm2+uw1qrcWOBG9wrbOEUMiFlt1c1y6CM7W0HiQg/FK+4Y4JiB7uaAlzUejTOI +zOL6no+QbQSWHIEVAYNpQGNcTG+AuFlhiSI5DitSGvW5yCLRLs7Fv5AnqLM6z1Qg +nRTXEKDaR/AFlAFB16izDRH4FYwpXtH01JTfdxvrFbPDjE2B07qlVwewnCVApXy1 +GNPPzEat9SO3vQ9t7PCKFzQV6OGGAn/dyMwguU6EDW8mcNxemcFiHUdiSfhhZpeH +IcnqAMISo7J5oznEHRV6eZ2t27p8fCR6kY+/9tdw+mhgfM47E9D+jOa2LZcvRNK0 +IxKxNWtgUL0KlYtkFTGEhG+p36IePpoZOlbFukyAkrvx2uvJdjDKNhR7fljgKZp9 +ntpSnYfXJhwQrP8yTvoXUhnLpaxBTrh8cyLUFVm+2UtqRrz/+WA/Du8u19N0NmoU +4Z65V0tXF/tW4DpeElKcg5Z9g3Srjon+LpuobgvaptlZ3rG7pXXklUAdxNfJ+4mu +g8S64RYvfLamt1za0XyFbePfAbEPHUNKbKIqzGRB92kxJ6jYjgC9RQHp35SL3T55 +2DhArYHiRs4HAieVOggerJ2mFKRe1jgXpNH28cIvReVtjhPSR0h2/N1kktJoFN9j +pAwsBXcE20H2DgeDq7MOl5klQOQIZqq2NOi/TtiDykzXOq9c52KT5YQDUiFYqQvD +H29baw+SyQUZTso78q8DVb5S1dB3XyHStAKgoGq93+Wz/B1RLpKYack4xd4rdS5s +pwx6XbBMdp7aDqOyz2KgKWf+dspEnt1aZSkLPUfnK1QqEuwBFSip0++f8lsYJwt6 +h2RR9rfNZmd8nt+mXhbGkKeiOagijsA/5zVB+4MgI0KR9sujHhdd3ikiYUTRDpcb +AA7w3mFn6w2oiAcHGimR/cBGrmo7m6L0USsPGqFYBLIQfdAn5dEBlb2BCoA5VFZj +jXKJF/jua7Y+DrPzh66goMGjpF9lBpoEP1rWQA/7bSpIp6mTsXcqppKrJq4X3UzK +fnxoXMOzyXak8Q0RLDFj9NSgAWzr4VmwVpFWnocoXpsQlisCkXdTJvGnor8LLZr9 +sDZmzgcSix39SaRGPrUkPl4jLdocSaImMFvFf75Ln2LkiFK2PwLHbdxu5OHmQoCw +7wBcsGkL2gXd3tYL2ns54yYSqMYHrxBbag+ndd5VaJnjZK34JNDCSh65qkKE7y7v +Behj6SqW7qWtdmufzd16RndX/9C4+tnd6CZRltVVSxqHORQEFpJfBX3qZLp11vTQ +Pib5SMqM0nVbJDVpqDeCAA== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +V7fazAcYfn/upNWI2MrDSQamEge7Y8sqGyEbHWTTDvIkXpdIuRisL8LJjvy83vue +ZgYLruqRxsDQR/Wu7PMlj65sb/NkxpSPTHfwdQcOEP3MsixExszjuA1HqHtg+aNQ +uFOiuMhxVPj6PMHq/Hqrqa85QcEVSbWPuLxSaFzY0ndkgyErZck8cU+0bbs6pFmr +tNIeglsOu6Am3uxBT62KHdsx5/dbyBFUXzyoeMcVqVN/dSwFJEWKXykd+OnIo8cg +TAWc+EOAJ6ExmKO/aLU8Un5EpThP6h/F+4FSrXQ8+zAfJHLLmWelIILCIn9r270y +7CUxtRRDMVrzxeZaHx87Jw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1200 ) +`pragma protect data_block +0H3ui++saKA3Qim7nBCnYyJXuXUUae6AJ4LYf9uQIt7dDyl6C5Q3z+wohgm7l6P/ +puE1YIk57wYrhZfaxaOZbQEeQcTD5dhNWYlNGXkVD3n3ordUMQqbpossg6k8GBbL +hcT5AJLRLWp1fmFYHU/sChpXsLIvsw4ylUF+kPCiM/E2Qrxqk+h6yKLdH/qUhhl9 +SFhgQaFfWNjj6ajZXfTXAeH01G9YVoXQTrTURK7LCmy8Exrca33pvD2n8qRjNHVC +SMvlBAlMyB9GhVbgRH5g1J3eexKd42EKVG1OYkkLmaw/2mYb6XQBYWGV+JPCs/lf +iK57mI1tmXdY1dZroI+VNNMZ2ERNO1xPtSdY84zkg7t8kqVOzrKucAQtG6cbtv1M +zOk4T1+sHwfHB5B0MAQxfUujCPIx48x0ucEJPziWVe4xGSV7Y/CdKWRJKyu1t9Fd +RrGJ90FB8JcoftYS17u1PRbcM0J+K9rYOujMCI2wOiGLeakIZUzeUlYgu3AhwJ+p +rFTdyQbZfeR1hJMbKn0z9kiVI7O//BPB79Ovy0ckHGOWpsznVPMik4mcftaUGBo/ +SKRhNP5RZ7ADTWwNcGVQ50K6Uk/FWRH/LjkzUDgrlN+BL9CVLgTUzw4n7TXZLYO1 +UUMwg1Abr+r4azUlV2lllRgjlWSPEmPeuWdkmDLE1kzi81/3MG9dkGcEzpCjQn1g +wlq08l1m/9D6ssj9X+L9zWestpPbK8KKA36LM44lR7JM48DHZp/GFFbwyCyfem5J +Yk9dQrVMSLDeQfsKUdIRfzsLFIcVo9j9nAjaOh5icY9Ju14nqLljzJxMSLXwpRpN +pHlAUZkLKZ81BR2lNUcueWoYr1mNO5wt/8ZXKNAe4baXyx5pQlkEoPhDAu/MmaoV +IQmRsNZAJw70Y6wneeDDkHad2vIHrOElxrM5Lnlhdq1qO4G2CjQ03nmLodMZn/cu +JhstoiAqinvEClsBGQAEn59Mk5wMvMergihuxdt6qTvztnpZTBcB2JqJyHkCY2xR +XYx3muggMb4QtLLic31NtDmfG8SMy5jpSvmNNdDUrcWI5vOaLo+t2/mVb5p6U/Z8 +WsFN6j8TpdcSc+yFYrWVYf/mabwUsQccMAaYaGcHwQTAXW/zRUxCfgK2BtB9AUG3 +Kwe4fuqZPo1NDmSSdATNh7Ls+wMag23tKAtoVCW+TQ3lLpto8vUWhWKQTH1PsQRx ++KWcJaJK96bA+80M/q4HUzR+yC6IUVQ9VRvWhgG0ygZTLKmQmJ/DKIzlw1lxCkA3 +JF0FRPBrpi2n+UOIXtU6FUAnUoSUl8Eeuwpycld1aaAI++CWVpk0pdWCRD85nBNb +vAQ7vQzvYravu3V0bHTVB/w+yyy05bUUjf1aVui34DyQ1QLLkq3XQF2v9st57JGH +egpS3SZqHPJ0AZAJJvkOXoxVRMHu48i9M6Wx9Qjtrh9EJee4xLdxqYrF04J9h9ck +AvKxciqIeVCjtaleTRBLEWnwUKa6wADHB0WNBFNEidDe8gAcwWkZyKkh/VaUiupU +5Cv90Shsjvie3xvNr1QXSLjEkUzHLYrvPv6IGVvcwtPvJNwajthWm4H1o8D7rdfK +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +idlb0ipwgIc0hiUfW9lCBvIc27j+O1T55dJ3BL9eUyC3AmELfvx2LyGUfXvUfYTf +8sHVL37lgxYwkxIH4ZSSZQ1GK2zLKlNHYUEmXZIR/WoNIg7U3rYo+/OAX5LDNWz3 +I3htHfdktV9gYc7iVdI9VNrqBa0Gg55NmIOrO+wM2ME4dVbdMJVDfW+oOu9rTeme +KOonn0oR5/zNCWcqkhf2z6BLLm49S0wwKQJc9Tn8j8aAVVAS5PR4HM/UAt+Pm5Qw +qUaeukXs5OImR86WKmCfOXrROtxYmBZ//zwyzxGdjene5Dzf1Lue74V7vg9Yy8Es +kofIx1Iiwvl5uhKqK0ZywQ== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1984 ) +`pragma protect data_block +W5IcpMWeZEmcNKazNSseGe/SkDOlgncKe6xygU4WozXer89CE7H74/gQ3yQQ4LCo +YC8yuYKcjPKApcXYJYuOgpsab8uIQGftqOoDnHHE/TFo5sK5ih7BYybPWYaaZIfN +U42fSf3IGBc/VJJMqP+4YGf2p7Dp5YE+Wy7VkeYE9mZmjDlwds+pPKcijo5Rgpy4 +aylibzsZkO5+oK4Olfl1/eP949zocOLdn828ECpQrR+1rd90XEST7JJU34+5nQR0 +iYx3aHjOcfjFetECQ73ZAYN9xqbs+aqjzeLBFzT66wgcNopyNE3rPObBjFm/FlMY +NJuj22N2AvkTuG1FfuBr5E5/i9RjA+BTgZPyYvLaoLqprEm8CWiFhmozo0TuSThV +oxsGKZXYjCpb3zoOzL++RaNuogj+rTHHnB4sjSyjcQXyW9FHyxQ9ou3pB0HSnVv9 +mmlv1FlvuwmXWRcsAbk9MN5Bu1XDI5gL7Ipu6jQGD76fGfDk5YZNwHHplmC9Hxoo +14fkoUi/IGM4yaR9gsmZ4/V39IhpdKS0TO3LMyFgBX1m9J69gD3agPTxpHvmjGBF +iBeClMI2X+GOMbRoQ7MTuRI/wsqqHaKZFnqG2JrdQ5jH4KCWRqJG4uuYi7J1i9bs +xY16r9KjF+6f0MFsxcK3KibLp7s5dEDpsw2XIf00NhedOsMfk9w9HgMaBIhHDYko +R9z9VCyALLVSnoVdMfGtgRCz9L0ZTjxm9XhyXpCWP2dQQ5YHyD+cFxCRM2u+sbOa +XCcYDb1UlKsoUKPrA6upaDj3TlNdAdCre4HET9kn0PDrdWIRz9my1VexCrOwQ/4v +/AGqqMzOkN1K3GiLhBjp7mc32jSK9Xwlf04J/O25O257w8YWwGgCDGh0YcXBAP9P +dRzMnjs3Uk7xrEq2VCihUs7MsFR2dplgxIVe/f4i6d9mLLp/cVw1tY4mO7GQJJL+ +NJxQNxDTfheXoNHxcaGlEvOWL2b3J/OVNbr/wJPsNPO3JZmZWUpP8CsvLDnb13uy +iNwDj4gZpR9546m0yEFGqGJTEKCKJEKdLC6E6Gdr4yH+RNK3GQAtivmlYR1RQi50 +PKxXgfvCk7ALJB0/AJ3VKJanssU7Hy6k/ihsWnMeUmW60hSGVcI7H4Dc2LD/zqWt +hTHS+BRPB55N1E551ExGrUEM85MWlZDv876GiCWMXvhRqs9srCM9ecVIL7dQAs33 +eEmvppS+tTUufZM9oZTu42ShCYqUVMSqeUy/xzqnGhbXu4Q7GBe6tQ22Qrny4jVx +0oqenju9rIFJylCiiAE55m3dRqcpZ/BW8zJT9E5xqywiyk2hKjD3cBa8sFQk4o0L +Q8sbZOGGnwkBiq09qANjvGvlkm1v9FDgC5FRhvdDYVbDc5kwRgkXw2C5yGo8ATdo +PBCMK39Rit7ogQUspBMSRycdQEknqdzSNQE/bSr+sFg7NtFexRxi9+4sFCfzdOdH ++cDNk2jJ3o5Pt3cxiWI+66BF+lGKauggjRt6wxcGgXxd1mAGo0E3ZAxv0Yzqu5pw +DiX9Ub+lowoE+P03j9ORmbT4fPh1vCZqOweT5yq4msNhPgF5yTiyJxa1f/nW/871 +YIJppXKMqggxL4xvTBLMFRRq5hyIaGUvjNRoml49I2/e1TeW/m4txLIR28P5W3g5 +XlPYaCFV3Q6BFDTb6hzglWO0MdX0htcU794klHzIjr9es0VaPjbGbgJwq13D3F/0 +Wq8j0HPafBZpvWLerjIfQntl7kZCuc2V2cANOqkVpbyXIWRCbZ7tsWyxylvndsWT +6E4JutWqIlD9ScB+1qz5I5aMLznRt/6iauVApWrYxEUIHKCY2O4d0GeF6lI4gTr2 +Ff4x1GYqVXjRfQ14+0Q/UVGYnaif0luhvPGRrZVCGBn5bYgic6aYLLVr39G/Bw5V +zhXtqIf1ISZtmmzRBJTn+QdkE1Rw+SrJcH8BdWjLo5Q4VpHvSX4wlw9lt2zjHr1g +Gw3jvpOsK0lFtMbrT1TOkk5TIAVkSEti7VAGeaycfKxXTfXsQcEdeTjsx/z+7E4s +5LmeTE6BUDvniF9TMGxAh8UNoorK/9h7raa/mc6UP1Ap0sVsn6FAnB5a3hp8AcfO +YyUI/+rE3uvbY7eV0TjnPlB2a4bKmip2sUnzCtjxk38a70NoSwvSF5fHD/gmb2Kt +In3bRGhQ51Ou8wyYtPtzpRKl9lfBj579kv2ljgctkPOCPxJ0qOO5U7vH9UVhyH4V +8Q6lGkKpbY+oJSEyXkd22SgAuuLMTQzychAeCZrzurKRTCJEkybeqpnHeMDZF144 +yT/sjynj+V1VANU1CW6cQPulbZj2svXukJupVa/ZhMF/Y2G5v2JIVKMZvprQfUMy +xrTAArhmrRjDrUfSaRBsr2icFO6IfrS7qjcKaFF4e7O/jDKLppha19sW6TL25Rzm +Ahjf7mc7/2mJeA/0ayik5t4ZP/xwgvgOII8quhw7Vrm37O9aT6wkCL/5JIKv6tpA +nWE/0iwIWwBWPYliaqFvsEcfMuowM9WrIG4B7EkD5jyS0Lwo/CezIdysfC7/rgBy +x3ZrJCp51uVHU3kT5JLDk0pb0CBXd7O/pLb7bpfJmQZYLmzXM7a6D32ZvJzsMxDq +M6eR/VTYArPQbA4OoPqXhQ== +`pragma protect end_protected + +//pragma protect end + + +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +kjevziVpR4HNp6ABOs1UfEhnb+dX0JPweI6S3+LX30C9LF3xx7Xd/zMszyIOAsff +hodfZOinnjjXzBncB8lZ/iwEBQcN9AOUuJkxqHw0xEX9lKugu7WOxROcH+yiXxDJ +yy9yDzS1F865ocB3xO9FWkMnml1XZRqox2FTUI5GMVk0MxMQPCoaWPmG40cuqt8H +oNSQWIvbZ0bwp2zXvC4BQlkXD2oWWu6JxxVIVspZ7XmHHSfSB+gK8bmQIk2JZPQd +nB3A0s+SLUanWE/u+Muh6A5t3kkuvJ5Fy1rRHEwle6WO6L5S2arPlksoYEp7hfDo +eW9+LO7WnZdnt0b3dQw5Mw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 1104 ) +`pragma protect data_block +LX5Dxt8B2z9u2haDN6HkGNj1Nxa2zeRWxlMLLnbgcY2+2ueKKYern04T7l3DicpU +GAgNW7GQnUadJWzOBc5yfD2Z7DyC1zg+m258ATNxkXP9Ag8Pfl4MhmlpUpmkc23o +YSNVfWttcQespNGB+Kj9g+/b/Ltzb/Pp1dgaxi5NIlG7FsWis/B/nSO/Vd0xLa8l +gdvKVbsSlGSB1tT5WBnrVIsaLuvPuUdgdvXFHzLrEscW/eC28+m22DdewgK9tHYj +l4yaTKwJ+7R2jtaFZr8jMmcRudxesBNt1kTJeA9U1nitqtdHVp23JcdwKc05jnrW +tx2+meDVE/d5vcxlhTdpO8sz2YOw2Z0bAN+ieJFfUDfTuopqPBMc5GBfsrD40ELk +H3q+hGhS+dIM3hrqhKDRW3tPFmcE5szwJbmOAxflm1SvQmlOnQVePLGdCuOZUUiI +tz++pZ5FH+uAdkA40yZWh5MnKo5IcfFxWM2Jsum3JZvmVMjnI7N1x8f70kUe3UgZ +KEcI12J/dpNLgdFOl+74xfjhKGoKm/BgN6Eb01T1RtdX6u5xQtgGCuv62jDE/Yt3 +eJjRnF/x+Ay39zeCLP9UQvypybEe14bN7gfHfWoAQe9HIG87Fm2nKjAzASr6QFRV +DL1jo931/n1Lv9oZuWMfaF7ZCTxH6A9fBYglk+u3TWHi+TkymppU4hV3XjEHw3B7 +wrSwISGJRMUoCJ0wh/W9Iqj3EDcLmFUIHicsgmfrUkpdpcDqQYIKmCedP/+uQ37E +hBOgLdq2ET/+T377dhiMAvLWIMnT6X9iEzqdVEMfkuPgbBZetAoTzb7IozmdA14+ +3PCjcT9XV5Hxvw1vyLKchF3xGFPaDFJgGJtzSIMeyTd9yK/++OeT1TQ0HFPfjjqB +LI0xhfRlEGqOj1YzmolIUWRdGapI6Ywt79vK6KTeqg9K4jHGe3R1t2SJUnNELlNy +Ju1RcPdn+2rNasE/ecNNfcArJ3ReZiWkO6Urua3WtmUiTzAVXd6UD4GUf3QUw0J5 +AefzuP3tFE5IfHRFmTZWTm7Y/JLAztWyBuag+6TRZLBlyPJDyNieFGTz4SEyTkAc +CyJ51RLW7x5j/8mo5k2anYrG7q1YYjOUQHyaLPL/RwYcBBJS38HGPAl44N6KsB9m +PGaS88rOnKmcVDest/nmsVi5/wR7C0xrMTpo2i2v7wOVW53j3SANDy4UhRYGQ75m +9+CZTXcObV1oXJW0me53hFtEJ+qHc7eFGKyCVwTNanP47XH3aJey3ulpiTKXp9iD +rurNoDvwMo1/Wv8495pWfGIS50V6wFEVgh2p6gt3S7meUf9sdMYrrKeQAKEna1ne +Rf8O+xm0FaLvKNBVaPV3ISnRU2qTxpWhaUb3vTQN4TODsKco29kkHPqYRTREwU5p +4ExJ23nclyx/By+ugg0UnN5jZ/DGDMK6ZJ2abjL+WrT31jFUNXgt+rmb/8ViJNIm +`pragma protect end_protected + +//pragma protect end + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Ti375C529_devkit/ip/gTSE_1to2_switch/gTSE_1to2_switch_define.vh b/Ti375C529_devkit/ip/gTSE_1to2_switch/gTSE_1to2_switch_define.vh new file mode 100644 index 0000000..5296368 --- /dev/null +++ b/Ti375C529_devkit/ip/gTSE_1to2_switch/gTSE_1to2_switch_define.vh @@ -0,0 +1,53 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2026.1.132 +// IP Version: 5.6 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2026 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam ARB_MODE = "ROUND_ROBIN_1"; +localparam S_PORTS = 1; +localparam DATA_WIDTH = 32; +localparam ADDR_WIDTH = 32; +localparam M_PORTS = 2; +localparam ID_WIDTH = 8; +localparam USER_WIDTH = 3; +localparam PROTOCOL = "AXI4_LITE"; diff --git a/Ti375C529_devkit/ip/gTSE_1to2_switch/gTSE_1to2_switch_tmpl.v b/Ti375C529_devkit/ip/gTSE_1to2_switch/gTSE_1to2_switch_tmpl.v new file mode 100644 index 0000000..228f904 --- /dev/null +++ b/Ti375C529_devkit/ip/gTSE_1to2_switch/gTSE_1to2_switch_tmpl.v @@ -0,0 +1,97 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2026.1.132 +// IP Version: 5.6 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2026 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +gTSE_1to2_switch u_gTSE_1to2_switch +( + .rst_n ( rst_n ), + .clk ( clk ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awlock ( s_axi_awlock ), + .s_axi_awready ( s_axi_awready ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arlock ( s_axi_arlock ), + .s_axi_arready ( s_axi_arready ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_wlast ( s_axi_wlast ), + .s_axi_wid ( s_axi_wid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_rready ( s_axi_rready ), + .s_axi_bid ( s_axi_bid ), + .s_axi_rid ( s_axi_rid ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rlast ( s_axi_rlast ), + .s_axi_wstrb ( s_axi_wstrb ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awready ( m_axi_awready ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arready ( m_axi_arready ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_bready ( m_axi_bready ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_rready ( m_axi_rready ), + .m_axi_bid ( m_axi_bid ), + .m_axi_rid ( m_axi_rid ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_rdata ( m_axi_rdata ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_wready ( m_axi_wready ), + .s_axi_wready ( s_axi_wready ) +); diff --git a/Ti375C529_devkit/ip/gTSE_1to2_switch/gTSE_1to2_switch_tmpl.vhd b/Ti375C529_devkit/ip/gTSE_1to2_switch/gTSE_1to2_switch_tmpl.vhd new file mode 100644 index 0000000..f73b627 --- /dev/null +++ b/Ti375C529_devkit/ip/gTSE_1to2_switch/gTSE_1to2_switch_tmpl.vhd @@ -0,0 +1,149 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2026 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +component gTSE_1to2_switch is +port ( + rst_n : in std_logic; + clk : in std_logic; + s_axi_awvalid : in std_logic_vector(0 to 0); + s_axi_awaddr : in std_logic_vector(31 downto 0); + s_axi_awlock : in std_logic_vector(1 downto 0); + s_axi_awready : out std_logic_vector(0 to 0); + s_axi_arvalid : in std_logic_vector(0 to 0); + s_axi_araddr : in std_logic_vector(31 downto 0); + s_axi_arlock : in std_logic_vector(1 downto 0); + s_axi_arready : out std_logic_vector(0 to 0); + s_axi_wvalid : in std_logic_vector(0 to 0); + s_axi_wlast : in std_logic_vector(0 to 0); + s_axi_wid : in std_logic_vector(7 downto 0); + s_axi_bready : in std_logic_vector(0 to 0); + s_axi_bresp : out std_logic_vector(1 downto 0); + s_axi_rready : in std_logic_vector(0 to 0); + s_axi_bid : out std_logic_vector(7 downto 0); + s_axi_rid : out std_logic_vector(7 downto 0); + s_axi_wdata : in std_logic_vector(31 downto 0); + s_axi_rdata : out std_logic_vector(31 downto 0); + s_axi_rresp : out std_logic_vector(1 downto 0); + s_axi_bvalid : out std_logic_vector(0 to 0); + s_axi_rvalid : out std_logic_vector(0 to 0); + s_axi_rlast : out std_logic_vector(0 to 0); + s_axi_wstrb : in std_logic_vector(3 downto 0); + m_axi_awvalid : out std_logic_vector(1 downto 0); + m_axi_awaddr : out std_logic_vector(63 downto 0); + m_axi_awlock : out std_logic_vector(3 downto 0); + m_axi_awready : in std_logic_vector(1 downto 0); + m_axi_arvalid : out std_logic_vector(1 downto 0); + m_axi_araddr : out std_logic_vector(63 downto 0); + m_axi_arlock : out std_logic_vector(3 downto 0); + m_axi_arready : in std_logic_vector(1 downto 0); + m_axi_wvalid : out std_logic_vector(1 downto 0); + m_axi_wlast : out std_logic_vector(1 downto 0); + m_axi_bready : out std_logic_vector(1 downto 0); + m_axi_bresp : in std_logic_vector(3 downto 0); + m_axi_rready : out std_logic_vector(1 downto 0); + m_axi_bid : in std_logic_vector(15 downto 0); + m_axi_rid : in std_logic_vector(15 downto 0); + m_axi_wdata : out std_logic_vector(63 downto 0); + m_axi_rdata : in std_logic_vector(63 downto 0); + m_axi_rresp : in std_logic_vector(3 downto 0); + m_axi_bvalid : in std_logic_vector(1 downto 0); + m_axi_rvalid : in std_logic_vector(1 downto 0); + m_axi_rlast : in std_logic_vector(1 downto 0); + m_axi_wstrb : out std_logic_vector(7 downto 0); + m_axi_wready : in std_logic_vector(1 downto 0); + s_axi_wready : out std_logic_vector(0 to 0) +); +end component gTSE_1to2_switch; + +---------------------- End COMPONENT Declaration ------------ +------------- Begin Cut here for INSTANTIATION Template ----- +u_gTSE_1to2_switch : gTSE_1to2_switch +port map ( + rst_n => rst_n, + clk => clk, + s_axi_awvalid => s_axi_awvalid, + s_axi_awaddr => s_axi_awaddr, + s_axi_awlock => s_axi_awlock, + s_axi_awready => s_axi_awready, + s_axi_arvalid => s_axi_arvalid, + s_axi_araddr => s_axi_araddr, + s_axi_arlock => s_axi_arlock, + s_axi_arready => s_axi_arready, + s_axi_wvalid => s_axi_wvalid, + s_axi_wlast => s_axi_wlast, + s_axi_wid => s_axi_wid, + s_axi_bready => s_axi_bready, + s_axi_bresp => s_axi_bresp, + s_axi_rready => s_axi_rready, + s_axi_bid => s_axi_bid, + s_axi_rid => s_axi_rid, + s_axi_wdata => s_axi_wdata, + s_axi_rdata => s_axi_rdata, + s_axi_rresp => s_axi_rresp, + s_axi_bvalid => s_axi_bvalid, + s_axi_rvalid => s_axi_rvalid, + s_axi_rlast => s_axi_rlast, + s_axi_wstrb => s_axi_wstrb, + m_axi_awvalid => m_axi_awvalid, + m_axi_awaddr => m_axi_awaddr, + m_axi_awlock => m_axi_awlock, + m_axi_awready => m_axi_awready, + m_axi_arvalid => m_axi_arvalid, + m_axi_araddr => m_axi_araddr, + m_axi_arlock => m_axi_arlock, + m_axi_arready => m_axi_arready, + m_axi_wvalid => m_axi_wvalid, + m_axi_wlast => m_axi_wlast, + m_axi_bready => m_axi_bready, + m_axi_bresp => m_axi_bresp, + m_axi_rready => m_axi_rready, + m_axi_bid => m_axi_bid, + m_axi_rid => m_axi_rid, + m_axi_wdata => m_axi_wdata, + m_axi_rdata => m_axi_rdata, + m_axi_rresp => m_axi_rresp, + m_axi_bvalid => m_axi_bvalid, + m_axi_rvalid => m_axi_rvalid, + m_axi_rlast => m_axi_rlast, + m_axi_wstrb => m_axi_wstrb, + m_axi_wready => m_axi_wready, + s_axi_wready => s_axi_wready +); + +------------------------ End INSTANTIATION Template --------- diff --git a/Ti375C529_devkit/ip/gTSE_1to2_switch/ipm/component.pickle b/Ti375C529_devkit/ip/gTSE_1to2_switch/ipm/component.pickle new file mode 100644 index 0000000..d2a83a4 Binary files /dev/null and b/Ti375C529_devkit/ip/gTSE_1to2_switch/ipm/component.pickle differ diff --git a/Ti375C529_devkit/ip/gTSE_1to2_switch/ipm/graph.pickle b/Ti375C529_devkit/ip/gTSE_1to2_switch/ipm/graph.pickle new file mode 100644 index 0000000..ed0f82c Binary files /dev/null and b/Ti375C529_devkit/ip/gTSE_1to2_switch/ipm/graph.pickle differ diff --git a/Ti375C529_devkit/ip/gTSE_1to2_switch/settings.json b/Ti375C529_devkit/ip/gTSE_1to2_switch/settings.json new file mode 100644 index 0000000..59f9f96 --- /dev/null +++ b/Ti375C529_devkit/ip/gTSE_1to2_switch/settings.json @@ -0,0 +1,54 @@ +{ + "args": [ + "-o", + "gTSE_1to2_switch", + "--base_path", + "ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "axi_infra", + "name": "efx_axi_interconnect", + "version": "5.6" + } + ], + "conf": { + "ARB_MODE": "\"ROUND_ROBIN_1\"", + "S_PORTS": "1", + "TABLE0_AXI_S0__MIN": "32'd0", + "TABLE0_AXI_S1__MIN": "32'd512", + "TABLE0_AXI_S2__MIN": "32'd285212672", + "TABLE0_AXI_S3__MIN": "32'd286261248", + "TABLE0_AXI_S4__MIN": "32'd536870912", + "TABLE0_AXI_S5__MIN": "32'd805306368", + "TABLE0_AXI_S6__MIN": "32'd1073741824", + "TABLE0_AXI_S7__MIN": "32'd1090519040", + "TABLE0_AXI_S0__MAX": "32'd9", + "TABLE0_AXI_S1__MAX": "32'd8", + "TABLE0_AXI_S2__MAX": "32'd12", + "TABLE0_AXI_S3__MAX": "32'd20", + "TABLE0_AXI_S4__MAX": "32'd28", + "TABLE0_AXI_S5__MAX": "32'd28", + "TABLE0_AXI_S6__MAX": "32'd24", + "TABLE0_AXI_S7__MAX": "32'd20", + "DATA_WIDTH": "32", + "ADDR_WIDTH": "32", + "M_PORTS": "2", + "ID_WIDTH": "8", + "USER_WIDTH": "3", + "PROTOCOL": "\"AXI4_LITE\"" + }, + "output": { + "external_script_generator": [], + "external_source_source": [], + "external_example_example": [], + "external_testbench_synopsys": [], + "external_testbench_modelsim": [], + "external_testbench_ncsim": [], + "external_testbench_aldec": [], + "external_testbench_testbench": [] + }, + "ooc_synthesis": {}, + "sw_version": "2026.1.132", + "external_path_option": "RELATIVE_PATH" +} \ No newline at end of file diff --git a/Ti375C529_devkit/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl.sv b/Ti375C529_devkit/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl.sv new file mode 100644 index 0000000..1562fb2 --- /dev/null +++ b/Ti375C529_devkit/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl.sv @@ -0,0 +1,1587 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 8.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _0340c286f12f4e3bb92b102aa178f77b +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module gTSE_core_fifo_ctrl +( + output full_o, + output empty_o, + input wr_clk_i, + input rd_clk_i, + input wr_en_i, + input rd_en_i, + input [15:0] wdata, + output rst_busy, + output [15:0] rdata, + input a_rst_i, + output [9:0] wr_datacount_o, + output [9:0] rd_datacount_o +); +`IP_MODULE_NAME(efx_fifo_top) +#( + .SYNC_CLK (0), + .SYNC_STAGE (2), + .DATA_WIDTH (16), + .MODE ("FWFT"), + .OUTPUT_REG (0), + .PROG_FULL_ASSERT (128), + .PROGRAMMABLE_FULL ("NONE"), + .PROG_FULL_NEGATE (128), + .PROGRAMMABLE_EMPTY ("NONE"), + .PROG_EMPTY_ASSERT (2), + .PROG_EMPTY_NEGATE (3), + .OPTIONAL_FLAGS (0), + .PIPELINE_REG (1), + .DEPTH (512), + .FAMILY ("TITANIUM"), + .ASYM_WIDTH_RATIO (4), + .BYPASS_RESET_SYNC (0), + .ENDIANESS (0), + .RAM_STYLE ("block_ram"), + .OVERFLOW_PROTECT (0), + .UNDERFLOW_PROTECT (0) +) +u_efx_fifo_top +( + .full_o ( full_o ), + .empty_o ( empty_o ), + .wr_clk_i ( wr_clk_i ), + .rd_clk_i ( rd_clk_i ), + .wr_en_i ( wr_en_i ), + .rd_en_i ( rd_en_i ), + .wdata ( wdata ), + .rst_busy ( rst_busy ), + .rdata ( rdata ), + .a_rst_i ( a_rst_i ), + .wr_datacount_o ( wr_datacount_o ), + .rd_datacount_o ( rd_datacount_o ) +); +endmodule + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian + parameter RAM_STYLE = "block_ram" +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + // NIC + //wr_ack <= wr_en_int & ~wr_overflow; + wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; + end + end + end + + if (OVERFLOW_PROTECT) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else begin + wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; + end + end + end + + if (UNDERFLOW_PROTECT) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else begin + rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + // NIC + else if (ASYM_WIDTH_RATIO == 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - raddr_int; + assign rd_datacount_int = waddr_int - raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + // NIC + //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_r <= 'h0; + end + else begin + waddr_cntr_r <= waddr_cntr; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + end + // NIC + //else if (rd_en_int) begin + else begin + //raddr_cntr <= raddr_cntr + 1'b1; + //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); + raddr_cntr <= ram_raddr; + end +end +// NIC +assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); + + +generate + if (SYNC_CLK) begin : sync_clk + if (MODE == "FWFT") begin + assign waddr_int = waddr_cntr_r; + assign raddr_int = raddr_cntr; + end + else begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr; + end + end + else begin : async_clk + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_resetsync) #( + parameter ASYNC_STAGE = 2, + parameter ACTIVE_LOW = 1 +) ( + input wire clk, + input wire reset, + output wire d_o +); + + +generate + if (ACTIVE_LOW == 1) begin: active_low + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (1), + .RST_VALUE (0) + ) efx_resetsync_active_low ( + .clk (clk), + .reset_n (reset), + .d_i (1'b1), + .d_o (d_o) + ); + end + else begin: active_high + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (0), + .RST_VALUE (1) + ) efx_resetsync_active_high ( + .clk (clk), + .reset_n (reset), + .d_i (1'b0), + .d_o (d_o) + ); + end +endgenerate + +endmodule + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_asyncreg) #( + parameter ASYNC_STAGE = 2, + parameter WIDTH = 4, + parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset + parameter RST_VALUE = 0, + parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance +) ( + input wire clk, + input wire reset_n, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + + + + + + + + + + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect author = "author-a" , author_info = "author-a-details" +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V +o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE +El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY +kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc +/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 +uYJaS5tuGEuFInBHa7oO8g== +`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 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+RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk +1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw +Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz +eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0 +2HflB1HYKxojQCcZU7qUgQ== +`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx +Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB +rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr +XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD +e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod +B2Zpo2FQ//YDRSAaEa9ksQ== +`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze +vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 +ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 +06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP +fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN +ZoPzFCMjGk5ZmMyIlytNCw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 ) +`pragma protect data_block +0d33xo/2RnBYy8BD6jq1J42m9u/75PA0owNvxlnr0TDOq7sF8XT6xouctVD1XQW2 +Ylwj0urY+dCJZku0aGRpcvb3H/nTlKVdEZOEl4QqB1gNGz/3mz75A3eudu5zgHEr +MaagjyQfDnoIqLWi1r5uTZrlS298IvNcGAJ+xXzpmkFmfG4Tk/5Jf2GPAPVtjREI +01kt8Go4CL1WNxBKcwm0xCiCchxvZ2oEtpERiC+7LUalgTJapIVoLFpvFv98229k +egvgF1KHNj0rAKedSG2Xo58TyA4iZXJJDdtgCxiKgu3Rimjno7l+ekApwmvx8n+p +yHkRGqetWfRhyE4A5q03RzOeSdA6NbCqijB3NPw/p58brAbA35rrjYpGIZXtZ4mU +De3As8VtD64nS2PRuf4/a2lIcDbwMjNTfMpN7iJfVBJ0/48tLHdetx592TLXenkF +GvAZ2yxoyBYzKctj4Keo+19Xp1UjVd3fr2MR3A7nmxLRKDA+upDxQ7ql8+pR7Moh +0b53/4Ri3Mkl+7EC1KXJNt2VbkZmcT7OAFIoPpibmcXS2R6DNVrhSKzfc2+TRM9r +mwRrJy9/R5RR+WGfw1S57Ho3wBPf4belj+Tfd7yhnwOVRXkTMq5M1BiigrGeeQ3q +z/hc1Kg8b/R+g7lnU0pqASnExPQW/DIMfH1RX75U68CAgaBAH22Vcbkoibp8sxyO +g18LefEh48UffnbpCKyv7SQ3LAdj+YO+KvvXHj1eW+CH7GA2lC5vt2be5Ah2/13H +bCeZ+srG6r7wmafy9MNNh8AgjUfZWwMnuJdCIcHTOfAncCd2B0T1Oza4VIkvnSl5 +60V34JXkfrGsNuHxwCF/sRSBbZUSpqig4ZGYHjOHldx2OANZQeUvLES3fwScYY5D +7SpR4ofVxIB/ev/+RXzvC3MNk1N0GT4F1XwokeeQIr/ilRETe/pFvEKttvviZ7uJ +uEVblS2v61DMXEgDavkbA0WdhMChPulwDvZtisWT4hCKRxfuBvNBtz0wH/WgRoX3 +aipWvPJG3G0xvO0u0EQVNdcxE+LZ7vyGF5HWEwKdQYDyhH+yVDeG+M/b08dU2aq4 +sG7dyygyVnzVbk2Lf0nCkGqKkUZUr05Zim0Wcflkhkqy348SOZ3xmEGuYAkzelLV +feQ+0ScsscFL5Cq4ETfFrN8GO8M5kkBN2ELs1MQecPRsgMCh0hcvd8IQrJTybQPW +aqwp9mgnFvS8AJ1ct+XgrAt8zgVnhaZGS9TKa6OWbr0U+SD5m+/pXjNsZA2dni6b +85/PmQeWeAarE/+EaJn/hlP6y3x3R3ItU8Itf6SB50LZ17LAhIRSIYsa7LBBNWOk +ngFHcGBCJnqTJv3hdVqa9cYipZ98XCa8dqrtAM5Rkxwd6H8KxXA+B+PWEz/cQWlb +szi9u5ufmyaJp6PWhklroQkPJEorUtF96X763itgtlAMHfkZglkElUD/gPlkXLtl +yquUmHqPK5D2pJDq0Q0jromE2yrr9fl3OI+eBehd2YBUivGKeaDFkPx7HbzWp9ok +9bT55H8VKYyF1awcjNND+WcXzm2WfvZHBDUJkRm7dnOQRvcX2RxlPRZSzAA3irVn +GFbHXD0RYn/dUR7Vy4kU68P5S5q4bUxD5vmUCN9vDoCivY7WCnlQCHQs3+iFblzP +A636C3dNQMSw0pjDisiZB63VczY8bivFh3cO82inNw5r2IZjvMB9XPhc4FHuIpfR +F7ptW0TUnO1MSDcZvCnjUfVSnHN22l2FM/P5oI1SbG3W+8YmxBvto8jwpES4ohOQ +YSECrvWkLklq68FVTzB7Tvg3JLdSy3TEKBuZE/ot0w/SXusFovOwd4aeiNDAmzwl +fQuCYHuJ0UKLaVNVAO4mw91PJODKCk2NYTr0ghOLovOXiMhUYtXZ+wFchXVkQKDI +B8BXjM7P+blhoOFA6AhRuCX4gZn0dP6m99qnyBJoxf1/FyfJXuklnPll93amUYUx +MzxNNTf7F08tnKQ8pTOk2mfFZnhA2MFn4XQ9FaGvtUrlJI8bvJTWiZFMF0eOJdIw +kzYOXEzKBjIdWW4rtTZmQJb7AOrznUpYdgTAPip/DQx6cg1+tZAVwhZPCjCsb5wa +em5hMtISQKDc92QrlU5O74OXe7641fzFRcKqy9AzwhZl+tmHk1uvpDkpsYiMa7Rk +YrbIjsKQV36PTqYPvxq1EiwYF8PMRf9FG8JZk85EZdM6QEGuehDHqFcZ+SlUb7/e +ji6GgjKxcZwaRREGKSOslcscHS6QNuGCF3iInqNCT4V2l7nboWOefMT2f1kmQOdE +szTFg563SQ8pu7ok3T3XNqUDi5ulvF+XGHDhcQ2hTkZ+xQ8dHFAWZdgzEGMXF2Lw +jU+ZRA2JULfjxOMIU2j9f+aGWmFx2PELMA5K5uOWYUQG2Fn04p1D6u8MEe7fIPeI +k7KH8j/Tumj+kG4t/lCrme6VM9u6A2NGddX1yH1NCejfophy3UWJg9wL/dNxzf6t +vXdm3rGPdZPWFgSIuGlmT03QZmWGPbs8qvkkUVAL37kMJP2r4L+PI00ZxbX8V5jp +GgYN1Rh+NSOwAcUEFCViRhFYC+Gi5eZ6AF6XDSU6qfjGsUKqJ9yrNx0Km6+SjpAK +7Zxblp7vweFVkJ7IESoFeB+vP8JNeoidbBPGEWo+2V08PgfGgjPEAA6pjj8uc0jC +SDFZ0sVrzvc66PZ5FxbI4g+VuXPJgyJsnQ/eHhPVTVTP3/oGMRVktNiJrkJYxAW7 +Sa/EJMjfXX+rMIWG5ssWLT6WfrojlHduEqJ9hJr24RZy514HHF8SMPRBLD6l1wd5 +07U/ChjFdy5qHn5Ce+lanjxnoxgvCsF3lMqoZ7e2bfzXakj7CxahwqRt6yeU0Q+/ +a8tvIJgHfdtOPw/r6HnSrzpdWzTx2e6/MEryHZqpMN63Lhakpjw1L7u3FD/rW40b +LGajigQ7Ql+cZmP7wYl+uSmTFIS6ZgXOc1ibb7yYxJwpeixPHL1iu5ltvriRiTZ6 +DMbbOjNpPuL7ie3AwgmwXwnpnTL6k/Rj2+ma3B7ImODBMkC4SLtTc0ynCcPAFZKA +Xh78wUAgt1T5Nm4XR555DBO7zPHX9rZzMLil4/j0RMDwn1gitmP2PSNFWsrXJG8p +C46kfpdqoM3Yf6HySlhsith6GW41sMF6imUXwahQQRw240HLW3N876LDe6bjTmgN +eIC7y/4NZk7OmpmP8udAEH+UsNfSGtKA8959AoJDr43XsWkOfccNWstu4sTXA5+w +pCALypmBMdholEsrW9DgsIgbgf2pcOAC9+mAjld+yyQ+UNdKRbmtRDHTztGmcVvw +Szip4YUuTM1tPzReucfm38gVFT7eo1qFQg/FJ4VgeYab7ku5OHuwZQmKyzng/t0U +A1lquVENVYQEIotBiOC7jQ1YTkTasGN4xoFgFTyKLFPyk8bl2/anzr1Fx0ieVGCx +2ipzG2JzIQf/FlHXaYrgkWiF817amty+KZp4/dCJtvDXxzOZKnBTVcjHXpqR1Ik+ +tdV+k+21tXZxP0rkG0yi4//2c5UiWGb0UegpemqutykLuT9tGjsqMuc5DaDH/8zk +wLTVfODT+HqN1/ZLqfq9VoAF5m/ujnPNt3wZcsjsAyBD153rW4Q2yVYMat0sFQN6 +XbNAeNBJZlO/aE1PfKBcSDFkJkPqRxlgdiE5B83/w1MP6Z4qwz7LJ8yTYM22xwRo +LIYpKq52yYMhJm42YeQxbBRTx0MyubCb+ompEVBF28Eh0vE98UAZj7t1szSweg99 +Wq6/4kxR2SQj8rFo2wrZe7ngsDmbIrMk2SinS6WmV4Mj+MBbPlmiuwB6NUV04Id1 +9enBBsJIfWt+PZJXyWkOoG/fOVBUxCY+CMCiab0qQ1EVdhggrdI30BgFqcLjfyD6 +/h5AqIzMGWrhWnap8WDEh1Ah6K9f2oCESSXO751sV5eK8jgl63FJMIVsnjVejxrl +Qa7PCXP3BO6Cnv896NBzAsddPq/AYBLHIC6eX3sTtOxTx52NsmJzoyUSJcAoA/QS +leHU1bLA2z+HGfMrkSzsuvXafmqr3B+PHfWdxrYzTxmVhMBPX/FvEU/gfxXGa6kj +niZYGue/Rk+zXL65ENgPwxiz0mm7QyQ6eMBMRovm6MGyIl/8obkOPygH+lhc+bgR +SNWLmxqjR2YABrKsUgCITQ6GK7VmVR3wOOwbZs+YW/0Yj2yzg7ESjaeqI40/OQFD +Ft2IHaURJPk6jl5vRrcCc0J0GCy7CK0BU14n+Nxfl2+CFRe4efoqZry/CmY2+S4M +p9OqgjUzHGSIbNRAXHf44nIAUjWYvijzzLSj9A7WY3TpYxgtqU8Wbf7SbWmw8RJV +pAYDHGmwHa8fL4Y9xEFF/WqmqWSL3g146i41MKWKY7lchvnWtc6yOgk+0geVFOpe +9BLs4TehFA/SueFC99S0Cxcxc0KMWXOKm0I3bI1CAlLje7wUcdI/pki33iqBLJlL +T2vz8ptPqfgAxDW0ZEvEYY/jfB+jCO0MKT7XK/LZNYSuEke3Y3CeuwZ/5IWkDcwy +7BArmDy7Hpw88le9ODL94mS1fUB8jsBaazeiXniZPNZjBkugt/ZAf4XYuoaGVPAM +DnRd8GW5eiDHFCEB42lpg9n7Ak8cXsSSlODCHeay2VtcQP1DEgwWdI5XdXE879gI +8lLU9bH2MfsxI2mNWCMv5immaioZJDorIVzyMGvIn3OcgqmhTU1owINUJf+Hm8Q7 +JfJq4m6t0J5eoKQH57uSGFkWRZ3dtp5QL3d5bBOMmorXUBzdrLt8wurvNke29bHD +UQdmANjayV8drYWAccZdPWyi9jNC/K31BTDI6RCpZdV3Wr5scOZdXWrl961jirm1 +g/2MGKxriuH2F4MRIh2vp3uS8PLbj4cHJv+5+LtLgs0lpdEMYAvJKDACRg68tDhY +XsF9lhHpcF5+tANOawRtnSvy/rlLn+A3wi7v8tnTZcLkocJ51c+nK5/Ij0YgUrA0 +eLrKNlJM78stswPWkvpBlAJ+G3D4Cw6P3XcJWrLyV3u79jf9PRJZmxMU/COGTmgQ +PJdXp90O3u2Pjdwhp4VdtBK2d/jTpk59j8xbQBavf5flZ+PzoLpd8NSt6GdPVJ5r +uVWvNy14pJXUsn+Tgxj+9Wp3vm5mofWtJAkEgr/Rfp7AVLLShJSd6vsbT7F2+TS/ +OMDv0XH92v1G4tqJ0rbxS1TnxX61+1sfjKlfIQdFR9gxLy71Tb705LQHBAw8vmSx +X6Uv+HbtPaEqRCF+pdvGsLNI2Seo6INA/mXqNpd6VPhfQHtp3bgV+Hxnlcc9lCiI +bCZq6KG4a6sVQHIZ3pZo7PQtoAo22niHvgZFoOVnBv+bu+blmvSV6gxCPoV8rwOe +/WD7YikHE7WVSq1SHtTIcbPv+K+1NKqZIiSCS2qDfJLgI7vH4zjIqibDhzGZTeKV +Km234SSlJ1OL4WQ5FtsxjednjUIAKqVe1auDiTzAKY28dwUkwGN/XXQ+EjrmxQuL +qIAT3WP49EeM+CQCp3D6Vxzm7Picq+RtwtbAXnnSQtvPcaSprODI089a0iR46Pp/ +4DLMUOLS+01HozXF1589YdqYep05No/Fp4eP2RdQxicYxK8d/OcvG7E8F1URVmAa +XdZxVa9caM3xYMWDZaiaOo6IZ+YM5VeZ4KxUblS1L1IlOnGOOZ3AiaLsHOh55ryc +Ei7EaFpheCmlTJyxUg8TdA== +`pragma protect end_protected + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Ti375C529_devkit/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_define.svh b/Ti375C529_devkit/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_define.svh new file mode 100644 index 0000000..d6e5cb2 --- /dev/null +++ b/Ti375C529_devkit/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_define.svh @@ -0,0 +1,66 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 8.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 2; +localparam DATA_WIDTH = 16; +localparam MODE = "FWFT"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 128; +localparam PROGRAMMABLE_FULL = "NONE"; +localparam PROG_FULL_NEGATE = 128; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 2; +localparam PROG_EMPTY_NEGATE = 3; +localparam OPTIONAL_FLAGS = 0; +localparam PIPELINE_REG = 1; +localparam DEPTH = 512; +localparam FAMILY = "TITANIUM"; +localparam ASYM_WIDTH_RATIO = 4; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; +localparam RAM_STYLE = "block_ram"; +localparam OVERFLOW_PROTECT = 0; +localparam UNDERFLOW_PROTECT = 0; diff --git a/Ti375C529_devkit/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.sv b/Ti375C529_devkit/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.sv new file mode 100644 index 0000000..a0f357f --- /dev/null +++ b/Ti375C529_devkit/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.sv @@ -0,0 +1,60 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 8.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +gTSE_core_fifo_ctrl u_gTSE_core_fifo_ctrl +( + .full_o ( full_o ), + .empty_o ( empty_o ), + .wr_clk_i ( wr_clk_i ), + .rd_clk_i ( rd_clk_i ), + .wr_en_i ( wr_en_i ), + .rd_en_i ( rd_en_i ), + .wdata ( wdata ), + .rst_busy ( rst_busy ), + .rdata ( rdata ), + .a_rst_i ( a_rst_i ), + .wr_datacount_o ( wr_datacount_o ), + .rd_datacount_o ( rd_datacount_o ) +); diff --git a/Ti375C529_devkit/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.vhd b/Ti375C529_devkit/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.vhd new file mode 100644 index 0000000..470be78 --- /dev/null +++ b/Ti375C529_devkit/ip/gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.vhd @@ -0,0 +1,75 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +component gTSE_core_fifo_ctrl is +port ( + full_o : out std_logic; + empty_o : out std_logic; + wr_clk_i : in std_logic; + rd_clk_i : in std_logic; + wr_en_i : in std_logic; + rd_en_i : in std_logic; + wdata : in std_logic_vector(15 downto 0); + rst_busy : out std_logic; + rdata : out std_logic_vector(15 downto 0); + a_rst_i : in std_logic; + wr_datacount_o : out std_logic_vector(9 downto 0); + rd_datacount_o : out std_logic_vector(9 downto 0) +); +end component gTSE_core_fifo_ctrl; + +---------------------- End COMPONENT Declaration ------------ +------------- Begin Cut here for INSTANTIATION Template ----- +u_gTSE_core_fifo_ctrl : gTSE_core_fifo_ctrl +port map ( + full_o => full_o, + empty_o => empty_o, + wr_clk_i => wr_clk_i, + rd_clk_i => rd_clk_i, + wr_en_i => wr_en_i, + rd_en_i => rd_en_i, + wdata => wdata, + rst_busy => rst_busy, + rdata => rdata, + a_rst_i => a_rst_i, + wr_datacount_o => wr_datacount_o, + rd_datacount_o => rd_datacount_o +); + +------------------------ End INSTANTIATION Template --------- diff --git a/Ti375C529_devkit/ip/gTSE_core_fifo_ctrl/ipm/component.pickle b/Ti375C529_devkit/ip/gTSE_core_fifo_ctrl/ipm/component.pickle new file mode 100644 index 0000000..61a1d4c Binary files /dev/null and b/Ti375C529_devkit/ip/gTSE_core_fifo_ctrl/ipm/component.pickle differ diff --git a/Ti375C529_devkit/ip/gTSE_core_fifo_ctrl/ipm/graph.pickle b/Ti375C529_devkit/ip/gTSE_core_fifo_ctrl/ipm/graph.pickle new file mode 100644 index 0000000..6aaff8c Binary files /dev/null and b/Ti375C529_devkit/ip/gTSE_core_fifo_ctrl/ipm/graph.pickle differ diff --git a/Ti375C529_devkit/ip/gTSE_core_fifo_ctrl/settings.json b/Ti375C529_devkit/ip/gTSE_core_fifo_ctrl/settings.json new file mode 100644 index 0000000..20c6360 --- /dev/null +++ b/Ti375C529_devkit/ip/gTSE_core_fifo_ctrl/settings.json @@ -0,0 +1,75 @@ +{ + "args": [ + "-o", + "gTSE_core_fifo_ctrl", + "--base_path", + "/projects/SSE/llching/repo/efx_IP_master/efx_IP/efx_hard_soc/fpga/Ti375C529_devkit/ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "memory", + "name": "efx_fifo_top", + "version": "8.1" + } + ], + "conf": { + "SYNC_CLK": "0", + "SYNC_STAGE": "2", + "DEPTH_2": "9", + "DATA_WIDTH": "16", + "MODE": "\"FWFT\"", + "OUTPUT_REG": "0", + "PROG_FULL_ASSERT": "128", + "PROGRAMMABLE_FULL": "\"NONE\"", + "PFN_INTERNAL": "127", + "PEA_INTERNAL": "2", + "PEN_INTERNAL": "3", + "PROGRAMMABLE_EMPTY": "\"NONE\"", + "OPTIONAL_FLAGS": "0", + "PIPELINE_REG": "1", + "ASYM_WIDTH_RATIO": "4", + "BYPASS_RESET_SYNC": "0", + "ENDIANESS": "0", + "RAM_STYLE": "\"block_ram\"", + "OVERFLOW_PROTECT": "0", + "UNDERFLOW_PROTECT": "0" + }, + "output": { + "external_source_source": [ + "gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl.sv", + "gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_define.svh", + "gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.sv", + "gTSE_core_fifo_ctrl/gTSE_core_fifo_ctrl_tmpl.vhd" + ], + "external_example_example": [ + "gTSE_core_fifo_ctrl/T20F256_devkit/fifo_demo.peri.xml", + "gTSE_core_fifo_ctrl/T20F256_devkit/fifo_demo.xml", + "gTSE_core_fifo_ctrl/T20F256_devkit/fifo_demo_top.v", + "gTSE_core_fifo_ctrl/T20F256_devkit/fifo_demo_T20.sdc", + "gTSE_core_fifo_ctrl/T20F256_devkit/efx_symmetric_width_fifo_top.sv", + "gTSE_core_fifo_ctrl/T20F256_devkit/gTSE_core_fifo_ctrl.sv", + "gTSE_core_fifo_ctrl/T20F256_devkit/gTSE_core_fifo_ctrl_define.svh" + ], + "external_example_2": [ + "gTSE_core_fifo_ctrl/Ti60F225_devkit/fifo_demo.peri.xml", + "gTSE_core_fifo_ctrl/Ti60F225_devkit/fifo_demo.xml", + "gTSE_core_fifo_ctrl/Ti60F225_devkit/fifo_demo_top.v", + "gTSE_core_fifo_ctrl/Ti60F225_devkit/fifo_demo_Ti60.sdc", + "gTSE_core_fifo_ctrl/Ti60F225_devkit/efx_symmetric_width_fifo_top.sv", + "gTSE_core_fifo_ctrl/Ti60F225_devkit/gTSE_core_fifo_ctrl.sv", + "gTSE_core_fifo_ctrl/Ti60F225_devkit/gTSE_core_fifo_ctrl_define.svh" + ], + "external_testbench_testbench": [ + "gTSE_core_fifo_ctrl/Testbench/fifo_tb.sv", + "gTSE_core_fifo_ctrl/Testbench/xrun.sh", + "gTSE_core_fifo_ctrl/Testbench/msim.sh", + "gTSE_core_fifo_ctrl/Testbench/flist", + "gTSE_core_fifo_ctrl/Testbench/modelsim.do", + "gTSE_core_fifo_ctrl/Testbench/gTSE_core_fifo_ctrl.sv", + "gTSE_core_fifo_ctrl/Testbench/gTSE_core_fifo_ctrl_define.svh" + ] + }, + "ooc_synthesis": {}, + "sw_version": "2025.2.272", + "generated_date": "2025-10-16T09:35:38.547531+00:00" +} \ No newline at end of file diff --git a/Ti375C529_devkit/ip/gTSE_core_fifo_data/gTSE_core_fifo_data.sv b/Ti375C529_devkit/ip/gTSE_core_fifo_data/gTSE_core_fifo_data.sv new file mode 100644 index 0000000..79ebb98 --- /dev/null +++ b/Ti375C529_devkit/ip/gTSE_core_fifo_data/gTSE_core_fifo_data.sv @@ -0,0 +1,1587 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 8.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +`define IP_UUID _b22e1dac76b0412988d984e3bea79485 +`define IP_NAME_CONCAT(a,b) a``b +`define IP_MODULE_NAME(name) `IP_NAME_CONCAT(name,`IP_UUID) +module gTSE_core_fifo_data +( + output full_o, + output empty_o, + input wr_clk_i, + input rd_clk_i, + input wr_en_i, + input rd_en_i, + input [12:0] wdata, + output rst_busy, + output [12:0] rdata, + input a_rst_i, + output [12:0] wr_datacount_o, + output [12:0] rd_datacount_o +); +`IP_MODULE_NAME(efx_fifo_top) +#( + .SYNC_CLK (0), + .SYNC_STAGE (2), + .DATA_WIDTH (13), + .MODE ("STANDARD"), + .OUTPUT_REG (0), + .PROG_FULL_ASSERT (128), + .PROGRAMMABLE_FULL ("NONE"), + .PROG_FULL_NEGATE (128), + .PROGRAMMABLE_EMPTY ("NONE"), + .PROG_EMPTY_ASSERT (2), + .PROG_EMPTY_NEGATE (3), + .OPTIONAL_FLAGS (0), + .PIPELINE_REG (1), + .DEPTH (4096), + .FAMILY ("TITANIUM"), + .ASYM_WIDTH_RATIO (4), + .BYPASS_RESET_SYNC (0), + .ENDIANESS (0), + .RAM_STYLE ("block_ram"), + .OVERFLOW_PROTECT (0), + .UNDERFLOW_PROTECT (0) +) +u_efx_fifo_top +( + .full_o ( full_o ), + .empty_o ( empty_o ), + .wr_clk_i ( wr_clk_i ), + .rd_clk_i ( rd_clk_i ), + .wr_en_i ( wr_en_i ), + .rd_en_i ( rd_en_i ), + .wdata ( wdata ), + .rst_busy ( rst_busy ), + .rdata ( rdata ), + .a_rst_i ( a_rst_i ), + .wr_datacount_o ( wr_datacount_o ), + .rd_datacount_o ( rd_datacount_o ) +); +endmodule + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / gray2bin.v +// / / .' / +// __/ /.' / Description: +// __ \ / Gray to Binary Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_gray2bin) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] bin_o, + // input + input [WIDTH-1:0] gray_i); + +//--------------------------------------------------------------------- +// Recursive Module +// Description: reduction xor +generate + if (WIDTH > 1) begin + wire [1:0] bin_1; + assign bin_1 = {gray_i[WIDTH-1], gray_i[WIDTH-1]^gray_i[WIDTH-2]}; + if (WIDTH == 2) begin + assign bin_o = bin_1; + end + else begin + assign bin_o[WIDTH-1] = bin_1[1]; + `IP_MODULE_NAME(efx_fifo_gray2bin) #(.WIDTH(WIDTH-1)) u_gray2bin (.bin_o(bin_o[WIDTH-2:0]), .gray_i({bin_1[0], gray_i[WIDTH-3:0]})); + end + end + else /* if (WIDTH == 1) */ + assign bin_o = gray_i; +endgenerate + +endmodule + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved. +// / / \ +// / / .. / bin2gray.v +// / / .' / +// __/ /.' / Description: +// __ \ / Binary to Gray Encoding Convertor +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// 1.0 Initial rev +// +// ******************************* + +`resetall +`timescale 1ns/1ps + +module `IP_MODULE_NAME(efx_fifo_bin2gray) +#(parameter WIDTH=5) +(// outputs + output wire [WIDTH-1:0] gray_o, + // input + input [WIDTH-1:0] bin_i + ); + +//--------------------------------------------------------------------- +// Function : bit_xor +// Description: reduction xor +function bit_xor ( + input [31:0] nex_bit, + input [31:0] curr_bit, + input [WIDTH-1:0] xor_in); + begin : fn_bit_xor + bit_xor = xor_in[nex_bit] ^ xor_in[curr_bit]; + end +endfunction + +// Convert Binary to Gray, bit by bit +generate +begin + genvar bit_idx; + for(bit_idx=0; bit_idx 1) begin + depth = depth - 1; + for (depth2width=0; depth>0; depth2width = depth2width + 1) + depth = depth>>1; + end + else + depth2width = 0; +end +endfunction + +function integer width2depth; +input [31:0] width; +begin : fnWidth2Depth + width2depth = width**2; +end +endfunction + +function integer rdwidthcompute; +input [31:0] asym_option; +input [31:0] wr_width; +begin : RdWidthCompute + rdwidthcompute = (asym_option==0)? wr_width/16 : + (asym_option==1)? wr_width/8 : + (asym_option==2)? wr_width/4 : + (asym_option==3)? wr_width/2 : + (asym_option==4)? wr_width/1 : + (asym_option==5)? wr_width*2 : + (asym_option==6)? wr_width*4 : + (asym_option==7)? wr_width*8 : + (asym_option==8)? wr_width*16 : wr_width/1; +end +endfunction + +function integer rddepthcompute; +input [31:0] wr_depth; +input [31:0] wr_width; +input [31:0] rd_width; +begin : RdDepthCompute + rddepthcompute = (wr_depth * wr_width) / rd_width; +end +endfunction + +endmodule + + +///////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2021 Efinix Inc. All rights reserved. +// / / \ +// / / .. / simple_dual_port_ram_fifo.v +// / / .' / +// __/ /.' / Description: +// __ \ / EFX FIFO +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// ******************************* +// Revisions: +// +// ******************************* + +module `IP_MODULE_NAME(efx_fifo_ram) #( + parameter FAMILY = "TRION", + parameter WR_DEPTH = 512, + parameter RD_DEPTH = 512, + parameter WDATA_WIDTH = 8, + parameter RDATA_WIDTH = 8, + parameter WADDR_WIDTH = 9, + parameter RADDR_WIDTH = 9, + parameter OUTPUT_REG = 1, + parameter RAM_MUX_RATIO = 4, + parameter ENDIANESS = 0, //0: Big endian (default) 1: Little endian + parameter RAM_STYLE = "block_ram" +) ( + input wire wclk, + input wire rclk, + input wire we, + input wire re, + input wire [(WDATA_WIDTH-1):0] wdata, + input wire [(WADDR_WIDTH-1):0] waddr, + input wire [(RADDR_WIDTH-1):0] raddr, + output wire [(RDATA_WIDTH-1):0] rdata +); + +localparam MEM_DEPTH = (WR_DEPTH > RD_DEPTH) ? WR_DEPTH : RD_DEPTH; +localparam MEM_DATA_WIDTH = (WDATA_WIDTH > RDATA_WIDTH) ? RDATA_WIDTH : WDATA_WIDTH; +localparam LSB_WIDTH = (WADDR_WIDTH > RADDR_WIDTH) ? (WADDR_WIDTH - RADDR_WIDTH) : (RADDR_WIDTH - WADDR_WIDTH); +localparam RDATA_WDATA_RATIO = (RDATA_WIDTH <= WDATA_WIDTH/32) ? "ONE_THIRTYTWO" : + (RDATA_WIDTH <= WDATA_WIDTH/16) ? "ONE_SIXTEENTH" : + (RDATA_WIDTH <= WDATA_WIDTH/8) ? "ONE_EIGHTH" : + (RDATA_WIDTH <= WDATA_WIDTH/4) ? "ONE_FOURTH" : + (RDATA_WIDTH <= WDATA_WIDTH/2) ? "ONE_HALF" : + (RDATA_WIDTH <= WDATA_WIDTH) ? "ONE" : + (RDATA_WIDTH <= WDATA_WIDTH*2) ? "TWO_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "FOUR_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "EIGHT_TIMES" : + (RDATA_WIDTH <= WDATA_WIDTH*4) ? "SIXTEEN_TIMES" : "THIRTYTWO_TIMES"; + +(* syn_ramstyle = RAM_STYLE *) reg [MEM_DATA_WIDTH-1:0] ram[MEM_DEPTH-1:0]; +reg [RDATA_WIDTH-1:0] r_rdata_1P; +reg [RDATA_WIDTH-1:0] r_rdata_2P; + +wire re_int; + +generate + if (FAMILY == "TRION") begin + if (RDATA_WDATA_RATIO == "ONE") begin + always @ (posedge wclk) begin + if (we) + ram[waddr] <= wdata; + end + + always @ (posedge rclk) begin + if (re_int) begin + r_rdata_1P <= ram[raddr]; + end + r_rdata_2P <= r_rdata_1P; + end + end + + else if (RDATA_WDATA_RATIO == "ONE_THIRTYTWO" || RDATA_WDATA_RATIO == "ONE_SIXTEENTH" || RDATA_WDATA_RATIO == "ONE_EIGHTH" || RDATA_WDATA_RATIO == "ONE_FOURTH" || RDATA_WDATA_RATIO == "ONE_HALF" ) begin + if (ENDIANESS == 0) begin + integer i; + always @ (posedge wclk) begin + for (i=0; i= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else if (PROGRAMMABLE_FULL == "STATIC_DUAL") begin + reg wr_prog_full_int; + assign wr_prog_full = wr_prog_full_int ? wr_datacount >= PROG_FULL_NEGATE : wr_datacount >= PROG_FULL_ASSERT; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_prog_full_int <= 1'b0; + end + else begin + wr_prog_full_int <= wr_prog_full; + end + end + end + else begin + assign wr_prog_full = 1'b0; + end + + if (PROGRAMMABLE_EMPTY == "STATIC_SINGLE") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_datacount <= PROG_EMPTY_ASSERT; + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else if (PROGRAMMABLE_EMPTY == "STATIC_DUAL") begin + reg rd_prog_empty_int; + assign rd_prog_empty = rd_prog_empty_int ? (rd_datacount <= PROG_EMPTY_NEGATE) : (rd_datacount <= PROG_EMPTY_ASSERT); + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_prog_empty_int <= 1'b1; + end + else begin + rd_prog_empty_int <= rd_prog_empty; + end + end + end + else begin + assign rd_prog_empty = 1'b0; + end + + if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_ack <= 1'b0; + end + else begin + // NIC + //wr_ack <= wr_en_int & ~wr_overflow; + wr_ack <= OVERFLOW_PROTECT ? wr_en_int & ~wr_overflow : wr_en_int; + end + end + end + + if (OVERFLOW_PROTECT) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else if (we && wr_full) begin + wr_overflow <= 1'b1; + end + else begin + wr_overflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + wr_overflow <= 1'b0; + end + else begin + wr_overflow <= we && wr_full ? 1'b1 : wr_overflow; + end + end + end + + if (UNDERFLOW_PROTECT) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else if (re && rd_empty) begin + rd_underflow <= 1'b1; + end + else begin + rd_underflow <= 1'b0; + end + end + end + else if (HANDSHAKE_FLAG) begin + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + rd_underflow <= 1'b0; + end + else begin + rd_underflow <= re && rd_empty ? 1'b1 : rd_underflow; + end + end + end + + localparam RATIO_WIDTH = (RADDR_WIDTH >= WADDR_WIDTH)? RADDR_WIDTH - WADDR_WIDTH : WADDR_WIDTH - RADDR_WIDTH; + + if (ASYM_WIDTH_RATIO < 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:RATIO_WIDTH]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:RATIO_WIDTH]; + assign wr_datacount_int = waddr_cntr - (raddr_int/RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int*RAM_MUX_RATIO)-raddr_cntr; + end + // NIC + else if (ASYM_WIDTH_RATIO == 4) begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:0] == raddr_int[RADDR_WIDTH-1:0]); + assign rd_empty_int = waddr_int[WADDR_WIDTH:0] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - raddr_int; + assign rd_datacount_int = waddr_int - raddr_cntr; + end + else begin + assign wr_full = (waddr_cntr[WADDR_WIDTH]^raddr_int[RADDR_WIDTH]) & (waddr_cntr[WADDR_WIDTH-1:RATIO_WIDTH] == raddr_int[RADDR_WIDTH-1:0]); + // NIC + //assign rd_empty_int = (waddr_int- raddr_cntr*RAM_MUX_RATIO) < RAM_MUX_RATIO; + assign rd_empty_int = waddr_int[WADDR_WIDTH:RATIO_WIDTH] == raddr_cntr[RADDR_WIDTH:0]; + assign wr_datacount_int = waddr_cntr - (raddr_int*RAM_MUX_RATIO); + assign rd_datacount_int = (waddr_int/RAM_MUX_RATIO)-raddr_cntr; + end +endgenerate + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr <= 'h0; + end + else if (wr_en_int) begin + waddr_cntr <= waddr_cntr + 1'b1; + end +end + +always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_r <= 'h0; + end + else begin + waddr_cntr_r <= waddr_cntr; + end +end + +always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr <= 'h0; + end + // NIC + //else if (rd_en_int) begin + else begin + //raddr_cntr <= raddr_cntr + 1'b1; + //raddr_cntr <= raddr_cntr + (re & ~rd_empty_int); + raddr_cntr <= ram_raddr; + end +end +// NIC +assign ram_raddr = raddr_cntr + (UNDERFLOW_PROTECT ? re & ~rd_empty_int : re); + + +generate + if (SYNC_CLK) begin : sync_clk + if (MODE == "FWFT") begin + assign waddr_int = waddr_cntr_r; + assign raddr_int = raddr_cntr; + end + else begin + assign waddr_int = waddr_cntr; + assign raddr_int = raddr_cntr; + end + end + else begin : async_clk + reg [RADDR_WIDTH:0] raddr_cntr_gry_r; + reg [WADDR_WIDTH:0] waddr_cntr_gry_r; + + wire [RADDR_WIDTH:0] raddr_cntr_gry; + wire [RADDR_WIDTH:0] raddr_cntr_gry_sync; + wire [RADDR_WIDTH:0] raddr_cntr_sync_g2b; + wire [WADDR_WIDTH:0] waddr_cntr_gry; + wire [WADDR_WIDTH:0] waddr_cntr_gry_sync; + wire [WADDR_WIDTH:0] waddr_cntr_sync_g2b; + + if (PIPELINE_REG) begin + reg [RADDR_WIDTH:0] raddr_cntr_sync_g2b_r; + reg [WADDR_WIDTH:0] waddr_cntr_sync_g2b_r; + + assign waddr_int = waddr_cntr_sync_g2b_r; + assign raddr_int = raddr_cntr_sync_g2b_r; + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + raddr_cntr_sync_g2b_r <= 'h0; + end + else begin + raddr_cntr_sync_g2b_r <= raddr_cntr_sync_g2b; + end + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + waddr_cntr_sync_g2b_r <= 'h0; + end + else begin + waddr_cntr_sync_g2b_r <= waddr_cntr_sync_g2b; + end + end + end + else begin + assign waddr_int = waddr_cntr_sync_g2b; + assign raddr_int = raddr_cntr_sync_g2b; + end + + always @ (posedge rclk or posedge rd_rst) begin + if (rd_rst) begin + raddr_cntr_gry_r <= 'h0; + end + else begin + raddr_cntr_gry_r <= raddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_bin2gray (.bin_i(raddr_cntr), .gray_o(raddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (RADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) xrd2wr_addr_sync (.clk(wclk), .reset_n(wr_rst), .d_i(raddr_cntr_gry_r), .d_o(raddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(RADDR_WIDTH+1) ) xrd2wr_gray2bin (.gray_i(raddr_cntr_gry_sync), .bin_o(raddr_cntr_sync_g2b)); + + always @ (posedge wclk or posedge wr_rst) begin + if (wr_rst) begin + waddr_cntr_gry_r <= 'h0; + end + else begin + waddr_cntr_gry_r <= waddr_cntr_gry; + end + end + `IP_MODULE_NAME(efx_fifo_bin2gray) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_bin2gray (.bin_i(waddr_cntr), .gray_o(waddr_cntr_gry)); + `IP_MODULE_NAME(efx_asyncreg) # (.ASYNC_STAGE(SYNC_STAGE), .WIDTH (WADDR_WIDTH+1), .ACTIVE_LOW(0), .OFF_ASSERTION (1)) wr2rd_addr_sync (.clk(rclk), .reset_n(rd_rst), .d_i(waddr_cntr_gry_r), .d_o(waddr_cntr_gry_sync)); + `IP_MODULE_NAME(efx_fifo_gray2bin) # (.WIDTH(WADDR_WIDTH+1) ) wr2rd_gray2bin (.gray_i(waddr_cntr_gry_sync), .bin_o(waddr_cntr_sync_g2b)); + + end +endgenerate +endmodule + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_resetsync) #( + parameter ASYNC_STAGE = 2, + parameter ACTIVE_LOW = 1 +) ( + input wire clk, + input wire reset, + output wire d_o +); + + +generate + if (ACTIVE_LOW == 1) begin: active_low + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (1), + .RST_VALUE (0) + ) efx_resetsync_active_low ( + .clk (clk), + .reset_n (reset), + .d_i (1'b1), + .d_o (d_o) + ); + end + else begin: active_high + `IP_MODULE_NAME(efx_asyncreg) #( + .WIDTH (1), + .ACTIVE_LOW (0), + .RST_VALUE (1) + ) efx_resetsync_active_high ( + .clk (clk), + .reset_n (reset), + .d_i (1'b0), + .d_o (d_o) + ); + end +endgenerate + +endmodule + + + +// synopsys translate_off +`timescale 1 ns / 1 ps +// synopsys translate_on + +module `IP_MODULE_NAME(efx_asyncreg) #( + parameter ASYNC_STAGE = 2, + parameter WIDTH = 4, + parameter ACTIVE_LOW = 1, // 0 - Active high reset, 1 - Active low reset + parameter RST_VALUE = 0, + parameter OFF_ASSERTION = 0 // 1 = Turn off PULSE_WIDTH_CHK assertion for a particular instance +) ( + input wire clk, + input wire reset_n, + input wire [WIDTH-1:0] d_i, + output wire [WIDTH-1:0] d_o +); + + + + + + + + + + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect author = "author-a" , author_info = "author-a-details" +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2023.4" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +IjzmeF2ACtI8q/MHPcSQakfCyuQSUgg747Z3U+BWZdCStFbqF/Rhg0VPl8JT+91V +o/8Ohsiw6GnpSIX69XazqGYmhEjb+W7W2ngBYentEXdSyzUYvEbr8i71cL04f1fE +El78uYgSvjFwoDyocXOVYk8JA0v7y6WnabkL02lAqASKGQK55nzfKeUVbJHKHjAY +kIT3Nf7JWK2NVVymI1Zs5QttwrNgKBSqoiPvmy4+16bTQMx4R205Bb4rT1MqSqIc +/5U5/Z1e1tZzOqoEyhfcMMKW0emdBIdByNvteK05ZATt11Uzj2M/Vn1r9KmYd0h1 +uYJaS5tuGEuFInBHa7oO8g== +`pragma protect key_keyowner = "Cadence Design Systems." , key_keyname = "CDS_RSA_KEY_VER_2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +ABJo/BvEH9XbZrt+xPOQ2C7yeLcnebDlRELbHyCdXeeNkZRVZ9m0ie+1HufS/I+3 +fC63lnVTenVdf9s4tm1RLd5VBkmFb37ikgaESy2aRKWsdLG6x2OyuODoMDRCjYUa +rxhnwLWh5E55yR3XVZgM2k7/NPP2cTL7iOSCjH4No38siNjs4Fapyc4FFq0TOsQq +PMqsZ5jgmM+ZT8cil0wMt5tpdEOwvchbe1GcZLIhcIFLD/Gb2XtP0Q0QkOlNzuiL +DNyobLTjDkV5si+/23Ng2E7tDq+SX+vJP4ciI63kXtsmQdn1ff2Y64ibNXJtpu/w +K3OoKmk3zFeArSsql8B4/Q== +`pragma protect key_keyowner = "Synopsys" , key_keyname = "SNPS-VCS-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 128 ) +`pragma protect key_block +RAoMYYsrw2j05cvQ8NR0lCh+Ia/OGVfdwZqq0pwIkgDzO3Z7ol96oQmQzFfIQY/M +GzEOFdYJTfjnxPvhSPxT1tpq2Fgx6PbC2FMWFtN6/TrG/s01ifIWIZ9Wrfo8Q01l +6XTAESHR1htrOOx6AiDHAQLOlBb0zgfZjayGJBRX7FI= +`pragma protect key_keyowner = "Aldec" , key_keyname = "ALDEC15_001" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +YclPuIbYLW/ftZYybucr9ooblGFkJDcdUWf6kCJBGKpIRjItUB3LdSwcREekRWqf +RGiSRFoyrOTiScT06zZ4fkm+PEKj8O3RU1VMMzDjuEUqkAEELJHNOH71tCSC6MWk +1dop7MZy8BSXhzg3W3RXIA8IGSJRDibliv+SjkbUzg/WceDI176fJmUwGUji93Tw +Zu2vRjA/RTi3ZMzS/2Z9YE156hpipJ/Cu6ca8V3y5Kt6DX4fcCS09xESr6soT5Oz +eKRExN7wu8dvYMUuu1YgCVVR47BBDQi3wdZHqlq1PLaycnNOwBPLOAzA19Hefh/0 +2HflB1HYKxojQCcZU7qUgQ== +`pragma protect key_keyowner = "Siemens" , key_keyname = "SIEMENS-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +fMvC6d2jTMqMqGFzPCPWt6pV9wRUCG4/taH3Nfn7RcekdiLyXQEQgm1SN+X+hkbx +Pu7552vaw2ez4j3zrTk2vRPnDAsxY8GidEnkJcULi8kiia9Xy/ePFLxOJHHigkiB +rU7uwrFblcYYBRwQjhMhJDowyR9HVAonxhOWVIlYagtABxLYlNdDEn+N4yPLVCsr +XUWy1E2L5GUFFNQffENN0iyUaKdWAKGIqgIZK1sB3tVOPVsULetSoyzRErWPNZQD +e5jbBBNZGyQQWgOJkOfy280ekoUUEZajqtB1jDvE3k8kbo4rzvr7yTkhSzLqjGod +B2Zpo2FQ//YDRSAaEa9ksQ== +`pragma protect key_keyowner = "Mentor Graphics Corporation" , key_keyname = "MGC-VERIF-SIM-RSA-2" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +TcmE9lQROafuvxGWP3fMVxDoeaiMX6ALoT3detg/qWZ36+yPTc/t8N7/DtSx17Ze +vr6iBb+ge3aAzWAq2QHyVfgVV15dvW/HsOXXTh7UqExiO7Dxa6nHXuAhYMON6NP2 +ihfIRSvdnrL2ufvg7A2rCHGAqnr6cVnRLfhNJxtA1lloQbJEtlf/CWNblDxEfyw2 +06l3l8pp1rS0E4tMqagmOr+yhNSpcS9vQswFltqroh6kNIE64zKri96HKkRFLNlP +fpsN7plEpLS54SxIMmh8Op+w0a/jXVOxxD+FLepsZWfGiNksENgu2Xo6TvZIQUUN +ZoPzFCMjGk5ZmMyIlytNCw== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 4288 ) +`pragma protect data_block +0d33xo/2RnBYy8BD6jq1J42m9u/75PA0owNvxlnr0TDOq7sF8XT6xouctVD1XQW2 +Ylwj0urY+dCJZku0aGRpcvb3H/nTlKVdEZOEl4QqB1gNGz/3mz75A3eudu5zgHEr +MaagjyQfDnoIqLWi1r5uTZrlS298IvNcGAJ+xXzpmkFmfG4Tk/5Jf2GPAPVtjREI +01kt8Go4CL1WNxBKcwm0xCiCchxvZ2oEtpERiC+7LUalgTJapIVoLFpvFv98229k +egvgF1KHNj0rAKedSG2Xo58TyA4iZXJJDdtgCxiKgu3Rimjno7l+ekApwmvx8n+p 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+eIC7y/4NZk7OmpmP8udAEH+UsNfSGtKA8959AoJDr43XsWkOfccNWstu4sTXA5+w +pCALypmBMdholEsrW9DgsIgbgf2pcOAC9+mAjld+yyQ+UNdKRbmtRDHTztGmcVvw +Szip4YUuTM1tPzReucfm38gVFT7eo1qFQg/FJ4VgeYab7ku5OHuwZQmKyzng/t0U +A1lquVENVYQEIotBiOC7jQ1YTkTasGN4xoFgFTyKLFPyk8bl2/anzr1Fx0ieVGCx +2ipzG2JzIQf/FlHXaYrgkWiF817amty+KZp4/dCJtvDXxzOZKnBTVcjHXpqR1Ik+ +tdV+k+21tXZxP0rkG0yi4//2c5UiWGb0UegpemqutykLuT9tGjsqMuc5DaDH/8zk +wLTVfODT+HqN1/ZLqfq9VoAF5m/ujnPNt3wZcsjsAyBD153rW4Q2yVYMat0sFQN6 +XbNAeNBJZlO/aE1PfKBcSDFkJkPqRxlgdiE5B83/w1MP6Z4qwz7LJ8yTYM22xwRo +LIYpKq52yYMhJm42YeQxbBRTx0MyubCb+ompEVBF28Eh0vE98UAZj7t1szSweg99 +Wq6/4kxR2SQj8rFo2wrZe7ngsDmbIrMk2SinS6WmV4Mj+MBbPlmiuwB6NUV04Id1 +9enBBsJIfWt+PZJXyWkOoG/fOVBUxCY+CMCiab0qQ1EVdhggrdI30BgFqcLjfyD6 +/h5AqIzMGWrhWnap8WDEh1Ah6K9f2oCESSXO751sV5eK8jgl63FJMIVsnjVejxrl +Qa7PCXP3BO6Cnv896NBzAsddPq/AYBLHIC6eX3sTtOxTx52NsmJzoyUSJcAoA/QS +leHU1bLA2z+HGfMrkSzsuvXafmqr3B+PHfWdxrYzTxmVhMBPX/FvEU/gfxXGa6kj +niZYGue/Rk+zXL65ENgPwxiz0mm7QyQ6eMBMRovm6MGyIl/8obkOPygH+lhc+bgR +SNWLmxqjR2YABrKsUgCITQ6GK7VmVR3wOOwbZs+YW/0Yj2yzg7ESjaeqI40/OQFD +Ft2IHaURJPk6jl5vRrcCc0J0GCy7CK0BU14n+Nxfl2+CFRe4efoqZry/CmY2+S4M +p9OqgjUzHGSIbNRAXHf44nIAUjWYvijzzLSj9A7WY3TpYxgtqU8Wbf7SbWmw8RJV +pAYDHGmwHa8fL4Y9xEFF/WqmqWSL3g146i41MKWKY7lchvnWtc6yOgk+0geVFOpe +9BLs4TehFA/SueFC99S0Cxcxc0KMWXOKm0I3bI1CAlLje7wUcdI/pki33iqBLJlL +T2vz8ptPqfgAxDW0ZEvEYY/jfB+jCO0MKT7XK/LZNYSuEke3Y3CeuwZ/5IWkDcwy +7BArmDy7Hpw88le9ODL94mS1fUB8jsBaazeiXniZPNZjBkugt/ZAf4XYuoaGVPAM +DnRd8GW5eiDHFCEB42lpg9n7Ak8cXsSSlODCHeay2VtcQP1DEgwWdI5XdXE879gI +8lLU9bH2MfsxI2mNWCMv5immaioZJDorIVzyMGvIn3OcgqmhTU1owINUJf+Hm8Q7 +JfJq4m6t0J5eoKQH57uSGFkWRZ3dtp5QL3d5bBOMmorXUBzdrLt8wurvNke29bHD +UQdmANjayV8drYWAccZdPWyi9jNC/K31BTDI6RCpZdV3Wr5scOZdXWrl961jirm1 +g/2MGKxriuH2F4MRIh2vp3uS8PLbj4cHJv+5+LtLgs0lpdEMYAvJKDACRg68tDhY +XsF9lhHpcF5+tANOawRtnSvy/rlLn+A3wi7v8tnTZcLkocJ51c+nK5/Ij0YgUrA0 +eLrKNlJM78stswPWkvpBlAJ+G3D4Cw6P3XcJWrLyV3u79jf9PRJZmxMU/COGTmgQ +PJdXp90O3u2Pjdwhp4VdtBK2d/jTpk59j8xbQBavf5flZ+PzoLpd8NSt6GdPVJ5r +uVWvNy14pJXUsn+Tgxj+9Wp3vm5mofWtJAkEgr/Rfp7AVLLShJSd6vsbT7F2+TS/ +OMDv0XH92v1G4tqJ0rbxS1TnxX61+1sfjKlfIQdFR9gxLy71Tb705LQHBAw8vmSx +X6Uv+HbtPaEqRCF+pdvGsLNI2Seo6INA/mXqNpd6VPhfQHtp3bgV+Hxnlcc9lCiI +bCZq6KG4a6sVQHIZ3pZo7PQtoAo22niHvgZFoOVnBv+bu+blmvSV6gxCPoV8rwOe +/WD7YikHE7WVSq1SHtTIcbPv+K+1NKqZIiSCS2qDfJLgI7vH4zjIqibDhzGZTeKV +Km234SSlJ1OL4WQ5FtsxjednjUIAKqVe1auDiTzAKY28dwUkwGN/XXQ+EjrmxQuL +qIAT3WP49EeM+CQCp3D6Vxzm7Picq+RtwtbAXnnSQtvPcaSprODI089a0iR46Pp/ +4DLMUOLS+01HozXF1589YdqYep05No/Fp4eP2RdQxicYxK8d/OcvG7E8F1URVmAa +XdZxVa9caM3xYMWDZaiaOo6IZ+YM5VeZ4KxUblS1L1IlOnGOOZ3AiaLsHOh55ryc +Ei7EaFpheCmlTJyxUg8TdA== +`pragma protect end_protected + +`undef IP_UUID +`undef IP_NAME_CONCAT +`undef IP_MODULE_NAME diff --git a/Ti375C529_devkit/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_define.svh b/Ti375C529_devkit/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_define.svh new file mode 100644 index 0000000..90fdc68 --- /dev/null +++ b/Ti375C529_devkit/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_define.svh @@ -0,0 +1,66 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 8.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +localparam SYNC_CLK = 0; +localparam SYNC_STAGE = 2; +localparam DATA_WIDTH = 13; +localparam MODE = "STANDARD"; +localparam OUTPUT_REG = 0; +localparam PROG_FULL_ASSERT = 128; +localparam PROGRAMMABLE_FULL = "NONE"; +localparam PROG_FULL_NEGATE = 128; +localparam PROGRAMMABLE_EMPTY = "NONE"; +localparam PROG_EMPTY_ASSERT = 2; +localparam PROG_EMPTY_NEGATE = 3; +localparam OPTIONAL_FLAGS = 0; +localparam PIPELINE_REG = 1; +localparam DEPTH = 4096; +localparam FAMILY = "TITANIUM"; +localparam ASYM_WIDTH_RATIO = 4; +localparam BYPASS_RESET_SYNC = 0; +localparam ENDIANESS = 0; +localparam RAM_STYLE = "block_ram"; +localparam OVERFLOW_PROTECT = 0; +localparam UNDERFLOW_PROTECT = 0; diff --git a/Ti375C529_devkit/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.sv b/Ti375C529_devkit/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.sv new file mode 100644 index 0000000..1305620 --- /dev/null +++ b/Ti375C529_devkit/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.sv @@ -0,0 +1,60 @@ +// ============================================================================= +// Generated by efx_ipmgr +// Version: 2025.2.272 +// IP Version: 8.1 +// ============================================================================= + +//////////////////////////////////////////////////////////////////////////////// +// Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +// +// This document contains proprietary information which is +// protected by copyright. All rights are reserved. This notice +// refers to original work by Efinix, Inc. which may be derivitive +// of other work distributed under license of the authors. In the +// case of derivative work, nothing in this notice overrides the +// original author's license agreement. Where applicable, the +// original license agreement is included in it's original +// unmodified form immediately below this header. +// +// WARRANTY DISCLAIMER. +// THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +// EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +// RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +// INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +// PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +// WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +// +// LIMITATION OF LIABILITY. +// NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +// INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +// MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +// OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +// SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +// CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +// GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +// MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +// THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +// (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +// BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +// NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +// CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +// APPLY TO LICENSEE. +// +//////////////////////////////////////////////////////////////////////////////// + +gTSE_core_fifo_data u_gTSE_core_fifo_data +( + .full_o ( full_o ), + .empty_o ( empty_o ), + .wr_clk_i ( wr_clk_i ), + .rd_clk_i ( rd_clk_i ), + .wr_en_i ( wr_en_i ), + .rd_en_i ( rd_en_i ), + .wdata ( wdata ), + .rst_busy ( rst_busy ), + .rdata ( rdata ), + .a_rst_i ( a_rst_i ), + .wr_datacount_o ( wr_datacount_o ), + .rd_datacount_o ( rd_datacount_o ) +); diff --git a/Ti375C529_devkit/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.vhd b/Ti375C529_devkit/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.vhd new file mode 100644 index 0000000..513297d --- /dev/null +++ b/Ti375C529_devkit/ip/gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.vhd @@ -0,0 +1,75 @@ +-------------------------------------------------------------------------------- +-- Copyright (C) 2013-2025 Efinix Inc. All rights reserved. +-- +-- This document contains proprietary information which is +-- protected by copyright. All rights are reserved. This notice +-- refers to original work by Efinix, Inc. which may be derivitive +-- of other work distributed under license of the authors. In the +-- case of derivative work, nothing in this notice overrides the +-- original author's license agreement. Where applicable, the +-- original license agreement is included in it's original +-- unmodified form immediately below this header. +-- +-- WARRANTY DISCLAIMER. +-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND +-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH +-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES, +-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF +-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED +-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE. +-- +-- LIMITATION OF LIABILITY. +-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY +-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT +-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY +-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT, +-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY +-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF +-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR +-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN +-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER +-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE +-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO +-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR +-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT +-- APPLY TO LICENSEE. +-- +-------------------------------------------------------------------------------- +------------- Begin Cut here for COMPONENT Declaration ------ +component gTSE_core_fifo_data is +port ( + full_o : out std_logic; + empty_o : out std_logic; + wr_clk_i : in std_logic; + rd_clk_i : in std_logic; + wr_en_i : in std_logic; + rd_en_i : in std_logic; + wdata : in std_logic_vector(12 downto 0); + rst_busy : out std_logic; + rdata : out std_logic_vector(12 downto 0); + a_rst_i : in std_logic; + wr_datacount_o : out std_logic_vector(12 downto 0); + rd_datacount_o : out std_logic_vector(12 downto 0) +); +end component gTSE_core_fifo_data; + +---------------------- End COMPONENT Declaration ------------ +------------- Begin Cut here for INSTANTIATION Template ----- +u_gTSE_core_fifo_data : gTSE_core_fifo_data +port map ( + full_o => full_o, + empty_o => empty_o, + wr_clk_i => wr_clk_i, + rd_clk_i => rd_clk_i, + wr_en_i => wr_en_i, + rd_en_i => rd_en_i, + wdata => wdata, + rst_busy => rst_busy, + rdata => rdata, + a_rst_i => a_rst_i, + wr_datacount_o => wr_datacount_o, + rd_datacount_o => rd_datacount_o +); + +------------------------ End INSTANTIATION Template --------- diff --git a/Ti375C529_devkit/ip/gTSE_core_fifo_data/ipm/component.pickle b/Ti375C529_devkit/ip/gTSE_core_fifo_data/ipm/component.pickle new file mode 100644 index 0000000..c2645c9 Binary files /dev/null and b/Ti375C529_devkit/ip/gTSE_core_fifo_data/ipm/component.pickle differ diff --git a/Ti375C529_devkit/ip/gTSE_core_fifo_data/ipm/graph.pickle b/Ti375C529_devkit/ip/gTSE_core_fifo_data/ipm/graph.pickle new file mode 100644 index 0000000..c15a035 Binary files /dev/null and b/Ti375C529_devkit/ip/gTSE_core_fifo_data/ipm/graph.pickle differ diff --git a/Ti375C529_devkit/ip/gTSE_core_fifo_data/settings.json b/Ti375C529_devkit/ip/gTSE_core_fifo_data/settings.json new file mode 100644 index 0000000..62ba683 --- /dev/null +++ b/Ti375C529_devkit/ip/gTSE_core_fifo_data/settings.json @@ -0,0 +1,75 @@ +{ + "args": [ + "-o", + "gTSE_core_fifo_data", + "--base_path", + "/projects/SSE/llching/repo/efx_IP_master/efx_IP/efx_hard_soc/fpga/Ti375C529_devkit/ip", + "--vlnv", + { + "vendor": "efinixinc.com", + "library": "memory", + "name": "efx_fifo_top", + "version": "8.1" + } + ], + "conf": { + "SYNC_CLK": "0", + "SYNC_STAGE": "2", + "DEPTH_2": "12", + "DATA_WIDTH": "13", + "MODE": "\"STANDARD\"", + "OUTPUT_REG": "0", + "PROG_FULL_ASSERT": "128", + "PROGRAMMABLE_FULL": "\"NONE\"", + "PFN_INTERNAL": "127", + "PEA_INTERNAL": "2", + "PEN_INTERNAL": "3", + "PROGRAMMABLE_EMPTY": "\"NONE\"", + "OPTIONAL_FLAGS": "0", + "PIPELINE_REG": "1", + "ASYM_WIDTH_RATIO": "4", + "BYPASS_RESET_SYNC": "0", + "ENDIANESS": "0", + "RAM_STYLE": "\"block_ram\"", + "OVERFLOW_PROTECT": "0", + "UNDERFLOW_PROTECT": "0" + }, + "output": { + "external_source_source": [ + "gTSE_core_fifo_data/gTSE_core_fifo_data.sv", + "gTSE_core_fifo_data/gTSE_core_fifo_data_define.svh", + "gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.sv", + "gTSE_core_fifo_data/gTSE_core_fifo_data_tmpl.vhd" + ], + "external_example_example": [ + "gTSE_core_fifo_data/T20F256_devkit/fifo_demo.peri.xml", + "gTSE_core_fifo_data/T20F256_devkit/fifo_demo.xml", + "gTSE_core_fifo_data/T20F256_devkit/fifo_demo_top.v", + "gTSE_core_fifo_data/T20F256_devkit/fifo_demo_T20.sdc", + "gTSE_core_fifo_data/T20F256_devkit/efx_symmetric_width_fifo_top.sv", + "gTSE_core_fifo_data/T20F256_devkit/gTSE_core_fifo_data.sv", + "gTSE_core_fifo_data/T20F256_devkit/gTSE_core_fifo_data_define.svh" + ], + "external_example_2": [ + "gTSE_core_fifo_data/Ti60F225_devkit/fifo_demo.peri.xml", + "gTSE_core_fifo_data/Ti60F225_devkit/fifo_demo.xml", + "gTSE_core_fifo_data/Ti60F225_devkit/fifo_demo_top.v", + "gTSE_core_fifo_data/Ti60F225_devkit/fifo_demo_Ti60.sdc", + "gTSE_core_fifo_data/Ti60F225_devkit/efx_symmetric_width_fifo_top.sv", + "gTSE_core_fifo_data/Ti60F225_devkit/gTSE_core_fifo_data.sv", + "gTSE_core_fifo_data/Ti60F225_devkit/gTSE_core_fifo_data_define.svh" + ], + "external_testbench_testbench": [ + "gTSE_core_fifo_data/Testbench/fifo_tb.sv", + "gTSE_core_fifo_data/Testbench/xrun.sh", + "gTSE_core_fifo_data/Testbench/msim.sh", + "gTSE_core_fifo_data/Testbench/flist", + "gTSE_core_fifo_data/Testbench/modelsim.do", + "gTSE_core_fifo_data/Testbench/gTSE_core_fifo_data.sv", + "gTSE_core_fifo_data/Testbench/gTSE_core_fifo_data_define.svh" + ] + }, + "ooc_synthesis": {}, + "sw_version": "2025.2.272", + "generated_date": "2025-10-16T09:35:27.104449+00:00" +} \ No newline at end of file diff --git a/Ti375C529_devkit/source/MacRxCheckSumChecker.v b/Ti375C529_devkit/source/MacRxCheckSumChecker.v new file mode 100644 index 0000000..d13420d --- /dev/null +++ b/Ti375C529_devkit/source/MacRxCheckSumChecker.v @@ -0,0 +1,460 @@ +`timescale 1ns/1ps +`define IP_MODULE_NAME(name) name +module `IP_MODULE_NAME(MacRxCheckSumChecker) ( + input wire io_input_valid, + output reg io_input_ready, + input wire io_input_payload_last, + input wire io_input_payload_fragment_error, + input wire [7:0] io_input_payload_fragment_data, + output reg io_output_valid, + input wire io_output_ready, + output reg io_output_payload_last, + output reg io_output_payload_fragment_error, + output reg [7:0] io_output_payload_fragment_data, + input wire clk, + input wire reset +); +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +hitigEdAF1oYulO+rzgvZGPZ/Fd2rMxle3YAk5YXRsXciII9biXM11yT9um6jJ8+ +3kzVSR81TQjw7cIj5GSOo/ZUXLyM5C31H4zOLXmkRszAL1LLpcHPwqj/0zmRQxsk +Crgj5D989eHlroC0Prpz3dn6NdNSKLXz0GqV6d9E9r24bdIdCEg7IOxSJrlw18oq +t6GUxKyKSqV8FcH3XaacJ6RYAf6AeAQgEC04VhojxONJQnPlp2dcTeMRl6NhnRqs +sxE1pShW8ERncX+VZUigeFks09GmTIJcmh3dk//EuICiBGVdKtEDU3w0bxIs8mkX +fv849ddnaoUeK2vjnaRMXg== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 20032 ) +`pragma protect data_block +rCwwbt0+cyBbGJvD3UcIfPB8PO9JeIfGCIrZ80ZeBp71sOWySAsRKDi/6hP1ZYPG +EZhL/2cc6+0Zb3hMl6Z7/PADwMV7Kwbd0MTfq9LGUupuU5kHnYl240MwTwe3X3v+ +VbiK/mU/HKeVWh8IPvoGri6nCkEwQ3F5uMNdt+5hy4AI5PWbOTy+BpjJS7q2UMsk +rfGa7X/R6da9gXlEZiG/KYDnQP78Gg5nPwRAl7HNOP9dXfFoFjvIrJr02D+yIYhe +Q4SeOeFDoSDUOg8Y2XSYEQpT8Y+jS39V0vOS02OS6ay3Fs1qIsNoI/lb3YjzwCsZ +x7ShWL4wVoBa60xVXwgimM2yPNQrity/qzIuP2rzLvE82kh4abl2s86HdcP6En6B +86QzOBudvzzPytAESeQkv7pkd+n19y+sfbCUXUirdfGoEYa1h+0zBYiw6/YD5HdK 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+CAqv6/guzIMhv0ji5/42Ut70sAiYnSuLtjUswBKFIIQ/4lE0Lf4nXuFPkngnD9ZR +vQWiDPAr6jvPkEo2WPWnuTWrRC65yWWGTy4LVRVgRssVff8wF0DvjsGgPUEcjcM5 +rbgJO3OLJ7mDTuBU8T2FWf0PomDbDbWw0m4XwEYkuZmz/NrkAl/IAjKyXgcSiJTI +cXUoJH/6AqXMUDxei5HV3aeqYusmciLa+p3r4rHP6JMUP7H7EA7bQuRMohkOhzRc +o3zoREhPGeNDrc1jReZszqIvl3AqojeRytiieHj0avAMPHmX0a+/0rJPfxjg0GY7 +1HaTisqxJbDWbV49GlfnQg== +`pragma protect end_protected + +//pragma protect end + +`undef IP_MODULE_NAME diff --git a/Ti375C529_devkit/source/MacTxLso.v b/Ti375C529_devkit/source/MacTxLso.v new file mode 100644 index 0000000..8805316 --- /dev/null +++ b/Ti375C529_devkit/source/MacTxLso.v @@ -0,0 +1,1744 @@ +`timescale 1ns/1ps +`define IP_MODULE_NAME(name) name +module `IP_MODULE_NAME(MacTxLso) ( + input wire io_input_valid, + output wire io_input_ready, + input wire io_input_payload_last, + input wire [7:0] io_input_payload_fragment_data, + output wire io_output_valid, + input wire io_output_ready, + output wire io_output_payload_last, + output wire [7:0] io_output_payload_fragment_data, + input wire clk, + input wire reset +); +//pragma protect +//pragma protect begin + +/* Encryption Envelope */ + +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "QuestaSim" , encrypt_agent_info = "2021.1" +`pragma protect key_keyowner = "Efinix Inc." , key_keyname = "EFX_K01" +`pragma protect key_method = "rsa" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 256 ) +`pragma protect key_block +EYAd3mbn/xhar3hlqQhHXmi9nJO/Sc1phUP+NTKHH/cySFdPR/c6LtYnfdaakOst +DZn8xJcYSAxgRQrxWTES7TEnvtmukjAiedXml9QEurP5HyD300CnuOA/HNrQFS72 +ijRe6hCva+3p6g+osbxssWNj43uf3H7A3z00f+6LU+gLjl/cLAQopvRSpv9Cq4Wf +GA3mmls9DUOQ96sxBgLufDQ2V6kAggNRmbMbb4iks2sRddHYw6khj4qpbBu601G3 +SfzSAZcejK7it73r7Ku/bv8a995UcODh5Ya0pEiQ1O0NHuROqzGo/+rFQrBwvMEv +oKFvKMZEUs4IM4MZeY9q3g== +`pragma protect data_method = "aes256-cbc" +`pragma protect encoding = ( enctype = "base64" , line_length = 64 , bytes = 81776 ) +`pragma protect data_block +z1UmCVj+11HZ7zlYo7iy18wd2AOfYne44/6ibkZX0OpmFrVq3bktCzQeZRUzswBC +ssCXyhvFauDWI/0OE+6daQD382Ai8tpsfiBspyhm+S/hxToiuieswOtJrCjjRsda +/sWPZQnnSMxdzGhGpRyOhnp2ekWubm9nVIYjGu7wNauKwLj3dcphUqY0r3wNr0hi +w4wMhDDVsh6KfWBiyUQviANxNpVMTHd8fYUL9PfMMpM7JHgfr74xYU/59caF6Ung +CFgscfR6Z11/SbRAwVOu1ABzpjw4WU/SR3idkVgxVYtql2TLEf+7RshFulpba7+u +AP+35GDmFR4RdNoSDx1hUcejBMNy5dAdx9xc2uGwi42q6rhigpOJiQJibtfe8QTr +fx6t8i/xY78FfcFpS5SNECnr02mNDcpSsnMpzEt45y8I1K7vp32D3nL9g+sFcLa2 +gj8avZp4OK37hk/V7VhrwOgjBfzuxeUqec/UPZ2rRtqvIhSxAYYfm9rbHWl5a7Nm +hfw8Mg5j3jAIgxc4xRJhzcr7cB8BehG57Y1HZT2rjoxTQw8i4nPK8t85URaSB8kS +3lXSaAnK3YSUCwaR80EdgKRulXIUW0AO8YV8OEHDFiPeg0j3vrZvqjlHgoE1kaik +wZRCLNfeZBSocPsIoyz9hdEbj7TgruDDg/wSVvOnl+OOmjBzx1Yce+rSB6dEgchz +PwB6rkMjfszkwmOx31vcEnl8Tp2N6CggP66Am3IgDUYmL+vUaRCETkAg/sqSrqG9 +ZR5G/W9LwQHZYc2I8ZC8lN8TDhmIC1KLyQRUBY68iSpxGgALX+OYGxV85wQe9bRu +W/jo1Vt08Qa5uikGkR7/6j0jShDRhl/LNaHAcS9ofH+XjsrRvEsyKAnsQRyNxQHK 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+1bMJsXMK2ZzNKSB2v/jTVAyrhgBEmPKJAzaQHx1Gyi1hl8hwU+XUBVS1L+DfwzCc +XX9ZRl8rgp5KzwmSNA1V+Bjl9svoEK0RZoM2sZovDoXWOtZWrq3f36E40JUzhkc+ +Y/9L851fPDqjHFTLNb5BnrHxzp9zujxd42kmu4iLszIcVfacqsO6NmW3SChGAWcg +dDbfSwi0obvQOjiMq9Jr3Gtf/+KNzNZm4JVBEeW0KZsvYMkTbr/qFuAEPo3u15PP +RXkD0FBW5WscXwm65H0zxme3MW3tzVdIJpYssfBJNVqpyJpKciPPyBwQrDrP8O8n +hlOXdepnSo6JVN4ZzflYK5UIX4zD5X+dVDva6NWJisvn2CEgPYJFe79Phi1tNopE +E4SLlSOmCIJ2J1vkO3oBkswAJwALPalgpZJkS/aWjsG6g9kvSeTLB70YCfkdoYEi +aICjJt8eKaGl15PG7YiVlnRGLB1tn2GJCLOoHwVmDlMXqWDUGQLK5wkqmKkfPhOY +WRtJp0QGKXO6r4tp8fVlNkoIgX7KA+rWAgGXkrQn+IDYAnvKnaed6rJfEnLXgGCD +01C9d74CY7mAd3Kg3YY858coKwiDhDwiT1IUCz0ceuY= +`pragma protect end_protected + +//pragma protect end + +`undef IP_MODULE_NAME diff --git a/Ti375C529_devkit/source/design_modules.v b/Ti375C529_devkit/source/design_modules.v new file mode 100644 index 0000000..d99ad61 --- /dev/null +++ b/Ti375C529_devkit/source/design_modules.v @@ -0,0 +1,1494 @@ +//////////////////////////////////////////////////////////////////////////// +// _____ +// / _______ Copyright (C) 2013-2022 Efinix Inc. All rights reserved. +// / / \ +// / / .. / design_modules.v +// / / .' / +// __/ /.' / Description: +// __ \ / Modules for SapphireSoC example design +// /_/ /\ \_____/ / +// ____/ \_______/ +// +// *********************************************************************** +// Revisions: +// 1.0 Initial rev +// 1.1 Added Custom ALU +// 1.2 Fixed AXI4 slave read first issue +// 1.3 Added axi full-duplex to half-duplex converter +// *********************************************************************** +`timescale 1ns/1ps + +module apb3_slave #( + // user parameter starts here + // + parameter ADDR_WIDTH = 16, + parameter DATA_WIDTH = 32, + parameter NUM_REG = 4 +) ( + // user logic starts here + input clk, + input resetn, + input [ADDR_WIDTH-1:0] PADDR, + input PSEL, + input PENABLE, + output PREADY, + input PWRITE, + input [DATA_WIDTH-1:0] PWDATA, + output [DATA_WIDTH-1:0] PRDATA, + output PSLVERROR + +); + + +/////////////////////////////////////////////////////////////////////////////// + +localparam [1:0] IDLE = 2'b00, + SETUP = 2'b01, + ACCESS = 2'b10; + +integer byteIndex; +reg [DATA_WIDTH-1:0] slaveReg [0:NUM_REG-1]; +reg [DATA_WIDTH-1:0] slaveRegOut; +reg [1:0] busState, + busNext; +reg slaveReady; +wire actWrite, + actRead; +reg [31:0] lfsr; +wire lfsr_stop; + + +/////////////////////////////////////////////////////////////////////////////// + + always@(posedge clk or negedge resetn) + begin + if(!resetn) + busState <= IDLE; + else + busState <= busNext; + end + + always@(*) + begin + busNext = busState; + + case(busState) + IDLE: + begin + if(PSEL && !PENABLE) + busNext = SETUP; + else + busNext = IDLE; + end + SETUP: + begin + if(PSEL && PENABLE) + busNext = ACCESS; + else + busNext = IDLE; + end + ACCESS: + begin + if(PREADY) + busNext = IDLE; + else + busNext = ACCESS; + end + default: + begin + busNext = IDLE; + end + endcase + end + + + assign actWrite = PWRITE & (busState == ACCESS); + assign actRead = !PWRITE & (busState == ACCESS); + assign PSLVERROR = 1'b0; + assign PRDATA = slaveRegOut; + assign PREADY = slaveReady & & (busState !== IDLE); + + always@ (posedge clk) + begin + slaveReady <= actWrite | actRead; + end + + always@ (posedge clk or negedge resetn) + begin + if(!resetn) + for(byteIndex = 0; byteIndex < NUM_REG; byteIndex = byteIndex + 1) + slaveReg[byteIndex] <= {DATA_WIDTH{1'b0}}; + else + begin + if(actWrite) + begin + for(byteIndex = 0; byteIndex < NUM_REG; byteIndex = byteIndex + 1) + if (PADDR[3:0] == (byteIndex*4)) + slaveReg[byteIndex] <= PWDATA; + end + else + begin + slaveReg[0] <= lfsr; + for(byteIndex = 1; byteIndex < NUM_REG; byteIndex = byteIndex + 1) + slaveReg[byteIndex] <= slaveReg[byteIndex]; + end + end + end + + always@ (posedge clk or negedge resetn) + begin + if(!resetn) + slaveRegOut <= {DATA_WIDTH{1'b0}}; + else begin + if(actRead) + slaveRegOut <= slaveReg[PADDR[7:2]]; + else + slaveRegOut <= slaveRegOut; + + end + + end + + assign lfsr_stop = slaveReg[1][0]; +//custom logics + + always@(posedge clk or negedge resetn) + begin + if (!resetn) + lfsr <= 'd1; + else + begin + if(!lfsr_stop) + begin + lfsr[31] <= lfsr[0]; + lfsr[30] <= lfsr[31]; + lfsr[29] <= lfsr[30]; + lfsr[28] <= lfsr[29]; + lfsr[27] <= lfsr[28]; + lfsr[26] <= lfsr[27]; + lfsr[25] <= lfsr[26]; + lfsr[24] <= lfsr[25]; + lfsr[23] <= lfsr[24]; + lfsr[22] <= lfsr[23]; + lfsr[21] <= lfsr[22]; + lfsr[20] <= lfsr[21]; + lfsr[19] <= lfsr[20]; + lfsr[18] <= lfsr[19]; + lfsr[17] <= lfsr[18]; + lfsr[16] <= lfsr[17]; + lfsr[15] <= lfsr[16]; + lfsr[14] <= lfsr[15]; + lfsr[13] <= lfsr[14]; + lfsr[12] <= lfsr[13]; + lfsr[11] <= lfsr[12]; + lfsr[10] <= lfsr[11]; + lfsr[9 ] <= lfsr[10]; + lfsr[8 ] <= lfsr[9 ]; + lfsr[7 ] <= lfsr[8 ]; + lfsr[6 ] <= lfsr[7 ]; + lfsr[5 ] <= lfsr[6 ]; + lfsr[4 ] <= lfsr[5 ]; + lfsr[3 ] <= lfsr[4 ] ^ lfsr[0]; + lfsr[2 ] <= lfsr[3 ]; + lfsr[1 ] <= lfsr[2 ]; + lfsr[0 ] <= lfsr[1 ] ^ lfsr[0]; + end + else + begin + lfsr <= lfsr; + end + end + end + +endmodule + +// *********************************************************************** + +module axi4_slave #( + parameter ADDR_WIDTH = 32, + parameter DATA_WIDTH = 32 +) ( + //custom logic starts here + output axi_interrupt, + // + input axi_aclk, + input axi_resetn, + //AW + input [7:0] axi_awid, + input [ADDR_WIDTH-1:0] axi_awaddr, + input [7:0] axi_awlen, + input [2:0] axi_awsize, + input [1:0] axi_awburst, + input axi_awlock, + input [3:0] axi_awcache, + input [2:0] axi_awprot, + input [3:0] axi_awqos, + input [3:0] axi_awregion, + input axi_awvalid, + output axi_awready, + //W + input [DATA_WIDTH-1:0] axi_wdata, + input [(DATA_WIDTH/8)-1:0] + axi_wstrb, + input axi_wlast, + input axi_wvalid, + output axi_wready, + //B + output [7:0] axi_bid, + output [1:0] axi_bresp, + output axi_bvalid, + input axi_bready, + //AR + input [7:0] axi_arid, + input [ADDR_WIDTH-1:0] axi_araddr, + input [7:0] axi_arlen, + input [2:0] axi_arsize, + input [1:0] axi_arburst, + input axi_arlock, + input [3:0] axi_arcache, + input [2:0] axi_arprot, + input [3:0] axi_arqos, + input [3:0] axi_arregion, + input axi_arvalid, + output axi_arready, + //R + output [7:0] axi_rid, + output [DATA_WIDTH-1:0] axi_rdata, + output [1:0] axi_rresp, + output axi_rlast, + output axi_rvalid, + input axi_rready +); + +/////////////////////////////////////////////////////////////////////////////// +localparam RAM_SIZE = 2048; +localparam RAMW = $clog2(RAM_SIZE); + +localparam [2:0] IDLE = 3'h0, + PRE_WR = 3'h1, + WR = 3'h2, + WR_RESP = 3'h3, + PRE_RD = 3'h4, + RD = 3'h5; + +reg [2:0] busState, + busNext; +wire busReady, + busPreWrite, + busWrite, + busWriteResp, + busPreRead, + busRead; +wire awWrap, + arWrap; +reg [7:0] awidReg; +reg [ADDR_WIDTH-1:0] awaddrReg; +reg [7:0] awlenReg; +reg [2:0] awsizeReg; +reg [1:0] awburstReg, + awlockReg; +reg [3:0] awcacheReg; +reg [2:0] awprotReg; +reg [3:0] awqosReg; +reg [3:0] awregionReg; + +reg [7:0] aridReg; +reg [ADDR_WIDTH-1:0] araddrReg; +reg [7:0] arlenReg; +reg [2:0] arsizeReg; +reg [1:0] arburstReg, + arlockReg; +reg [3:0] arcacheReg; +reg [2:0] arprotReg; +reg [3:0] arqosReg; +reg [3:0] arregionReg; + +reg [31:0] awaddr_base; +wire [31:0] awWrapSize; +reg [7:0] decodeAwsize; + +wire [31:0] araddr_wrap; +reg [7:0] decodeArsize; + +reg [31:0] araddr_base; +wire [31:0] arWrapSize; +reg [7:0] ridReg; +reg [1:0] rrespReg; +reg [1:0] rlastReg; + +wire pWr_done; +wire pRd_done; +wire awaddr_ext; +wire araddr_ext; +wire [(DATA_WIDTH/8)-1:0] + rlast; +wire [(DATA_WIDTH/8)-1:0] + rvalid; +//custom logic +wire [9:0] wdata [0:3]; +wire wEnable[0:3]; +wire [9:0] rdata [0:3]; +wire [31:0] data_o; +wire rEnable; +reg r_axi_interrupt; + +/////////////////////////////////////////////////////////////////////////////// + + + always@ (posedge axi_aclk or negedge axi_resetn) + begin + if(!axi_resetn) + busState <= IDLE; + else + busState <= busNext; + + end + + always@ (*) + begin + busNext = busState; + + case(busState) + IDLE: + begin + if(axi_awvalid) + busNext = PRE_WR; + else if(axi_arvalid) + busNext = PRE_RD; + else + busNext = IDLE; + end + PRE_WR: + begin + if(pWr_done) + busNext = WR; + else + busNext = PRE_WR; + end + WR: + begin + if(axi_wlast) + busNext = WR_RESP; + else + busNext = WR; + end + WR_RESP: + begin + if(axi_bready) + busNext = IDLE; + else + busNext = WR_RESP; + end + PRE_RD: + begin + if(pRd_done) + busNext = RD; + else + busNext = PRE_RD; + end + RD: + begin + if(axi_rlast && axi_rready) + busNext = IDLE; + else + busNext = RD; + end + default: + busNext = IDLE; + endcase + end + + assign busReady = (busState == IDLE); + assign busPreWrite = (busState == PRE_WR); + assign busWrite = (busState == WR); + assign busWriteResp = (busState == WR_RESP); + assign busPreRead = (busState == PRE_RD); + assign busRead = (busState == RD); + + //PRE_WRITE + assign pWr_done = (awburstReg == 2'b10)? awaddr_ext : 1'b1; + //AW Control + + assign axi_awready = busReady; + + //Wrap Control + always@ (posedge axi_aclk or negedge axi_resetn) + begin + if (!axi_resetn) + awaddr_base <= 'h0; + else begin + if(busReady) + awaddr_base <= 'h0; + else if(busPreWrite && !awaddr_ext) + awaddr_base <= awaddr_base + awWrapSize; + else + awaddr_base <= awaddr_base; + end + end + + assign awaddr_ext = busPreWrite ? (awaddr_base[RAMW:0] > awaddrReg[RAMW:0]) : 1'b0; + assign awWrap = busWrite && (axi_awburst == 2'b10) ? (awaddrReg[RAMW:0] == awaddr_base - 4) : 1'b0; + assign awWrapSize = (DATA_WIDTH/8) * awlenReg; + + //AW Info + always@ (posedge axi_aclk) + begin + if(axi_awvalid) begin + awidReg <= axi_awid; + awlenReg <= axi_awlen + 1'b1; + awsizeReg <= axi_awsize; + awburstReg <= axi_awburst; + awlockReg <= axi_awlock; + awcacheReg <= axi_awcache; + awprotReg <= axi_awprot; + awqosReg <= axi_awqos; + awregionReg <= axi_awregion; + end + else begin + awidReg <= awidReg; + awlenReg <= awlenReg; + awsizeReg <= awsizeReg; + awburstReg <= awburstReg; + awlockReg <= awlockReg; + awcacheReg <= awcacheReg; + awprotReg <= awprotReg; + awqosReg <= awqosReg; + awregionReg <= awregionReg; + end + end + + always@ (awsizeReg) + begin + case(awsizeReg) + 3'h0:decodeAwsize <= 8'd1; + 3'h1:decodeAwsize <= 8'd2; + 3'h2:decodeAwsize <= 8'd4; + 3'h3:decodeAwsize <= 8'd8; + 3'h4:decodeAwsize <= 8'd16; + 3'h5:decodeAwsize <= 8'd32; + 3'h6:decodeAwsize <= 8'd64; + 3'h7:decodeAwsize <= 8'd128; + default:decodeAwsize <= 8'd1; + endcase + end + + always@ (posedge axi_aclk) + begin + if(axi_awvalid) + awaddrReg <= axi_awaddr; + else if (busWrite) begin + case(awburstReg) + 2'b00://fixed burst + awaddrReg <= awaddrReg; + 2'b01://incremental burst + awaddrReg <= awaddrReg + decodeAwsize; + 2'b10://wrap burst + begin + if(awWrap) + awaddrReg <= awaddrReg - awWrapSize; + else + awaddrReg <= awaddrReg + decodeAwsize; + end + default: + awaddrReg <= awaddrReg; + endcase + end + end + //W operation + assign axi_wready = busWrite; + + //B Response + assign axi_bid = awidReg; + assign axi_bresp = 2'b00; + assign axi_bvalid = busWriteResp; + + //PRE_READ + assign pRd_done = (arburstReg == 2'b10)? araddr_ext : 1'b1; + + //AR Control + assign axi_arready = busReady; + + //Wrap Control + always@ (posedge axi_aclk or negedge axi_resetn) + begin + if (!axi_resetn) + araddr_base <= 'h0; + else begin + if(busReady) + araddr_base <= 'h0; + else if(busPreRead && !araddr_ext) + araddr_base <= araddr_base + arWrapSize; + else + araddr_base <= araddr_base; + end + end + + assign araddr_ext = busPreRead ? (araddr_base[RAMW:0] > araddrReg[RAMW:0]) : 1'b0; + assign arWrap = (busRead && axi_arburst == 2'b10) ? (araddrReg[RAMW:0] == araddr_base - 4) : 1'b0; + assign arWrapSize = (DATA_WIDTH/8) * arlenReg; + + //AR Info + always@ (posedge axi_aclk) + begin + if(axi_arvalid) begin + aridReg <= axi_arid; + arlenReg <= axi_arlen + 1'b1; + arsizeReg <= axi_arsize; + arburstReg <= axi_arburst; + arlockReg <= axi_arlock; + arcacheReg <= axi_arcache; + arprotReg <= axi_arprot; + arqosReg <= axi_arqos; + arregionReg <= axi_arregion; + end + else begin + aridReg <= aridReg; + arlenReg <= arlenReg; + arsizeReg <= arsizeReg; + arburstReg <= arburstReg; + arlockReg <= arlockReg; + arcacheReg <= arcacheReg; + arprotReg <= arprotReg; + arqosReg <= arqosReg; + arregionReg <= arregionReg; + end + end + + always@ (arsizeReg) + begin + case(arsizeReg) + 3'h0:decodeArsize <= 8'd1; + 3'h1:decodeArsize <= 8'd2; + 3'h2:decodeArsize <= 8'd4; + 3'h3:decodeArsize <= 8'd8; + 3'h4:decodeArsize <= 8'd16; + 3'h5:decodeArsize <= 8'd32; + 3'h6:decodeArsize <= 8'd64; + 3'h7:decodeArsize <= 8'd128; + default:decodeArsize <= 8'd1; + endcase + end + + always@ (posedge axi_aclk) + begin + if(axi_arvalid) + araddrReg <= axi_araddr; + else if (rEnable && axi_rready) begin + case(arburstReg) + 2'b00://fixed burst + araddrReg <= araddrReg; + 2'b01://incremental burst + araddrReg <= araddrReg + decodeArsize; + 2'b10://wrap burst + begin + if(arWrap) + araddrReg <= araddrReg - arWrapSize; + else + araddrReg <= araddrReg + decodeArsize; + end + default: + araddrReg <= araddrReg; + endcase + end + end + + // R Operation + assign axi_rdata = data_o; + + // R Response + assign axi_rvalid = busRead? |rvalid : 1'b0 ; + assign axi_rlast = busRead? |rlast : 1'b0 ; + + assign axi_rresp = 2'b00; + assign axi_rid = aridReg; + + //custom logic starts here + assign axi_interrupt = r_axi_interrupt; + assign rEnable = (axi_arburst == 2'b10)? busRead : busPreRead; + + always@ (posedge axi_aclk) + begin + if (!axi_resetn) + begin + r_axi_interrupt <= 1'b0; + end + else + begin + if((axi_wvalid) && (axi_wdata == 16'hABCD)) + r_axi_interrupt <= 1'b1; + else + r_axi_interrupt <= 1'b0; + end + end + + genvar i; + generate + for(i=0;i < (DATA_WIDTH/8); i = i + 1) begin + + assign rvalid[i] = (arlenReg != 'h1)? rdata[i][8] : 1'b1; + assign rlast[i] = (arlenReg != 'h1)? rdata[i][9] : 1'b1; + assign wdata[i] = {axi_wlast, axi_wvalid, axi_wdata[(i*8+7) -: 8]} ; + assign data_o[(i*8+7) -: 8] = rdata[i]; + assign wEnable[i] = axi_wready & axi_wvalid & axi_wstrb[i]; + + ext_mem #( + .DATA_WIDTH (10), + .ADDR_WIDTH (RAMW-2), + .OUTPUT_REG ("TRUE") + + ) user_ram ( + .wdata (wdata[i]), + .waddr (awaddrReg[RAMW-1:2]), + .raddr (araddrReg[RAMW-1:2]), + .we (wEnable[i]), + .wclk (axi_aclk), + .re (rEnable), + .rclk (axi_aclk), + .rdata (rdata[i]) + ); + end + endgenerate + +endmodule + +// *********************************************************************** + +module memory_checker #( + parameter WIDTH = 32, + parameter ALEN = 23, + parameter START_ADDR = 32'h00000000, + parameter STOP_ADDR = 32'h00100000, + parameter ADDR_OFFSET = (ALEN + 1)*(WIDTH/8) +) ( +input axi_clk, +input rstn, +input start, +output [7:0] aid, +output reg [31:0] aaddr, +output reg [7:0] alen, +output reg [2:0] asize, +output reg [1:0] aburst, +output reg [1:0] alock, +output reg avalid, +input aready, +output reg atype, + +output [7:0] wid, +output reg [WIDTH-1:0] wdata, +output [WIDTH/8-1:0] wstrb, +output reg wlast, +output reg wvalid, +input wready, + +input [3:0] rid, +input [WIDTH-1:0] rdata, +input rlast, +input rvalid, +output reg rready, +input [1:0] rresp, + +input [7:0] bid, +input bvalid, +output reg bready, +output pass + +); + +/////////////////////////////////////////////////////////////////////////////// +localparam ASIZE = (WIDTH == 512)? 6 : + (WIDTH == 256)? 5 : + (WIDTH == 128)? 4 : + (WIDTH == 64)? 3 : 2; + +//Main states +localparam COMPARE_WIDTH = WIDTH; +localparam IDLE = 4'b0000, + WRITE_ADDR = 4'b0001, + PRE_WRITE = 4'b0010, + WRITE = 4'b0011, + POST_WRITE = 4'b0100, + READ_ADDR = 4'b0101, + PRE_READ = 4'b0110, + READ_COMPARE = 4'b0111, + POST_READ = 4'b1000, + DONE = 4'b1001; + +//reg [3:0] states, nstates; +reg fail; +reg done; +reg [3:0] states; +reg [3:0] nstates; +reg bvalid_done; +reg [1:0] start_sync; +reg [8:0] write_cnt, read_cnt; +reg [WIDTH-1:0] rdata_store; +reg wburst_done, + rburst_done, + write_done, + read_done; + +/////////////////////////////////////////////////////////////////////////////// + assign aid = 8'h00; + assign wstrb = {WIDTH/8{1'b1}}; + assign wid = 8'h00; + assign pass = done & ~fail; + + always @(posedge axi_clk or negedge rstn) + begin + if (!rstn) begin + start_sync <= 2'b00; + end else begin + start_sync[0] <= start; + start_sync[1] <= start_sync[0]; + end + end + + always @(posedge axi_clk or negedge rstn) + begin + if (!rstn) begin + states <= IDLE; + end else begin + states <= nstates; + end + end + + always @(states or start_sync[1] or write_cnt or rburst_done or write_done or read_done or bvalid_done or aready) + begin + case(states) + IDLE : + if (start_sync[1]) + nstates = WRITE_ADDR; + else + nstates = IDLE; + WRITE_ADDR : + if (aready) + nstates = PRE_WRITE; + else + nstates = WRITE_ADDR; + PRE_WRITE : + nstates = WRITE; + WRITE : + if (write_cnt == 9'd0) + nstates = POST_WRITE; + else + nstates = WRITE; + POST_WRITE : + if (write_done & bvalid_done) + nstates = READ_ADDR; + else if (bvalid_done) + nstates = WRITE_ADDR; + else + nstates = POST_WRITE; + READ_ADDR : + if (aready) + nstates = PRE_READ; + else + nstates = READ_ADDR; + PRE_READ : + nstates = READ_COMPARE; + READ_COMPARE : + if (rburst_done) + nstates = POST_READ; + else + nstates = READ_COMPARE; + POST_READ : + if (read_done) + nstates = DONE; + else + nstates = READ_ADDR; + DONE : + nstates = DONE; + default : + nstates = IDLE; + endcase + end + + always @(posedge axi_clk or negedge rstn) + begin + if (!rstn) begin + aaddr <= START_ADDR; + avalid <= 1'b0; + atype <= 1'b0; + aburst <= 2'b00; + asize <= 3'b000; + alen <= 8'd0; + alock <= 2'b00; + wvalid <= 1'b0; + write_cnt <= ALEN + 1; + write_done <= 1'b0; + wdata <= {WIDTH{1'b0}}; + wburst_done <= 1'b0; + wlast <= 1'b0; + bready <= 1'b0; + fail <= 1'b0; + done <= 1'b0; + rready <= 1'b0; + bvalid_done <=1'b0; + end + else + begin + if (states == IDLE) + begin + aaddr <= START_ADDR; + avalid <= 1'b0; + atype <= 1'b0; + aburst <= 2'b00; + asize <= 3'b000; + alen <= 8'd0; + alock <= 2'b00; + wvalid <= 1'b0; + write_cnt <= ALEN + 1; + wdata <= {WIDTH{1'b0}}; + wburst_done <= 1'b0; + wlast <= 1'b0; + bready <= 1'b0; + rready <= 1'b0; + bvalid_done <= 1'b0; + fail <= 1'b0; + done <= 1'b0; + end + if (states == WRITE_ADDR) + begin + avalid <= 1'b1; + atype <= 1'b1; + asize <= ASIZE; + alen <= ALEN; + aburst <= 2'b01; + alock <= 2'b00; + wvalid <= 1'b0; + write_cnt <= ALEN + 1; + wburst_done <= 1'b0; + bvalid_done <= 1'b0; + bready <= 1'b0; + rready <= 1'b0; + done <= 1'b0; + fail <= 1'b0; + end + if (states == PRE_WRITE) + begin + avalid <= 1'b0; + atype <= 1'b0; + wvalid <= 1'b1; + wdata <= {{WIDTH/32{~aaddr[7:0]}},{WIDTH/32{~write_cnt[7:0]}},{WIDTH/32{aaddr[7:0]}},{WIDTH/32{write_cnt[7:0]}}}; + bready <= 1'b1; + write_cnt <= write_cnt - 1; + if(alen == 'd0) + begin + wlast <= 1'b1; + end + end + if (states == WRITE) + begin + if (wready == 1'b1) + begin + wdata <= {{WIDTH/32{~aaddr[7:0]}},{WIDTH/32{~write_cnt[7:0]}},{WIDTH/32{aaddr[7:0]}},{WIDTH/32{write_cnt[7:0]}}}; + if (write_cnt == 9'd0) + begin + wburst_done <= 1'b1; + wlast <= 1'b0; + wvalid <= 1'b0; + if (aaddr >= STOP_ADDR) + begin + write_done <= 1'b1; + end else + begin + write_done <= 1'b0; + end + end if (write_cnt == 9'd1) + begin + wlast <= 1'b1; + write_cnt <= write_cnt - 1; + end + else + begin + write_cnt <= write_cnt - 1; + end + end + end + if (states == POST_WRITE) + begin + if (write_done) + begin + aaddr <= START_ADDR; + end + else + begin + if (bvalid) begin + aaddr <= aaddr + ADDR_OFFSET; + end + end + if (wready == 1'b1) + begin + wlast <= 1'b0; + wvalid <= 1'b0; + end + if (bvalid) + begin + bvalid_done <= 1'b1; + bready <= 1'b0; + end + end + if (states == READ_ADDR) + begin + avalid <= 1'b1; + read_cnt <= ALEN + 1; + + end + if (states == PRE_READ) + begin + avalid <= 1'b0; + rburst_done <= 1'b0; + rdata_store <= {{WIDTH/32{~aaddr[7:0]}},{WIDTH/32{~read_cnt[7:0]}},{WIDTH/32{aaddr[7:0]}},{WIDTH/32{read_cnt[7:0]}}}; + read_cnt <= read_cnt - 1'b1; + end + if (states == READ_COMPARE) + begin + rready <= 1'b1; + if (read_cnt != 9'd0) + begin + if (rvalid == 1'b1) + begin + rdata_store <= {{WIDTH/32{~aaddr[7:0]}},{WIDTH/32{~read_cnt[7:0]}},{WIDTH/32{aaddr[7:0]}},{WIDTH/32{read_cnt[7:0]}}}; + read_cnt <= read_cnt - 1'b1; + if (rdata[COMPARE_WIDTH-1:0] != rdata_store[COMPARE_WIDTH-1:0]) + fail <= 1'b1; + else + fail <= 1'b0; + end + + end + end + if (read_cnt == 9'd0) + begin + if (rvalid == 1'b1) + begin + if (rdata[COMPARE_WIDTH-1:0] != rdata_store[COMPARE_WIDTH-1:0]) + begin + fail <= 1'b1; + end + else + begin + fail <= 1'b0; + end + if (aaddr >= STOP_ADDR) + begin + read_done <= 1'b1; + end + else + begin + read_done <= 1'b0; + end + rburst_done <= 1'b1; + end + end + if (states == POST_READ) + begin + aaddr <= aaddr + ADDR_OFFSET; + rready <= 1'b1; + end + if (states == DONE) + begin + done <= 1'b1; + end + end + end +endmodule + +// *********************************************************************** +module timer_start #( + parameter MHZ = 50, + parameter SECOND = 3, + parameter PULSE = 0 +) ( + input clk, + input rst_n, + output start +); + +reg [35:0] delay_cnt; +wire second_tick; +reg [4:0] second_cnt; +reg [3:0] pulse_reg; +wire start_reg; + +/////////////////////////////////////////////////////////////////////////////// + +`ifndef EFX_SIM +localparam tick_cnt = (MHZ * 1000000) >> 1; +`else +localparam tick_cnt = MHZ * 200; +`endif + + always@(posedge clk or negedge rst_n) + begin + if(!rst_n) + delay_cnt <= 'd0; + else + begin + if(delay_cnt == tick_cnt || start_reg == 1'b1) + delay_cnt <= 'd0; + else + delay_cnt <= delay_cnt + 1'b1; + end + end + + assign second_tick = ((delay_cnt) == (tick_cnt - 1)); + + always@(posedge clk or negedge rst_n) + begin + if(!rst_n) + second_cnt <= 'd0; + else + begin + if(second_tick) + second_cnt <= second_cnt + 1'b1; + else + second_cnt <= second_cnt; + end + end + + assign start_reg = (second_cnt == SECOND); + + always@(posedge clk) + begin + pulse_reg <= {pulse_reg[2:0],start_reg}; + end + +generate +if(PULSE == 1) + assign start = ~pulse_reg[3] & start_reg; +else + assign start = start_reg; +endgenerate + +endmodule + +// *********************************************************************** +module ext_mem #( + parameter DATA_WIDTH = 8, + parameter ADDR_WIDTH = 9, + parameter OUTPUT_REG = "TRUE", + parameter RAM_INIT_FILE = "" +) ( + input [DATA_WIDTH-1:0] wdata, + input [ADDR_WIDTH-1:0] waddr, + input [ADDR_WIDTH-1:0] raddr, + input we, + input wclk, + input re, + input rclk, + output [DATA_WIDTH-1:0] rdata +); + +///////////////////////////////////////////////////////////////////////////// + + localparam MEMORY_DEPTH = 2**ADDR_WIDTH; + localparam MAX_DATA = (1< 7.5 cycles in (split over 2 cycles) -// for 128 bit data, this is at 30/16 -> 1.875 cycles (also split over 2 cycles) - -localparam WAIT_CYCLES = DATA_W == 32 ? 10 : 3; - -// Dest IP scanner - -enum logic {SCAN, DRAIN} state, state_next; -logic [4:0] counter, counter_next; - -logic [31:0] temp_dest_ip, temp_dest_ip_next; - -logic [31:0] dest_ip, dest_ip_next; - -assign int_axis_data.tready = '1; - -always_ff @(posedge clk) begin - if (rst) begin - counter <= '0; - state <= SCAN; - temp_dest_ip <= '0; - dest_ip <= '0; - end else begin - counter <= counter_next; - state <= state_next; - temp_dest_ip <= temp_dest_ip_next; - dest_ip <= dest_ip_next; - end -end - -always_comb begin - counter_next = counter; - state_next = state; - temp_dest_ip_next = temp_dest_ip; - dest_ip_next = dest_ip; - - if (s_axis_data.tvalid && s_axis_data.tready) begin - if (state == SCAN) begin - counter_next = counter + 1; - if (DATA_W == 32) begin - if (counter == 7) begin - temp_dest_ip_next[31:16] = {s_axis_data.tdata[23:16], s_axis_data.tdata[31:24]}; - end else if (counter == 8) begin - dest_ip_next = {temp_dest_ip[31:16], s_axis_data.tdata[7:0], s_axis_data.tdata[15:8]}; - state_next = DRAIN; - counter_next = '0; - end - end else if (DATA_W == 128) begin - - end - - end else if (state == DRAIN) begin - if (s_axis_data.tlast) begin - state_next = SCAN; - end - end - end -end - - -// Shift register - -assign s_axis_data.tready = int_axis_data.tready; - -logic [1+1+s_axis_data.KEEP_W+s_axis_data.DATA_W-1:0] data_sr [WAIT_CYCLES]; - -always_ff @(posedge clk) begin - if (s_axis_data.tready) begin - for (int idx = 0; idx < WAIT_CYCLES-1; idx++) begin - data_sr[idx+1] <= data_sr[idx]; - end - data_sr[0] <= {s_axis_data.tvalid, s_axis_data.tlast, s_axis_data.tkeep, s_axis_data.tdata}; - end -end - -assign {int_axis_data.tvalid, int_axis_data.tlast, int_axis_data.tkeep, int_axis_data.tdata} = data_sr[WAIT_CYCLES-1]; - - -// Demux - -logic dest_ip_matches; - -taxi_axis_if #(.DATA_W(DATA_W)) int_axis_demux[2](); - -taxi_axis_tie u_data_tie ( - .s_axis(int_axis_demux[1]), - .m_axis(m_axis_data) -); - -taxi_axis_tie u_dma_tie ( - .s_axis(int_axis_demux[0]), - .m_axis(m_axis_dma) -); - -always_ff @(posedge clk) begin - dest_ip_matches <= dest_ip == i_dest_ip; -end - -taxi_axis_demux #( - .M_COUNT(2) -) u_demux ( - .clk (clk), - .rst (rst), - - .s_axis (int_axis_data), - - .m_axis (int_axis_demux), - - .enable ('1), - .drop ('0), // we could drop here if a bit is set. - .select (dest_ip_matches) -); - -endmodule \ No newline at end of file diff --git a/src/sub/upstream_path/src/upstream_path.sv b/src/sub/upstream_path/src/upstream_path.sv deleted file mode 100644 index 82dc141..0000000 --- a/src/sub/upstream_path/src/upstream_path.sv +++ /dev/null @@ -1,17 +0,0 @@ -module upstream_path ( - input clk, - input rst, - - taxi_axis_if.snk s_axis_data, - taxi_axis_if.src m_axis_data, - - taxi_axi_if.rd_mst m_axi_rd, - taxi_axi_if.wr_mst m_axi_wr, - - taxi_apb_if.slv s_apb_cfg, - - output logic o_irq_m2s, - output logic o_irq_s2m -); - -endmodule \ No newline at end of file