Zip CPU ISA -CheatSheet

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04'DR5'OpCode3'Cond018'Immediate
1B-Reg14'Immediate
4'DRMOV 3'CondAB-RegB13'Immediate
4'DRLDI23'Immediate
14'DR 3'OpCodeA 7'Op-B  4'DR3'OpCode07'Imm
4'DR3'OpCode1B-Reg3'Imm

Normal instructionsCompressed
00000SUB 10000CMP000SUB
00001AND 10001TEST001AND
00010ADD 10010LW010ADD
00011OR 10011SW011CMP
00100XOR10100LH100LW
00101LSR10101SH101SW
00110LSL10110LB110LDI
00111ASR10111SB111MOV
01000BREV11000LDIReserved for FPU
01001LDILO11001
01010MPYUHISpecial Insn11010FPADD
01011MPYSHI11011FPSUB
01100MPY11100BREAK11100FPMPY
01101MOV11101LOCK11101FPDIV
01110DIVU11110SIM11110FPI2F
01111DIVS11111NOOP11111FPF2I

ASSEMBLER SUPPORTED DERIVED INSTRUCTIONS

SourceDerived Instructions
ADDBRA, BLT, BZ, BC, BV, BGE, BNZ, BNC, BUSY
ORRTU, WAIT, HALT, STEP
ANDTRAP
XORNOT
MOV(Indirect) JMP, RETN
LWLJMP
BREVCLR
MultipleJSR, LJSR, NEG, SEXTH, SEXTB

COMPRESSED INSTRUCTION SET (CIS) EXCEPTIONS

The CIS LDI instruction uses an 8'bit signed immediate, not 7-bit (-128 to 127).

MOV will use all opcode bits, and the extra bit selecting reg/imm will be extended to be an immediate bit, so that we can have any 4'bit register offset (-8 to 7)

To make this more usable, the compressed LW/SW instructions will assume the register is SP if no register is given. This will allow compressed accesses to stack offsets by between -64 to 63.

SIM Codes

SIM and NOOP instructions are both 32-bit instructions, and both take an 18-bit immediate. This immediate, together with the destination register, is ignored by the CPU--only the simulation pays attention to either. SIM and NOOP instructions are to be treated identically by the simulation (if the CPU is run within a simulation). The CPU will create an illegal instruction on any SIM opcode outside of the simulator, and ignore any NOOP instruction--no matter what the immediate value. Particular immediate values include:

  1. OUT/SOUT:
  2. NEXIT/SEXIT: with an 8-bit (signed) exit code
  3. SIMNOOP: useful for testing if the simulator is present. Will cause an ILLegal instruction if the simulator is not present, but ignored otherwise. This will be the immediate value of zero.
  4. NDUMP/SDUMP: dump the CPU state (all the registers) to the output