31 | 27 | 23 | 19 | 15 | 11 | 7 | 3 | 0 | |||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 | 4'DR | 5'OpCode | 3'Cond | 0 | 18'Immediate | ||||||||||||||||||||||||||
1 | B-Reg | 14'Immediate | |||||||||||||||||||||||||||||
4'DR | MOV | 3'Cond | A | B-Reg | B | 13'Immediate | |||||||||||||||||||||||||
4'DR | LDI | 23'Immediate | |||||||||||||||||||||||||||||
1 | 4'DR | 3'OpCode | A | 7'Op-B | 4'DR | 3'OpCode | 0 | 7'Imm | |||||||||||||||||||||||
4'DR | 3'OpCode | 1 | B-Reg | 3'Imm |
Normal instructions | Compressed | ||||
00000 | SUB | 10000 | CMP | 000 | SUB |
00001 | AND | 10001 | TEST | 001 | AND |
00010 | ADD | 10010 | LW | 010 | ADD |
00011 | OR | 10011 | SW | 011 | CMP |
00100 | XOR | 10100 | LH | 100 | LW |
00101 | LSR | 10101 | SH | 101 | SW |
00110 | LSL | 10110 | LB | 110 | LDI |
00111 | ASR | 10111 | SB | 111 | MOV |
01000 | BREV | 11000 | LDI | Reserved for FPU | |
01001 | LDILO | 11001 | |||
01010 | MPYUHI | Special Insn | 11010 | FPADD | |
01011 | MPYSHI | 11011 | FPSUB | ||
01100 | MPY | 11100 | BREAK | 11100 | FPMPY |
01101 | MOV | 11101 | LOCK | 11101 | FPDIV |
01110 | DIVU | 11110 | SIM | 11110 | FPI2F |
01111 | DIVS | 11111 | NOOP | 11111 | FPF2I |
Source | Derived Instructions |
---|---|
ADD | BRA, BLT, BZ, BC, BV, BGE, BNZ, BNC, BUSY |
OR | RTU, WAIT, HALT, STEP |
AND | TRAP |
XOR | NOT |
MOV | (Indirect) JMP, RETN |
LW | LJMP |
BREV | CLR |
Multiple | JSR, LJSR, NEG, SEXTH, SEXTB |
The CIS LDI instruction uses an 8'bit signed immediate, not 7-bit (-128 to 127).
MOV will use all opcode bits, and the extra bit selecting reg/imm will be extended to be an immediate bit, so that we can have any 4'bit register offset (-8 to 7)
To make this more usable, the compressed LW/SW instructions will assume the register is SP if no register is given. This will allow compressed accesses to stack offsets by between -64 to 63.
SIM and NOOP instructions are both 32-bit instructions, and both take an 18-bit immediate. This immediate, together with the destination register, is ignored by the CPU--only the simulation pays attention to either. SIM and NOOP instructions are to be treated identically by the simulation (if the CPU is run within a simulation). The CPU will create an illegal instruction on any SIM opcode outside of the simulator, and ignore any NOOP instruction--no matter what the immediate value. Particular immediate values include: