diff --git a/flow/syn/tcl_scripts/synth.tcl b/flow/syn/tcl_scripts/synth.tcl index 37d1f9d..ea0c8de 100644 --- a/flow/syn/tcl_scripts/synth.tcl +++ b/flow/syn/tcl_scripts/synth.tcl @@ -81,7 +81,7 @@ define_design_lib WORK -path ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/W #can be omitted# source tcl_scripts/file_to_list.tcl -analyze -format sverilog [concat [expand_file_list "$env(PROJ_ROOT)/tb/${FLIST_NAME}"]] +analyze -format sverilog [concat [expand_file_list "$env(PROJ_ROOT)/rtl/rvh_noc/tb/${FLIST_NAME}"]] #analyze HDL source code and save intermediate results named .syn in ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/work dir, which can be used by elaborate directly even without anlyzing; TODO: what does es1y_define.sv mean?# elaborate ${TOP_NAME} # write_file -hierarchy -format verilog -output output/rvh1.synth.elaborate.v diff --git a/rtl/hn_router_sam.sv b/rtl/hn_router_sam.sv new file mode 100644 index 0000000..3365935 --- /dev/null +++ b/rtl/hn_router_sam.sv @@ -0,0 +1,46 @@ +module hn_router_sam + import rvh_noc_pkg::*; +#( + parameter type flit_payload_t = logic[256-1:0] + // parameter VC_NUM_IDX_W = 1 +) +( + input logic flit_v_i, + input flit_payload_t flit_i, + input io_port_t flit_look_ahead_routing_i, + + input logic [NodeID_X_Width-1:0] node_id_x_i, + input logic [NodeID_Y_Width-1:0] node_id_y_i, + + output flit_dec_t flit_dec_o, + output flit_payload_t flit_o +); + +`ifdef USE_QOS_VALUE +assign flit_dec_o.qos_value = flit_i.qos_value; +`endif + +always_comb begin + flit_o = flit_i; + flit_o.tgt_id.x_position = flit_i.id.cid ? (flit_i.id.cid + 1) % NODE_NUM_X_DIMESION : '0; + flit_o.tgt_id.y_position = flit_i.id.cid ? (flit_i.id.cid + 1) / NODE_NUM_X_DIMESION : '0; + flit_o.tgt_id.device_port = 0; + flit_o.tgt_id.device_id = 0; + flit_o.src_id.x_position = node_id_x_i; + flit_o.src_id.y_position = node_id_y_i; + flit_o.src_id.device_port = 0; + flit_o.src_id.device_id = 0; +end + +assign flit_dec_o.tgt_id.x_position = flit_i.id.cid ? (flit_i.id.cid + 1) % NODE_NUM_X_DIMESION : '0; +assign flit_dec_o.tgt_id.y_position = flit_i.id.cid ? (flit_i.id.cid + 1) / NODE_NUM_X_DIMESION : '0; +assign flit_dec_o.tgt_id.device_port = 0; +assign flit_dec_o.tgt_id.device_id = 0; +assign flit_dec_o.src_id.x_position = node_id_x_i; +assign flit_dec_o.src_id.y_position = node_id_y_i; +assign flit_dec_o.src_id.device_port = 0; +assign flit_dec_o.src_id.device_id = 0; + +assign flit_dec_o.look_ahead_routing = flit_look_ahead_routing_i; + +endmodule \ No newline at end of file diff --git a/rtl/include/rvh_noc_pkg.sv b/rtl/include/rvh_noc_pkg.sv index dd44ad7..0979807 100755 --- a/rtl/include/rvh_noc_pkg.sv +++ b/rtl/include/rvh_noc_pkg.sv @@ -5,7 +5,7 @@ // local port configuration // ---------- `define HAVE_LOCAL_PORT -`define LOCAL_PORT_NUM_2 // local port num >= 2 +// `define LOCAL_PORT_NUM_2 // local port num >= 2 // `define LOCAL_PORT_NUM_3 // local port num >= 3 // `define LOCAL_PORT_NUM_4 // local port num >= 4 @@ -24,6 +24,13 @@ `endif `endif +// `define ENABLE_TXN_ID // for noc test, enable it + +// ---------- +// Single vc per input port +// ---------- +// `define SINGLE_VC_PER_INPUT_PORT + // ---------- // use unified dual-port ram per input port vc data buffer (default: dff) // ---------- @@ -37,14 +44,19 @@ // ---------- // whether allow local ports in same router transfer flit, at least 2 local ports // ---------- -`define ALLOW_SAME_ROUTER_L2L_TRANSFER +// `define ALLOW_SAME_ROUTER_L2L_TRANSFER + +// ---------- +// insert a pipeline register between local sa and global sa, for better timing +// ---------- +// `define INSERT_PIPELINE_REG_BETWEEN_SA // ---------- // QoS, at most one of follow macros can be defined // ---------- -// `define COMMON_QOS // No special vc, all vc head flits ranked by QoS value. -`define COMMON_QOS_EXTRA_RT_VC // Add special vc for highest priority flits, all vc head flits ranked by QoS value +`define COMMON_QOS // No special vc, all vc head flits ranked by QoS value. +// `define COMMON_QOS_EXTRA_RT_VC // Add special vc for highest priority flits, all vc head flits ranked by QoS value // not implemented: // `define RT_BYPASS_QOS_EXTRA_RT_VC // Add special vc for highest priority flits, other vc head flits have no QoS support @@ -61,7 +73,7 @@ package rvh_noc_pkg; -localparam CHANNEL_NUM = 4; // 4 channels: req, resp, data, snp +localparam CHANNEL_NUM = 5; // 5 channels: req, resp, evict, data, snp // 4*4 nodes max localparam NodeID_X_Width = 2; @@ -73,11 +85,10 @@ localparam NodeID_Width = NodeID_X_Width + NodeID_Y_Width + NodeID_Device_Port_ localparam TxnID_Width = 12; localparam QoS_Value_Width = 4; -localparam FLIT_LENGTH = 256; -localparam INPUT_PORT_NUMBER = 6; // N,S,E,W,L +localparam INPUT_PORT_NUMBER = 5; // N,S,E,W,L localparam INPUT_PORT_NUMBER_IDX_W = INPUT_PORT_NUMBER > 1 ? $clog2(INPUT_PORT_NUMBER) : 1; -localparam OUTPUT_PORT_NUMBER = 6; // N,S,E,W,L +localparam OUTPUT_PORT_NUMBER = 5; // N,S,E,W,L localparam ROUTER_PORT_NUMBER = 4; localparam LOCAL_PORT_NUMBER = INPUT_PORT_NUMBER-ROUTER_PORT_NUMBER; @@ -87,13 +98,18 @@ localparam QOS_VC_NUM_PER_INPUT = 1; localparam QOS_VC_NUM_PER_INPUT = 0; `endif +`ifdef SINGLE_VC_PER_INPUT_PORT +localparam VC_ID_NUM_MAX = 1+QOS_VC_NUM_PER_INPUT; +`else localparam VC_ID_NUM_MAX = (CHANNEL_NUM-1)+LOCAL_PORT_NUMBER+QOS_VC_NUM_PER_INPUT; +`endif + localparam VC_ID_NUM_MAX_W = VC_ID_NUM_MAX > 1 ? $clog2(VC_ID_NUM_MAX) : 1; localparam SA_GLOBAL_INPUT_NUM_MAX = (CHANNEL_NUM-1)+LOCAL_PORT_NUMBER; localparam SA_GLOBAL_INPUT_NUM_MAX_W = SA_GLOBAL_INPUT_NUM_MAX > 1 ? $clog2(SA_GLOBAL_INPUT_NUM_MAX) : 1; -localparam VC_DEPTH_MAX = 4; +localparam VC_DEPTH_MAX = 2; `ifdef VC_DATA_USE_DUAL_PORT_RAM `ifdef RETURN_CREDIT_AT_SA_STAGE localparam VC_DPRAM_DEPTH_MAX = VC_ID_NUM_MAX * (VC_DEPTH_MAX+1); @@ -133,7 +149,9 @@ typedef struct packed { typedef struct packed { node_id_t tgt_id; // target id node_id_t src_id; // source id +`ifdef ENABLE_TXN_ID logic [TxnID_Width-1:0] txn_id; // transaction id +`endif io_port_t look_ahead_routing; `ifdef USE_QOS_VALUE logic [QoS_Value_Width-1:0] qos_value; @@ -153,5 +171,88 @@ typedef struct packed { logic [VC_ID_NUM_MAX_W-1:0] rt_vc_id; } vc_select_vc_id_t; + + + + + // mesh parameters + parameter NODE_NUM_X_DIMESION = 3; + parameter NODE_NUM_Y_DIMESION = 3; + + // router parameters + parameter INPUT_PORT_NUM = INPUT_PORT_NUMBER; + parameter OUTPUT_PORT_NUM = OUTPUT_PORT_NUMBER; + parameter LOCAL_PORT_NUM = INPUT_PORT_NUM-4; + + + typedef struct packed { + logic [256-1:0] data; + + node_id_t tgt_id; // target id + node_id_t src_id; // source id +`ifdef ENABLE_TXN_ID + logic [TxnID_Width-1:0] txn_id; // transaction id +`endif + +`ifdef USE_QOS_VALUE + logic [QoS_Value_Width-1:0] qos_value; +`endif + } cache_scu_cc_test_t; + + parameter FLIT_LENGTH = $bits(cache_scu_cc_test_t); + + // parameter type flit_payload_t = logic[FLIT_LENGTH-1:0]; + parameter type flit_payload_t = cache_scu_cc_test_t; + + // parameter QOS_VC_NUM_PER_INPUT = QOS_VC_NUM_PER_INPUT; +`ifdef SINGLE_VC_PER_INPUT_PORT + parameter VC_NUM_INPUT_N = 1+QOS_VC_NUM_PER_INPUT; + parameter VC_NUM_INPUT_S = 1+QOS_VC_NUM_PER_INPUT; + parameter VC_NUM_INPUT_E = 1+QOS_VC_NUM_PER_INPUT; + parameter VC_NUM_INPUT_W = 1+QOS_VC_NUM_PER_INPUT; + `ifdef ALLOW_SAME_ROUTER_L2L_TRANSFER + parameter VC_NUM_INPUT_L = 1+QOS_VC_NUM_PER_INPUT; + `else + parameter VC_NUM_INPUT_L = 1+QOS_VC_NUM_PER_INPUT; + `endif +`else + parameter VC_NUM_INPUT_N = 1+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT; + parameter VC_NUM_INPUT_S = 1+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT; + parameter VC_NUM_INPUT_E = 3+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT; + parameter VC_NUM_INPUT_W = 3+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT; + `ifdef ALLOW_SAME_ROUTER_L2L_TRANSFER + parameter VC_NUM_INPUT_L = 4+LOCAL_PORT_NUM-1+QOS_VC_NUM_PER_INPUT; + `else + parameter VC_NUM_INPUT_L = 4+QOS_VC_NUM_PER_INPUT; + `endif +`endif + parameter SA_GLOBAL_INPUT_NUM_N = 3+LOCAL_PORT_NUM; + parameter SA_GLOBAL_INPUT_NUM_S = 3+LOCAL_PORT_NUM; + parameter SA_GLOBAL_INPUT_NUM_E = 1+LOCAL_PORT_NUM; + parameter SA_GLOBAL_INPUT_NUM_W = 1+LOCAL_PORT_NUM; +`ifdef ALLOW_SAME_ROUTER_L2L_TRANSFER + parameter SA_GLOBAL_INPUT_NUM_L = 4+LOCAL_PORT_NUM-1; +`else + parameter SA_GLOBAL_INPUT_NUM_L = 4; +`endif +`ifdef SINGLE_VC_PER_INPUT_PORT + parameter VC_NUM_OUTPUT_N = 1+QOS_VC_NUM_PER_INPUT; + parameter VC_NUM_OUTPUT_S = 1+QOS_VC_NUM_PER_INPUT; + parameter VC_NUM_OUTPUT_E = 1+QOS_VC_NUM_PER_INPUT; + parameter VC_NUM_OUTPUT_W = 1+QOS_VC_NUM_PER_INPUT; +`else + parameter VC_NUM_OUTPUT_N = 1+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT; + parameter VC_NUM_OUTPUT_S = 1+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT; + parameter VC_NUM_OUTPUT_E = 3+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT; + parameter VC_NUM_OUTPUT_W = 3+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT; +`endif + parameter VC_NUM_OUTPUT_L = 1; + parameter VC_DEPTH_INPUT_N = VC_DEPTH_MAX; + parameter VC_DEPTH_INPUT_S = VC_DEPTH_MAX; + parameter VC_DEPTH_INPUT_E = VC_DEPTH_MAX; + parameter VC_DEPTH_INPUT_W = VC_DEPTH_MAX; + parameter VC_DEPTH_INPUT_L = VC_DEPTH_MAX; + + endpackage `endif diff --git a/rtl/input_port.sv b/rtl/input_port.sv index 0fa7947..e1c5380 100644 --- a/rtl/input_port.sv +++ b/rtl/input_port.sv @@ -110,26 +110,40 @@ input_port_vc_u `ifndef SYNTHESIS +int noc_debug_print=0; + +initial begin + if ($value$plusargs("noc_debug_print=%d", noc_debug_print)) begin + // $display("NOC: noc_debug_print_in=%d", noc_debug_print); + end +end + `ifdef V_INPORT_PRINT_EN // debug print always_ff @(posedge clk) begin - if(rstn) begin - if(rx_flit_v_i) begin - $display("[%16d] info: receive flit: router:(%d,%d); inport: %1d(N0,S1,E2,W3,L4-7); vc_id: %1d; look_ahead_routing: %1d(N0,S1,E2,W3,L4-7), QoS = %d", - $time(), - node_id_x_ths_hop_i, node_id_y_ths_hop_i, - INPUT_PORT_NO, - rx_flit_vc_id_i, - flit_ctrl_info.look_ahead_routing, - rx_flit_i[QoS_Value_Width-1:0]); - $write(" "); - $display("txn_id: 0x%h, sender: (%d,%d), sender_local_port: %1d", - flit_ctrl_info.txn_id, - flit_ctrl_info.src_id.x_position, flit_ctrl_info.src_id.y_position, - flit_ctrl_info.src_id.device_port); - $write(" "); - $display("tgt_id: (%d,%d), tgt_local_port: %1d", - flit_ctrl_info.tgt_id.x_position, flit_ctrl_info.tgt_id.y_position, flit_ctrl_info.tgt_id.device_port); + if(noc_debug_print) begin + if(rstn) begin + if(rx_flit_v_i) begin + $display("[%16d] info: receive flit: router:(%d,%d); inport: %1d(N0,S1,E2,W3,L4-7); vc_id: %1d; look_ahead_routing: %1d(N0,S1,E2,W3,L4-7), QoS = %d", + $time(), + node_id_x_ths_hop_i, node_id_y_ths_hop_i, + INPUT_PORT_NO, + rx_flit_vc_id_i, + flit_ctrl_info.look_ahead_routing, + rx_flit_i[QoS_Value_Width-1:0]); + $write(" "); + $display("txn_id: 0x%h, sender: (%d,%d), sender_local_port: %1d", +`ifdef ENABLE_TXN_ID + flit_ctrl_info.txn_id, +`else + '0, +`endif + flit_ctrl_info.src_id.x_position, flit_ctrl_info.src_id.y_position, + flit_ctrl_info.src_id.device_port); + $write(" "); + $display("tgt_id: (%d,%d), tgt_local_port: %1d", + flit_ctrl_info.tgt_id.x_position, flit_ctrl_info.tgt_id.y_position, flit_ctrl_info.tgt_id.device_port); + end end end end diff --git a/rtl/input_port_flit_decoder.sv b/rtl/input_port_flit_decoder.sv index 74eafcf..3057f48 100644 --- a/rtl/input_port_flit_decoder.sv +++ b/rtl/input_port_flit_decoder.sv @@ -13,11 +13,13 @@ module input_port_flit_decoder ); `ifdef USE_QOS_VALUE -assign flit_dec_o.qos_value = flit_i[QoS_Value_Width-1:0]; +assign flit_dec_o.qos_value = flit_i.qos_value; +`endif +assign flit_dec_o.tgt_id = flit_i.tgt_id; +assign flit_dec_o.src_id = flit_i.src_id; +`ifdef ENABLE_TXN_ID +assign flit_dec_o.txn_id = flit_i.txn_id; `endif -assign flit_dec_o.tgt_id = flit_i[QoS_Value_Width+NodeID_Width-1:QoS_Value_Width]; -assign flit_dec_o.src_id = flit_i[QoS_Value_Width+NodeID_Width+NodeID_Width-1:QoS_Value_Width+NodeID_Width]; -assign flit_dec_o.txn_id = flit_i[QoS_Value_Width+NodeID_Width+NodeID_Width+TxnID_Width-1:QoS_Value_Width+NodeID_Width+NodeID_Width]; assign flit_dec_o.look_ahead_routing = flit_look_ahead_routing_i; diff --git a/rtl/input_port_vc.sv b/rtl/input_port_vc.sv index 4129d7f..2d7ee19 100644 --- a/rtl/input_port_vc.sv +++ b/rtl/input_port_vc.sv @@ -93,7 +93,9 @@ end assign vc_data_din = flit_i; assign vc_ctrl_din.tgt_id = flit_dec_i.tgt_id; assign vc_ctrl_din.src_id = flit_dec_i.src_id; +`ifdef ENABLE_TXN_ID assign vc_ctrl_din.txn_id = flit_dec_i.txn_id; +`endif assign vc_ctrl_din.look_ahead_routing = flit_dec_i.look_ahead_routing; `ifdef USE_QOS_VALUE assign vc_ctrl_din.qos_value = flit_dec_i.qos_value; @@ -276,11 +278,19 @@ endgenerate generate for(i = 0; i < QOS_VC_NUM_PER_INPUT; i++) begin assert property(@(posedge clk)disable iff(~rstn) (vc_ctrl_head_vld[i]) |-> (vc_ctrl_head[i].qos_value == 15)) +`ifdef ENABLE_TXN_ID else $fatal("noc_input_vc: rt VC has flit with lower QoS value, txn_id: 0x%x", vc_ctrl_head[i].txn_id); +`else + else $fatal("noc_input_vc: rt VC has flit with lower QoS value"); +`endif end for(i = QOS_VC_NUM_PER_INPUT; i < VC_NUM; i++) begin assert property(@(posedge clk)disable iff(~rstn) (vc_ctrl_head_vld[i]) |-> (vc_ctrl_head[i].qos_value != 15)) +`ifdef ENABLE_TXN_ID else $fatal("noc_input_vc: common VC has flit with highest QoS value, txn_id: 0x%x", vc_ctrl_head[i].txn_id); +`else + else $fatal("noc_input_vc: common VC has flit with highest QoS value"); +`endif end endgenerate `endif diff --git a/rtl/local_port_couple_module.sv b/rtl/local_port_couple_module.sv index 053c22f..b1a6d00 100644 --- a/rtl/local_port_couple_module.sv +++ b/rtl/local_port_couple_module.sv @@ -37,7 +37,7 @@ import rvh_noc_pkg::*; input logic flit_vld_i, input logic [QoS_Value_Width-1:0] flit_qos_value_i, output logic free_credit_vld_o, - output logic [VC_NUM_OUTPORT_IDX_W-1:0] free_credit_vc_id_o, + output logic [VC_ID_NUM_MAX_W-1:0] free_credit_vc_id_o, input logic clk, input logic rstn @@ -46,7 +46,10 @@ import rvh_noc_pkg::*; logic [VC_NUM_OUTPORT-1:0][VC_DEPTH_OUTPORT_COUNTER_W-1:0] vc_credit_counter; logic [VC_NUM_OUTPORT-1:0] vc_credit_counter_non_zero; logic [VC_NUM_OUTPORT-QOS_VC_NUM_PER_INPUT-1:0] vc_allocate_common_vc_grt_oh; -logic [$clog2(VC_NUM_OUTPORT-QOS_VC_NUM_PER_INPUT)-1:0] vc_allocate_common_vc_grt_idx; + +localparam GRT_IDX_W = VC_NUM_OUTPORT-QOS_VC_NUM_PER_INPUT > 1 ? $clog2(VC_NUM_OUTPORT-QOS_VC_NUM_PER_INPUT) : 1; +logic [GRT_IDX_W-1:0] vc_allocate_common_vc_grt_idx; + `ifdef COMMON_QOS_EXTRA_RT_VC logic [QOS_VC_NUM_PER_INPUT-1:0] vc_allocate_rt_vc_grt_oh; logic [$clog2(QOS_VC_NUM_PER_INPUT)-1:0] vc_allocate_rt_vc_grt_idx; @@ -93,7 +96,7 @@ assign free_credit_vld = ( ); assign free_credit_vld_o = free_credit_vld; -assign free_credit_vc_id_o = consume_vc_credit_vc_id; +assign free_credit_vc_id_o = VC_ID_NUM_MAX_W'(consume_vc_credit_vc_id); assign flit_buffer_dequeue_vld = flit_vld_i & // head valid free_credit_vld; // vc not empty @@ -158,7 +161,7 @@ output_port_vc_credit_counter ) output_port_vc_credit_counter_u ( .free_vc_credit_vld_i (tx_lcrd_v_i ), - .free_vc_credit_vc_id_i (tx_lcrd_id_i ), + .free_vc_credit_vc_id_i (tx_lcrd_id_i[VC_NUM_OUTPORT_IDX_W-1:0] ), .consume_vc_credit_vld_i (consume_vc_credit_vld ), .consume_vc_credit_vc_id_i (consume_vc_credit_vc_id ), .vc_credit_counter_o (vc_credit_counter ), diff --git a/rtl/output_port_vc_assignment.sv b/rtl/output_port_vc_assignment.sv index e4467eb..5c7936d 100644 --- a/rtl/output_port_vc_assignment.sv +++ b/rtl/output_port_vc_assignment.sv @@ -12,7 +12,9 @@ parameter OUTPUT_TO_N = 0, parameter OUTPUT_TO_S = 0, parameter OUTPUT_TO_E = 0, parameter OUTPUT_TO_W = 0, -parameter OUTPUT_TO_L = 0 +parameter OUTPUT_TO_L = 0, + +parameter COMMON_OUTPUT_VC_NUM = OUTPUT_TO_L ? 1 + QOS_VC_NUM_PER_INPUT : OUTPUT_VC_NUM-QOS_VC_NUM_PER_INPUT ) ( // input from global sa @@ -54,9 +56,9 @@ onehot_mux_look_ahead_routing_sel_u ( assign look_ahead_routing_sel_o = look_ahead_routing_sel; -logic sa_global_sel_rt_vc_flit_en; -logic [OUTPUT_VC_NUM-QOS_VC_NUM_PER_INPUT-1:0] vc_select_vld; // if local port as outport, doesn't take rt vc into consideration -logic [OUTPUT_VC_NUM-QOS_VC_NUM_PER_INPUT-1:0][VC_ID_NUM_MAX_W-1:0] vc_select_vc_id; // if local port as outport, doesn't take rt vc into consideration +logic sa_global_sel_rt_vc_flit_en; +logic [COMMON_OUTPUT_VC_NUM-1:0] vc_select_vld; // if local port as outport, doesn't take rt vc into consideration +logic [COMMON_OUTPUT_VC_NUM-1:0][VC_ID_NUM_MAX_W-1:0] vc_select_vc_id; // if local port as outport, doesn't take rt vc into consideration `ifdef COMMON_QOS_EXTRA_RT_VC assign sa_global_sel_rt_vc_flit_en = &sa_global_qos_value_i; // rt vc has highest QoS value @@ -66,23 +68,39 @@ assign sa_global_sel_rt_vc_flit_en = '0; // vc_select_vld -// for vc_select_vld_i, the [0:QOS_VC_NUM_PER_INPUT-1] is rt vc, [QOS_VC_NUM_PER_INPUT:OUTPUT_VC_NUM-1] is common vc generate - for(i = 0; i < OUTPUT_VC_NUM-QOS_VC_NUM_PER_INPUT; i++) begin: gen_vc_select_vld - assign vc_select_vld[i] = sa_global_sel_rt_vc_flit_en ? vc_select_vld_i[0].rt_vld : vc_select_vld_i[i+QOS_VC_NUM_PER_INPUT].common_vld; - end -endgenerate + if(!OUTPUT_TO_L) begin -// vc_select_vc_id -generate - for(i = 0; i < OUTPUT_VC_NUM-QOS_VC_NUM_PER_INPUT; i++) begin: gen_vc_select_vc_id - assign vc_select_vc_id[i] = sa_global_sel_rt_vc_flit_en ? vc_select_vc_id_i[0].rt_vc_id : vc_select_vc_id_i[i+QOS_VC_NUM_PER_INPUT].common_vc_id; + // for vc_select_vld_i, the [0:QOS_VC_NUM_PER_INPUT-1] is rt vc, [QOS_VC_NUM_PER_INPUT:OUTPUT_VC_NUM-1] is common vc + for(i = 0; i < OUTPUT_VC_NUM-QOS_VC_NUM_PER_INPUT; i++) begin: gen_vc_select_vld + assign vc_select_vld[i] = sa_global_sel_rt_vc_flit_en ? vc_select_vld_i[0].rt_vld : vc_select_vld_i[i+QOS_VC_NUM_PER_INPUT].common_vld; + end + + // vc_select_vc_id + for(i = 0; i < OUTPUT_VC_NUM-QOS_VC_NUM_PER_INPUT; i++) begin: gen_vc_select_vc_id + assign vc_select_vc_id[i] = sa_global_sel_rt_vc_flit_en ? vc_select_vc_id_i[0].rt_vc_id : vc_select_vc_id_i[i+QOS_VC_NUM_PER_INPUT].common_vc_id; + end + end else begin + assign vc_select_vld = '0; + assign vc_select_vc_id = '0; end endgenerate // vc assignment for different output ports // to N vc: // vc0 +`ifdef SINGLE_VC_PER_INPUT_PORT +generate + if(!OUTPUT_TO_L) begin + assign vc_assignment_vld_o = vc_select_vld[0]; + assign vc_assignment_vc_id_o = vc_select_vc_id[0]; + end else begin + assign vc_assignment_vld_o = vc_select_vld_i [0].common_vld; + assign vc_assignment_vc_id_o = vc_select_vc_id_i[0].common_vc_id; + end +endgenerate +`else + generate if(OUTPUT_TO_N) begin: gen_output_to_n // output to N, next hop input is S @@ -263,6 +281,6 @@ generate end endgenerate - +`endif endmodule diff --git a/rtl/rn_router_sam.sv b/rtl/rn_router_sam.sv new file mode 100644 index 0000000..c81aec1 --- /dev/null +++ b/rtl/rn_router_sam.sv @@ -0,0 +1,47 @@ +module rn_router_sam + import rvh_noc_pkg::*; +#( + parameter type flit_payload_t = logic[256-1:0] + // parameter VC_NUM_IDX_W = 1 +) +( + input logic flit_v_i, + input flit_payload_t flit_i, + input io_port_t flit_look_ahead_routing_i, + + input logic [NodeID_X_Width-1:0] node_id_x_i, + input logic [NodeID_Y_Width-1:0] node_id_y_i, + + output flit_dec_t flit_dec_o, + output flit_payload_t flit_o + +); + +`ifdef USE_QOS_VALUE +assign flit_dec_o.qos_value = flit_i.qos_value; +`endif + +always_comb begin + flit_o = flit_i; + flit_o.tgt_id.x_position = 1; + flit_o.tgt_id.y_position = 0; + flit_o.tgt_id.device_port = 0; + flit_o.tgt_id.device_id = 0; + flit_o.src_id.x_position = node_id_x_i; + flit_o.src_id.y_position = node_id_y_i; + flit_o.src_id.device_port = 0; + flit_o.src_id.device_id = 0; +end + +assign flit_dec_o.tgt_id.x_position = 1; +assign flit_dec_o.tgt_id.y_position = 0; +assign flit_dec_o.tgt_id.device_port = 0; +assign flit_dec_o.tgt_id.device_id = 0; +assign flit_dec_o.src_id.x_position = node_id_x_i; +assign flit_dec_o.src_id.y_position = node_id_y_i; +assign flit_dec_o.src_id.device_port = 0; +assign flit_dec_o.src_id.device_id = 0; + +assign flit_dec_o.look_ahead_routing = flit_look_ahead_routing_i; + +endmodule \ No newline at end of file diff --git a/rtl/vnet_router.sv b/rtl/vnet_router.sv index 46f5850..cc543bd 100644 --- a/rtl/vnet_router.sv +++ b/rtl/vnet_router.sv @@ -126,8 +126,8 @@ logic [OUTPUT_PORT_NUM-1:0] vc_assignment_vld; logic [OUTPUT_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] vc_assignment_vc_id; io_port_t [OUTPUT_PORT_NUM-1:0] look_ahead_routing_sel; -logic [INPUT_PORT_NUM-1:0][OUTPUT_PORT_NUMBER-1:0] sa_local_vld_to_sa_global; logic [INPUT_PORT_NUM-1:0] sa_local_vld; +logic [INPUT_PORT_NUM-1:0][OUTPUT_PORT_NUMBER-1:0] sa_local_vld_to_sa_global; logic [INPUT_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] sa_local_vc_id; logic [INPUT_PORT_NUM-1:0][VC_ID_NUM_MAX-1:0] sa_local_vc_id_oh; `ifdef USE_QOS_VALUE @@ -137,6 +137,24 @@ logic [INPUT_PORT_NUM-1:0][QoS_Value_Width-1:0] sa_local_qos_value; dpram_used_idx_t [INPUT_PORT_NUM-1:0] sa_local_dpram_idx; `endif +`ifdef INSERT_PIPELINE_REG_BETWEEN_SA +logic [INPUT_PORT_NUM-1:0] sa_local_vld_q; +logic [INPUT_PORT_NUM-1:0][OUTPUT_PORT_NUMBER-1:0] sa_local_vld_to_sa_global_q; +logic [INPUT_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] sa_local_vc_id_q; +logic [INPUT_PORT_NUM-1:0][VC_ID_NUM_MAX-1:0] sa_local_vc_id_oh_q; + `ifdef USE_QOS_VALUE +logic [INPUT_PORT_NUM-1:0][QoS_Value_Width-1:0] sa_local_qos_value_q; + `endif + `ifdef VC_DATA_USE_DUAL_PORT_RAM +dpram_used_idx_t [INPUT_PORT_NUM-1:0] sa_local_dpram_idx_q; + `endif + +logic [INPUT_PORT_NUM-1:0] sa_global_stall; +logic [INPUT_PORT_NUM-1:0] sa_local_vld_ena; +logic [INPUT_PORT_NUM-1:0] sa_local_ena; + +`endif + // ============= // 1 input port // ============= @@ -192,7 +210,12 @@ input_port_fromN_u .vc_data_head_o (vc_data_head_N ), // input pop flit ctrl fifo (comes from SA stage) +`ifdef INSERT_PIPELINE_REG_BETWEEN_SA + .inport_read_enable_sa_stage_i (sa_local_ena [0]), +`else .inport_read_enable_sa_stage_i (inport_read_enable_sa_stage [0]), +`endif + .inport_read_vc_id_sa_stage_i (sa_local_vc_id [0][VC_NUM_INPUT_N_IDX_W-1:0]), // use sa_local_vc_id instead inport_read_vc_id_sa_stage to remove it from critical path `ifdef VC_DATA_USE_DUAL_PORT_RAM .inport_read_dpram_idx_i (sa_local_dpram_idx [0]), @@ -241,7 +264,12 @@ input_port_fromS_u .vc_data_head_o (vc_data_head_S ), // input pop flit ctrl fifo (comes from SA stage) +`ifdef INSERT_PIPELINE_REG_BETWEEN_SA + .inport_read_enable_sa_stage_i (sa_local_ena [1]), +`else .inport_read_enable_sa_stage_i (inport_read_enable_sa_stage [1]), +`endif + .inport_read_vc_id_sa_stage_i (sa_local_vc_id [1][VC_NUM_INPUT_S_IDX_W-1:0]), // use sa_local_vc_id instead inport_read_vc_id_sa_stage to remove it from critical path `ifdef VC_DATA_USE_DUAL_PORT_RAM .inport_read_dpram_idx_i (sa_local_dpram_idx [1]), @@ -290,7 +318,12 @@ input_port_fromE_u .vc_data_head_o (vc_data_head_E ), // input pop flit ctrl fifo (comes from SA stage) +`ifdef INSERT_PIPELINE_REG_BETWEEN_SA + .inport_read_enable_sa_stage_i (sa_local_ena [2]), +`else .inport_read_enable_sa_stage_i (inport_read_enable_sa_stage [2]), +`endif + .inport_read_vc_id_sa_stage_i (sa_local_vc_id [2][VC_NUM_INPUT_E_IDX_W-1:0]), // use sa_local_vc_id instead inport_read_vc_id_sa_stage to remove it from critical path `ifdef VC_DATA_USE_DUAL_PORT_RAM .inport_read_dpram_idx_i (sa_local_dpram_idx [2]), @@ -339,7 +372,12 @@ input_port_fromW_u .vc_data_head_o (vc_data_head_W ), // input pop flit ctrl fifo (comes from SA stage) +`ifdef INSERT_PIPELINE_REG_BETWEEN_SA + .inport_read_enable_sa_stage_i (sa_local_ena [3]), +`else .inport_read_enable_sa_stage_i (inport_read_enable_sa_stage [3]), +`endif + .inport_read_vc_id_sa_stage_i (sa_local_vc_id [3][VC_NUM_INPUT_W_IDX_W-1:0]), // use sa_local_vc_id instead inport_read_vc_id_sa_stage to remove it from critical path `ifdef VC_DATA_USE_DUAL_PORT_RAM .inport_read_dpram_idx_i (sa_local_dpram_idx [3]), @@ -391,7 +429,12 @@ generate .vc_data_head_o (vc_data_head_L [i] ), // input pop flit ctrl fifo (comes from SA stage) +`ifdef INSERT_PIPELINE_REG_BETWEEN_SA + .inport_read_enable_sa_stage_i (sa_local_ena [4+i]), +`else .inport_read_enable_sa_stage_i (inport_read_enable_sa_stage [4+i]), +`endif + .inport_read_vc_id_sa_stage_i (sa_local_vc_id [4+i][VC_NUM_INPUT_L_IDX_W-1:0]), // use sa_local_vc_id instead inport_read_vc_id_sa_stage to remove it from critical path `ifdef VC_DATA_USE_DUAL_PORT_RAM .inport_read_dpram_idx_i (sa_local_dpram_idx [4+i]), @@ -437,8 +480,11 @@ sa_local_fromN_u ( .sa_local_dpram_idx_o (sa_local_dpram_idx [0]), `endif - +`ifdef INSERT_PIPELINE_REG_BETWEEN_SA + .inport_read_enable_sa_stage_i (sa_local_ena [0]), +`else .inport_read_enable_sa_stage_i (inport_read_enable_sa_stage [0]), +`endif .clk (clk ), .rstn (rstn) @@ -469,7 +515,11 @@ sa_local_fromS_u ( .sa_local_dpram_idx_o (sa_local_dpram_idx [1]), `endif +`ifdef INSERT_PIPELINE_REG_BETWEEN_SA + .inport_read_enable_sa_stage_i (sa_local_ena [1]), +`else .inport_read_enable_sa_stage_i (inport_read_enable_sa_stage [1]), +`endif .clk (clk ), .rstn (rstn) @@ -500,7 +550,11 @@ sa_local_fromE_u ( .sa_local_dpram_idx_o (sa_local_dpram_idx [2]), `endif +`ifdef INSERT_PIPELINE_REG_BETWEEN_SA + .inport_read_enable_sa_stage_i (sa_local_ena [2]), +`else .inport_read_enable_sa_stage_i (inport_read_enable_sa_stage [2]), +`endif .clk (clk ), .rstn (rstn) @@ -531,7 +585,11 @@ sa_local_fromW_u ( .sa_local_dpram_idx_o (sa_local_dpram_idx [3]), `endif +`ifdef INSERT_PIPELINE_REG_BETWEEN_SA + .inport_read_enable_sa_stage_i (sa_local_ena [3]), +`else .inport_read_enable_sa_stage_i (inport_read_enable_sa_stage [3]), +`endif .clk (clk ), .rstn (rstn) @@ -565,7 +623,11 @@ generate .sa_local_dpram_idx_o (sa_local_dpram_idx [4+i]), `endif + `ifdef INSERT_PIPELINE_REG_BETWEEN_SA + .inport_read_enable_sa_stage_i (sa_local_ena [4+i]), + `else .inport_read_enable_sa_stage_i (inport_read_enable_sa_stage [4+i]), + `endif .clk (clk ), .rstn (rstn) @@ -610,6 +672,35 @@ logic [SA_GLOBAL_INPUT_NUM_E-1:0][QoS_Value_Width-1:0] sa_local_qos_value_all_i logic [SA_GLOBAL_INPUT_NUM_W-1:0][QoS_Value_Width-1:0] sa_local_qos_value_all_inport_toW; `endif +`ifdef INSERT_PIPELINE_REG_BETWEEN_SA + +assign sa_local_vld_to_sa_global_all_inport_toN[0] = sa_local_vld_to_sa_global_q[1][0]; +assign sa_local_vld_to_sa_global_all_inport_toN[1] = sa_local_vld_to_sa_global_q[2][0]; +assign sa_local_vld_to_sa_global_all_inport_toN[2] = sa_local_vld_to_sa_global_q[3][0]; +assign sa_local_vc_id_all_inport_toN [0] = sa_local_vc_id_q [1]; +assign sa_local_vc_id_all_inport_toN [1] = sa_local_vc_id_q [2]; +assign sa_local_vc_id_all_inport_toN [2] = sa_local_vc_id_q [3]; + + `ifdef USE_QOS_VALUE +assign sa_local_qos_value_all_inport_toN [0] = sa_local_qos_value_q [1]; +assign sa_local_qos_value_all_inport_toN [1] = sa_local_qos_value_q [2]; +assign sa_local_qos_value_all_inport_toN [2] = sa_local_qos_value_q [3]; + `endif + +generate + if(LOCAL_PORT_NUM > 0) begin: gen_sa_local_vld_to_sa_global_all_inport_toN_fromL_signal + for(i = 0; i < LOCAL_PORT_NUM; i++) begin + assign sa_local_vld_to_sa_global_all_inport_toN[3+i] = sa_local_vld_to_sa_global_q[4+i][0]; + assign sa_local_vc_id_all_inport_toN [3+i] = sa_local_vc_id_q [4+i]; + `ifdef USE_QOS_VALUE + assign sa_local_qos_value_all_inport_toN [3+i] = sa_local_qos_value_q [4+i]; + `endif + end + end +endgenerate + +`else + assign sa_local_vld_to_sa_global_all_inport_toN[0] = sa_local_vld_to_sa_global[1][0]; assign sa_local_vld_to_sa_global_all_inport_toN[1] = sa_local_vld_to_sa_global[2][0]; assign sa_local_vld_to_sa_global_all_inport_toN[2] = sa_local_vld_to_sa_global[3][0]; @@ -617,24 +708,25 @@ assign sa_local_vc_id_all_inport_toN [0] = sa_local_vc_id [1 assign sa_local_vc_id_all_inport_toN [1] = sa_local_vc_id [2]; assign sa_local_vc_id_all_inport_toN [2] = sa_local_vc_id [3]; -`ifdef USE_QOS_VALUE + `ifdef USE_QOS_VALUE assign sa_local_qos_value_all_inport_toN [0] = sa_local_qos_value [1]; assign sa_local_qos_value_all_inport_toN [1] = sa_local_qos_value [2]; assign sa_local_qos_value_all_inport_toN [2] = sa_local_qos_value [3]; -`endif + `endif generate if(LOCAL_PORT_NUM > 0) begin: gen_sa_local_vld_to_sa_global_all_inport_toN_fromL_signal for(i = 0; i < LOCAL_PORT_NUM; i++) begin assign sa_local_vld_to_sa_global_all_inport_toN[3+i] = sa_local_vld_to_sa_global[4+i][0]; assign sa_local_vc_id_all_inport_toN [3+i] = sa_local_vc_id [4+i]; - `ifdef USE_QOS_VALUE + `ifdef USE_QOS_VALUE assign sa_local_qos_value_all_inport_toN [3+i] = sa_local_qos_value [4+i]; - `endif + `endif end end endgenerate +`endif sa_global @@ -668,6 +760,34 @@ generate end endgenerate +`ifdef INSERT_PIPELINE_REG_BETWEEN_SA + +assign sa_local_vld_to_sa_global_all_inport_toS[0] = sa_local_vld_to_sa_global_q[0][1]; +assign sa_local_vld_to_sa_global_all_inport_toS[1] = sa_local_vld_to_sa_global_q[2][1]; +assign sa_local_vld_to_sa_global_all_inport_toS[2] = sa_local_vld_to_sa_global_q[3][1]; +assign sa_local_vc_id_all_inport_toS [0] = sa_local_vc_id_q [0]; +assign sa_local_vc_id_all_inport_toS [1] = sa_local_vc_id_q [2]; +assign sa_local_vc_id_all_inport_toS [2] = sa_local_vc_id_q [3]; + + `ifdef USE_QOS_VALUE +assign sa_local_qos_value_all_inport_toS [0] = sa_local_qos_value_q [0]; +assign sa_local_qos_value_all_inport_toS [1] = sa_local_qos_value_q [2]; +assign sa_local_qos_value_all_inport_toS [2] = sa_local_qos_value_q [3]; + `endif + +generate + if(LOCAL_PORT_NUM > 0) begin: gen_sa_local_vld_to_sa_global_all_inport_toS_fromL_signal + for(i = 0; i < LOCAL_PORT_NUM; i++) begin + assign sa_local_vld_to_sa_global_all_inport_toS[3+i] = sa_local_vld_to_sa_global_q[4+i][1]; + assign sa_local_vc_id_all_inport_toS [3+i] = sa_local_vc_id_q [4+i]; + `ifdef USE_QOS_VALUE + assign sa_local_qos_value_all_inport_toS [3+i] = sa_local_qos_value_q [4+i]; + `endif + end + end +endgenerate + +`else assign sa_local_vld_to_sa_global_all_inport_toS[0] = sa_local_vld_to_sa_global[0][1]; assign sa_local_vld_to_sa_global_all_inport_toS[1] = sa_local_vld_to_sa_global[2][1]; @@ -676,24 +796,26 @@ assign sa_local_vc_id_all_inport_toS [0] = sa_local_vc_id [0 assign sa_local_vc_id_all_inport_toS [1] = sa_local_vc_id [2]; assign sa_local_vc_id_all_inport_toS [2] = sa_local_vc_id [3]; -`ifdef USE_QOS_VALUE + `ifdef USE_QOS_VALUE assign sa_local_qos_value_all_inport_toS [0] = sa_local_qos_value [0]; assign sa_local_qos_value_all_inport_toS [1] = sa_local_qos_value [2]; assign sa_local_qos_value_all_inport_toS [2] = sa_local_qos_value [3]; -`endif + `endif generate if(LOCAL_PORT_NUM > 0) begin: gen_sa_local_vld_to_sa_global_all_inport_toS_fromL_signal for(i = 0; i < LOCAL_PORT_NUM; i++) begin assign sa_local_vld_to_sa_global_all_inport_toS[3+i] = sa_local_vld_to_sa_global[4+i][1]; assign sa_local_vc_id_all_inport_toS [3+i] = sa_local_vc_id [4+i]; - `ifdef USE_QOS_VALUE + `ifdef USE_QOS_VALUE assign sa_local_qos_value_all_inport_toS [3+i] = sa_local_qos_value [4+i]; - `endif + `endif end end endgenerate +`endif + sa_global #( .INPUT_NUM (SA_GLOBAL_INPUT_NUM_S ) @@ -725,26 +847,50 @@ generate end endgenerate +`ifdef INSERT_PIPELINE_REG_BETWEEN_SA + +assign sa_local_vld_to_sa_global_all_inport_toE[0] = sa_local_vld_to_sa_global_q[3][2]; +assign sa_local_vc_id_all_inport_toE [0] = sa_local_vc_id_q [3]; + + `ifdef USE_QOS_VALUE +assign sa_local_qos_value_all_inport_toE [0] = sa_local_qos_value_q [3]; + `endif + +generate + if(LOCAL_PORT_NUM > 0) begin: gen_sa_local_vld_to_sa_global_all_inport_toE_fromL_signal + for(i = 0; i < LOCAL_PORT_NUM; i++) begin + assign sa_local_vld_to_sa_global_all_inport_toE[1+i] = sa_local_vld_to_sa_global_q[4+i][2]; + assign sa_local_vc_id_all_inport_toE [1+i] = sa_local_vc_id_q [4+i]; + `ifdef USE_QOS_VALUE + assign sa_local_qos_value_all_inport_toE [1+i] = sa_local_qos_value_q [4+i]; + `endif + end + end +endgenerate + +`else assign sa_local_vld_to_sa_global_all_inport_toE[0] = sa_local_vld_to_sa_global[3][2]; assign sa_local_vc_id_all_inport_toE [0] = sa_local_vc_id [3]; -`ifdef USE_QOS_VALUE + `ifdef USE_QOS_VALUE assign sa_local_qos_value_all_inport_toE [0] = sa_local_qos_value [3]; -`endif + `endif generate if(LOCAL_PORT_NUM > 0) begin: gen_sa_local_vld_to_sa_global_all_inport_toE_fromL_signal for(i = 0; i < LOCAL_PORT_NUM; i++) begin assign sa_local_vld_to_sa_global_all_inport_toE[1+i] = sa_local_vld_to_sa_global[4+i][2]; assign sa_local_vc_id_all_inport_toE [1+i] = sa_local_vc_id [4+i]; - `ifdef USE_QOS_VALUE + `ifdef USE_QOS_VALUE assign sa_local_qos_value_all_inport_toE [1+i] = sa_local_qos_value [4+i]; - `endif + `endif end end endgenerate +`endif + sa_global #( .INPUT_NUM (SA_GLOBAL_INPUT_NUM_E ) @@ -777,26 +923,50 @@ generate endgenerate +`ifdef INSERT_PIPELINE_REG_BETWEEN_SA + +assign sa_local_vld_to_sa_global_all_inport_toW[0] = sa_local_vld_to_sa_global_q[2][3]; +assign sa_local_vc_id_all_inport_toW [0] = sa_local_vc_id_q [2]; + + `ifdef USE_QOS_VALUE +assign sa_local_qos_value_all_inport_toW [0] = sa_local_qos_value_q [2]; + `endif + +generate + if(LOCAL_PORT_NUM > 0) begin: gen_sa_local_vld_to_sa_global_all_inport_toW_fromL_signal + for(i = 0; i < LOCAL_PORT_NUM; i++) begin + assign sa_local_vld_to_sa_global_all_inport_toW[1+i] = sa_local_vld_to_sa_global_q[4+i][3]; + assign sa_local_vc_id_all_inport_toW [1+i] = sa_local_vc_id_q [4+i]; + `ifdef USE_QOS_VALUE + assign sa_local_qos_value_all_inport_toW [1+i] = sa_local_qos_value_q [4+i]; + `endif + end + end +endgenerate + +`else assign sa_local_vld_to_sa_global_all_inport_toW[0] = sa_local_vld_to_sa_global[2][3]; assign sa_local_vc_id_all_inport_toW [0] = sa_local_vc_id [2]; -`ifdef USE_QOS_VALUE + `ifdef USE_QOS_VALUE assign sa_local_qos_value_all_inport_toW [0] = sa_local_qos_value [2]; -`endif + `endif generate if(LOCAL_PORT_NUM > 0) begin: gen_sa_local_vld_to_sa_global_all_inport_toW_fromL_signal for(i = 0; i < LOCAL_PORT_NUM; i++) begin assign sa_local_vld_to_sa_global_all_inport_toW[1+i] = sa_local_vld_to_sa_global[4+i][3]; assign sa_local_vc_id_all_inport_toW [1+i] = sa_local_vc_id [4+i]; - `ifdef USE_QOS_VALUE + `ifdef USE_QOS_VALUE assign sa_local_qos_value_all_inport_toW [1+i] = sa_local_qos_value [4+i]; - `endif + `endif end end endgenerate +`endif + sa_global #( .INPUT_NUM (SA_GLOBAL_INPUT_NUM_W ) @@ -832,6 +1002,35 @@ endgenerate `ifdef HAVE_LOCAL_PORT +`ifdef INSERT_PIPELINE_REG_BETWEEN_SA + +always_comb begin + int k; + for(int i = 0; i < LOCAL_PORT_NUM; i++) begin + for(int j = 0; j < 4; j++) begin + sa_local_vld_to_sa_global_all_inport_toL[i][j] = sa_local_vld_to_sa_global_q[j][4+i]; + sa_local_vc_id_all_inport_toL [i][j] = sa_local_vc_id_q [j]; + `ifdef USE_QOS_VALUE + sa_local_qos_value_all_inport_toL [i][j] = sa_local_qos_value_q [j]; + `endif + end + `ifdef ALLOW_SAME_ROUTER_L2L_TRANSFER + k = 0; + for(int j = 0; j < LOCAL_PORT_NUM; j++) begin + if(i != j) begin + sa_local_vld_to_sa_global_all_inport_toL[i][4+k] = sa_local_vld_to_sa_global_q[4+j][4+i]; + sa_local_vc_id_all_inport_toL [i][4+k] = sa_local_vc_id_q [4+j]; + `ifdef USE_QOS_VALUE + sa_local_qos_value_all_inport_toL [i][4+k] = sa_local_qos_value_q [4+j]; + `endif + k++; + end + end + `endif + end +end + +`else always_comb begin int k; for(int i = 0; i < LOCAL_PORT_NUM; i++) begin @@ -858,6 +1057,8 @@ always_comb begin end end +`endif + generate if(LOCAL_PORT_NUM > 0) begin: gen_have_sa_global_toL for(i = 0; i < LOCAL_PORT_NUM; i++) begin: gen_sa_global_toL @@ -900,6 +1101,9 @@ endgenerate // =================== io_port_t [INPUT_PORT_NUM-1:0] look_ahead_routing; flit_dec_t [INPUT_PORT_NUM-1:0] vc_ctrl_head_sa_local_sel; +`ifdef INSERT_PIPELINE_REG_BETWEEN_SA +flit_dec_t [INPUT_PORT_NUM-1:0] vc_ctrl_head_sa_local_sel_q; +`endif onehot_mux @@ -917,8 +1121,13 @@ look_ahead_routing #( ) look_ahead_routing_fromN_u ( +`ifdef INSERT_PIPELINE_REG_BETWEEN_SA + .vc_ctrl_head_vld_i (sa_local_vld_q [0] ), + .vc_ctrl_head_i (vc_ctrl_head_sa_local_sel_q[0] ), +`else .vc_ctrl_head_vld_i (sa_local_vld [0] ), .vc_ctrl_head_i (vc_ctrl_head_sa_local_sel[0] ), +`endif .node_id_x_ths_hop_i (node_id_x_ths_hop_i ), .node_id_y_ths_hop_i (node_id_y_ths_hop_i ), @@ -941,8 +1150,13 @@ look_ahead_routing #( ) look_ahead_routing_fromS_u ( +`ifdef INSERT_PIPELINE_REG_BETWEEN_SA + .vc_ctrl_head_vld_i (sa_local_vld_q [1] ), + .vc_ctrl_head_i (vc_ctrl_head_sa_local_sel_q[1] ), +`else .vc_ctrl_head_vld_i (sa_local_vld [1] ), .vc_ctrl_head_i (vc_ctrl_head_sa_local_sel[1] ), +`endif .node_id_x_ths_hop_i (node_id_x_ths_hop_i ), .node_id_y_ths_hop_i (node_id_y_ths_hop_i ), @@ -965,8 +1179,13 @@ look_ahead_routing #( ) look_ahead_routing_fromE_u ( +`ifdef INSERT_PIPELINE_REG_BETWEEN_SA + .vc_ctrl_head_vld_i (sa_local_vld_q [2] ), + .vc_ctrl_head_i (vc_ctrl_head_sa_local_sel_q[2] ), +`else .vc_ctrl_head_vld_i (sa_local_vld [2] ), .vc_ctrl_head_i (vc_ctrl_head_sa_local_sel[2] ), +`endif .node_id_x_ths_hop_i (node_id_x_ths_hop_i ), .node_id_y_ths_hop_i (node_id_y_ths_hop_i ), @@ -989,8 +1208,13 @@ look_ahead_routing #( ) look_ahead_routing_fromW_u ( +`ifdef INSERT_PIPELINE_REG_BETWEEN_SA + .vc_ctrl_head_vld_i (sa_local_vld_q [3] ), + .vc_ctrl_head_i (vc_ctrl_head_sa_local_sel_q[3] ), +`else .vc_ctrl_head_vld_i (sa_local_vld [3] ), .vc_ctrl_head_i (vc_ctrl_head_sa_local_sel[3] ), +`endif .node_id_x_ths_hop_i (node_id_x_ths_hop_i ), .node_id_y_ths_hop_i (node_id_y_ths_hop_i ), @@ -1015,8 +1239,13 @@ generate #( ) look_ahead_routing_fromL_u ( + `ifdef INSERT_PIPELINE_REG_BETWEEN_SA + .vc_ctrl_head_vld_i (sa_local_vld_q [4+i] ), + .vc_ctrl_head_i (vc_ctrl_head_sa_local_sel_q[4+i] ), + `else .vc_ctrl_head_vld_i (sa_local_vld [4+i] ), .vc_ctrl_head_i (vc_ctrl_head_sa_local_sel[4+i] ), + `endif .node_id_x_ths_hop_i (node_id_x_ths_hop_i ), .node_id_y_ths_hop_i (node_id_y_ths_hop_i ), @@ -1413,6 +1642,104 @@ input_to_output_u .consume_vc_credit_vc_id_o (consume_vc_credit_vc_id ) ); +// =================== +// SA Local to SA Global stage reg +// =================== + +`ifdef INSERT_PIPELINE_REG_BETWEEN_SA +generate + for(i = 0; i < INPUT_PORT_NUM; i++) begin: gen_sa_local_to_sa_global_reg + + assign sa_global_stall [i] = sa_local_vld_q[i] & ~inport_read_enable_sa_stage[i]; + assign sa_local_vld_ena[i] = ~sa_global_stall[i]; + assign sa_local_ena [i] = sa_local_vld[i] & ~sa_global_stall[i]; + + std_dffre + #(.WIDTH(1)) + U_STA_SA_LOCAL_VLD + ( + .clk(clk), + .rstn(rstn), + .en(sa_local_vld_ena[i]), + .d (sa_local_vld [i]), + .q (sa_local_vld_q [i]) + ); + + std_dffre + #(.WIDTH(OUTPUT_PORT_NUMBER)) + U_STA_SA_LOCAL_VLD_TO_GLOBAL + ( + .clk(clk), + .rstn(rstn), + .en(sa_local_vld_ena [i]), + .d (sa_local_vld_to_sa_global [i]), + .q (sa_local_vld_to_sa_global_q [i]) + ); + + std_dffre + #(.WIDTH(VC_ID_NUM_MAX_W)) + U_DAT_SA_LOCAL_VC_ID + ( + .clk(clk), + .rstn(rstn), + .en(sa_local_ena [i]), + .d (sa_local_vc_id [i]), + .q (sa_local_vc_id_q [i]) + ); + + std_dffre + #(.WIDTH(VC_ID_NUM_MAX)) + U_DAT_SA_LOCAL_VC_ID_OH + ( + .clk(clk), + .rstn(rstn), + .en(sa_local_ena [i]), + .d (sa_local_vc_id_oh [i]), + .q (sa_local_vc_id_oh_q [i]) + ); + + `ifdef USE_QOS_VALUE + std_dffre + #(.WIDTH(QoS_Value_Width)) + U_DAT_SA_LOCAL_QOS_VALUE + ( + .clk(clk), + .rstn(rstn), + .en(sa_local_ena [i]), + .d (sa_local_qos_value [i]), + .q (sa_local_qos_value_q [i]) + ); + `endif + + `ifdef VC_DATA_USE_DUAL_PORT_RAM + std_dffre + #(.WIDTH($bits(dpram_used_idx_t))) + U_DAT_SA_LOCAL_DPRAM_IDX + ( + .clk(clk), + .rstn(rstn), + .en(sa_local_ena [i]), + .d (sa_local_dpram_idx [i]), + .q (sa_local_dpram_idx_q [i]) + ); + `endif + + std_dffre + #(.WIDTH($bits(flit_dec_t))) + U_DAT_VC_CTRL_HEAD_SA_LOCAL_SEL + ( + .clk(clk), + .rstn(rstn), + .en(sa_local_ena [i]), + .d (vc_ctrl_head_sa_local_sel [i]), + .q (vc_ctrl_head_sa_local_sel_q [i]) + ); + + end +endgenerate + +`endif + // =================== // SA to ST stage reg // =================== diff --git a/tb/Makefile b/tb/Makefile index 6d6c54d..c099b37 100644 --- a/tb/Makefile +++ b/tb/Makefile @@ -36,5 +36,8 @@ run: run_regression: time ./simv +vcs+loopreport +dumpon=0 +self_finish=0 +wave: + Verdi-SX -ssf novas.fsdb + clean: rm -rf simv* csrc Verdi* novas* ucli.key \ No newline at end of file diff --git a/tb/flist_mesh.f b/tb/flist_mesh.f index 1c7e060..7088da4 100644 --- a/tb/flist_mesh.f +++ b/tb/flist_mesh.f @@ -1,6 +1,6 @@ +incdir+$PROJ_ROOT/rtl/include +incdir+$PROJ_ROOT/tb - +// $PROJ_ROOT/$L1D_ROOT/include/rvh_uncore_param_pkg.sv $PROJ_ROOT/rtl/include/rvh_noc_pkg.sv $PROJ_ROOT/tb/v_noc_pkg.sv diff --git a/tb/flist_mesh.syn.f b/tb/flist_mesh.syn.f index 234cc16..13307fb 100644 --- a/tb/flist_mesh.syn.f +++ b/tb/flist_mesh.syn.f @@ -1,12 +1,12 @@ -+incdir+$PROJ_ROOT/rtl/include -+incdir+$PROJ_ROOT/tb ++incdir+$PROJ_ROOT/rtl/rvh_noc/rtl/include ++incdir+$PROJ_ROOT/rtl/rvh_noc/tb -$PROJ_ROOT/rtl/include/rvh_noc_pkg.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/include/rvh_noc_pkg.sv -$PROJ_ROOT/rtl/model/cells/std_dffe.sv -$PROJ_ROOT/rtl/model/cells/std_dffr.sv -$PROJ_ROOT/rtl/model/cells/std_dffre.sv -$PROJ_ROOT/rtl/model/cells/std_dffrve.sv +$PROJ_ROOT/$L1D_ROOT/models/cells/std_dffe.sv +$PROJ_ROOT/$L1D_ROOT/models/cells/std_dffr.sv +$PROJ_ROOT/$L1D_ROOT/models/cells/std_dffre.sv +$PROJ_ROOT/$L1D_ROOT/models/cells/std_dffrve.sv $PROJ_ROOT/rtl/util/usage_manager.sv $PROJ_ROOT/rtl/util/mp_fifo.sv @@ -26,22 +26,22 @@ $PROJ_ROOT/rtl/util/commoncell/src/Basic/hw/MuxOH.v $PROJ_ROOT/rtl/util/commoncell/src/Queue/hw/AgeMatrixSelector.v // TODO: need to change to compiled dpsram -$PROJ_ROOT/rtl/rtl/model/simple_dual_one_clock.v +$PROJ_ROOT/rtl/rvh_noc/rtl/model/simple_dual_one_clock.v -$PROJ_ROOT/rtl/input_port.sv -$PROJ_ROOT/rtl/look_adead_routing.sv -$PROJ_ROOT/rtl/output_port_vc_selection.sv -$PROJ_ROOT/rtl/input_port_vc.sv -$PROJ_ROOT/rtl/output_port_vc_assignment.sv -$PROJ_ROOT/rtl/priority_req_select.sv -$PROJ_ROOT/rtl/sa_global.sv -$PROJ_ROOT/rtl/switch.sv -$PROJ_ROOT/rtl/input_port_flit_decoder.sv -$PROJ_ROOT/rtl/input_to_output.sv -$PROJ_ROOT/rtl/output_port_vc_credit_counter.sv -$PROJ_ROOT/rtl/sa_local.sv -$PROJ_ROOT/rtl/performance_monitor.sv -$PROJ_ROOT/rtl/vnet_router.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/input_port.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/look_adead_routing.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/output_port_vc_selection.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/input_port_vc.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/output_port_vc_assignment.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/priority_req_select.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/sa_global.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/switch.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/input_port_flit_decoder.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/input_to_output.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/output_port_vc_credit_counter.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/sa_local.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/performance_monitor.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/vnet_router.sv -$PROJ_ROOT/tb/top_mesh_syn.sv -// $PROJ_ROOT/tb/testbench.sv +$PROJ_ROOT/rtl/rvh_noc/tb/top_mesh_syn.sv +// $PROJ_ROOT/rtl/rvh_noc/tb/testbench.sv diff --git a/tb/flist_mesh_3x3.f b/tb/flist_mesh_3x3.f new file mode 100644 index 0000000..ae9906d --- /dev/null +++ b/tb/flist_mesh_3x3.f @@ -0,0 +1,33 @@ ++incdir+$PROJ_ROOT/rtl/rvh_noc/rtl/include ++incdir+$PROJ_ROOT/rtl/rvh_noc/tb + +// $PROJ_ROOT/rtl/rvh_noc/rtl/include/rvh_noc_pkg.sv +// $PROJ_ROOT/rtl/rvh_noc/tb/v_noc_pkg.sv + + + +// TODO: need to change to compiled dpsram +$PROJ_ROOT/rtl/rvh_noc/rtl/model/simple_dual_one_clock.v + +$PROJ_ROOT/rtl/rvh_noc/rtl/input_port.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/look_adead_routing.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/output_port_vc_selection.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/input_port_vc.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/output_port_vc_assignment.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/priority_req_select.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/sa_global.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/switch.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/input_port_flit_decoder.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/input_to_output.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/output_port_vc_credit_counter.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/sa_local.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/performance_monitor.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/vnet_router.sv + + +$PROJ_ROOT/rtl/rvh_noc/rtl/local_port_look_adead_routing.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/local_port_couple_module.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/hn_router_sam.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/rn_router_sam.sv +$PROJ_ROOT/tb/ruby_testbench/rn_tile.sv +$PROJ_ROOT/tb/ruby_testbench/hn_tile.sv \ No newline at end of file diff --git a/tb/flist_single_router.f b/tb/flist_single_router.f index 2eb9152..48eeb6a 100644 --- a/tb/flist_single_router.f +++ b/tb/flist_single_router.f @@ -1,12 +1,12 @@ -+incdir+$PROJ_ROOT/rtl/include -+incdir+$PROJ_ROOT/tb ++incdir+$PROJ_ROOT/rtl/rvh_noc/rtl/include ++incdir+$PROJ_ROOT/rtl/rvh_noc/tb -$PROJ_ROOT/rtl/include/rvh_noc_pkg.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/include/rvh_noc_pkg.sv -$PROJ_ROOT/rtl/model/cells/std_dffe.sv -$PROJ_ROOT/rtl/model/cells/std_dffr.sv -$PROJ_ROOT/rtl/model/cells/std_dffre.sv -$PROJ_ROOT/rtl/model/cells/std_dffrve.sv +$PROJ_ROOT/$L1D_ROOT/models/cells/std_dffe.sv +$PROJ_ROOT/$L1D_ROOT/models/cells/std_dffr.sv +$PROJ_ROOT/$L1D_ROOT/models/cells/std_dffre.sv +$PROJ_ROOT/$L1D_ROOT/models/cells/std_dffrve.sv $PROJ_ROOT/rtl/util/usage_manager.sv $PROJ_ROOT/rtl/util/mp_fifo.sv @@ -26,34 +26,34 @@ $PROJ_ROOT/rtl/util/commoncell/src/Basic/hw/MuxOH.v $PROJ_ROOT/rtl/util/commoncell/src/Queue/hw/AgeMatrixSelector.v // TODO: need to change to compiled dpsram -$PROJ_ROOT/rtl/rtl/model/simple_dual_one_clock.v +$PROJ_ROOT/rtl/rvh_noc/rtl/model/simple_dual_one_clock.v -$PROJ_ROOT/rtl/input_port.sv -$PROJ_ROOT/rtl/look_adead_routing.sv -$PROJ_ROOT/rtl/output_port_vc_selection.sv -$PROJ_ROOT/rtl/input_port_vc.sv -$PROJ_ROOT/rtl/output_port_vc_assignment.sv -$PROJ_ROOT/rtl/priority_req_select.sv -$PROJ_ROOT/rtl/sa_global.sv -$PROJ_ROOT/rtl/switch.sv -$PROJ_ROOT/rtl/input_port_flit_decoder.sv -$PROJ_ROOT/rtl/input_to_output.sv -$PROJ_ROOT/rtl/output_port_vc_credit_counter.sv -$PROJ_ROOT/rtl/sa_local.sv -$PROJ_ROOT/rtl/performance_monitor.sv -$PROJ_ROOT/rtl/vnet_router.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/input_port.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/look_adead_routing.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/output_port_vc_selection.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/input_port_vc.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/output_port_vc_assignment.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/priority_req_select.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/sa_global.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/switch.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/input_port_flit_decoder.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/input_to_output.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/output_port_vc_credit_counter.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/sa_local.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/performance_monitor.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/vnet_router.sv -$PROJ_ROOT/tb/v_noc_pkg.sv +$PROJ_ROOT/rtl/rvh_noc/tb/v_noc_pkg.sv $PROJ_ROOT/rtl/rvh_l1d/ruby/ut_lib.sv -$PROJ_ROOT/rtl/local_port_look_adead_routing.sv -$PROJ_ROOT/rtl/local_port_couple_module.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/local_port_look_adead_routing.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/local_port_couple_module.sv -$PROJ_ROOT/tb/v_receiver.sv -$PROJ_ROOT/tb/v_scoreboard.sv -$PROJ_ROOT/tb/v_sender.sv -$PROJ_ROOT/tb/v_test_generator.sv +$PROJ_ROOT/rtl/rvh_noc/tb/v_receiver.sv +$PROJ_ROOT/rtl/rvh_noc/tb/v_scoreboard.sv +$PROJ_ROOT/rtl/rvh_noc/tb/v_sender.sv +$PROJ_ROOT/rtl/rvh_noc/tb/v_test_generator.sv -$PROJ_ROOT/tb/tb_single_router.sv -// $PROJ_ROOT/tb/testbench.sv +$PROJ_ROOT/rtl/rvh_noc/tb/tb_single_router.sv +// $PROJ_ROOT/rtl/rvh_noc/tb/testbench.sv diff --git a/tb/flist_single_router.syn.f b/tb/flist_single_router.syn.f index 17b3914..3c96db1 100644 --- a/tb/flist_single_router.syn.f +++ b/tb/flist_single_router.syn.f @@ -1,12 +1,12 @@ -+incdir+$PROJ_ROOT/rtl/include -+incdir+$PROJ_ROOT/tb ++incdir+$PROJ_ROOT/rtl/rvh_noc/rtl/include ++incdir+$PROJ_ROOT/rtl/rvh_noc/tb -$PROJ_ROOT/rtl/include/rvh_noc_pkg.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/include/rvh_noc_pkg.sv -$PROJ_ROOT/rtl/model/cells/std_dffe.sv -$PROJ_ROOT/rtl/model/cells/std_dffr.sv -$PROJ_ROOT/rtl/model/cells/std_dffre.sv -$PROJ_ROOT/rtl/model/cells/std_dffrve.sv +$PROJ_ROOT/$L1D_ROOT/models/cells/std_dffe.sv +$PROJ_ROOT/$L1D_ROOT/models/cells/std_dffr.sv +$PROJ_ROOT/$L1D_ROOT/models/cells/std_dffre.sv +$PROJ_ROOT/$L1D_ROOT/models/cells/std_dffrve.sv $PROJ_ROOT/rtl/util/usage_manager.sv $PROJ_ROOT/rtl/util/mp_fifo.sv @@ -26,22 +26,22 @@ $PROJ_ROOT/rtl/util/commoncell/src/Basic/hw/MuxOH.v $PROJ_ROOT/rtl/util/commoncell/src/Queue/hw/AgeMatrixSelector.v // TODO: need to change to compiled dpsram -$PROJ_ROOT/rtl/rtl/model/simple_dual_one_clock.v +$PROJ_ROOT/rtl/rvh_noc/rtl/model/simple_dual_one_clock.v -$PROJ_ROOT/rtl/input_port.sv -$PROJ_ROOT/rtl/look_adead_routing.sv -$PROJ_ROOT/rtl/output_port_vc_selection.sv -$PROJ_ROOT/rtl/input_port_vc.sv -$PROJ_ROOT/rtl/output_port_vc_assignment.sv -$PROJ_ROOT/rtl/priority_req_select.sv -$PROJ_ROOT/rtl/sa_global.sv -$PROJ_ROOT/rtl/switch.sv -$PROJ_ROOT/rtl/input_port_flit_decoder.sv -$PROJ_ROOT/rtl/input_to_output.sv -$PROJ_ROOT/rtl/output_port_vc_credit_counter.sv -$PROJ_ROOT/rtl/sa_local.sv -$PROJ_ROOT/rtl/performance_monitor.sv -$PROJ_ROOT/rtl/vnet_router.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/input_port.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/look_adead_routing.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/output_port_vc_selection.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/input_port_vc.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/output_port_vc_assignment.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/priority_req_select.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/sa_global.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/switch.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/input_port_flit_decoder.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/input_to_output.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/output_port_vc_credit_counter.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/sa_local.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/performance_monitor.sv +$PROJ_ROOT/rtl/rvh_noc/rtl/vnet_router.sv -$PROJ_ROOT/tb/top_single_router_syn.sv -// $PROJ_ROOT/tb/testbench.sv +$PROJ_ROOT/rtl/rvh_noc/tb/top_single_router_syn.sv +// $PROJ_ROOT/rtl/rvh_noc/tb/testbench.sv diff --git a/tb/noc_top.sv b/tb/noc_top.sv new file mode 100644 index 0000000..843f5a5 --- /dev/null +++ b/tb/noc_top.sv @@ -0,0 +1,324 @@ +module noc_top +import rvh_noc_pkg::*; +#( + // mesh parameters + parameter NODE_NUM_X_DIMESION = 3, + parameter NODE_NUM_Y_DIMESION = 3, + + // router parameters + parameter INPUT_PORT_NUM = INPUT_PORT_NUMBER, + parameter OUTPUT_PORT_NUM = OUTPUT_PORT_NUMBER, + parameter LOCAL_PORT_NUM = INPUT_PORT_NUM-4, + parameter type flit_payload_t = logic[FLIT_LENGTH-1:0], + parameter VC_NUM_INPUT_N = 1+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT, + parameter VC_NUM_INPUT_S = 1+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT, + parameter VC_NUM_INPUT_E = 3+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT, + parameter VC_NUM_INPUT_W = 3+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT, +`ifdef ALLOW_SAME_ROUTER_L2L_TRANSFER + parameter VC_NUM_INPUT_L = 4+LOCAL_PORT_NUM-1+QOS_VC_NUM_PER_INPUT, +`else + parameter VC_NUM_INPUT_L = 4+QOS_VC_NUM_PER_INPUT, +`endif + parameter SA_GLOBAL_INPUT_NUM_N = 3+LOCAL_PORT_NUM, + parameter SA_GLOBAL_INPUT_NUM_S = 3+LOCAL_PORT_NUM, + parameter SA_GLOBAL_INPUT_NUM_E = 1+LOCAL_PORT_NUM, + parameter SA_GLOBAL_INPUT_NUM_W = 1+LOCAL_PORT_NUM, +`ifdef ALLOW_SAME_ROUTER_L2L_TRANSFER + parameter SA_GLOBAL_INPUT_NUM_L = 4+LOCAL_PORT_NUM-1, +`else + parameter SA_GLOBAL_INPUT_NUM_L = 4, +`endif + parameter VC_NUM_OUTPUT_N = 1+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT, + parameter VC_NUM_OUTPUT_S = 1+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT, + parameter VC_NUM_OUTPUT_E = 3+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT, + parameter VC_NUM_OUTPUT_W = 3+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT, + parameter VC_NUM_OUTPUT_L = 1, + parameter VC_DEPTH_INPUT_N = VC_DEPTH_MAX, + parameter VC_DEPTH_INPUT_S = VC_DEPTH_MAX, + parameter VC_DEPTH_INPUT_E = VC_DEPTH_MAX, + parameter VC_DEPTH_INPUT_W = VC_DEPTH_MAX, + parameter VC_DEPTH_INPUT_L = VC_DEPTH_MAX +) +( + output logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][LOCAL_PORT_NUM-1:0] tx_flit_pend_o, + output logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][LOCAL_PORT_NUM-1:0] tx_flit_v_o, + output flit_payload_t [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][LOCAL_PORT_NUM-1:0] tx_flit_o, + output logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][LOCAL_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] tx_flit_vc_id_o, + output io_port_t [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][LOCAL_PORT_NUM-1:0] tx_flit_look_ahead_routing_o, + + input logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][LOCAL_PORT_NUM-1:0] rx_flit_pend_i, + input logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][LOCAL_PORT_NUM-1:0] rx_flit_v_i, + input flit_payload_t [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][LOCAL_PORT_NUM-1:0] rx_flit_i, + input logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][LOCAL_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] rx_flit_vc_id_i, + input io_port_t [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][LOCAL_PORT_NUM-1:0] rx_flit_look_ahead_routing_i, + + input logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][LOCAL_PORT_NUM-1:0] tx_lcrd_v_i, + input logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][LOCAL_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] tx_lcrd_id_i, + + output logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][LOCAL_PORT_NUM-1:0] rx_lcrd_v_o, + output logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][LOCAL_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] rx_lcrd_id_o, + + input logic clk, + input logic rst + +); + + genvar i, j, k; + + // Ports + logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][OUTPUT_PORT_NUM-1:0] tx_flit_pend; + logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][OUTPUT_PORT_NUM-1:0] tx_flit_v; + flit_payload_t [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][OUTPUT_PORT_NUM-1:0] tx_flit; + logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][OUTPUT_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] tx_flit_vc_id; + io_port_t [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][OUTPUT_PORT_NUM-1:0] tx_flit_look_ahead_routing; + + logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][OUTPUT_PORT_NUM-1:0] rx_flit_pend; + logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][OUTPUT_PORT_NUM-1:0] rx_flit_v; + flit_payload_t [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][OUTPUT_PORT_NUM-1:0] rx_flit; + logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][OUTPUT_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] rx_flit_vc_id; + io_port_t [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][OUTPUT_PORT_NUM-1:0] rx_flit_look_ahead_routing; + + logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][INPUT_PORT_NUM-1:0] tx_lcrd_v; + logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][INPUT_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] tx_lcrd_id; + + logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][INPUT_PORT_NUM-1:0] rx_lcrd_v; + logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][INPUT_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] rx_lcrd_id; + + + logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][NodeID_X_Width-1:0] node_id_x; + logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][CHANNEL_NUM-1:0][NodeID_Y_Width-1:0] node_id_y; + + + + + // generate mesh routers + generate + for(i = 0; i < NODE_NUM_X_DIMESION; i++) begin: gen_mesh_routers_x_dimesion + for(j = 0; j < NODE_NUM_Y_DIMESION; j++) begin: gen_mesh_routers_y_dimesion + for(z = 0; z < CHANNEL_NUM; z++) begin: gen_channel + vnet_router + #( + .INPUT_PORT_NUM(INPUT_PORT_NUM ), + .OUTPUT_PORT_NUM(OUTPUT_PORT_NUM ), + .flit_payload_t(flit_payload_t), + .QOS_VC_NUM_PER_INPUT(QOS_VC_NUM_PER_INPUT), + .VC_NUM_INPUT_N(VC_NUM_INPUT_N ), + .VC_NUM_INPUT_S(VC_NUM_INPUT_S ), + .VC_NUM_INPUT_E(VC_NUM_INPUT_E ), + .VC_NUM_INPUT_W(VC_NUM_INPUT_W ), + .VC_NUM_INPUT_L(VC_NUM_INPUT_L ), + .SA_GLOBAL_INPUT_NUM_N(SA_GLOBAL_INPUT_NUM_N ), + .SA_GLOBAL_INPUT_NUM_S(SA_GLOBAL_INPUT_NUM_S ), + .SA_GLOBAL_INPUT_NUM_E(SA_GLOBAL_INPUT_NUM_E ), + .SA_GLOBAL_INPUT_NUM_W(SA_GLOBAL_INPUT_NUM_W ), + .SA_GLOBAL_INPUT_NUM_L(SA_GLOBAL_INPUT_NUM_L ), + .VC_NUM_OUTPUT_N(VC_NUM_OUTPUT_N ), + .VC_NUM_OUTPUT_S(VC_NUM_OUTPUT_S ), + .VC_NUM_OUTPUT_E(VC_NUM_OUTPUT_E ), + .VC_NUM_OUTPUT_W(VC_NUM_OUTPUT_W ), + .VC_NUM_OUTPUT_L(VC_NUM_OUTPUT_L ), + .VC_DEPTH_INPUT_N(VC_DEPTH_INPUT_N ), + .VC_DEPTH_INPUT_S(VC_DEPTH_INPUT_S ), + .VC_DEPTH_INPUT_E(VC_DEPTH_INPUT_E ), + .VC_DEPTH_INPUT_W(VC_DEPTH_INPUT_W ), + .VC_DEPTH_INPUT_L(VC_DEPTH_INPUT_L ) + ) + vnet_router_dut ( + .rx_flit_pend_i (rx_flit_pend [i][j][z] ), + .rx_flit_v_i (rx_flit_v [i][j][z] ), + .rx_flit_i (rx_flit [i][j][z] ), + .rx_flit_vc_id_i (rx_flit_vc_id [i][j][z] ), + .rx_flit_look_ahead_routing_i (rx_flit_look_ahead_routing [i][j][z] ), + + .tx_flit_pend_o (tx_flit_pend [i][j][z] ), + .tx_flit_v_o (tx_flit_v [i][j][z] ), + .tx_flit_o (tx_flit [i][j][z] ), + .tx_flit_vc_id_o (tx_flit_vc_id [i][j][z] ), + .tx_flit_look_ahead_routing_o (tx_flit_look_ahead_routing [i][j][z] ), + + .rx_lcrd_v_o (rx_lcrd_v [i][j][z] ), + .rx_lcrd_id_o (rx_lcrd_id [i][j][z] ), + + .tx_lcrd_v_i (tx_lcrd_v [i][j][z] ), + .tx_lcrd_id_i (tx_lcrd_id [i][j][z] ), + + .node_id_x_ths_hop_i (node_id_x [i][j][z] ), + .node_id_y_ths_hop_i (node_id_y [i][j][z] ), + + .clk (clk ), + .rstn (rst) + ); + end + end + end + endgenerate + + // assign node id to each router + generate + for(i = 0; i < NODE_NUM_X_DIMESION; i++) begin: gen_node_id_x_x_dimesion + for(j = 0; j < NODE_NUM_Y_DIMESION; j++) begin: gen_node_id_x_y_dimesion + for(z = 0; z < CHANNEL_NUM; z++) begin: gen_channel + assign node_id_x [i][j][z] = i; + end + end + end + for(i = 0; i < NODE_NUM_Y_DIMESION; i++) begin: gen_node_id_y_y_dimesion + for(j = 0; j < NODE_NUM_X_DIMESION; j++) begin: gen_node_id_y_x_dimesion + for(z = 0; z < CHANNEL_NUM; z++) begin: gen_channel + assign node_id_y [j][i][z] = i; + end + end + end + endgenerate + + // connect each router together + generate + for(i = 0; i < NODE_NUM_X_DIMESION; i++) begin: gen_connect_routers_ns_x_dimesion + for(j = 0; j < NODE_NUM_Y_DIMESION-1; j++) begin: gen_connect_routers_ns_y_dimesion + for(z = 0; z < CHANNEL_NUM; z++) begin: gen_channel + // connect N inport to S outport + assign rx_flit_pend [i][j][z][0] = tx_flit_pend [i][j+1][z][1]; + assign rx_flit_v [i][j][z][0] = tx_flit_v [i][j+1][z][1]; + assign rx_flit [i][j][z][0] = tx_flit [i][j+1][z][1]; + assign rx_flit_vc_id [i][j][z][0] = tx_flit_vc_id [i][j+1][z][1]; + assign rx_flit_look_ahead_routing [i][j][z][0] = tx_flit_look_ahead_routing [i][j+1][z][1]; + + assign tx_lcrd_v [i][j][z][0] = rx_lcrd_v [i][j+1][z][1]; + assign tx_lcrd_id [i][j][z][0] = rx_lcrd_id [i][j+1][z][1]; + + // connect S inport to N outport + assign rx_flit_pend [i][j+1][z][1] = tx_flit_pend [i][j][z][0]; + assign rx_flit_v [i][j+1][z][1] = tx_flit_v [i][j][z][0]; + assign rx_flit [i][j+1][z][1] = tx_flit [i][j][z][0]; + assign rx_flit_vc_id [i][j+1][z][1] = tx_flit_vc_id [i][j][z][0]; + assign rx_flit_look_ahead_routing [i][j+1][z][1] = tx_flit_look_ahead_routing [i][j][z][0]; + + assign tx_lcrd_v [i][j+1][z][1] = rx_lcrd_v [i][j][z][0]; + assign tx_lcrd_id [i][j+1][z][1] = rx_lcrd_id [i][j][z][0]; + end + end + end + endgenerate + + generate + for(i = 0; i < NODE_NUM_Y_DIMESION; i++) begin: gen_connect_routers_ew_x_dimesion + for(j = 0; j < NODE_NUM_X_DIMESION-1; j++) begin: gen_connect_routers_ew_y_dimesion + for(z = 0; z < CHANNEL_NUM; z++) begin: gen_channel + // connect E inport to W outport + assign rx_flit_pend [j][i][z][2] = tx_flit_pend [j+1][i][z][3]; + assign rx_flit_v [j][i][z][2] = tx_flit_v [j+1][i][z][3]; + assign rx_flit [j][i][z][2] = tx_flit [j+1][i][z][3]; + assign rx_flit_vc_id [j][i][z][2] = tx_flit_vc_id [j+1][i][z][3]; + assign rx_flit_look_ahead_routing [j][i][z][2] = tx_flit_look_ahead_routing [j+1][i][z][3]; + + assign tx_lcrd_v [j][i][z][2] = rx_lcrd_v [j+1][i][z][3]; + assign tx_lcrd_id [j][i][z][2] = rx_lcrd_id [j+1][i][z][3]; + + // connect W inport to E outport + assign rx_flit_pend [j+1][i][z][3] = tx_flit_pend [j][i][z][2]; + assign rx_flit_v [j+1][i][z][3] = tx_flit_v [j][i][z][2]; + assign rx_flit [j+1][i][z][3] = tx_flit [j][i][z][2]; + assign rx_flit_vc_id [j+1][i][z][3] = tx_flit_vc_id [j][i][z][2]; + assign rx_flit_look_ahead_routing [j+1][i][z][3] = tx_flit_look_ahead_routing [j][i][z][2]; + + assign tx_lcrd_v [j+1][i][z][3] = rx_lcrd_v [j][i][z][2]; + assign tx_lcrd_id [j+1][i][z][3] = rx_lcrd_id [j][i][z][2]; + end + end + end + endgenerate + + // other unused non-local ports, assign router rx to 0 + generate + for(i = 0; i < NODE_NUM_X_DIMESION; i++) begin: gen_unused_non_local_ports_x_dimesion + for(z = 0; z < CHANNEL_NUM; z++) begin: gen_channel + assign rx_flit_pend [i][NODE_NUM_Y_DIMESION-1][z][0] = '0; + assign rx_flit_v [i][NODE_NUM_Y_DIMESION-1][z][0] = '0; + assign rx_flit [i][NODE_NUM_Y_DIMESION-1][z][0] = '0; + assign rx_flit_vc_id [i][NODE_NUM_Y_DIMESION-1][z][0] = '0; + assign rx_flit_look_ahead_routing [i][NODE_NUM_Y_DIMESION-1][z][0] = '0; + + assign tx_lcrd_v [i][NODE_NUM_Y_DIMESION-1][z][0] = '0; + assign tx_lcrd_id [i][NODE_NUM_Y_DIMESION-1][z][0] = '0; + + + assign rx_flit_pend [i][0][z][1] = '0; + assign rx_flit_v [i][0][z][1] = '0; + assign rx_flit [i][0][z][1] = '0; + assign rx_flit_vc_id [i][0][z][1] = '0; + assign rx_flit_look_ahead_routing [i][0][z][1] = '0; + + assign tx_lcrd_v [i][0][z][1] = '0; + assign tx_lcrd_id [i][0][z][1] = '0; + end + end + + for(i = 0; i < NODE_NUM_Y_DIMESION; i++) begin: gen_unused_non_local_ports_y_dimesion + for(z = 0; z < CHANNEL_NUM; z++) begin: gen_channel + // connect E inport to W outport + assign rx_flit_pend [NODE_NUM_X_DIMESION-1][i][z][2] = '0; + assign rx_flit_v [NODE_NUM_X_DIMESION-1][i][z][2] = '0; + assign rx_flit [NODE_NUM_X_DIMESION-1][i][z][2] = '0; + assign rx_flit_vc_id [NODE_NUM_X_DIMESION-1][i][z][2] = '0; + assign rx_flit_look_ahead_routing [NODE_NUM_X_DIMESION-1][i][z][2] = '0; + + assign tx_lcrd_v [NODE_NUM_X_DIMESION-1][i][z][2] = '0; + assign tx_lcrd_id [NODE_NUM_X_DIMESION-1][i][z][2] = '0; + + // connect W inport to E outport + assign rx_flit_pend [0][i][z][3] = '0; + assign rx_flit_v [0][i][z][3] = '0; + assign rx_flit [0][i][z][3] = '0; + assign rx_flit_vc_id [0][i][z][3] = '0; + assign rx_flit_look_ahead_routing [0][i][z][3] = '0; + + assign tx_lcrd_v [0][i][z][3] = '0; + assign tx_lcrd_id [0][i][z][3] = '0; + end + end + endgenerate + + + + generate + for(i = 0; i < NODE_NUM_X_DIMESION; i++) begin: gen_v_sender_x_dimesion + for(j = 0; j < NODE_NUM_Y_DIMESION; j++) begin: gen_v_sender_y_dimesion + for(k = 0; k < LOCAL_PORT_NUM; k++) begin: gen_v_sender_device_port + for(z = 0; z < CHANNEL_NUM; z++) begin: gen_channel + assign rx_flit_pend [i][j][z][4+k] = rx_flit_pend_i [i][j][z][k]; + assign rx_flit_v [i][j][z][4+k] = rx_flit_v_i [i][j][z][k]; + assign rx_flit [i][j][z][4+k] = rx_flit_i [i][j][z][k]; + assign rx_flit_vc_id [i][j][z][4+k] = rx_flit_vc_id_i [i][j][z][k]; + assign rx_flit_look_ahead_routing [i][j][z][4+k] = rx_flit_look_ahead_routing_i [i][j][z][k]; + + assign rx_lcrd_v_o [i][j][z][k] = rx_lcrd_v [i][j][z][4+k]; + assign rx_lcrd_id_o [i][j][z][k] = rx_lcrd_id [i][j][z][4+k]; + end + end + end + end + endgenerate + + + generate + for(i = 0; i < NODE_NUM_X_DIMESION; i++) begin: gen_v_receiver_x_dimesion + for(j = 0; j < NODE_NUM_Y_DIMESION; j++) begin: gen_v_receiver_y_dimesion + for(k = 0; k < LOCAL_PORT_NUM; k++) begin: gen_v_sender_device_port + for(z = 0; z < CHANNEL_NUM; z++) begin: gen_channel + assign tx_flit_pend_o [i][j][z][k] = tx_flit_pend [i][j][z][4+k]; + assign tx_flit_v_o [i][j][z][k] = tx_flit_v [i][j][z][4+k]; + assign tx_flit_o [i][j][z][k] = tx_flit [i][j][z][4+k]; + assign tx_flit_vc_id_o [i][j][z][k] = tx_flit_vc_id [i][j][z][4+k]; + assign tx_flit_look_ahead_routing_o [i][j][z][k] = tx_flit_look_ahead_routing [i][j][z][4+k]; + + assign tx_lcrd_v [i][j][z][4+k] = tx_lcrd_v_i [i][j][z][k]; + assign tx_lcrd_id [i][j][z][4+k] = tx_lcrd_id_i [i][j][z][k]; + end + end + end + end + endgenerate + + + +endmodule diff --git a/tb/tb_mesh.sv b/tb/tb_mesh.sv index 077e30d..9b9ae7a 100644 --- a/tb/tb_mesh.sv +++ b/tb/tb_mesh.sv @@ -1,6 +1,9 @@ module tb_mesh import rvh_noc_pkg::*; import v_noc_pkg::*; +`ifdef EBI +import test_ebi_pkg::*; +`endif #( // mesh parameters parameter NODE_NUM_X_DIMESION = 3, @@ -10,7 +13,7 @@ import v_noc_pkg::*; parameter INPUT_PORT_NUM = INPUT_PORT_NUMBER, parameter OUTPUT_PORT_NUM = OUTPUT_PORT_NUMBER, parameter LOCAL_PORT_NUM = INPUT_PORT_NUM-4, - parameter type flit_payload_t = logic[FLIT_LENGTH-1:0], + parameter type flit_payload_t = cache_scu_cc_test_t, // parameter QOS_VC_NUM_PER_INPUT = QOS_VC_NUM_PER_INPUT, @@ -56,9 +59,17 @@ import v_noc_pkg::*; // test_generator parameters - parameter TEST_CASE_MESH_RANDOM = 1, // random sender and receiver - parameter TEST_CASE_MESH_DIAGONAL = !TEST_CASE_MESH_RANDOM, // from (0,0) to (NODE_NUM_X_DIMESION-1, NODE_NUM_Y_DIMESION-1) - + parameter TEST_CASE_MESH_RANDOM = 1, // random sender and receiver + parameter TEST_CASE_MESH_DIAGONAL = 0, // from (0,0) to (NODE_NUM_X_DIMESION-1, NODE_NUM_Y_DIMESION-1) + parameter TEST_CASE_MESH_BIT_COMPLEMENT = 0, + parameter TEST_CASE_MESH_BIT_REVERSE = 0, + parameter TEST_CASE_MESH_BIT_ROTATION = 0, + parameter TEST_CASE_MESH_NEIGHBOR = 0, + parameter TEST_CASE_MESH_SHUFFLE = 0, + parameter TEST_CASE_MESH_TRANSPOSE = 0, + parameter TEST_CASE_MESH_TORNADO = 0, + + parameter RANDOM_BIT_NUM = 168, // 32,64,80,128,168 parameter SCOREBOARD_TIMEOUT_EN = !TEST_CASE_MESH_DIAGONAL, @@ -116,6 +127,17 @@ import v_noc_pkg::*; logic clk; logic rstn; +`ifdef EBI +logic bus_clk; +logic [NODE_NUM_X_DIMESION-2:0][NODE_NUM_Y_DIMESION-1:0][OFF_DIE_WD-1:0] x_inc_bus; +logic [NODE_NUM_X_DIMESION-2:0][NODE_NUM_Y_DIMESION-1:0][OFF_DIE_WD-1:0] x_dec_bus; +logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-2:0][OFF_DIE_WD-1:0] y_inc_bus; +logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-2:0][OFF_DIE_WD-1:0] y_dec_bus; +logic [NODE_NUM_X_DIMESION-2:0][NODE_NUM_Y_DIMESION-1:0] x_inc_credit; +logic [NODE_NUM_X_DIMESION-2:0][NODE_NUM_Y_DIMESION-1:0] x_dec_credit; +logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-2:0] y_inc_credit; +logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-2:0] y_dec_credit; +`endif // generate mesh routers @@ -191,7 +213,7 @@ import v_noc_pkg::*; end end endgenerate - +`ifndef EBI // connect each router together generate for(i = 0; i < NODE_NUM_X_DIMESION; i++) begin: gen_connect_routers_ns_x_dimesion @@ -245,6 +267,203 @@ import v_noc_pkg::*; end endgenerate +`else +genvar z; + +generate + for(i = 0; i < NODE_NUM_X_DIMESION-1; i++) begin: gen_x_dimension_router + for(j = 0; j < NODE_NUM_Y_DIMESION; j++) begin + test_ebi ebi_X_u1( + .m1_clk(clk), + .bus_clk(bus_clk), + .rst(~rstn), + // control signals + .tx_flit_pend_i(tx_flit_pend[i][j][2]), + .tx_flit_v_i(tx_flit_v[i][j][2]), + .tx_flit_vc_id_i(tx_flit_vc_id[i][j][2]), + .tx_flit_look_ahead_routing_i(tx_flit_look_ahead_routing[i][j][2]), + + .rx_flit_pend_o(rx_flit_pend[i][j][2]), + .rx_flit_v_o(rx_flit_v[i][j][2]), + .rx_flit_vc_id_o(rx_flit_vc_id[i][j][2]), + .rx_flit_look_ahead_routing_o(rx_flit_look_ahead_routing[i][j][2]), + + .tx_lcrd_v_o(tx_lcrd_v[i][j][2]), + .tx_lcrd_id_o(tx_lcrd_id[i][j][2]), + + .rx_lcrd_v_i(rx_lcrd_v[i][j][2]), + .rx_lcrd_id_i(rx_lcrd_id[i][j][2]), + + .tx_flit_channel_0_i(tx_flit[i][j][2]), // req + .rx_flit_channel_0_o(rx_flit[i][j][2]), // req + + //external interface + .m1_m2_bus_o(x_inc_bus[i][j]), + .m2_m1_credit_i(x_inc_credit[i][j]), + .m2_m1_bus_i(x_dec_bus[i][j]), + .m1_m2_credit_o(x_dec_credit[i][j]) + ); + test_ebi ebi_X_u2( + .m1_clk(clk), + .bus_clk(bus_clk), + .rst(~rstn), + // control signals + .tx_flit_pend_i(tx_flit_pend[i+1][j][3]), + .tx_flit_v_i(tx_flit_v[i+1][j][3]), + .tx_flit_vc_id_i(tx_flit_vc_id[i+1][j][3]), + .tx_flit_look_ahead_routing_i(tx_flit_look_ahead_routing[i+1][j][3]), + + .rx_flit_pend_o(rx_flit_pend[i+1][j][3]), + .rx_flit_v_o(rx_flit_v[i+1][j][3]), + .rx_flit_vc_id_o(rx_flit_vc_id[i+1][j][3]), + .rx_flit_look_ahead_routing_o(rx_flit_look_ahead_routing[i+1][j][3]), + + .tx_lcrd_v_o(tx_lcrd_v[i+1][j][3]), + .tx_lcrd_id_o(tx_lcrd_id[i+1][j][3]), + + .rx_lcrd_v_i(rx_lcrd_v[i+1][j][3]), + .rx_lcrd_id_i(rx_lcrd_id[i+1][j][3]), + + .tx_flit_channel_0_i(tx_flit[i+1][j][3]), // req + .rx_flit_channel_0_o(rx_flit[i+1][j][3]), // req + + //external interface + .m1_m2_bus_o(x_dec_bus[i][j]), + .m2_m1_credit_i(x_dec_credit[i][j]), + .m2_m1_bus_i(x_inc_bus[i][j]), + .m1_m2_credit_o(x_inc_credit[i][j]) + ); + end + end +endgenerate + +generate + for(i = 0; i < NODE_NUM_X_DIMESION; i++) begin: gen_y_dimension_router + for(j = 0; j < NODE_NUM_Y_DIMESION-1; j++) begin + test_ebi ebi_Y_u1( + .m1_clk(clk), + .bus_clk(bus_clk), + .rst(~rstn), + // control signals + .tx_flit_pend_i(tx_flit_pend[i][j][0]), + .tx_flit_v_i(tx_flit_v[i][j][0]), + .tx_flit_vc_id_i(tx_flit_vc_id[i][j][0]), + .tx_flit_look_ahead_routing_i(tx_flit_look_ahead_routing[i][j][0]), + + .rx_flit_pend_o(rx_flit_pend[i][j][0]), + .rx_flit_v_o(rx_flit_v[i][j][0]), + .rx_flit_vc_id_o(rx_flit_vc_id[i][j][0]), + .rx_flit_look_ahead_routing_o(rx_flit_look_ahead_routing[i][j][0]), + + .tx_lcrd_v_o(tx_lcrd_v[i][j][0]), + .tx_lcrd_id_o(tx_lcrd_id[i][j][0]), + + .rx_lcrd_v_i(rx_lcrd_v[i][j][0]), + .rx_lcrd_id_i(rx_lcrd_id[i][j][0]), + + .tx_flit_channel_0_i(tx_flit[i][j][0]), // req + .rx_flit_channel_0_o(rx_flit[i][j][0]), + + //external interface + .m1_m2_bus_o(y_inc_bus[i][j]), + .m2_m1_credit_i(y_inc_credit[i][j]), + .m2_m1_bus_i(y_dec_bus[i][j]), + .m1_m2_credit_o(y_dec_credit[i][j]) + ); + test_ebi ebi_Y_u2( + .m1_clk(clk), + .bus_clk(bus_clk), + .rst(~rstn), + // control signals + .tx_flit_pend_i(tx_flit_pend[i][j+1][1]), + .tx_flit_v_i(tx_flit_v[i][j+1][1]), + .tx_flit_vc_id_i(tx_flit_vc_id[i][j+1][1]), + .tx_flit_look_ahead_routing_i(tx_flit_look_ahead_routing[i][j+1][1]), + + .rx_flit_pend_o(rx_flit_pend[i][j+1][1]), + .rx_flit_v_o(rx_flit_v[i][j+1][1]), + .rx_flit_vc_id_o(rx_flit_vc_id[i][j+1][1]), + .rx_flit_look_ahead_routing_o(rx_flit_look_ahead_routing[i][j+1][1]), + + .tx_lcrd_v_o(tx_lcrd_v[i][j+1][1]), + .tx_lcrd_id_o(tx_lcrd_id[i][j+1][1]), + + .rx_lcrd_v_i(rx_lcrd_v[i][j+1][1]), + .rx_lcrd_id_i(rx_lcrd_id[i][j+1][1]), + + .tx_flit_channel_0_i(tx_flit[i][j+1][1]), // req + .rx_flit_channel_0_o(rx_flit[i][j+1][1]), + + //external interface + .m1_m2_bus_o(y_dec_bus[i][j]), + .m2_m1_credit_i(y_dec_credit[i][j]), + .m2_m1_bus_i(y_inc_bus[i][j]), + .m1_m2_credit_o(y_inc_credit[i][j]) + ); + end + end +endgenerate + + +//debug print +always_ff @(posedge clk) begin + for (int i = 0; i < NODE_NUM_X_DIMESION; i++) begin: ebi_debug_log_tx + for (int j = 0; j < NODE_NUM_Y_DIMESION; j++) begin + for (int z = 0; z < ROUTER_PORT_NUMBER; z++) begin + if(tx_flit_v[i][j][z]) begin + $write("[%16d] info flit: flit_sender router: (%0d, %0d); target router: ", $time(), i, j); + case (z) + 0: $write("(%0d, %0d)", i, j+1); + 1: $write("(%0d, %0d)", i, j-1); + 2: $write("(%0d, %0d)", i+1, j); + 3: $write("(%0d, %0d)", i-1, j); + 4: $write("local? wrong!"); + endcase + $write("vc_id: %1d; look_ahead_routing: %1d(N0,S1,E2,W3,L4-7), flit:", tx_flit_vc_id[i][j][z], tx_flit_look_ahead_routing[i][j][z], "%0h", tx_flit[i][j][z]); + $write(" \n"); + end + if(rx_flit_v[i][j][z]) begin + $write("[%16d] info flit: flit_receiver router: (%0d, %0d); source router: ", $time(), i, j); + case (z) + 0: $write("(%0d, %0d)", i, j+1); + 1: $write("(%0d, %0d)", i, j-1); + 2: $write("(%0d, %0d)", i+1, j); + 3: $write("(%0d, %0d)", i-1, j); + 4: $write("local? wrong!"); + endcase + $write("vc_id: %1d; look_ahead_routing: %1d(N0,S1,E2,W3,L4-7), flit:", rx_flit_vc_id[i][j][z], rx_flit_look_ahead_routing[i][j][z], "%0h", rx_flit[i][j][z]); + $write(" \n"); + end + if(tx_lcrd_v[i][j][z]) begin + $write("[%16d] info credit: crd_receiver router: (%0d, %0d); source router: ", $time(), i, j); + case (z) + 0: $write("(%0d, %0d)", i, j+1); + 1: $write("(%0d, %0d)", i, j-1); + 2: $write("(%0d, %0d)", i+1, j); + 3: $write("(%0d, %0d)", i-1, j); + 4: $write("local? wrong!"); + endcase + $write(" credit id:", tx_lcrd_id[i][j][z]); + $write(" \n"); + end + if(rx_lcrd_v[i][j][z]) begin + $write("[%16d] info credit: crd_sender router: (%0d, %0d); target router: ", $time(), i, j); + case (z) + 0: $write("(%0d, %0d)", i, j+1); + 1: $write("(%0d, %0d)", i, j-1); + 2: $write("(%0d, %0d)", i+1, j); + 3: $write("(%0d, %0d)", i-1, j); + 4: $write("local? wrong!"); + endcase + $write(" credit id:", rx_lcrd_id[i][j][z]); + $write(" \n"); + end + end + end + end +end +`endif + // other unused non-local ports, assign router rx to 0 generate for(i = 0; i < NODE_NUM_X_DIMESION; i++) begin: gen_unused_non_local_ports_x_dimesion @@ -335,6 +554,15 @@ import v_noc_pkg::*; .TEST_CASE_NUM_PER_CYCLE(TEST_CASE_NUM_PER_CYCLE ), .TEST_CASE_MESH_RANDOM (TEST_CASE_MESH_RANDOM ), .TEST_CASE_MESH_DIAGONAL(TEST_CASE_MESH_DIAGONAL ), + + .TEST_CASE_MESH_BIT_COMPLEMENT(TEST_CASE_MESH_BIT_COMPLEMENT), + .TEST_CASE_MESH_BIT_REVERSE (TEST_CASE_MESH_BIT_REVERSE), + .TEST_CASE_MESH_BIT_ROTATION (TEST_CASE_MESH_BIT_ROTATION), + .TEST_CASE_MESH_NEIGHBOR (TEST_CASE_MESH_NEIGHBOR), + .TEST_CASE_MESH_SHUFFLE (TEST_CASE_MESH_SHUFFLE), + .TEST_CASE_MESH_TRANSPOSE (TEST_CASE_MESH_TRANSPOSE), + .TEST_CASE_MESH_TORNADO (TEST_CASE_MESH_TORNADO), + .NODE_NUM_X_DIMESION (NODE_NUM_X_DIMESION ), .NODE_NUM_Y_DIMESION (NODE_NUM_Y_DIMESION ), .LOCAL_PORT_NUM (LOCAL_PORT_NUM ), @@ -538,6 +766,12 @@ endgenerate forever #5 clk = ~clk; end +`ifdef EBI + initial begin + bus_clk = 1'b0; + forever #5 bus_clk = ~bus_clk; + end +`endif //reset generate initial begin rstn = 1'b0; diff --git a/tb/v_noc_pkg.sv b/tb/v_noc_pkg.sv index dfb7d07..d5af861 100644 --- a/tb/v_noc_pkg.sv +++ b/tb/v_noc_pkg.sv @@ -22,7 +22,9 @@ package v_noc_pkg; typedef struct packed { node_id_t tgt_id; // target id node_id_t src_id; // source id +`ifdef ENABLE_TXN_ID logic [TxnID_Width-1:0] txn_id; // transaction id +`endif logic [SCOREBOARD_TIMEOUT_W-1:0] timeout_threshold; io_port_t look_ahead_routing; logic [VC_ID_NUM_MAX_W-1:0] inport_vc_id; @@ -45,7 +47,9 @@ package v_noc_pkg; typedef struct packed { node_id_t rec_id; // receiver id (should be the same as tgt_id) node_id_t src_id; // source id +`ifdef ENABLE_TXN_ID logic [TxnID_Width-1:0] txn_id; // transaction id +`endif logic [FLIT_DATA_LENGTH-1:0] flit_data; } receiver_info_t; diff --git a/tb/v_receiver.sv b/tb/v_receiver.sv index 42f0b00..7b03b0f 100644 --- a/tb/v_receiver.sv +++ b/tb/v_receiver.sv @@ -47,7 +47,9 @@ receiver_flit_decoder_u assign check_scoreboard_vld_o = rx_flit_v_i; assign check_scoreboard_o.rec_id = node_id_i; assign check_scoreboard_o.src_id = flit_ctrl_info.src_id; +`ifdef ENABLE_TXN_ID assign check_scoreboard_o.txn_id = flit_ctrl_info.txn_id; +`endif assign check_scoreboard_o.flit_data = rx_flit_i[FLIT_LENGTH-1-:FLIT_DATA_LENGTH]; assign rx_lcrd_v_o = rx_flit_v_i; diff --git a/tb/v_scoreboard.sv b/tb/v_scoreboard.sv index 84e6c14..31855e3 100644 --- a/tb/v_scoreboard.sv +++ b/tb/v_scoreboard.sv @@ -86,7 +86,9 @@ always_comb begin for(int k = 0; k < SCOREBOARD_ENTRY_NUM_PER_SENDER; k++) begin if(scoreboard_entry_vld_q[j][k]) begin if( +`ifdef ENABLE_TXN_ID (scoreboard_entry_q[j][k].txn_id == check_scoreboard_i[i].txn_id) & +`endif (scoreboard_entry_q[j][k].src_id == check_scoreboard_i[i].src_id) & (scoreboard_entry_q[j][k].tgt_id == check_scoreboard_i[i].rec_id) & (scoreboard_entry_q[j][k].flit_data == check_scoreboard_i[i].flit_data) @@ -175,7 +177,9 @@ always_ff @(posedge clk) begin for(int k = 0; k < SCOREBOARD_ENTRY_NUM_PER_SENDER; k++) begin if(scoreboard_entry_vld_q[j][k]) begin if((scoreboard_entry_q[j][k].src_id == check_scoreboard_i[i].src_id) && +`ifdef ENABLE_TXN_ID (scoreboard_entry_q[j][k].txn_id == check_scoreboard_i[i].txn_id) && +`endif (TEST_CASE_SINGLE_ROUTER || (scoreboard_entry_q[j][k].tgt_id == check_scoreboard_i[i].rec_id) && (scoreboard_entry_q[j][k].flit_data == check_scoreboard_i[i].flit_data) @@ -188,7 +192,11 @@ always_ff @(posedge clk) begin ) begin $display("[%16d] error: receiver position mismatch", $time()); $display("txn_id: 0x%h, sender: %2d (%d,%d), receiver: %d (%d,%d)", +`ifdef ENABLE_TXN_ID check_scoreboard_i[i].txn_id, +`else + '0, +`endif j, check_scoreboard_i[i].src_id.x_position, check_scoreboard_i[i].src_id.y_position, i, check_scoreboard_i[i].rec_id.x_position, check_scoreboard_i[i].rec_id.y_position); $display("tgt_id: (%d,%d), tgt_local_port: %d, look_ahead_routing: %d, send_time: %d", @@ -205,7 +213,11 @@ always_ff @(posedge clk) begin if(scoreboard_entry_q[j][k].tgt_id.device_port != check_scoreboard_i[i].rec_id.device_port) begin $display("[%16d] error: receiver local_port_id mismatch", $time()); $display("txn_id: 0x%h, sender: %2d (%d,%d), sender_local_port: %d; receiver: %d (%d,%d), receiver_local_port: %d", - check_scoreboard_i[i].txn_id, +`ifdef ENABLE_TXN_ID + check_scoreboard_i[i].txn_id, +`else + '0, +`endif j, check_scoreboard_i[i].src_id.x_position, check_scoreboard_i[i].src_id.y_position, check_scoreboard_i[i].src_id.device_port, i, check_scoreboard_i[i].rec_id.x_position, check_scoreboard_i[i].rec_id.y_position, @@ -221,7 +233,11 @@ always_ff @(posedge clk) begin if(scoreboard_entry_q[j][k].flit_data != check_scoreboard_i[i].flit_data) begin $display("[%16d] error: data mismatch", $time()); $display("txn_id: 0x%h, sender: %2d (%d,%d), receiver: %d (%d,%d), received_data: %h", +`ifdef ENABLE_TXN_ID check_scoreboard_i[i].txn_id, +`else + '0, +`endif j, check_scoreboard_i[i].src_id.x_position, check_scoreboard_i[i].src_id.y_position, i, check_scoreboard_i[i].rec_id.x_position, check_scoreboard_i[i].rec_id.y_position, check_scoreboard_i[i].flit_data); @@ -237,7 +253,12 @@ always_ff @(posedge clk) begin end if(find_entry[i] == 1'b0) begin $display("[%16d] error: scoreboard failed to find the entry, txn_id: 0x%h, sender: (%d,%d), receiver: (%d,%d)", - $time(), check_scoreboard_i[i].txn_id, + $time(), +`ifdef ENABLE_TXN_ID + check_scoreboard_i[i].txn_id, +`else + '0, +`endif check_scoreboard_i[i].src_id.x_position, check_scoreboard_i[i].src_id.y_position, check_scoreboard_i[i].rec_id.x_position, check_scoreboard_i[i].rec_id.y_position); $finish(); @@ -256,7 +277,11 @@ always_ff @(posedge clk) begin $display("[%16d] error: scoreboard entry timeout, timeout_threshold: %d", $time(), scoreboard_entry_q[i][j].timeout_threshold); $display("txn_id: 0x%h, sender: %2d (%d,%d), sender_local_port: %d, qos_value = %d", - scoreboard_entry_q[i][j].txn_id, +`ifdef ENABLE_TXN_ID + scoreboard_entry_q[i][j].txn_id, +`else + '0, +`endif i, scoreboard_entry_q[i][j].src_id.x_position, scoreboard_entry_q[i][j].src_id.y_position, scoreboard_entry_q[i][j].src_id.device_port, scoreboard_entry_q[i][j].qos_value); @@ -404,7 +429,11 @@ always_ff @(posedge clk) begin $display("[%16d] info: scoreboard allocate entry, sender: %2d (%d,%d), txn_id: 0x%h, QoS = %d, inport_vc_id:%d, tgt_id: (%d,%d), tgt_local_port: %d, look_ahead_routing: %d, send_data: %h", $time(), i, scoreboard_entry_d[i][j].src_id.x_position, scoreboard_entry_d[i][j].src_id.y_position, +`ifdef ENABLE_TXN_ID scoreboard_entry_d[i][j].txn_id, +`else + '0, +`endif scoreboard_entry_d[i][j].qos_value, scoreboard_entry_d[i][j].inport_vc_id, scoreboard_entry_d[i][j].tgt_id.x_position, scoreboard_entry_d[i][j].tgt_id.y_position, scoreboard_entry_d[i][j].tgt_id.device_port, @@ -419,7 +448,11 @@ always_ff @(posedge clk) begin $display("[%16d] info: scoreboard deallocate entry, sender: %2d (%d,%d), txn_id: 0x%h, QoS = %d, inport_vc_id:%d, tgt_id: (%d,%d), tgt_local_port: %d, send_data: %h, [noc_latency: %4d], [app_latency: %4d], [receiver (%d,%d) port %d average_noc_bandwidth: %fGBps])", $time(), i, scoreboard_entry_q[i][j].src_id.x_position, scoreboard_entry_q[i][j].src_id.y_position, +`ifdef ENABLE_TXN_ID scoreboard_entry_q[i][j].txn_id, +`else + '0, +`endif scoreboard_entry_q[i][j].qos_value, scoreboard_entry_q[i][j].inport_vc_id, scoreboard_entry_q[i][j].tgt_id.x_position, scoreboard_entry_q[i][j].tgt_id.y_position, scoreboard_entry_q[i][j].tgt_id.device_port, diff --git a/tb/v_sender.sv b/tb/v_sender.sv index 400a95d..fb96448 100644 --- a/tb/v_sender.sv +++ b/tb/v_sender.sv @@ -143,11 +143,21 @@ assign flit_buffer_dequeue_vld = free_credit_vld & flit_vld; // output to dut assign tx_flit_pend_o = 1'b1; assign tx_flit_v_o = flit_buffer_dequeue_vld; -assign tx_flit_o = {flit_buffer_head.flit_data, - flit_buffer_head.flit_head.txn_id, - flit_buffer_head.flit_head.src_id, - flit_buffer_head.flit_head.tgt_id, - flit_buffer_head.qos_value}; +// assign tx_flit_o = {flit_buffer_head.flit_data, +// flit_buffer_head.flit_head.txn_id, +// flit_buffer_head.flit_head.src_id, +// flit_buffer_head.flit_head.tgt_id, +// flit_buffer_head.qos_value}; +assign tx_flit_o[(FLIT_LENGTH-1)-:FLIT_DATA_LENGTH] = flit_buffer_head.flit_data; +assign tx_flit_o.tgt_id = flit_buffer_head.flit_head.tgt_id; +assign tx_flit_o.src_id = flit_buffer_head.flit_head.src_id; +`ifdef ENABLE_TXN_ID +assign tx_flit_o.txn_id = flit_buffer_head.flit_head.txn_id; +`endif +`ifdef USE_QOS_VALUE +assign tx_flit_o.qos_value = flit_buffer_head.flit_head.qos_value; +`endif + assign tx_flit_vc_id_o = {{(VC_ID_NUM_MAX_W-VC_NUM_OUTPORT_IDX_W){1'b0}}, free_credit_vc_id}; assign tx_flit_look_ahead_routing_o = flit_buffer_head.flit_head.look_ahead_routing; @@ -155,7 +165,9 @@ assign tx_flit_look_ahead_routing_o = flit_buffer_head.flit_head.look_ahead_ro assign new_scoreboard_entry_vld_o = tx_flit_v_o; assign new_scoreboard_entry_o.tgt_id = flit_buffer_head.flit_head.tgt_id; assign new_scoreboard_entry_o.src_id = flit_buffer_head.flit_head.src_id; +`ifdef ENABLE_TXN_ID assign new_scoreboard_entry_o.txn_id = flit_buffer_head.flit_head.txn_id; +`endif assign new_scoreboard_entry_o.timeout_threshold = flit_buffer_head.timeout_threshold; assign new_scoreboard_entry_o.look_ahead_routing = flit_buffer_head.flit_head.look_ahead_routing; assign new_scoreboard_entry_o.inport_vc_id = tx_flit_vc_id_o; diff --git a/tb/v_test_generator.sv b/tb/v_test_generator.sv index 027f580..496a7c7 100644 --- a/tb/v_test_generator.sv +++ b/tb/v_test_generator.sv @@ -18,7 +18,16 @@ import v_noc_pkg::*; // | \ // sender1 (1,0) (local) sender4 parameter TEST_CASE_MESH_RANDOM = 0, // random sender and receiver - parameter TEST_CASE_MESH_DIAGONAL = 0, // from (0,0) to (NODE_NUM_X_DIMESION-1, NODE_NUM_Y_DIMESION-1) + parameter TEST_CASE_MESH_DIAGONAL = 0, // from (0, 0) to (NODE_NUM_X_DIMESION-1, NODE_NUM_Y_DIMESION-1) + + parameter TEST_CASE_MESH_BIT_COMPLEMENT = 0, // from (x, y) to (radix-x-1, radix-y-1) + parameter TEST_CASE_MESH_BIT_REVERSE = 0, + parameter TEST_CASE_MESH_BIT_ROTATION = 0, + parameter TEST_CASE_MESH_NEIGHBOR = 0, + parameter TEST_CASE_MESH_SHUFFLE = 0, + parameter TEST_CASE_MESH_TRANSPOSE = 0, + parameter TEST_CASE_MESH_TORNADO = 0, + parameter NODE_NUM_X_DIMESION = 2, // only used in TEST_CASE_MESH_* mode parameter NODE_NUM_Y_DIMESION = 3, // only used in TEST_CASE_MESH_* mode parameter LOCAL_PORT_NUM = 1, // only used in TEST_CASE_MESH_* mode @@ -91,7 +100,7 @@ generate - else if(TEST_CASE_MESH_RANDOM || TEST_CASE_MESH_DIAGONAL) begin: gen_map_test_case_mesh_x + else /*if(TEST_CASE_MESH_RANDOM || TEST_CASE_MESH_DIAGONAL)*/ begin: gen_map_test_case_mesh_x // sender id = x_posotion*(NODE_NUM_Y_DIMESION*LOCAL_PORT_NUM) + y_posotion*LOCAL_PORT_NUM + local_port_id always_comb begin new_test_vld_o = '0; @@ -219,7 +228,9 @@ generate new_test[i].flit_data = ((src_id_lfsr_data[RANDOM_BIT_NUM-1:0] ^ i) << tgt_id_lfsr_data[$clog2(FLIT_DATA_LENGTH-RANDOM_BIT_NUM)-1:0]) | flit_data_mask; end +`ifdef ENABLE_TXN_ID assign new_test[i].flit_head.txn_id = txn_counter + i; +`endif assign new_test[i].timeout_threshold = SCOREBOARD_TIMEOUT_EN ? SCOREBOARD_TIMEOUT_THRESHOLD : '0; // 0 means no timeout error @@ -267,79 +278,153 @@ generate end endcase end - end - end + end else begin: gen_test_case_mesh + logic [FLIT_DATA_LENGTH-1:0] flit_data_mask; + assign flit_data_mask = ~({RANDOM_BIT_NUM{1'b1}} << tgt_id_lfsr_data[$clog2(FLIT_DATA_LENGTH-RANDOM_BIT_NUM)-1:0]); - else if(TEST_CASE_MESH_RANDOM) begin: gen_test_case_mesh_random - for(i = 0; i < TEST_CASE_NUM_PER_CYCLE; i++) begin: gen_new_test - always_comb begin - new_test[i].flit_head.src_id.x_position = src_id_lfsr_data[i*3+:3] % NODE_NUM_X_DIMESION; - new_test[i].flit_head.src_id.y_position = src_id_lfsr_data[RANDOM_BIT_NUM-1-i*3-:3] % NODE_NUM_Y_DIMESION; - - new_test[i].flit_head.tgt_id.x_position = tgt_id_lfsr_data[i*3+:3] % NODE_NUM_X_DIMESION; - new_test[i].flit_head.tgt_id.y_position = tgt_id_lfsr_data[RANDOM_BIT_NUM-1-i*3-:3] % NODE_NUM_Y_DIMESION; + logic [TEST_CASE_NUM_PER_CYCLE-1:0][$clog2(NODE_NUM_X_DIMESION*NODE_NUM_Y_DIMESION)-1:0] source_id; + logic [TEST_CASE_NUM_PER_CYCLE-1:0][$clog2(NODE_NUM_X_DIMESION*NODE_NUM_Y_DIMESION)-1:0] source_id_rev; + logic [TEST_CASE_NUM_PER_CYCLE-1:0][$clog2(NODE_NUM_X_DIMESION*NODE_NUM_Y_DIMESION)-1:0] dest_id; + for(genvar i_id = 0; i_id < TEST_CASE_NUM_PER_CYCLE; i_id++) begin + assign source_id[i_id] = new_test[i_id].flit_head.src_id.y_position * NODE_NUM_X_DIMESION + new_test[i_id].flit_head.src_id.x_position; + for(genvar j_id = 0; j_id < $clog2(NODE_NUM_X_DIMESION*NODE_NUM_Y_DIMESION); j_id++) begin + assign source_id_rev[i_id][j_id] = source_id[i_id][$clog2(NODE_NUM_X_DIMESION*NODE_NUM_Y_DIMESION)-1-j_id]; end - - - logic [FLIT_DATA_LENGTH-1:0] flit_data_mask; - always_comb begin - flit_data_mask = ~({RANDOM_BIT_NUM{1'b1}} << tgt_id_lfsr_data[$clog2(FLIT_DATA_LENGTH-RANDOM_BIT_NUM)-1:0]); + end + + always_comb begin + // default values + for(int i = 0; i < TEST_CASE_NUM_PER_CYCLE; i++) begin new_test[i].flit_data = '1; new_test[i].flit_data = ((src_id_lfsr_data[RANDOM_BIT_NUM-1:0] ^ i) << tgt_id_lfsr_data[$clog2(FLIT_DATA_LENGTH-RANDOM_BIT_NUM)-1:0]) | flit_data_mask; - end - assign new_test[i].flit_head.txn_id = txn_counter + i; - -`ifdef COMMON_QOS_EXTRA_RT_VC - assign new_test[i].timeout_threshold = (new_test[i].qos_value == '1) ? 2 * (NODE_NUM_X_DIMESION + NODE_NUM_Y_DIMESION - 1) : - SCOREBOARD_TIMEOUT_EN ? SCOREBOARD_TIMEOUT_THRESHOLD : '0; -`else - assign new_test[i].timeout_threshold = SCOREBOARD_TIMEOUT_EN ? SCOREBOARD_TIMEOUT_THRESHOLD : '0; +`ifdef ENABLE_TXN_ID + new_test[i].flit_head.txn_id = txn_counter + i; `endif - assign new_test[i].mcycle_when_generated = mcycle_i; +`ifdef COMMON_QOS_EXTRA_RT_VC + new_test[i].timeout_threshold = //(new_test[i].qos_value == '1) ? 2 * (NODE_NUM_X_DIMESION + NODE_NUM_Y_DIMESION - 1) : + SCOREBOARD_TIMEOUT_EN ? SCOREBOARD_TIMEOUT_THRESHOLD : '0; +`else + new_test[i].timeout_threshold = SCOREBOARD_TIMEOUT_EN ? SCOREBOARD_TIMEOUT_THRESHOLD : '0; +`endif - assign new_test[i].flit_head.src_id.device_id = '0; - assign new_test[i].flit_head.tgt_id.device_id = '0; + new_test[i].mcycle_when_generated = mcycle_i; - assign new_test[i].flit_head.src_id.device_port = (src_id_lfsr_data[i*2+:2] ^ tgt_id_lfsr_data[RANDOM_BIT_NUM-1-i*2-:2]) % LOCAL_PORT_NUM; - assign new_test[i].flit_head.tgt_id.device_port = (src_id_lfsr_data[RANDOM_BIT_NUM-1-i*2-:2] ^ tgt_id_lfsr_data[i*2+:2]) % LOCAL_PORT_NUM; - end - end + new_test[i].flit_head.src_id.device_id = '0; + new_test[i].flit_head.tgt_id.device_id = '0; - else if(TEST_CASE_MESH_DIAGONAL) begin: gen_test_case_mesh_diagonal - for(i = 0; i < TEST_CASE_NUM_PER_CYCLE; i++) begin: gen_new_test - always_comb begin - new_test[i].flit_head.src_id.x_position = 0; - new_test[i].flit_head.src_id.y_position = 0; + new_test[i].flit_head.src_id.device_port = (src_id_lfsr_data[i*2+:2] ^ tgt_id_lfsr_data[RANDOM_BIT_NUM-1-i*2-:2]) % LOCAL_PORT_NUM; + new_test[i].flit_head.tgt_id.device_port = (src_id_lfsr_data[RANDOM_BIT_NUM-1-i*2-:2] ^ tgt_id_lfsr_data[i*2+:2]) % LOCAL_PORT_NUM; - new_test[i].flit_head.tgt_id.x_position = NODE_NUM_X_DIMESION - 1; - new_test[i].flit_head.tgt_id.y_position = NODE_NUM_Y_DIMESION - 1; + dest_id[i] = '0; end - logic [FLIT_DATA_LENGTH-1:0] flit_data_mask; - always_comb begin - flit_data_mask = ~({RANDOM_BIT_NUM{1'b1}} << tgt_id_lfsr_data[$clog2(FLIT_DATA_LENGTH-RANDOM_BIT_NUM)-1:0]); - new_test[i].flit_data = '1; - new_test[i].flit_data = ((src_id_lfsr_data[RANDOM_BIT_NUM-1:0] ^ i) << tgt_id_lfsr_data[$clog2(FLIT_DATA_LENGTH-RANDOM_BIT_NUM)-1:0]) | flit_data_mask; + + if(TEST_CASE_MESH_RANDOM) begin + for(int i = 0; i < TEST_CASE_NUM_PER_CYCLE; i++) begin + new_test[i].flit_head.src_id.x_position = src_id_lfsr_data[i*3+:3] % NODE_NUM_X_DIMESION; + new_test[i].flit_head.src_id.y_position = src_id_lfsr_data[RANDOM_BIT_NUM-1-i*3-:3] % NODE_NUM_Y_DIMESION; + + new_test[i].flit_head.tgt_id.x_position = tgt_id_lfsr_data[i*3+:3] % NODE_NUM_X_DIMESION; + new_test[i].flit_head.tgt_id.y_position = tgt_id_lfsr_data[RANDOM_BIT_NUM-1-i*3-:3] % NODE_NUM_Y_DIMESION; + end + + end else if(TEST_CASE_MESH_DIAGONAL) begin + for(int i = 0; i < TEST_CASE_NUM_PER_CYCLE; i++) begin + new_test[i].flit_head.src_id.x_position = 0; + new_test[i].flit_head.src_id.y_position = 0; + + new_test[i].flit_head.tgt_id.x_position = NODE_NUM_X_DIMESION - 1; + new_test[i].flit_head.tgt_id.y_position = NODE_NUM_Y_DIMESION - 1; + + new_test[i].timeout_threshold = SCOREBOARD_TIMEOUT_EN ? SCOREBOARD_TIMEOUT_THRESHOLD : '0; + + new_test[i].flit_head.src_id.device_id = '0; + new_test[i].flit_head.tgt_id.device_id = '0; + + new_test[i].flit_head.src_id.device_port = 0; + new_test[i].flit_head.tgt_id.device_port = 0; + end + + end else if (TEST_CASE_MESH_BIT_COMPLEMENT) begin + for(int i = 0; i < TEST_CASE_NUM_PER_CYCLE; i++) begin + new_test[i].flit_head.src_id.x_position = src_id_lfsr_data[i*3+:3] % NODE_NUM_X_DIMESION; + new_test[i].flit_head.src_id.y_position = src_id_lfsr_data[RANDOM_BIT_NUM-1-i*3-:3] % NODE_NUM_Y_DIMESION; + + new_test[i].flit_head.tgt_id.x_position = NODE_NUM_X_DIMESION-1-new_test[i].flit_head.src_id.x_position; + new_test[i].flit_head.tgt_id.y_position = NODE_NUM_Y_DIMESION-1-new_test[i].flit_head.src_id.y_position; + end + + end else if (TEST_CASE_MESH_BIT_REVERSE) begin + for(int i = 0; i < TEST_CASE_NUM_PER_CYCLE; i++) begin + new_test[i].flit_head.src_id.x_position = src_id_lfsr_data[i*3+:3] % NODE_NUM_X_DIMESION; + new_test[i].flit_head.src_id.y_position = src_id_lfsr_data[RANDOM_BIT_NUM-1-i*3-:3] % NODE_NUM_Y_DIMESION; + + new_test[i].flit_head.tgt_id.x_position = source_id_rev % NODE_NUM_X_DIMESION; + new_test[i].flit_head.tgt_id.y_position = (source_id_rev / NODE_NUM_X_DIMESION) % NODE_NUM_Y_DIMESION; + end + + end else if (TEST_CASE_MESH_BIT_ROTATION) begin + for(int i = 0; i < TEST_CASE_NUM_PER_CYCLE; i++) begin + new_test[i].flit_head.src_id.x_position = src_id_lfsr_data[i*3+:3] % NODE_NUM_X_DIMESION; + new_test[i].flit_head.src_id.y_position = src_id_lfsr_data[RANDOM_BIT_NUM-1-i*3-:3] % NODE_NUM_Y_DIMESION; + + new_test[i].flit_head.tgt_id.x_position = new_test[i].flit_head.src_id.x_position > 0 ? new_test[i].flit_head.src_id.x_position - 1: + new_test[i].flit_head.src_id.y_position > 0 ? NODE_NUM_X_DIMESION-1: + new_test[i].flit_head.src_id.x_position; + new_test[i].flit_head.tgt_id.y_position = new_test[i].flit_head.src_id.x_position > 0 ? new_test[i].flit_head.src_id.y_position : + new_test[i].flit_head.src_id.y_position > 0 ? new_test[i].flit_head.src_id.y_position - 1: + new_test[i].flit_head.src_id.y_position; + end + + end else if (TEST_CASE_MESH_NEIGHBOR) begin + for(int i = 0; i < TEST_CASE_NUM_PER_CYCLE; i++) begin + new_test[i].flit_head.src_id.x_position = src_id_lfsr_data[i*3+:3] % NODE_NUM_X_DIMESION; + new_test[i].flit_head.src_id.y_position = src_id_lfsr_data[RANDOM_BIT_NUM-1-i*3-:3] % NODE_NUM_Y_DIMESION; + + new_test[i].flit_head.tgt_id.x_position = (new_test[i].flit_head.src_id.x_position + 1) % NODE_NUM_X_DIMESION; + new_test[i].flit_head.tgt_id.y_position = new_test[i].flit_head.src_id.y_position ; + end + + end else if (TEST_CASE_MESH_SHUFFLE) begin + for(int i = 0; i < TEST_CASE_NUM_PER_CYCLE; i++) begin + new_test[i].flit_head.src_id.x_position = src_id_lfsr_data[i*3+:3] % NODE_NUM_X_DIMESION; + new_test[i].flit_head.src_id.y_position = src_id_lfsr_data[RANDOM_BIT_NUM-1-i*3-:3] % NODE_NUM_Y_DIMESION; + + if(source_id[i] < (NODE_NUM_X_DIMESION*NODE_NUM_Y_DIMESION)/2) begin + dest_id[i] = source_id[i] * 2; + end else begin + dest_id[i] = (source_id[i] *2) - (NODE_NUM_X_DIMESION*NODE_NUM_Y_DIMESION) + 1; + end + new_test[i].flit_head.tgt_id.x_position = dest_id % NODE_NUM_X_DIMESION; + new_test[i].flit_head.tgt_id.y_position = (dest_id / NODE_NUM_X_DIMESION) % NODE_NUM_Y_DIMESION; + end + + end else if (TEST_CASE_MESH_TRANSPOSE) begin + for(int i = 0; i < TEST_CASE_NUM_PER_CYCLE; i++) begin + new_test[i].flit_head.src_id.x_position = src_id_lfsr_data[i*3+:3] % NODE_NUM_X_DIMESION; + new_test[i].flit_head.src_id.y_position = src_id_lfsr_data[RANDOM_BIT_NUM-1-i*3-:3] % NODE_NUM_Y_DIMESION; + + new_test[i].flit_head.tgt_id.x_position = new_test[i].flit_head.src_id.y_position % NODE_NUM_X_DIMESION; + new_test[i].flit_head.tgt_id.y_position = new_test[i].flit_head.src_id.x_position % NODE_NUM_Y_DIMESION; + end + + end else if (TEST_CASE_MESH_TORNADO) begin + for(int i = 0; i < TEST_CASE_NUM_PER_CYCLE; i++) begin + new_test[i].flit_head.src_id.x_position = src_id_lfsr_data[i*3+:3] % NODE_NUM_X_DIMESION; + new_test[i].flit_head.src_id.y_position = src_id_lfsr_data[RANDOM_BIT_NUM-1-i*3-:3] % NODE_NUM_Y_DIMESION; + + new_test[i].flit_head.tgt_id.x_position = (new_test[i].flit_head.src_id.x_position + int'($ceil(NODE_NUM_X_DIMESION*1.0/2)) - 1) % NODE_NUM_X_DIMESION; + new_test[i].flit_head.tgt_id.y_position = new_test[i].flit_head.src_id.y_position; + end + end - - assign new_test[i].flit_head.txn_id = txn_counter + i; - - assign new_test[i].timeout_threshold = SCOREBOARD_TIMEOUT_EN ? SCOREBOARD_TIMEOUT_THRESHOLD : '0; - - assign new_test[i].mcycle_when_generated = mcycle_i; - - assign new_test[i].flit_head.src_id.device_id = '0; - assign new_test[i].flit_head.tgt_id.device_id = '0; - - assign new_test[i].flit_head.src_id.device_port = 0; - assign new_test[i].flit_head.tgt_id.device_port = 0; end end endgenerate @@ -389,7 +474,7 @@ generate - else if(TEST_CASE_MESH_RANDOM || TEST_CASE_MESH_DIAGONAL) begin: gen_test_case_look_ahead_routing_mesh_x + else /*if(TEST_CASE_MESH_RANDOM || TEST_CASE_MESH_DIAGONAL)*/ begin: gen_test_case_look_ahead_routing_mesh_x for(i = 0; i < TEST_CASE_NUM_PER_CYCLE; i++) begin: gen_new_test_look_ahead_routing always_comb begin if(new_test[i].flit_head.tgt_id.x_position > new_test[i].flit_head.src_id.x_position) begin