third-party/OpenExSys_NoC
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initial commit for open source NoC IP

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This commit is contained in:
Zexin Fu
2023-11-26 14:59:34 +01:00
commit 6ba3d27334
122 changed files with 14907 additions and 0 deletions
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14
flow/lint/Makefile Executable file
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NAME := rvh_core
run-goals: run-goal-design_read run-goal-lint_lint_rtl
run-goal-design_read:
sg_shell -tcl spyglass-run-design_read.tcl
run-goal-lint_lint_rtl:
sg_shell -enable_pass_exit_codes -tcl spyglass-run-lint_lint_rtl.tcl
run-gui:
spyglass -project $(NAME).prj
clean:
@rm -rf rvh_core

25
flow/lint/rvh_core.prj Executable file
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#!SPYGLASS_PROJECT_FILE
#!VERSION 3.0
# -------------------------------------------------------------------
# This is a automatically generated project file by fusesoc.
# -------------------------------------------------------------------
set_option projectwdir .
set_option language_mode mixed
set_option designread_enable_synthesis yes
set_option designread_disable_flatten no
# Make no only FATAL messages return a non-zero exit code, but also ERRORs and
# WARNINGs
set_option enable_pass_exit_codes yes
read_file -type sourcelist ../../tb/flist_mesh.syn.f
set_option top top_mesh_syn
set_option enableSV09 yes
set_option active_methodology $SPYGLASS_HOME/GuideWare/latest/block/rtl_handoff
current_methodology $SPYGLASS_HOME/GuideWare/latest/block/rtl_handoff

21
flow/lint/spyglass-run-design_read.tcl Executable file
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open_project rvh_core.prj
current_goal Design_Read
# Parameters which are not used/defined in a given goal/methodology raise
# a WARNING, which fails the lint process. That's a bit over the top, we hence
# disable this warning.
waive -rule {checkCMD_unknown}
set rc [run_goal]
close_project -force
set errorCode [lindex $rc 0]
set errorMsg [lindex $rc 1]
if { $errorCode } {
puts stderr "SpyGlass run failed: $errorMsg ($errorCode)"
}
# requires sg_shell to be called with -enable_pass_exit_codes, otherwise
# all non-fatal exit codes are mapped to 0
exit $errorCode

21
flow/lint/spyglass-run-lint_lint_rtl.tcl Executable file
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open_project rvh_core.prj
current_goal lint/lint_rtl
# Parameters which are not used/defined in a given goal/methodology raise
# a WARNING, which fails the lint process. That's a bit over the top, we hence
# disable this warning.
waive -rule {checkCMD_unknown}
set rc [run_goal]
close_project -force
set errorCode [lindex $rc 0]
set errorMsg [lindex $rc 1]
if { $errorCode } {
puts stderr "SpyGlass run failed: $errorMsg ($errorCode)"
}
# requires sg_shell to be called with -enable_pass_exit_codes, otherwise
# all non-fatal exit codes are mapped to 0
exit $errorCode

33
flow/syn/Makefile Normal file
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## prefered path: proj_root/syn/dc/
export TIMESTAMP=$(shell date +%Y%m%d%H%M%S)
export DESIGN_NAME=rvh_noc
# T12/GF22
export SYN_PDK=T12
# SINGLE_ROUTER/MESH
export SYN_TOP=SINGLE_ROUTER
all:
export TIMESTAMP=$(shell date +%Y%m%d%H%M%S)
export DESIGN_NAME=rvh_noc
export SYN_PDK=T12
export SYN_TOP=SINGLE_ROUTER
mkdir ./$(TIMESTAMP)_$(SYN_PDK)_$(SYN_TOP)_run && cd ./$(TIMESTAMP)_$(SYN_PDK)_$(SYN_TOP)_run && mkdir rpt && mkdir output
/opt/cad/synopsys/installs/syn/Q-2019.12-SP5-1/bin/dc_shell-t -checkout DesignWare -f tcl_scripts/synth.tcl | tee $(TIMESTAMP)_$(SYN_PDK)_$(SYN_TOP)_run/$(SYN_PDK)_$(SYN_TOP).log
PHONY:
clean:
rm -rf *_run
rm *.log
# -topographical_mode means using physical constraints on your design, this will allow you to
# accurately predict post-layout timing, area, and power during synthesis without the need for
# timing approximations based on wire load models. It uses placement and optimization
# technologies to drive accurate timing prediction within synthesis and automatically performs
# leakage power optimization, ensuring better correlation with the final physical design.

53
flow/syn/tcl_scripts/assert.tcl Normal file
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proc assert {cond {msg ""}} {
if {![uplevel 1 expr $cond]} {
return -code error "$msg\n assertion failed: $cond"
}
}
proc assert_is_file { fpath } {
global ours
if {![file isfile $fpath]} {
error "Error: file ($fpath) not found"
# if {$ours(tcl_check_only) == "false"} {
# uplevel suspend
# } else {
# error ""
# }
}
}
proc assert_is_dir { dpath } {
global ours
if {![file isdirectory $dpath]} {
error "Error: dir ($dpath) not found"
# if {$ours(tcl_check_only) == "false"} {
# uplevel suspend
# } else {
# error ""
# }
}
}
proc assert_exist { dpath } {
global ours
if {![file exists $dpath]} {
error "Error: dir ($dpath) not found"
# if {$ours(tcl_check_only) == "false"} {
# uplevel suspend
# } else {
# error ""
# }
}
}
proc assert_is_file_list { ls_fpath } {
foreach fpath $ls_fpath {
assert_is_file $fpath
}
}
proc assert_is_dir_list { ls_dpath } {
foreach dpath $ls_dpath {
assert_is_dir $dpath
}
}

315
flow/syn/tcl_scripts/constraints.sdc Normal file
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#**************************************************************
# Create Clock
#**************************************************************
set clk_period 1
# set clk_period 0.66
# set clk_uncertainty [expr $clk_period * 0.1]
set clk_uncertainty_setup [expr $clk_period * 0.2]
set clk_uncertainty_hold [expr $clk_period * 0.05]
set latency_input_transition [expr $clk_period * 0.04]
set latency_input_transition_clocks [expr $clk_period * 0.003]
#MARGIN 0.9/0.65/1.0
set MARGIN 0.9
set period_1000m [expr $MARGIN * $clk_period];
#**************************************************************
# List clk ports
#**************************************************************
set CLK_PORT_LIST_IN "clk"
set RST_PORT_LIST_IN "rst"
set main_clk [get_ports clk]
#**************************************************************
# Create Clock
#**************************************************************
#create_clock -period 0.500 -waveform {0.0 0.25} -name clk [get_ports clk]
set period_main_clock $period_1000m
#create_clock -name CLK -period $clk_period [get_ports clk]
create_clock -name clk -period $period_main_clock -waveform [list 0 [expr $period_main_clock *0.5]] $main_clk -add
# create_clock -name vir_main_clk -period $period_main_clock -waveform [list 0 [expr $period_main_clock *0.5]]
#**************************************************************
# Create Generated Clock
#**************************************************************
#derive_pll_clocks
#**************************************************************
# ScanEnable to be 0
#**************************************************************
# Please include vcore_fp_top.disable_scan_constraints.v
set DRC_data_max_transition 0.25
set DRC_clock_max_transition 0.15
#**************************************************************
# Power Pin
#**************************************************************
#set ours(iport,cfg_pwr) [get_ports {*/cfg_is_clk_gated */cfg_thread_cnt*} -filter "direction==in"]
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#derive_clock_uncertainty
#set_clock_uncertainty 0.125 [all_clocks]
# set_clock_uncertainty $clk_uncertainty [all_clocks]
set_clock_uncertainty -setup $clk_uncertainty_setup [all_clocks]
set_clock_uncertainty -hold $clk_uncertainty_hold [all_clocks]
#**************************************************************
# Set I/O Delay
#**************************************************************
# set_input_delay [expr 0.5 * $clk_period] -max -clock vir_main_clk [remove_from_collection [all_inputs] [get_ports clk]]
# set_input_delay [expr 0.0 * $clk_period] -min -clock vir_main_clk [remove_from_collection [all_inputs] [get_ports clk]]
# set_output_delay [expr 0.5 * $clk_period] -max -clock vir_main_clk [all_outputs]
# set_output_delay [expr 0.0 * $clk_period] -max -clock vir_main_clk [all_outputs]
set_input_delay [expr $clk_period * 0.4] -clock clk [remove_from_collection [all_inputs] {clk}]
set_output_delay [expr $clk_period * 0.4] -clock clk [all_outputs]
#**************************************************************
# Set ideal_network
#**************************************************************
if {[sizeof_collection [get_cells -quiet -hierarchical -filter "ref_name =~CKLNQD*"]]} {
set_ideal_network [get_pins -filter "pin_direction == out" -of_object [get_cells -hierarchical -filter "ref_name =~ *CKLNQD*"]]
}
if {[sizeof_collection [get_cells -quiet -hierarchical -filter "ref_name =~CKLHQD*"]]} {
set_ideal_network [get_pins -filter "pin_direction == out" -of_object [get_cells -hierarchical -filter "ref_name =~ *CKKHQD*"]]
}
set_ideal_network [get_ports -quiet "$CLK_PORT_LIST_IN "]
set_ideal_network [get_ports -quiet "$RST_PORT_LIST_IN "]
# set_ideal_network [get_attribute [get_clocks -filter "full_name !~ vir*"] source]
# set_dont_touch_network [get_clocks -filter "full_name !~ vir*"]
set_dont_touch_network [all_clocks]
set_ideal_network [all_fanout -flat -clock_tree]
#**************************************************************
# Set False Path
#**************************************************************
# false path to power switch control ack (use pre-placed and pre-routing in ICC2)
#set_false_path -from [get_ports */cfg_is_clk_gated] -to [get_ports */cfg_is_clk_gated]
#set_false_path -from [get_ports */cfg_thread_cnt* ] -to [get_ports */cfg_thread_cnt*]
# false path from SLP to Q in SRAM (SLP not valid in VCORE yet, only on top level)
#set ours(pin,sram_slp) [get_pins -of [get_cells * -hier -filter "ref_name=~TS*N28HPCP*"] -filter "full_name=~*/SLP"]
#set ours(pin,sram_q) [get_pins -of [get_cells * -hier -filter "ref_name=~TS*N28HPCP*"] -filter "full_name=~*/Q*"]
#set_false_path -th $ours(pin,sram_slp) -th $ours(pin,sram_q)
#**************************************************************
# Begin
#**************************************************************
set global_setup_uncertainty 0.09
set global_hold_uncertainty 0.08
set ENV_data_input_max_transition 0.25
set ENV_input_min_transition 0.010
set DRC_max_fanout_inner 40
set DRC_max_fanout_input 1
set_max_transition $DRC_data_max_transition [current_design]
set_max_transition $DRC_data_max_transition -data_path [all_clocks]
set_max_transition $DRC_clock_max_transition -clock_path [all_clocks]
set_max_fanout $DRC_max_fanout_inner [current_design];#40
set_max_fanout $DRC_max_fanout_input [all_inputs];#1
set inputs [remove_from_collection [all_inputs] $CLK_PORT_LIST_IN]
set_input_transition -max $ENV_data_input_max_transition $inputs
set_input_transition -min $ENV_input_min_transition $inputs
set_load -max 0.050 [all_outputs]
set_load -max 0.004 [all_outputs]
if {[info exists dft_clks]} {
set func_clocks [remove_from_collection [all_clocks] $dft_clks]
} else {
set func_clocks [all_clocks]
}
set_clock_uncertainty -setup $global_setup_uncertainty $func_clocks
set_clock_uncertainty -hold $global_hold_uncertainty [all_clocks]
#**************************************************************
# Set Multicycle Path
#**************************************************************
# set_multicycle_path 18 -setup -end \
# -through [get_pins div_u/ff_div_a_u/q[*]] \
# -through [get_pins div_u/ff_div_output_data_u/d[*]]
# set_multicycle_path 17 -hold -end \
# -through [get_pins div_u/ff_div_a_u/q[*]] \
# -through [get_pins div_u/ff_div_output_data_u/d[*]]
# set_multicycle_path 18 -setup -end \
# -through [get_pins div_u/ff_div_b_u/q[*]] \
# -through [get_pins div_u/ff_div_output_data_u/d[*]]
# set_multicycle_path 17 -hold -end \
# -through [get_pins div_u/ff_div_b_u/q[*]] \
# -through [get_pins div_u/ff_div_output_data_u/d[*]]
# set_multicycle_path -setup 2 -through [get_cells {btb_u/BTB_SET_*__btb_tag/*}] -to [get_cells { \
# npc_gen_u/* \
# icache_u/req_valid_s1_reg \
# instr_buffer/wr_ptr_reg* \
# kill_f1_reg \
# btq_u/target_ram_reg* \
# }]
# set_multicycle_path -setup 2 -through [get_pins {btb_u/BTB_SET_*__btb_tag/*}]
# set_multicycle_path -setup 8 -through [get_pins {EX/DIV/*}] -to [get_pins { \
# EX/DIV/DW_DIV_SEQ/* \
# EX/DIV/* \
# }]
# set_multicycle_path -setup 8 -through [get_pins {EX/DIV/*}]
# set_multicycle_path -hold 7 -through [get_pins {EX/DIV/*}]
# set_multicycle_path -setup 8 -through [get_pins {EX/DIV/*/*}]
# set_multicycle_path -hold 7 -through [get_pins {EX/DIV/*/*}]
# set_multicycle_path -setup 5 -through [get_pins {EX/MUL/*}]
# set_multicycle_path -hold 4 -through [get_pins {EX/MUL/*}]
# set_multicycle_path -hold 7 -through [get_cells {EX/DIV/*}] -to [get_cells { \
# EX/DIV/* \
# EX/DIV/DW_DIV_SEQ_part_rem_reg_reg_*_ \
# EX/DIV/DW_DIV_SEQ_shf_reg_reg_*__*_ \
# EX/DIV/DW_DIV_SEQ*reg* \
# EX/ex2ma_ff_reg** \
# ID/id2div_ff_reg* \
# ID/id2ex_ff_reg* \
# ID/id2ex_ff_reg* \
# ID/id2ex_fp_rs1* \
# ID/id2fp_add_d_ff_reg* \
# ID/id2fp_add_s_ff_reg* \
# ID/id2fp_div_d_ff_reg* \
# ID/id2fp_div_s_ff_reg* \
# ID/id2fp_mac_d_ff_reg* \
# ID/id2fp_mac_s_ff_reg* \
# ID/id2fp_misc_ff_reg* \
# ID/id2fp_sqrt_d_ff_reg* \
# ID/id2fp_sqrt_s_ff_reg* \
# ID/id2mul_ff_reg* \
# itlb_u/dff_sfence_req_reg* \
# }]
# set_multicycle_path -hold 7 -through [get_pins {EX/DIV/*}] -to [get_pins { \
# EX/DIV/DW_DIV_SEQ/* \
# EX/DIV/* \
# }]
# set_multicycle_path -setup 5 -through [get_cells {EX/MUL/*}] -to [get_cells { \
# EX/ex2ma_ff_reg* \
# EX/MUL/DW_MULT_SEQ*reg* \
# EX/MUL/* \
# ID/id2div_ff_reg* \
# ID/id2ex_ff_reg* \
# ID/id2ex_ff_reg* \
# ID/id2ex_fp_rs1_ff_reg* \
# ID/id2fp_add_d_ff_reg* \
# ID/id2fp_add_s_ff_reg* \
# ID/id2fp_div_d_ff_reg* \
# ID/id2fp_div_s_ff_reg* \
# ID/id2fp_mac_d_ff_reg* \
# ID/id2fp_mac_s_ff_reg* \
# ID/id2fp_misc_ff_reg* \
# ID/id2fp_sqrt_d_ff_reg* \
# ID/id2fp_sqrt_s_ff_reg* \
# ID/id2mul_ff_reg* \
# itlb_u/dff_sfence_req_reg* \
# }]
# set_multicycle_path -setup 5 -through [get_pins {EX/MUL/*}] -to [get_pins { \
# EX/MUL/DW_MULT_SEQ/* \
# EX/MUL/* \
# }]
# set_multicycle_path -hold 4 -through [get_cells {EX/MUL/*}] -to [get_cells { \
# EX/ex2ma_ff_reg* \
# EX/MUL/DW_MULT_SEQ*reg* \
# EX/MUL/* \
# ID/id2div_ff_reg* \
# ID/id2ex_ff_reg* \
# ID/id2ex_ff_reg* \
# ID/id2ex_fp_rs1_ff_reg* \
# ID/id2fp_add_d_ff_reg* \
# ID/id2fp_add_s_ff_reg* \
# ID/id2fp_div_d_ff_reg* \
# ID/id2fp_div_s_ff_reg* \
# ID/id2fp_mac_d_ff_reg* \
# ID/id2fp_mac_s_ff_reg* \
# ID/id2fp_misc_ff_reg* \
# ID/id2fp_sqrt_d_ff_reg* \
# ID/id2fp_sqrt_s_ff_reg* \
# ID/id2mul_ff_reg* \
# itlb_u/dff_sfence_req_reg* \
# }]
# set_multicycle_path -hold 4 -through [get_pins {EX/MUL/*}] -to [get_pins { \
# EX/MUL/DW_MULT_SEQ/* \
# EX/MUL/* \
# }]
# set ours(ff,fp) [get_cells -hier {id2ex_ctrl_ff_reg*fp_* id2fp_add_s_ff_reg* id2fp_add_d_ff_reg* id2fp_mac_s_ff_reg* id2fp_mac_d_ff_reg* id2fp_div_s_ff_reg* id2fp_div_d_ff_reg* id2fp_sqrt_s_ff_reg* id2fp_sqrt_d_ff_reg* id2fp_misc_ff_reg*}]
# set ours(ff,fpsqrt) [get_cells -hier {id2fp_sqrt_s_ff_reg*}]
# # multicycle for fp units
# set_multicycle_path -setup 32 -from $ours(ff,fp)
# set_multicycle_path -hold 31 -from $ours(ff,fp)
# set_multicycle_path -setup 33 -from $ours(ff,fpsqrt)
# set_multicycle_path -hold 32 -from $ours(ff,fpsqrt)
# set_multicycle_path -setup 10 -from [get_ports {*_pwr_on* *rst_pc*}]
# set_multicycle_path -hold 9 -from [get_ports {*_pwr_on* *rst_pc*}]
# ## END ORV64
# ## ORV64 <-> VP
# #set vcore(orv,vc) [get_cells -hier { *VCORE_DEC_U* *orv2vc* *vc2orv*}]
# ### set vcore(orv,vc) [get_pins -hier {*orv2vc* *vc2orv*}]
# ### set_multicycle_path -setup 6 -from $vcore(orv,vc)
# ### set_multicycle_path -hold 4 -from $vcore(orv,vc)
# ## END ORV64 <-> VP
# #
# #set_max_delay 1.0 -to _vector_core/u_FP__floatpoint/v_*___vector/regs__*__regs/regs_*__r/wq_reg/D
# #set_max_delay 1.0 -from _vector_core/u_FP__floatpoint/clk -to _vector_core/u_FP__floatpoint/v_*___vector/regs__*__regs/regs_*__r/wq_reg/D
# #**************************************************************
# # Set Maximum Delay
# #**************************************************************
# # assuming 14%
# set_input_delay [expr $clk_period * 0.5] -clock CLK [all_inputs]
# set_output_delay [expr $clk_period * 0.5] -clock CLK [all_outputs]
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************
#set_driving_cell -lib_cell BUFFD12BWP35P140HVT [all_inputs]
#set_load [get_attr [get_lib_pin tcbn28hpcplusbwp35p140hvtssg0p81vm40c_ccs/BUFFD12BWP35P140HVT/I] pin_capacitance] [all_outputs]
#set_input_transition $latency_input_transition [all_inputs]
#set_input_transition $latency_input_transition_clocks [get_ports clk]
#**************************************************************
# Set Load
#**************************************************************
#set_load [expr $clk_period * 0.01] [all_outputs]

139
flow/syn/tcl_scripts/file_to_list.tcl Normal file
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#!/bin/env tclsh
source [file join [file dirname [file normalize [info script]]] "parse_arg.tcl"]
source [file join [file dirname [file normalize [info script]]] "assert.tcl"]
proc resolve_env path {
regsub -all {\$\{?([^\s\/\{\}]+)\}?} $path {$::env(\1)} path
eval "set resolved $path"
return $resolved
}
proc file_to_list args {
parse_arg "-fpath(path)() -col(int)(1) -prefix(string)(.) -suffix(string)(.)" $args
if {![file isfile $fpath]} {
error "Error: file ($fpath) is missing"
}
set ls [list]
set f [open $fpath "r"]
while {[gets $f line] >= 0} {
set line [string trim $line]
if {[string length $line] == 0 || [string index $line 0] == "#" || [string range $line 0 1] == "//"} {
continue
}
regsub -all {\s+} $line " " line
set ls_line [split $line " "]
set item [lindex $ls_line [expr $col-1]]
lappend ls $item
}
close $f
if {$prefix != "."} {
set ls_new [list]
foreach item $ls {
lappend ls_new "${prefix}${item}"
}
set ls $ls_new
}
if {$suffix != "."} {
set ls_new [list]
foreach item $ls {
lappend ls_new "${item}${suffix}"
}
set ls $ls_new
}
return $ls
}
proc file_list_remove_duplicate {ls_fpath} {
set ls_new [list]
foreach fpath $ls_fpath {
set fpath_norm [file normalize $fpath]
if {[lsearch -exact $ls_new $fpath_norm] == -1} {
lappend ls_new $fpath_norm
}
}
return $ls_new
}
proc expand_file_list {file_list_fpath} {
if {![file isfile $file_list_fpath]} {
error "Error: file ($file_list_fpath) is missing"
}
set file_list_dpath [file dirname $file_list_fpath]
set ls_file [list]
set f [open $file_list_fpath "r"]
while {[gets $f line] >= 0} {
set line [string trim $line]
if {[string length $line] == 0 || [string index $line 0] == "#" || [string range $line 0 1] == "//"} {
continue
}
if {[string match +* $line]} {
continue
}
regsub -all {\s+} $line " " line
set ls_item [split $line " "]
if {[llength $ls_item] == 1} {
# single item
set fpath [lindex $ls_item 0]
set fpath [resolve_env $fpath]
if {[string index $fpath 0] == "/"} {
# absolute path
} else {
# relative path
set fpath [file join $file_list_dpath $fpath]
}
assert_exist $fpath
lappend ls_file $fpath
} elseif {[llength $ls_item] == 2} {
if {[lindex $ls_item 0] == "-f"} {
set fpath [resolve_env [lindex $ls_item 1]]
set nested_file_list_fpath [file join $file_list_dpath $fpath]
set ls_file [concat $ls_file [expand_file_list $nested_file_list_fpath]]
} elseif {[lindex $ls_item 0] == "-v"} {
set fpath [lindex $ls_item 1]
set fpath [resolve_env $fpath]
if {[string index $fpath 0] == "/"} {
# absolute path
} else {
# relative path
set fpath [file join $file_list_dpath $fpath]
}
assert_exist $fpath
lappend ls_file $fpath
} elseif {[lindex $ls_item 0] == "-y"} {
set path [resolve_env [lindex $ls_item 1]]
set ls_file [concat $ls_file [glob -nocomplain -directory $path *.sv]]
set ls_file [concat $ls_file [glob -nocomplain -directory $path *.v]]
} else {
error "Error: line ($line) is not recognized"
}
} else {
error "Error: line ($line) is not recognized"
}
}
close $f
return [file_list_remove_duplicate $ls_file]
}
if {[info exists argv0]} {
if {[file tail $argv0] == [file tail [info script]]} {
foreach fpath [expand_file_list [lindex $argv 0]] {
puts $fpath
}
}
}

130
flow/syn/tcl_scripts/parse_arg.tcl Normal file
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#!/bin/env tclsh
################################################################
# prase_arg
# ls_arg_definition
# one expected argument = "-${arg_name}(type)(default_value)"
# arg_name will be defined in up-level proc.
# To match defined arguments, we support shortcuts like Synopsys DC/PT/ICC
# type = <int|float|string|path|bool>
# default is the default value if it's not given in ls_arg.
# if default is empty, then this is a must-have argument.
# ls_arg can be $args for a proc or $argv for command line script
################################################################
proc parse_arg { ls_arg_definition ls_arg } {
# parse ls_arg_definition
set arg(name) {}
set usage "usage:\n"
foreach arg_def $ls_arg_definition {
if {[regexp {^-([_0-9a-zA-Z]+)\(([a-z]+)\)\((.*)\)$} $arg_def match arg_name arg_type default_value]} {
if {$default_value == ""} {
set default_value "NULL"
set optional "Must-have"
} else {
set optional "Optional"
}
set arg(name) [lappend arg(name) $arg_name]
set arg($arg_name,arg_type) $arg_type
set arg($arg_name,value) $default_value
uplevel set $arg_name $arg($arg_name,value)
# usage
set usage "$usage -$arg_name ($optional) TYPE=$arg_type; DEFAULT=$default_value\n"
} else {
error "Error: arg_definition ($arg_def) is not recognized"
}
}
# parse ls_arg
if {$ls_arg == "-help"} {
puts $usage
uplevel exit
}
if {$ls_arg == ""} {
set expect_arg_name -1
} else {
set expect_arg_name 1
}
while {$expect_arg_name >= 0} {
set input [lindex $ls_arg 0]
set ls_arg [lrange $ls_arg 1 end]
if {$expect_arg_name} {
# parse arg name
if {[regexp {^-([_0-9a-zA-Z]+)$} $input match input_arg_name]} {
set num_match 0
set match_arg_name ""
foreach arg_name $arg(name) {
if {[string match "${input_arg_name}*" $arg_name]} {
incr num_match 1
set match_arg_name $arg_name
}
}
if {$num_match == 0} {
# no match found
error "Error: argument ($input_arg_name) is not defined in ($ls_arg_definition)."
} elseif {$num_match > 1} {
# multi matches found
error "Error: argument ($input_arg_name) is too ambiguouse. $num_match matches are found."
} else {
# 1 match found
if {$arg($match_arg_name,arg_type) == "bool"} {
set arg($match_arg_name,value) 1
set expect_arg_name 1
} else {
set arg($match_arg_name,value) "NULL"
set expect_arg_name 0
}
}
} else {
error "Error: expecting argument name at ($input)"
}
} else {
# parse arg value
if {($arg($match_arg_name,arg_type) == "int" && ![regexp {^[0-9]+$} $input]) \
|| ($arg($match_arg_name,arg_type) == "float" && ![regexp {^[0-9]+\.[0-9]+} $input]) \
} {
error "Error: argument type is wrong. Expecting $arg($match_arg_name,arg_type) for $match_arg_name at ($input)"
} elseif {$arg($match_arg_name,arg_type) == "string"} {
regsub -all {\$} $input {\\$} input
regsub -all "\n" $input "\\n" input
regsub -all "\t" $input "\\t" input
regsub -all "\"" $input "\\\"" input
set arg($match_arg_name,value) "\"$input\""
} else {
set arg($match_arg_name,value) $input
}
set expect_arg_name 1
}
if {[llength $ls_arg] == 0} {
break
}
}
foreach arg_name $arg(name) {
if {$arg($arg_name,value) == "NULL"} {
error "Error: argument ($arg_name) has no value defined"
}
uplevel set $arg_name $arg($arg_name,value)
}
}
# test
if {[info exists argv0]} {
if {[file tail $argv0] == [file tail [info script]]} {
proc test_parse_arg args {
parse_arg "-num(int)(100) -input_file(path)() -output_file(path)() -is_cool(bool)(0) -some_string(string)(.)" $args
puts $num
puts $input_file
puts $output_file
puts $is_cool
puts "($some_string)"
}
test_parse_arg -num 123 -in ./input -out ../output -is_cool
test_parse_arg -num 123 -in ./input -out ../output
}
}

257
flow/syn/tcl_scripts/synth.tcl Normal file
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# choose pdk
# set SYN_PDK GF22
# set SYN_PDK T12
# choose synthesis top
# set SYN_TOP SINGLE_ROUTER
# set SYN_TOP MESH
# start
echo "RUN STARTED AT [date]"
if { $env(SYN_PDK)=="GF22" } {
# gf22n
source tcl_scripts/synth_init_lib.tcl
} elseif { $env(SYN_PDK)=="T12" } {
# t12n
source tcl_scripts/synth_init_library.t12.tcl
} else {
exit 1
}
#start from the path of Makefile rather than#
# set saving path of formality file
set DESIGN_NAME $env(DESIGN_NAME)
if { $env(SYN_TOP)=="MESH" } {
# mesh
set TOP_NAME top_mesh_syn
set FLIST_NAME flist_mesh.syn.f
} else {
# single_router
set TOP_NAME top_single_router_syn
set FLIST_NAME flist_single_router.syn.f
}
set_svf ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/output/${DESIGN_NAME}.synth.svf
# setup will be included in .synopsys_dc.setup file
source ./.synopsys_dc.setup
###################################################################
#------------------------Specify the libraries---------------------#
set_app_var search_path "$search_path ."
#license is needed#
if { $env(SYN_PDK)=="GF22" } {
# gf22n
set_app_var target_library [concat "$DB(ssg0p45v,m40c)"]
} elseif { $env(SYN_PDK)=="T12" } {
# t12n
set_app_var target_library [concat "$DB(ssg0p72v,125c)"]
} else {
exit 1
}
#.db, TODO: simplify the way of importing target libs#
#----designware setting-------#
set_app_var synthetic_library "dw_foundation.sldb"
set_dp_smartgen_options -hierarchy -smart_compare true -tp_oper_sel auto -tp_opt_tree auto -brent_kung_adder true -adder_radix auto -inv_out_adder_cell auto -mult_radix4 auto -sop2pos_transformation auto -mult_arch auto -optimize_for area,speed
#Analyzes DesignWare datapath extraction.#
set_app_var link_library "* $target_library $synthetic_library"
#all libs which might be used#
#------------------------- Read the design ------------------------#
#----------------------#
## read
### in dc_shell: read -format sverilog rtl.sv
### in tcl shell: read_verilog rtl.v; read_db lib.db
#---------------------#
## or analyze+elaborate+WORK dir(default)
define_design_lib WORK -path ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/WORK
#can be omitted#
source tcl_scripts/file_to_list.tcl
analyze -format sverilog [concat [expand_file_list "$env(PROJ_ROOT)/tb/${FLIST_NAME}"]]
#analyze HDL source code and save intermediate results named .syn in ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/work dir, which can be used by elaborate directly even without anlyzing; TODO: what does es1y_define.sv mean?#
elaborate ${TOP_NAME}
# write_file -hierarchy -format verilog -output output/rvh1.synth.elaborate.v
#for dbg#
current_design ${TOP_NAME}
link
#not necessary after anal. and elab.?, link lib has been defined before#
analyze_datapath_extraction -no_autoungroup
#-------------------- Define the design environment -------------------#
# set_load 2.2 sout
# set_load 1.5 cout
# set_driving_cell -lib_cell FD1 [all_inputs]
#---------------------- Set the design constraints --------------------#
## Design Rule constraints
# set_max_transistion
# set_max_fanout
# set_max_capacitance
#provided by foundary company, can be setted tightly in advance; TODO: get precise indicators#
## Set the optimization constraints
#----delay----#
#----area-----#
set_host_options -max_cores 16
source tcl_scripts/constraints.sdc
set_clock_transition 0.1 [all_clocks]
set_critical_range 10 [current_design]
group_path -weight 0.1 -name input_path -from [all_inputs]
group_path -weight 0.1 -name output_path -to [all_outputs]
group_path -weight 0.1 -name in2out -from [all_inputs] -to [all_outputs]
set_dynamic_optimization false
set_leakage_optimization false
set compile_timing_high_effort true
set placer_tns_driven true
set psynopt_tns_high_effort true
set compile_timing_high_effort_tns true
set_cost_priority -delay
puts "TIMESTAMP Pre-Compile [clock format [clock second ] -format %T] [expr [mem] /1024]M"
set compile_final_drc_fix all
set compile_automatic_clock_phase_inference relaxed
set compile_enable_constant_propagation_with_no_boundary_opt true
set compile_advanced_fix_multiple_port_nets true
set compile_rewire_multiple_port_nets true
set_fix_multiple_port_nets -all -buffer_constants [get_designs *]
set_auto_disable_drc_nets -clock true -constant true -on_clock_network true
#copied from original /script/vp_fp.03-05-2020_20.30.59.sdc, TODO: define accurate constraints and optimizations#
# write_sdc output/rvh1.synth.elaborate.sdc
# report_clock_tree -structure > rpt/clock_tree_structure.rpt
#for dbg#
#--------------------- Define clock gating -------------------------#
set_clock_gating_style -sequential_cell latch -positive_edge_logic {integrated} -negative_edge_logic {integrated} \
-control_point before -control_signal scan_enable \
-minimum_bitwidth 4 -observation_point false \
-max_fanout 16
set_clock_latency 0 [all_clocks]
set_clock_gate_latency -overwrite -stage 0 -fanout_latency {1-inf 0}
set_clock_gate_latency -overwrite -stage 1 -fanout_latency {1-inf -0.05}
set_clock_gate_latency -overwrite -stage 2 -fanout_latency {1-inf -0.1}
set_clock_gate_latency -overwrite -stage 3 -fanout_latency {1-inf -0.15}
set_clock_gate_latency -overwrite -stage 4 -fanout_latency {1-inf -0.2}
set_clock_gate_latency -overwrite -stage 5 -fanout_latency {1-inf -0.25}
set ALL_INPUTS [all_inputs]
foreach_in_collection INPUTS $ALL_INPUTS {
append_to_collection -unique INPUT_REG [ filter_collection [all_fanout -from $INPUTS -flat -endpoints_only] "full_name =~ */synch_toggle || full_name =~ */synch_preset || full_name =~ */synch_enable || full_name =~ */synch_clear || full_name =~ */next_state "]
}
set_clock_gating_objects -exclude [get_cells -of_object $INPUT_REG]
#--------------------- Select compile strategy -------------------------#
#--------------------- Synthesize and optimize the design ------------------------#
# echo [get_object_name [get_lib_cells */* -filter dont_use==true]] > rpt/dont_use_list.rpt
# check_design > rpt/check_design.precompile.rpt
#for dbg#
set_verification_top
#set_dynamic_optimization true
#run 2 times compile_ultra
compile_ultra -gate_clock -retime -no_autoungroup -no_boundary_optimization
compile_ultra -gate_clock -retime -no_autoungroup -no_boundary_optimization
#compile_ultra (of DC Ultra) provides concurrent optimization of timing, area, power, and test for high performance designs#
#it also provides advanced delay and arithmetic optimization, advanced timing analysis, automatic leakage power optimization, and register retiming#
#--------------------- Analyze and debug the design/resolve design problems --------------------#
analyze_datapath > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/datapath.compile.rpt
report_resources > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/resources.compile.rpt
write_file -hierarchy -format verilog -output ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/output/rvh1.synth.compile.v
write_sdc ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/output/rvh1.synth.compile.sdc
update_timing
report_timing -nosplit > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/timing.compile.rpt
report_area -nosplit -hier > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/area.hier.compile.rpt
check_design > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/check_design.preopt.rpt
optimize_netlist -area -no_boundary_optimization
check_design > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/check_design.postopt.rpt
define_name_rules preserve_struct_bus_rule -preserve_struct_ports
define_name_rules ours_verilog_name_rule -allowed "a-z A-Z 0-9 _" \
-check_internal_net_name \
-case_insensitive
change_names -rules preserve_struct_bus_rule -hierarchy -log_changes ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/struct_name_change.log
change_names -rules ours_verilog_name_rule -hierarchy -log_changes ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/legalize_name_change.log
write -format verilog -hierarchy -output ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/output/rvh1.synth.final.v
write -format ddc -hierarchy -output ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/output/rvh1.synth.final.ddc
write_sdc -nosplit ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/output/rvh1.synth.final.sdc
report_clock_gating > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/clock_gating.rpt
report_timing -tran -net -input -max_paths 500 -significant_digits 3 -nosplit > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/synth.timing.rpt
report_timing -delay_type min -max_paths 500 -input_pins -nets -transition_time -capacitance -significant_digits 3 > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/synth.min_delay.rpt
report_timing -delay_type max -max_paths 500 -input_pins -nets -transition_time -capacitance -significant_digits 3 > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/synth.max_delay.rpt
report_constraint -all_violators -significant_digits 3 > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/synth.all_viol_constraints.rpt
report_area -nosplit -hier > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/synth.area.hier.rpt
report_resources -nosplit -hier > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/synth.resources.rpt
report_timing_requirements > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/synth.mulcycle.rpt
report_compile_options -nosplit > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/synth.compile_options.rpt
#report_timing -tran -net -input -max_paths 1000 > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/timing.rpt
report_clock_gating -nosplit -verbose -multi_stage > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/clock_gating.rpt
report_clock_gating -gated -nosplit -verbose > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/clock_gating_gated.rpt
report_clock_gating -ungated -nosplit -verbose > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/clock_ungating_gated.rpt
report_power -nosplit > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/power.rpt
report_qor > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/qor.rpt
#report_area -hierarchy > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/area.rpt
#report_constraint -all_violators -verbose -max_capacitance -max_transition > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/drc.rpt
report_clocks > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/clock.rpt
check_design -unmapped > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/check_design.rpt
#check_timing -include {clock_no_period data_check_no_clock generated_clock generic} ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/check_timing.rpt
report_dont_touch -nosplit -class cell > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/dont_touch.rpt
report_threshold_voltage_group > ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/rpt/threshold_voltage_group.rpt
#--------------------- Save the design database ---------------------#
write_file -format ddc -hierarchy -output ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/output/${DESIGN_NAME}.ddc
#.ddc is the whole project, can be modified and checked#
write_file -format verilog -hierarchy -output ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/output/${DESIGN_NAME}_netlist.v
#netlist.v for P&R and sim#
#write_sdf ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/output/${DESIGN_NAME}_sdf
#recording the latency of std cells, also useful for post-sim#
#write_parasitics -output ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/output/${DESIGN_NAME}_parasitics
#Writes parasitics in SPEF format or as a Tcl script that contains set_load and set_resistance commands.#
# write_sdc sdc_file_name
#Writes out a script in Synopsys Design Constraints (SDC) format.#
#This script contains commands that can be used with PrimeTime or with Design Compiler. SDC is also licensed by external vendors through the Tap-in program. SDC-formatted script files are read into PrimeTime or Design Compiler using the read_sdc command.#
# write_floorplan -all ./$env(TIMESTAMP)_$env(SYN_PDK)_$env(SYN_TOP)_run/output/${DESIGN_NAME}_phys_cstr_file_name.tcl
#writes a Tcl script file that contains floorplan information for the current or user-specified design. writes commands relative to the top of the design, regardless of the current instance.#
#-------------------------------------------------------------------#
echo "RUN ENDED AT [date]"

4
flow/syn/tcl_scripts/synth_init_lib.tcl Normal file
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set DB(ssg0p45v,m40c) {
/work/tech/GF22FDX/LIB/DesignWare_logic_libs/globalfoundaries22nhsda/36hd/edl/ulvt/4.00a/liberty/ccs/gf22nsdvlogl36edl116a_TT_0P80V_0P00V_0P00V_0P00V_25C.db \
/work/tech/GF22FDX/LIB/DesignWare_logic_libs/globalfoundaries22nhsda/24hd/edl/lvt/4.00a/liberty/ccs/gf22nsdllogl24edl116a_TT_0P80V_0P00V_0P00V_0P00V_25C.db \
}

57
flow/syn/tcl_scripts/synth_init_library.t12.tcl Executable file
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@@ -0,0 +1,57 @@
set DB(ssg0p72v,125c) {
/work/tech/t12nm/Mem/db/ts1n12ffcllsblvtd128x32m4swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllsblvtd640x34m4swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta1024x128m4swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta1024x64m4swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta1024x72m4swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta1024x76m4swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta1024x80m4swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta128x256m2swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta128x262m2swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta128x32m2swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta128x51m4swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta128x59m4swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta128x82m4swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta128x88m4swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta16384x30m16swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta16384x32m16swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta16384x39m16swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta16x88m2swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta2048x128m4swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta2048x66m4swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta2048x98m4swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta256x80m4swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta32x86m4swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta4096x32m4swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta4096x32m8swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta4096x64m4swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta512x78m4swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta64x84m4swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts1n12ffcllulvta8192x32m8swbsho_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts3n12ffcllulvta1024x64m16bo_130b_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts6n12ffcllulvta1088x34m8fwbsho_150a_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts6n12ffcllulvta288x68m2fwbsho_150a_ssgnp0p72v125c.db \
/work/tech/t12nm/Mem/db/ts6n12ffcllulvta368x34m2fwbsho_150a_ssgnp0p72v125c.db \
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}