initial commit for open source NoC IP

rtl/model/cells/rrv64_cell_clkgate.v

@@ -0,0 +1,30 @@
+module rrv64_cell_clkgate (
+    input wire clk_i,
+    input wire clk_enable_i,
+    input wire clk_senable_i,
+    output wire clk_gated_o
+);
+
+// CKGATE
+// CKGATE_inst
+//     (
+//         .cko (clk_gated_o),
+//         .cki (clk_i      ),
+//         .e   (clk_enable_i),
+//         .te  (clk_senable_i),   
+//     );
+
+    wire clk_en;
+    reg clk_en_reg;
+
+    assign clk_en = clk_enable_i | clk_senable_i;
+
+    always @ (clk_i or clk_en) begin
+        if(clk_i == 1'b0) begin
+            clk_en_reg <= clk_en;
+        end
+    end
+
+    assign clk_gated_o = clk_i & clk_en_reg;
+
+endmodule

rtl/model/cells/std_dff.sv

@@ -0,0 +1,27 @@
+//===============================================
+//Name          : STD_DFF
+//Author        : cuiluping
+//Email         : luping.cui@rivai-ic.com.cn
+//Date          : 2019-08-24
+//Description   : no reset no enable D flip flop
+//-----------------------------------------------
+//All Rights Reserved by rivai company
+//===============================================
+
+module std_dff
+#(
+    parameter WIDTH = 8
+)
+(
+    input                       clk,
+    input       [WIDTH-1:0]     d,
+    output      [WIDTH-1:0]     q
+);
+
+logic [WIDTH-1:0]   dff_q;
+always_ff @(posedge clk) begin
+    dff_q <= d;
+end
+
+assign  q = dff_q;
+endmodule

rtl/model/cells/std_dffe.sv

@@ -0,0 +1,31 @@
+//===============================================
+//Name          : STD_DFFE
+//Author        : cuiluping
+//Email         : luping.cui@rivai-ic.com.cn
+//Date          : 2019-08-24
+//Description   : no reset ,with enable D flip flop
+//-----------------------------------------------
+//All Rights Reserved by rivai company
+//===============================================
+
+module std_dffe
+#(
+    parameter WIDTH = 8
+)
+(
+    input                       clk,
+    input                       en,
+    input       [WIDTH-1:0]     d,
+    output      [WIDTH-1:0]     q
+);
+
+logic    [WIDTH-1:0] dff_q;
+
+always_ff @(posedge clk) begin
+    if(en) begin
+        dff_q <= d;
+    end
+end
+assign  q = dff_q;
+
+endmodule

rtl/model/cells/std_dffr.sv

@@ -0,0 +1,34 @@
+//===============================================
+//Name          : STD_DFFR
+//Author        : cuiluping
+//Email         : luping.cui@rivai-ic.com.cn
+//Date          : 2019-08-24
+//Description   : with reset ,no enable D flip flop
+//-----------------------------------------------
+//All Rights Reserved by rivai company
+//===============================================
+
+module std_dffr
+#(
+    parameter WIDTH = 8
+)
+(
+    input                       clk,
+    input                       rstn,
+    input       [WIDTH-1:0]     d,
+    output      [WIDTH-1:0]     q
+);
+
+logic    [WIDTH-1:0] dff_q;
+
+always_ff @(posedge clk or negedge rstn) begin
+    if(~rstn)begin
+        dff_q <= {WIDTH{1'b0}};
+    end
+    else begin
+        dff_q <= d;
+    end
+end
+
+assign  q = dff_q;
+endmodule

rtl/model/cells/std_dffre.sv

@@ -0,0 +1,36 @@
+//===============================================
+//Name          : STD_DFFRE
+//Author        : cuiluping
+//Email         : luping.cui@rivai-ic.com.cn
+//Date          : 2019-08-24
+//Description   : with reset ,with enable D flip flop
+//-----------------------------------------------
+//All Rights Reserved by rivai company
+//===============================================
+
+module std_dffre
+#(
+    parameter WIDTH = 8
+)
+(
+    input                       clk,
+    input                       rstn,
+    input                       en,
+    input       [WIDTH-1:0]     d,
+    output      [WIDTH-1:0]     q
+);
+
+logic     [WIDTH-1:0]     dff_q;
+
+always_ff @(posedge clk or negedge rstn) begin
+    if(~rstn)begin
+        dff_q <= {WIDTH{1'b0}};
+    end
+    else if(en)begin
+        dff_q <= d;
+    end
+end
+
+assign  q = dff_q;
+
+endmodule

rtl/model/cells/std_dffrve.sv

@@ -0,0 +1,38 @@
+//===============================================
+//Name          : STD_DFFRVE
+//Author        : cuiluping
+//Email         : luping.cui@rivai-ic.com.cn
+//Date          : 2019-08-24
+//Description   : with reset ,with enable D flip flop,
+//                reset value can be configured
+//-----------------------------------------------
+//All Rights Reserved by rivai company
+//===============================================
+
+module std_dffrve
+#(
+    parameter WIDTH = 8
+)
+(
+    input                       clk,
+    input                       rstn,
+    input       [WIDTH-1:0]     rst_val,
+    input                       en,
+    input       [WIDTH-1:0]     d,
+    output      [WIDTH-1:0]     q
+);
+
+logic    [WIDTH-1:0]     dff_q;
+
+always_ff @(posedge clk or negedge rstn) begin
+    if(~rstn)begin
+        dff_q <= rst_val;
+    end
+    else if(en)begin
+        dff_q <= d;
+    end
+end
+
+assign  q = dff_q;
+
+endmodule

rtl/model/simple_dual_one_clock.v

@@ -0,0 +1,47 @@
+// Simple Dual-Port Block RAM with One Clock
+// reference: https://docs.xilinx.com/r/en-US/ug901-vivado-synthesis/Single-Port-Block-RAM-No-Change-Mode-Verilog
+// File: simple_dual_one_clock.v
+
+module simple_dual_one_clock 
+#(
+  parameter ADDR_BITS   = 4,
+  parameter DATA_BITS   = 8
+  // parameter RAM_LATENCY = 1,
+  // parameter WE_SIZE     = 1,
+
+)
+(clk,ena,enb,wea,addra,addrb,dia,dob);
+
+input clk,ena,enb,wea;
+
+input [ADDR_BITS-1:0] addra,addrb;
+
+input [DATA_BITS-1:0] dia;
+
+output [DATA_BITS-1:0] dob;
+
+reg [DATA_BITS-1:0] ram [(1'b1<<ADDR_BITS)-1:0];
+
+reg [DATA_BITS-1:0] doa,dob;
+
+always @(posedge clk) begin
+
+if (ena) begin
+
+if (wea)
+
+ram[addra] <= dia;
+
+end
+
+end
+
+always @(posedge clk) begin
+
+if (enb)
+
+dob <= ram[addrb];
+
+end
+
+endmodule