initial commit for open source NoC IP
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43
rtl/priority_req_select.sv
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43
rtl/priority_req_select.sv
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// select req(s) with the highest priority from the req input vector
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module priority_req_select
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import rvh_noc_pkg::*;
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#(
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parameter INPUT_NUM = 4,
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parameter INPUT_NUM_IDX_W = INPUT_NUM > 1 ? $clog2(INPUT_NUM) : 1,
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parameter INPUT_PRIORITY_W = 4
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)
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(
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input logic [INPUT_NUM-1:0] req_vld_i,
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input logic [INPUT_NUM-1:0][INPUT_PRIORITY_W-1:0] req_priority_i,
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output logic [INPUT_NUM-1:0] req_vld_o
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);
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genvar i,j;
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// x >= y -> 1 else 0
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// req_vld_i pri 3 9 2 8 & req_vld_o
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// 1 3 1 1 1 0 0 0
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// 0 9 0 0 0 0 0 0
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// 1 2 0 1 1 0 0 0
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// 1 8 1 1 1 1 1 1
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logic [INPUT_NUM-1:0][INPUT_NUM-1:0] priority_compare_vector;
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generate
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for(i = 0; i < INPUT_NUM; i++) begin: gen_priority_compare_vector_i
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for(j = 0; j < INPUT_NUM; j++) begin: gen_priority_compare_vector_j
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if (i == j) begin: gen_diagonal
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assign priority_compare_vector[i][j] = req_vld_i[i];
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end else begin: gen_others
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assign priority_compare_vector[i][j] = ~req_vld_i[j] | (req_priority_i[i] >= req_priority_i[j]);
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end
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end
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end
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endgenerate
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generate
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for(i = 0; i < INPUT_NUM; i++) begin: gen_req_vld_o
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assign req_vld_o[i] = &(priority_compare_vector[i]);
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end
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endgenerate
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endmodule
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