initial commit for open source NoC IP
This commit is contained in:
Zexin Fu
467
rtl/ruby/ut_lib.sv
Executable file
467
rtl/ruby/ut_lib.sv
Executable file
@@ -0,0 +1,467 @@
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`define LFSR_HIGH_16BIT_ENABLE
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module LFSR #(parameter NUM_BITS)
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(
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input i_Clk,
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input i_Enable,
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//Optional Seed Value
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input i_Seed_DV,
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input [NUM_BITS-1:0] i_Seed_Data,
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output[NUM_BITS-1:0] o_LFSR_Data,
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output o_LFSR_Done
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);
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reg [NUM_BITS:1] r_LFSR = 0;
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reg r_XNOR;
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always @(posedge i_Clk or negedge i_Enable)
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begin
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if(~i_Enable) begin
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r_LFSR <= i_Seed_Data;
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end else if (i_Seed_DV == 1'b1) begin
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r_LFSR <= i_Seed_Data;
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end else begin
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r_LFSR <= {r_LFSR[NUM_BITS-1:1],r_XNOR};
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end
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end
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// Linear Feedback Shift Register Taps refer to https://docs.xilinx.com/v/u/en-US/xapp052
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// use same or becaure the default seed can be '0, and should not be '1
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always @(*)
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begin
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case (NUM_BITS)
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2: begin
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r_XNOR = r_LFSR[2] ^ ~r_LFSR[1];
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end
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3: begin
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r_XNOR = r_LFSR[3] ^ ~r_LFSR[2];
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end
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4: begin
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r_XNOR = r_LFSR[4] ^ ~r_LFSR[3];
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end
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5: begin
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r_XNOR = r_LFSR[5] ^ ~r_LFSR[3];
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end
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6: begin
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r_XNOR = r_LFSR[6] ^ ~r_LFSR[5];
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end
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7: begin
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r_XNOR = r_LFSR[7] ^ ~r_LFSR[6];
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end
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8: begin
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r_XNOR = r_LFSR[8] ^ ~r_LFSR[6] ^ ~r_LFSR[5] ^ ~r_LFSR[4];
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end
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9: begin
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r_XNOR = r_LFSR[9] ^ ~r_LFSR[5];
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end
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10: begin
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r_XNOR = r_LFSR[10] ^ ~r_LFSR[7];
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end
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11: begin
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r_XNOR = r_LFSR[11] ^ ~r_LFSR[9];
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end
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12: begin
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r_XNOR = r_LFSR[12] ^ ~r_LFSR[6] ^ ~r_LFSR[4] ^ ~r_LFSR[1];
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end
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13: begin
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r_XNOR = r_LFSR[13] ^ ~r_LFSR[4] ^ ~r_LFSR[3] ^ ~r_LFSR[1];
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end
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14: begin
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r_XNOR = r_LFSR[14] ^ ~r_LFSR[5] ^ ~r_LFSR[3] ^ ~r_LFSR[1];
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end
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15: begin
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r_XNOR = r_LFSR[15] ^ ~r_LFSR[14];
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end
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16: begin
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r_XNOR = r_LFSR[16] ^ ~r_LFSR[15] ^ ~r_LFSR[13] ^ ~r_LFSR[4];
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end
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`ifdef LFSR_HIGH_16BIT_ENABLE
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17: begin
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r_XNOR = r_LFSR[17] ^ ~r_LFSR[14];
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end
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18: begin
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r_XNOR = r_LFSR[18] ^ ~r_LFSR[11];
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end
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19: begin
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r_XNOR = r_LFSR[19] ^ ~r_LFSR[6] ^ ~r_LFSR[2] ^ ~r_LFSR[1];
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end
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20: begin
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r_XNOR = r_LFSR[20] ^ ~r_LFSR[17];
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end
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21: begin
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r_XNOR = r_LFSR[21] ^ ~r_LFSR[19];
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end
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22: begin
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r_XNOR = r_LFSR[22] ^ ~r_LFSR[21];
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end
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23: begin
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r_XNOR = r_LFSR[23] ^ ~r_LFSR[18];
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end
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24: begin
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r_XNOR = r_LFSR[24] ^ ~r_LFSR[23] ^ ~r_LFSR[22] ^ ~r_LFSR[17];
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end
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25: begin
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r_XNOR = r_LFSR[25] ^ ~r_LFSR[22];
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end
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26: begin
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r_XNOR = r_LFSR[26] ^ ~r_LFSR[6] ^ ~r_LFSR[2] ^ ~r_LFSR[1];
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end
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27: begin
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r_XNOR = r_LFSR[27] ^ ~r_LFSR[5] ^ ~r_LFSR[2] ^ ~r_LFSR[1];
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end
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28: begin
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r_XNOR = r_LFSR[28] ^ ~r_LFSR[25];
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end
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29: begin
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r_XNOR = r_LFSR[29] ^ ~r_LFSR[27];
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end
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30: begin
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r_XNOR = r_LFSR[30] ^ ~r_LFSR[6] ^ ~r_LFSR[4] ^ ~r_LFSR[1];
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end
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31: begin
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r_XNOR = r_LFSR[31] ^ ~r_LFSR[28];
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end
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32: begin
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r_XNOR = r_LFSR[32] ^ ~r_LFSR[22] ^ ~r_LFSR[2] ^ ~r_LFSR[1];
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end
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64: begin
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r_XNOR = r_LFSR[64] ^ ~r_LFSR[63] ^ ~r_LFSR[61] ^ ~r_LFSR[60];
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end
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80: begin
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r_XNOR = r_LFSR[80] ^ ~r_LFSR[79] ^ ~r_LFSR[43] ^ ~r_LFSR[42];
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end
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128: begin
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r_XNOR = r_LFSR[128] ^ ~r_LFSR[126] ^ ~r_LFSR[101] ^ ~r_LFSR[99];
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end
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168: begin
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r_XNOR = r_LFSR[168] ^ ~r_LFSR[166] ^ ~r_LFSR[153] ^ ~r_LFSR[151];
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end
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`endif
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default: begin
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r_XNOR = '0;
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end
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endcase
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end
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assign o_LFSR_Data = r_LFSR[NUM_BITS:1];
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assign o_LFSR_Done = (r_LFSR[NUM_BITS:1] == i_Seed_Data) ? 1'b1 : 1'b0;
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endmodule
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module id_pool_2w1r
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#( parameter depth=8,
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parameter width=32,
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parameter ptr_sz=$clog2(depth)
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)
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(
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input logic clk,
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input logic rst_n,
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input logic [1:0] c_srdy,
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output logic [1:0] c_drdy,
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input logic [1:0][width-1:0] c_data,
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output logic p_srdy,
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input logic p_drdy,
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output logic [width-1:0] p_data,
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output logic [ptr_sz:0] usage
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);
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localparam depth_sub_1 = depth-1;
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localparam depth_sub_2 = depth-2;
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logic [ptr_sz-1:0] wr_addr_d;
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logic [ptr_sz-1:0] rd_addr_d;
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logic [ptr_sz-1:0] wr_addr_q;
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logic [ptr_sz-1:0] rd_addr_q;
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logic [depth-1:0][width-1:0] array_d;
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logic [depth-1:0][width-1:0] array_q;
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logic [ptr_sz:0] occupy_cnt_d;
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logic [ptr_sz:0] occupy_cnt_q;
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logic full;
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logic empty;
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logic wr_2_en;
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logic wr_2_vld;
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logic wr_en;
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logic rd_en;
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logic [ptr_sz-1:0] wr_addr_p1;
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assign c_drdy = wr_2_vld ? 2'b11 : (occupy_cnt_q == depth_sub_1) ? ((c_srdy == 2'b10) ? 2'b10 : 2'b01) : '0;
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assign p_srdy = ~empty;
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assign p_data = array_q[rd_addr_q];
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assign empty = (occupy_cnt_q == '0);
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assign full = (occupy_cnt_q == depth[ptr_sz:0]);
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assign rd_en = p_drdy & ~empty;
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assign wr_en = (c_srdy[0] | c_srdy[1]) & ~full;
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assign wr_2_vld = (occupy_cnt_q < depth_sub_1);
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assign wr_2_en = (c_srdy == 2'b11) & wr_2_vld;
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assign rd_addr_d = rd_en ? ((rd_addr_q == depth_sub_1) ? '0 : rd_addr_q+1) : rd_addr_q;
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assign wr_addr_p1 = (wr_addr_q == depth_sub_1) ? '0 : wr_addr_q+1;
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assign wr_addr_d = wr_2_en ? ((wr_addr_q == depth_sub_1) ? ptr_sz'('d1) : (wr_addr_q == depth_sub_2) ? '0 : wr_addr_q+2) : wr_en ? wr_addr_p1 : wr_addr_q;
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always_comb begin
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occupy_cnt_d = occupy_cnt_q;
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case ({wr_2_en,wr_en,rd_en})
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3'b110: begin
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occupy_cnt_d = occupy_cnt_q+{{(ptr_sz-1){1'b0}},2'd2};
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end
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3'b111: begin
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occupy_cnt_d = occupy_cnt_q+{{(ptr_sz){1'b0}},1'b1};
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end
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3'b010: begin
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occupy_cnt_d = occupy_cnt_q+{{(ptr_sz){1'b0}},1'b1};
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end
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3'b001: begin
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occupy_cnt_d = occupy_cnt_q-{{(ptr_sz){1'b0}},1'b1};
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end
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endcase
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end
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std_dffr #(ptr_sz) FF_WR_ADDR (.clk(clk) ,.rstn(rst_n),.d(wr_addr_d),.q(wr_addr_q));
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std_dffr #(ptr_sz) FF_RD_ADDR (.clk(clk) ,.rstn(rst_n),.d(rd_addr_d),.q(rd_addr_q));
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std_dffrve #(ptr_sz+1) FF_OCCUPY_CNT (.clk(clk),.rstn(rst_n),.rst_val(depth),.en(1'b1),.d(occupy_cnt_d),.q(occupy_cnt_q));
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generate
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for (genvar ii=0; ii<depth ;ii++) begin
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assign array_d[ii] = ((wr_addr_q == ii[ptr_sz-1:0]) & wr_en) ? (c_srdy[0] ? c_data[0] : c_data[1]) :
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((wr_addr_p1 == ii[ptr_sz-1:0]) & wr_2_en) ? c_data[1] :
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array_q[ii];
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std_dffrve #(width) FF_ARRAY (.clk(clk) ,.rstn(rst_n) ,.rst_val(ii) ,.en(1'b1) ,.d(array_d[ii]) ,.q(array_q[ii]));
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end
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endgenerate
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assign usage = occupy_cnt_q;
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endmodule
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// module sd_id_pool
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// #( parameter depth=8,
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// parameter width=32,
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// parameter ptr_sz=$clog2(depth)
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// )
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// (
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// input clk,
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// input rst,
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// input c_srdy,
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// output c_drdy,
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// input[width-1:0] c_data,
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// output p_srdy,
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// input p_drdy,
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// output[width-1:0] p_data,
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// output[ptr_sz:0] usage
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// );
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// localparam depth_sub_1 = depth-1;
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// logic wr_en;
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// logic rd_en;
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// logic [ptr_sz-1:0] wr_addr;
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// logic [ptr_sz-1:0] rd_addr;
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// logic [ptr_sz-1:0] nxt_wr_addr;
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// logic [ptr_sz-1:0] nxt_rd_addr;
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// logic [depth-1:0][width-1:0] array;
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// logic [ptr_sz:0] occupy_cnt;
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// logic [ptr_sz:0] nxt_occupy_cnt;
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// logic full;
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// logic empty;
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// assign wr_en = c_srdy & ~full;
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// assign rd_en = p_srdy & p_drdy;
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// genvar ii;
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// generate
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// for(ii=0; ii<depth;ii=ii+1) begin: array_entry_ii
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// always @(posedge clk) begin
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// if (rst) begin
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// array[ii] <= ii[width-1:0];
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// end
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// else begin
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// if ((wr_addr==ii[ptr_sz-1:0]) & wr_en)
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// array[ii] <= c_data;
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// end
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// end
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// end
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// endgenerate
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// assign p_data = array[rd_addr];
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// assign nxt_wr_addr = (wr_en) ? ((wr_addr==depth_sub_1[ptr_sz-1:0]) ? {ptr_sz{1'b0}} : wr_addr+1'b1) : wr_addr;
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// always @(posedge clk) begin
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// if (rst)
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// wr_addr <= {ptr_sz{1'b0}};
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// else
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// wr_addr <= nxt_wr_addr;
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// end
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// assign nxt_rd_addr = (rd_en) ? ((rd_addr==depth_sub_1[ptr_sz-1:0]) ? {ptr_sz{1'b0}} : rd_addr+1'b1) : rd_addr;
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// always @(posedge clk) begin
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// if (rst)
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// rd_addr <= {ptr_sz{1'b0}};
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// else
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// rd_addr <= nxt_rd_addr;
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// end
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// always @* begin
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// case ({wr_en, rd_en})
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// 2'b00: begin
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// nxt_occupy_cnt = occupy_cnt;
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// end
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// 2'b01: begin
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// nxt_occupy_cnt = occupy_cnt-1'b1;
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// end
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// 2'b10: begin
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// nxt_occupy_cnt = occupy_cnt+1'b1;
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// end
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// 2'b11: begin
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// nxt_occupy_cnt = occupy_cnt;
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// end
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// endcase
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// end
|
||||
|
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// always @(posedge clk) begin
|
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// if(rst) begin
|
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// occupy_cnt <= depth[ptr_sz:0];
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// end
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// else begin
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// occupy_cnt <= nxt_occupy_cnt;
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// end
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// end
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// assign empty = (occupy_cnt == {(ptr_sz+1){1'b0}}) ? 1'b1 : 1'b0;
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// assign full = (occupy_cnt == depth[ptr_sz:0]) ? 1'b1 : 1'b0;
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// assign c_drdy = ~full;
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// assign p_srdy = ~empty;
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// assign usage = occupy_cnt;
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// endmodule
|
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|
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// module rrv64_vld_rdy_rr_arb #(
|
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// parameter BACKEND_DOMAIN = 0,
|
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// parameter N_INPUT = 2
|
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// )(
|
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// input logic [N_INPUT-1:0] vld,
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// input logic rdy,
|
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// output logic [N_INPUT-1:0] grt,
|
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// input logic rstn,clk
|
||||
// );
|
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// localparam N_INPUT_BITS = $clog2(N_INPUT);
|
||||
|
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// typedef enum logic {
|
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// ST_PASS_THROUGH,
|
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// ST_HOLD
|
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// } vld_rdy_rr_arb_st_t;
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|
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// generate
|
||||
// if(N_INPUT==1) begin
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// assign grt = vld;
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// end else begin
|
||||
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// vld_rdy_rr_arb_st_t rff_state, next_state;
|
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// logic [N_INPUT_BITS-1:0] rrf_last_grt_id, grt_id;
|
||||
// logic [N_INPUT-1:0] vld_with_priority;
|
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// logic [N_INPUT-1:0] grt_with_priority, next_grt, rff_grt;
|
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// logic do_save_grt;
|
||||
|
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// // vld_with_priority
|
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// always_comb begin
|
||||
// vld_with_priority = vld;
|
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// if (rff_last_grt_id != N_INPUT_BITS'(N_INPUT-1)) begin
|
||||
// for(int i = 0;i < N_INPUT; i++) begin
|
||||
// if(i > rff_last_grt_id) begin
|
||||
// vld_with_priority[i - rff_last_grt_id - 1'b1] = vld[i];
|
||||
// end else begin
|
||||
// vld_with_priority[N_INPUT - rff_last_grt_id - 1'b1 + i] = vld[i];
|
||||
// end
|
||||
// end
|
||||
// end
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||||
// end
|
||||
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||||
// //grt_with_priority
|
||||
// always_comb begin
|
||||
// grt_with_priority = {N_INPUT{1'b0}}:
|
||||
// if (|vld_with_priority) begin
|
||||
// for (int i = 0; i < N_INPUT; i++) begin
|
||||
// if (vld_with_priority[i] == 1'b1) begin
|
||||
// grt_with_priority[i] = 1'b1;
|
||||
// break;
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
|
||||
// // next_grt
|
||||
// always_comb begin
|
||||
// if(rff_last_grt_id == N_INPUT_BITS'(N_INPUT-1)) begin
|
||||
// next_grt = grt_with_priority;
|
||||
// end else begin
|
||||
// for(int i = 0; i < N_INPUT;i++) begin
|
||||
// if(i > rff_last_grt_id) begin
|
||||
// next_grt[i] = grt_with_priority[i - rff_last_grt_id - 1'b1];
|
||||
// end else begin
|
||||
// next_grt[i] = grt_with_priority[N_INPUT - rff_last_grt_id - 1'b1 + i];
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
|
||||
// // Grant Update
|
||||
// always_ff @(posedge clk or negedge rstn) begin
|
||||
// if (!rstn) begin
|
||||
// rff_grt <= '0;
|
||||
// end else begin
|
||||
// if (do_save_grt) begin
|
||||
// rff_grt <= grt;
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
|
||||
// always_ff @(posedge clk or negedge rstn ) begin
|
||||
// if (!rstn) begin
|
||||
// rff_last_grt_id <= N_INPUT_BITS'(N_INPUT-1);
|
||||
// end else begin
|
||||
// if ((|grt) & rdy) begin
|
||||
// rff_last_grt_id <= grt_id;
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
|
||||
// always_ff @(posedge clk or negedge rstn) begin
|
||||
// if(!rstn) begin
|
||||
// rff_state <= ST_PASS_THROUGH;
|
||||
// end else begin
|
||||
// rff_state <= next_state;
|
||||
// end
|
||||
// end
|
||||
|
||||
// always_comb begin
|
||||
// case (rff_state)
|
||||
// ST_HOLD: begin
|
||||
// do_save_grt = '0;
|
||||
// if (rdy) begin
|
||||
// next_state = ST_PASS_THROUGH;
|
||||
// end else begin
|
||||
// next_state = ST_HOLD;
|
||||
// end
|
||||
// end
|
||||
// default: begin
|
||||
// if((|grt) & ~rdy) begin
|
||||
// do_save_grt = '1;
|
||||
// next_state = ST_HOLD;
|
||||
// end else begin
|
||||
// do_save_grt = '0;
|
||||
// next_state = ST_PASS_THROUGH;
|
||||
// end
|
||||
// end
|
||||
// endcase
|
||||
// end
|
||||
|
||||
// assign grt = (rff_state == ST_HOLD) ? rff_grt: next_grt;
|
||||
// end
|
||||
// endgenerate
|
||||
//endmodule
|
||||
|
||||
Reference in New Issue
Block a user