third-party/OpenExSys_NoC
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[func] add sam support for sliced llc and scu

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This commit is contained in:
Zexin Fu
2023-12-01 17:08:38 +01:00
parent b47e435786
commit d56d0ca6a9
3 changed files with 119 additions and 25 deletions
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95
rtl/rn_router_sam.sv
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@@ -1,7 +1,14 @@
module rn_router_sam
import rvh_noc_pkg::*;
#(
parameter type flit_payload_t = logic[256-1:0]
parameter type flit_payload_t = logic[256-1:0],
parameter int sliced_llc = 0,
parameter int has_addr = 0, // for req and evict, thsy have addr and need to do sam, for resp and data, only send to the correspond hn
parameter int interleave_granularity = 64, // should be (2 ** n) * 64byte, n is integer and >= 0
parameter int llc_slice_num = 9,
parameter int INTERLEAVE_BIT = $clog2(interleave_granularity),
parameter int INTERLEAVE_LENGTH = $clog2(llc_slice_num)
// parameter VC_NUM_IDX_W = 1
)
(
@@ -21,21 +28,79 @@ module rn_router_sam
assign flit_dec_o.qos_value = flit_i.qos_value;
`endif
always_comb begin
flit_o = flit_i;
flit_o.tgt_id.x_position = 1;
flit_o.tgt_id.y_position = 0;
flit_o.tgt_id.device_port = 0;
flit_o.tgt_id.device_id = 0;
flit_o.src_id.x_position = node_id_x_i;
flit_o.src_id.y_position = node_id_y_i;
flit_o.src_id.device_port = 0;
flit_o.src_id.device_id = 0;
end
logic [40-1:0] req_addr;
generate
if(has_addr) begin
assign req_addr = flit_i.addr;
end
endgenerate
assign flit_dec_o.tgt_id.x_position = 1;
assign flit_dec_o.tgt_id.y_position = 0;
assign flit_dec_o.tgt_id.device_port = 0;
generate
if(sliced_llc) begin
if(has_addr) begin
always_comb begin
flit_o = flit_i;
flit_o.tgt_id.x_position = (req_addr[INTERLEAVE_BIT+INTERLEAVE_LENGTH-1:INTERLEAVE_BIT] % llc_slice_num) % NODE_NUM_X_DIMESION;
flit_o.tgt_id.y_position = (req_addr[INTERLEAVE_BIT+INTERLEAVE_LENGTH-1:INTERLEAVE_BIT] % llc_slice_num) / NODE_NUM_Y_DIMESION;
flit_o.tgt_id.device_port = 1;
flit_o.tgt_id.device_id = 0;
flit_o.src_id.x_position = node_id_x_i;
flit_o.src_id.y_position = node_id_y_i;
flit_o.src_id.device_port = 0;
flit_o.src_id.device_id = 0;
end
end else begin
always_comb begin
flit_o = flit_i;
flit_o.tgt_id.x_position = flit_i.id.sid % NODE_NUM_X_DIMESION;
flit_o.tgt_id.y_position = flit_i.id.sid / NODE_NUM_Y_DIMESION;
flit_o.tgt_id.device_port = 1;
flit_o.tgt_id.device_id = 0;
flit_o.src_id.x_position = node_id_x_i;
flit_o.src_id.y_position = node_id_y_i;
flit_o.src_id.device_port = 0;
flit_o.src_id.device_id = 0;
end
end
end else begin
always_comb begin
flit_o = flit_i;
flit_o.tgt_id.x_position = 1;
flit_o.tgt_id.y_position = 0;
flit_o.tgt_id.device_port = 0;
flit_o.tgt_id.device_id = 0;
flit_o.src_id.x_position = node_id_x_i;
flit_o.src_id.y_position = node_id_y_i;
flit_o.src_id.device_port = 0;
flit_o.src_id.device_id = 0;
end
end
endgenerate
generate
if(sliced_llc) begin: gen_sliced_llc
if(has_addr) begin: gen_has_addr
assign flit_dec_o.tgt_id.x_position = (req_addr[INTERLEAVE_BIT+INTERLEAVE_LENGTH-1:INTERLEAVE_BIT] % llc_slice_num) % NODE_NUM_X_DIMESION;
assign flit_dec_o.tgt_id.y_position = (req_addr[INTERLEAVE_BIT+INTERLEAVE_LENGTH-1:INTERLEAVE_BIT] % llc_slice_num) / NODE_NUM_Y_DIMESION;
assign flit_dec_o.tgt_id.device_port = 1;
end else begin: gen_no_addr
assign flit_dec_o.tgt_id.x_position = flit_i.id.sid % NODE_NUM_X_DIMESION;
assign flit_dec_o.tgt_id.y_position = flit_i.id.sid / NODE_NUM_Y_DIMESION;
assign flit_dec_o.tgt_id.device_port = 1;
end
end else begin: gen_whole_llc // when the hn is at (1,0)
assign flit_dec_o.tgt_id.x_position = 1;
assign flit_dec_o.tgt_id.y_position = 0;
assign flit_dec_o.tgt_id.device_port = 0;
end
endgenerate
assign flit_dec_o.tgt_id.device_id = 0;
assign flit_dec_o.src_id.x_position = node_id_x_i;
assign flit_dec_o.src_id.y_position = node_id_y_i;