30 lines
584 B
Verilog
Executable File
30 lines
584 B
Verilog
Executable File
module rrv64_cell_clkgate (
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input wire clk_i,
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input wire clk_enable_i,
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input wire clk_senable_i,
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output wire clk_gated_o
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);
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// CKGATE
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// CKGATE_inst
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// (
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// .cko (clk_gated_o),
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// .cki (clk_i ),
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// .e (clk_enable_i),
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// .te (clk_senable_i),
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// );
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wire clk_en;
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reg clk_en_reg;
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assign clk_en = clk_enable_i | clk_senable_i;
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always @ (clk_i or clk_en) begin
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if(clk_i == 1'b0) begin
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clk_en_reg <= clk_en;
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end
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end
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assign clk_gated_o = clk_i & clk_en_reg;
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endmodule |