259 lines
7.9 KiB
Systemverilog
Executable File
259 lines
7.9 KiB
Systemverilog
Executable File
`ifndef __RVH_NOC_PKG_SV__
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`define __RVH_NOC_PKG_SV__
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// ----------
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// local port configuration
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// ----------
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`define HAVE_LOCAL_PORT
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// `define LOCAL_PORT_NUM_2 // local port num >= 2
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// `define LOCAL_PORT_NUM_3 // local port num >= 3
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// `define LOCAL_PORT_NUM_4 // local port num >= 4
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`ifdef LOCAL_PORT_NUM_4
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`ifndef LOCAL_PORT_NUM_3
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`define LOCAL_PORT_NUM_3
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`endif
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`ifndef LOCAL_PORT_NUM_2
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`define LOCAL_PORT_NUM_2
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`endif
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`endif
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`ifdef LOCAL_PORT_NUM_3
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`ifndef LOCAL_PORT_NUM_2
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`define LOCAL_PORT_NUM_2
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`endif
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`endif
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// `define ENABLE_TXN_ID // for noc test, enable it
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// ----------
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// Single vc per input port
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// ----------
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// `define SINGLE_VC_PER_INPUT_PORT
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// ----------
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// use unified dual-port ram per input port vc data buffer (default: dff)
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// ----------
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// `define VC_DATA_USE_DUAL_PORT_RAM
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// ----------
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// reture credit to send at sa stage rather than st atage
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// ----------
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// `define RETURN_CREDIT_AT_SA_STAGE
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// ----------
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// whether allow local ports in same router transfer flit, at least 2 local ports
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// ----------
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// `define ALLOW_SAME_ROUTER_L2L_TRANSFER
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// ----------
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// insert a pipeline register between local sa and global sa, for better timing
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// ----------
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// `define INSERT_PIPELINE_REG_BETWEEN_SA
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// ----------
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// QoS, at most one of follow macros can be defined
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// ----------
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`define COMMON_QOS // No special vc, all vc head flits ranked by QoS value.
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// `define COMMON_QOS_EXTRA_RT_VC // Add special vc for highest priority flits, all vc head flits ranked by QoS value
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// not implemented:
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// `define RT_BYPASS_QOS_EXTRA_RT_VC // Add special vc for highest priority flits, other vc head flits have no QoS support
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`ifdef COMMON_QOS
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`define USE_QOS_VALUE
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`endif
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`ifdef COMMON_QOS_EXTRA_RT_VC
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`define USE_QOS_VALUE
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`endif
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package rvh_noc_pkg;
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localparam CHANNEL_NUM = 5; // 5 channels: req, resp, evict, data, snp
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// 4*4 nodes max
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localparam NodeID_X_Width = 2;
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localparam NodeID_Y_Width = 2;
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localparam NodeID_Device_Port_Width = 2;
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localparam NodeID_Device_Id_Width = 1;
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localparam NodeID_Width = NodeID_X_Width + NodeID_Y_Width + NodeID_Device_Port_Width + NodeID_Device_Id_Width; // 7
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localparam TxnID_Width = 12;
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localparam QoS_Value_Width = 4;
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localparam INPUT_PORT_NUMBER = 5; // N,S,E,W,L
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localparam INPUT_PORT_NUMBER_IDX_W = INPUT_PORT_NUMBER > 1 ? $clog2(INPUT_PORT_NUMBER) : 1;
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localparam OUTPUT_PORT_NUMBER = 5; // N,S,E,W,L
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localparam ROUTER_PORT_NUMBER = 4;
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localparam LOCAL_PORT_NUMBER = INPUT_PORT_NUMBER-ROUTER_PORT_NUMBER;
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`ifdef COMMON_QOS_EXTRA_RT_VC
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localparam QOS_VC_NUM_PER_INPUT = 1;
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`else
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localparam QOS_VC_NUM_PER_INPUT = 0;
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`endif
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`ifdef SINGLE_VC_PER_INPUT_PORT
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localparam VC_ID_NUM_MAX = 1+QOS_VC_NUM_PER_INPUT;
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`else
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localparam VC_ID_NUM_MAX = (CHANNEL_NUM-1)+LOCAL_PORT_NUMBER+QOS_VC_NUM_PER_INPUT;
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`endif
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localparam VC_ID_NUM_MAX_W = VC_ID_NUM_MAX > 1 ? $clog2(VC_ID_NUM_MAX) : 1;
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localparam SA_GLOBAL_INPUT_NUM_MAX = (CHANNEL_NUM-1)+LOCAL_PORT_NUMBER;
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localparam SA_GLOBAL_INPUT_NUM_MAX_W = SA_GLOBAL_INPUT_NUM_MAX > 1 ? $clog2(SA_GLOBAL_INPUT_NUM_MAX) : 1;
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localparam VC_DEPTH_MAX = 2;
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`ifdef VC_DATA_USE_DUAL_PORT_RAM
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`ifdef RETURN_CREDIT_AT_SA_STAGE
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localparam VC_DPRAM_DEPTH_MAX = VC_ID_NUM_MAX * (VC_DEPTH_MAX+1);
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localparam VC_BUFFER_DEPTH_MAX_W = (VC_DEPTH_MAX+1) > 1 ? $clog2(VC_DEPTH_MAX+1) : 1;
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`else
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localparam VC_DPRAM_DEPTH_MAX = VC_ID_NUM_MAX * VC_DEPTH_MAX;
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localparam VC_BUFFER_DEPTH_MAX_W = VC_DEPTH_MAX > 1 ? $clog2(VC_DEPTH_MAX) : 1;
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`endif
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localparam VC_DPRAM_DEPTH_MAX_W = VC_DPRAM_DEPTH_MAX > 1 ? $clog2(VC_DPRAM_DEPTH_MAX) : 1;
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`endif
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typedef enum logic [2:0] {
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N = 0,
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S = 1,
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E = 2,
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W = 3,
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L0 = 4,
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L1 = 5,
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L2 = 6,
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L3 = 7
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} io_port_t;
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typedef struct packed {
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logic [NodeID_X_Width-1:0] x_position;
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logic [NodeID_Y_Width-1:0] y_position;
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logic [NodeID_Device_Port_Width-1:0] device_port;
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logic [1-1:0] device_id;
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} node_id_t;
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`ifdef VC_DATA_USE_DUAL_PORT_RAM
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typedef struct packed {
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logic [VC_DPRAM_DEPTH_MAX_W-1:0] dpram_idx; // == VC_BUFFER_DEPTH * vc_id + per_vc_idx
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logic [VC_BUFFER_DEPTH_MAX_W-1:0] per_vc_idx;
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} dpram_used_idx_t;
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`endif
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typedef struct packed {
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node_id_t tgt_id; // target id
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node_id_t src_id; // source id
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`ifdef ENABLE_TXN_ID
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logic [TxnID_Width-1:0] txn_id; // transaction id
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`endif
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io_port_t look_ahead_routing;
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`ifdef USE_QOS_VALUE
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logic [QoS_Value_Width-1:0] qos_value;
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`endif
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`ifdef VC_DATA_USE_DUAL_PORT_RAM
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dpram_used_idx_t dpram_used_idx;
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`endif
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} flit_dec_t;
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typedef struct packed {
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logic common_vld;
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logic rt_vld;
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} vc_select_vld_t;
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typedef struct packed {
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logic [VC_ID_NUM_MAX_W-1:0] common_vc_id;
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logic [VC_ID_NUM_MAX_W-1:0] rt_vc_id;
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} vc_select_vc_id_t;
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// mesh parameters
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parameter NODE_NUM_X_DIMESION = 3;
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parameter NODE_NUM_Y_DIMESION = 3;
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// router parameters
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parameter INPUT_PORT_NUM = INPUT_PORT_NUMBER;
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parameter OUTPUT_PORT_NUM = OUTPUT_PORT_NUMBER;
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parameter LOCAL_PORT_NUM = INPUT_PORT_NUM-4;
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typedef struct packed {
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logic [256-1:0] data;
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node_id_t tgt_id; // target id
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node_id_t src_id; // source id
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`ifdef ENABLE_TXN_ID
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logic [TxnID_Width-1:0] txn_id; // transaction id
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`endif
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`ifdef USE_QOS_VALUE
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logic [QoS_Value_Width-1:0] qos_value;
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`endif
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} cache_scu_cc_test_t;
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parameter FLIT_LENGTH = $bits(cache_scu_cc_test_t);
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// parameter type flit_payload_t = logic[FLIT_LENGTH-1:0];
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parameter type flit_payload_t = cache_scu_cc_test_t;
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// parameter QOS_VC_NUM_PER_INPUT = QOS_VC_NUM_PER_INPUT;
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`ifdef SINGLE_VC_PER_INPUT_PORT
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parameter VC_NUM_INPUT_N = 1+QOS_VC_NUM_PER_INPUT;
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parameter VC_NUM_INPUT_S = 1+QOS_VC_NUM_PER_INPUT;
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parameter VC_NUM_INPUT_E = 1+QOS_VC_NUM_PER_INPUT;
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parameter VC_NUM_INPUT_W = 1+QOS_VC_NUM_PER_INPUT;
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`ifdef ALLOW_SAME_ROUTER_L2L_TRANSFER
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parameter VC_NUM_INPUT_L = 1+QOS_VC_NUM_PER_INPUT;
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`else
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parameter VC_NUM_INPUT_L = 1+QOS_VC_NUM_PER_INPUT;
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`endif
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`else
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parameter VC_NUM_INPUT_N = 1+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT;
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parameter VC_NUM_INPUT_S = 1+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT;
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parameter VC_NUM_INPUT_E = 3+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT;
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parameter VC_NUM_INPUT_W = 3+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT;
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`ifdef ALLOW_SAME_ROUTER_L2L_TRANSFER
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parameter VC_NUM_INPUT_L = 4+LOCAL_PORT_NUM-1+QOS_VC_NUM_PER_INPUT;
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`else
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parameter VC_NUM_INPUT_L = 4+QOS_VC_NUM_PER_INPUT;
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`endif
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`endif
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parameter SA_GLOBAL_INPUT_NUM_N = 3+LOCAL_PORT_NUM;
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parameter SA_GLOBAL_INPUT_NUM_S = 3+LOCAL_PORT_NUM;
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parameter SA_GLOBAL_INPUT_NUM_E = 1+LOCAL_PORT_NUM;
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parameter SA_GLOBAL_INPUT_NUM_W = 1+LOCAL_PORT_NUM;
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`ifdef ALLOW_SAME_ROUTER_L2L_TRANSFER
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parameter SA_GLOBAL_INPUT_NUM_L = 4+LOCAL_PORT_NUM-1;
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`else
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parameter SA_GLOBAL_INPUT_NUM_L = 4;
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`endif
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`ifdef SINGLE_VC_PER_INPUT_PORT
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parameter VC_NUM_OUTPUT_N = 1+QOS_VC_NUM_PER_INPUT;
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parameter VC_NUM_OUTPUT_S = 1+QOS_VC_NUM_PER_INPUT;
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parameter VC_NUM_OUTPUT_E = 1+QOS_VC_NUM_PER_INPUT;
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parameter VC_NUM_OUTPUT_W = 1+QOS_VC_NUM_PER_INPUT;
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`else
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parameter VC_NUM_OUTPUT_N = 1+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT;
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parameter VC_NUM_OUTPUT_S = 1+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT;
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parameter VC_NUM_OUTPUT_E = 3+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT;
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parameter VC_NUM_OUTPUT_W = 3+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT;
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`endif
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parameter VC_NUM_OUTPUT_L = 1;
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parameter VC_DEPTH_INPUT_N = VC_DEPTH_MAX;
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parameter VC_DEPTH_INPUT_S = VC_DEPTH_MAX;
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parameter VC_DEPTH_INPUT_E = VC_DEPTH_MAX;
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parameter VC_DEPTH_INPUT_W = VC_DEPTH_MAX;
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parameter VC_DEPTH_INPUT_L = VC_DEPTH_MAX;
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endpackage
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`endif
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