153 lines
4.5 KiB
Systemverilog
153 lines
4.5 KiB
Systemverilog
module input_port
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import rvh_noc_pkg::*;
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#(
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parameter type flit_payload_t = logic[256-1:0],
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parameter VC_NUM = 1,
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parameter VC_DEPTH = 1,
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parameter VC_NUM_IDX_W =VC_NUM > 1 ? $clog2(VC_NUM) : 1,
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parameter INPUT_PORT_NO = 0
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)
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(
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// input from other router or local port
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input logic rx_flit_pend_i,
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input logic rx_flit_v_i,
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input flit_payload_t rx_flit_i,
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input logic [VC_NUM_IDX_W-1:0] rx_flit_vc_id_i,
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input io_port_t rx_flit_look_ahead_routing_i,
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// free vc credit sent to sender
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output logic rx_lcrd_v_o,
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output logic [VC_ID_NUM_MAX_W-1:0] rx_lcrd_id_o,
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// output head flit ctrl info to SA & RC unit
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output logic [VC_NUM-1:0] vc_ctrl_head_vld_o,
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output flit_dec_t [VC_NUM-1:0] vc_ctrl_head_o,
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// output data to switch traversal
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output flit_payload_t [VC_NUM-1:0] vc_data_head_o,
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// input pop flit ctrl fifo (comes from SA stage)
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input logic inport_read_enable_sa_stage_i,
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input logic [VC_NUM_IDX_W-1:0] inport_read_vc_id_sa_stage_i,
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`ifdef VC_DATA_USE_DUAL_PORT_RAM
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input dpram_used_idx_t inport_read_dpram_idx_i,
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`endif
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// input pop flit ctrl fifo (comes from ST stage)
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input logic inport_read_enable_st_stage_i,
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input logic [VC_NUM_IDX_W-1:0] inport_read_vc_id_st_stage_i,
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`ifndef SYNTHESIS
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// router addr
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input logic [NodeID_X_Width-1:0] node_id_x_ths_hop_i,
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input logic [NodeID_Y_Width-1:0] node_id_y_ths_hop_i,
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`endif
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input logic clk,
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input logic rstn
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);
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flit_dec_t flit_ctrl_info;
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// 1 decode flit, get input vc and routing info
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input_port_flit_decoder
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#(
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.flit_payload_t (flit_payload_t)
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// .VC_NUM_IDX_W (VC_NUM_IDX_W)
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)
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input_port_flit_decoder_u
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(
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.flit_v_i (rx_flit_v_i ),
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.flit_i (rx_flit_i ),
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.flit_look_ahead_routing_i(rx_flit_look_ahead_routing_i),
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.flit_dec_o (flit_ctrl_info )
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);
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// 2 input vc fifo
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input_port_vc
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#(
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.flit_payload_t (flit_payload_t ),
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.VC_NUM (VC_NUM ),
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.VC_DEPTH (VC_DEPTH )
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)
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input_port_vc_u
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(
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// input from input port
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.flit_v_i (rx_flit_v_i ),
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.flit_i (rx_flit_i ),
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.flit_dec_i (flit_ctrl_info ),
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.flit_vc_id_i (rx_flit_vc_id_i),
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// free vc credit sent to sender
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.lcrd_v_o (rx_lcrd_v_o ),
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.lcrd_id_o (rx_lcrd_id_o ),
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// output ctrl to local allocate
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.vc_ctrl_head_vld_o (vc_ctrl_head_vld_o),
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.vc_ctrl_head_o (vc_ctrl_head_o ),
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// output data to switch traversal
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.vc_data_head_o (vc_data_head_o ),
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// input pop flit ctrl fifo (comes from SA stage)
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.inport_read_enable_sa_stage_i (inport_read_enable_sa_stage_i ),
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.inport_read_vc_id_sa_stage_i (inport_read_vc_id_sa_stage_i ),
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`ifdef VC_DATA_USE_DUAL_PORT_RAM
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.inport_read_dpram_idx_i (inport_read_dpram_idx_i ),
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`endif
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// input pop flit ctrl fifo (comes from ST stage)
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.inport_read_enable_st_stage_i (inport_read_enable_st_stage_i ),
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.inport_read_vc_id_st_stage_i (inport_read_vc_id_st_stage_i ),
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.clk (clk ),
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.rstn (rstn )
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);
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`ifndef SYNTHESIS
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int noc_debug_print=0;
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initial begin
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if ($value$plusargs("noc_debug_print=%d", noc_debug_print)) begin
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// $display("NOC: noc_debug_print_in=%d", noc_debug_print);
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end
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end
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`ifdef V_INPORT_PRINT_EN
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// debug print
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always_ff @(posedge clk) begin
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if(noc_debug_print) begin
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if(rstn) begin
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if(rx_flit_v_i) begin
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$display("[%16d] info: receive flit: router:(%d,%d); inport: %1d(N0,S1,E2,W3,L4-7); vc_id: %1d; look_ahead_routing: %1d(N0,S1,E2,W3,L4-7), QoS = %d",
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$time(),
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node_id_x_ths_hop_i, node_id_y_ths_hop_i,
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INPUT_PORT_NO,
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rx_flit_vc_id_i,
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flit_ctrl_info.look_ahead_routing,
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rx_flit_i[QoS_Value_Width-1:0]);
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$write(" ");
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$display("txn_id: 0x%h, sender: (%d,%d), sender_local_port: %1d",
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`ifdef ENABLE_TXN_ID
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flit_ctrl_info.txn_id,
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`else
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'0,
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`endif
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flit_ctrl_info.src_id.x_position, flit_ctrl_info.src_id.y_position,
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flit_ctrl_info.src_id.device_port);
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$write(" ");
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$display("tgt_id: (%d,%d), tgt_local_port: %1d",
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flit_ctrl_info.tgt_id.x_position, flit_ctrl_info.tgt_id.y_position, flit_ctrl_info.tgt_id.device_port);
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end
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end
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end
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end
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`endif
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`endif
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endmodule
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