67 lines
2.1 KiB
Systemverilog
67 lines
2.1 KiB
Systemverilog
`ifndef __INORDER_ROUTER_SV__
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`define __INORDER_ROUTER_SV__
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module inorder_router
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#(
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parameter int unsigned SRC_COUNT = 4,
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parameter int unsigned DES_COUNT = 4
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) (
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input logic[SRC_COUNT-1:0] src_vld_i,
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input logic[SRC_COUNT-1:0][DES_COUNT-1:0] src_des_en_i,
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output logic[SRC_COUNT-1:0] success_o,
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output logic[DES_COUNT-1:0][SRC_COUNT-1:0] src_des_sel_o
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);
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logic[SRC_COUNT-1:0] success;
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logic[SRC_COUNT-1:0][DES_COUNT-1:0] des_sel_mask;
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logic[SRC_COUNT-1:0][DES_COUNT-1:0] des_disable_mask;
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logic[SRC_COUNT-1:0][DES_COUNT-1:0] des_rdy_mask;
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generate
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for(genvar src = 0 ; src < SRC_COUNT; src++) begin : gen_des_disable_mask
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if(src == 0) begin
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assign des_disable_mask[src] = {DES_COUNT{1'b0}};
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end else begin
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assign des_disable_mask[src] = des_disable_mask[src-1] | des_sel_mask[src-1];
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end
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end
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endgenerate
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generate
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for(genvar src = 0 ; src < SRC_COUNT ; src++) begin : gen_des_rdy_mask
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if(src == 0) begin
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assign des_rdy_mask[src] = {DES_COUNT{src_vld_i[src]}} & src_des_en_i[src];
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end else begin
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assign des_rdy_mask[src] = {DES_COUNT{src_vld_i[src]}} & src_des_en_i[src] & ~des_disable_mask[src] & {DES_COUNT{success[src-1]}};
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end
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end
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endgenerate
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generate
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for(genvar src = 0 ; src < SRC_COUNT ; src++) begin : gen_success_vec
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assign success[src] = |des_sel_mask[src];
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end
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endgenerate
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always_comb begin : output_logic
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success_o = success;
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for(int src = 0 ; src < SRC_COUNT; src++) begin
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for(int des = 0 ; des < DES_COUNT; des++) begin
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src_des_sel_o[des][src] = des_sel_mask[src][des];
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end
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end
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end
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generate
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for(genvar src = 0 ; src < SRC_COUNT ; src++) begin
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one_hot_priority_encoder
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#(
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.SEL_WIDTH(DES_COUNT)
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) u_routing_encoder (
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.sel_i(des_rdy_mask[src]),
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.sel_o(des_sel_mask[src])
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);
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end
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endgenerate
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endmodule
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`endif |