16 lines
501 B
Systemverilog
16 lines
501 B
Systemverilog
module left_circular_rotate #(
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parameter N_INPUT = 2,
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localparam int unsigned N_INPUT_WIDTH = N_INPUT > 1 ? $clog2(N_INPUT) : 1
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) (
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input logic [N_INPUT-1:0] ori_vector_i,
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input logic [N_INPUT_WIDTH-1:0] req_left_rotate_num_i,
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output logic [N_INPUT-1:0] roteted_vector_o
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);
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logic [N_INPUT*2-1:0] ori_vector_mid;
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assign ori_vector_mid = {ori_vector_i, ori_vector_i} << req_left_rotate_num_i;
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assign roteted_vector_o = ori_vector_mid[N_INPUT*2-1-:N_INPUT];
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endmodule
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