30 lines
588 B
Systemverilog
30 lines
588 B
Systemverilog
module oh2idx
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#(
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parameter int unsigned N_INPUT = 2,
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localparam int unsigned N_INPUT_WIDTH = N_INPUT > 1 ? $clog2(N_INPUT) : 1
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)
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(
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input [N_INPUT-1:0] oh_i,
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output [N_INPUT_WIDTH-1:0] idx_o
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);
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genvar i, j;
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logic [N_INPUT_WIDTH-1:0][N_INPUT-1:0] mask;
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generate
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for(i = 0; i < N_INPUT_WIDTH; i++) begin: gen_mask_i
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for(j = 0; j < N_INPUT; j++) begin: gen_mask_j
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assign mask[i][j] = (j/(2**i)) % 2;
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end
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end
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endgenerate
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generate
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for(i = 0; i < N_INPUT_WIDTH; i++) begin: gen_idx_o
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assign idx_o[i] = |(oh_i & mask[i]);
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end
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endgenerate
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endmodule
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