37 lines
880 B
Systemverilog
Executable File
37 lines
880 B
Systemverilog
Executable File
`ifndef __ONEHOT_MUX_SV__
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`define __ONEHOT_MUX_SV__
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module onehot_mux
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#(
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parameter int unsigned SOURCE_COUNT = 2,
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parameter int unsigned DATA_WIDTH = 1
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)
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(
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input logic[SOURCE_COUNT-1:0] sel_i,
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input logic[SOURCE_COUNT-1:0][DATA_WIDTH-1:0] data_i,
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output logic[DATA_WIDTH-1:0] data_o
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);
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logic[DATA_WIDTH-1:0][SOURCE_COUNT-1:0] trans_data;
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logic[DATA_WIDTH-1:0][SOURCE_COUNT-1:0] select_mat;
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generate
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for(genvar i = 0 ; i < DATA_WIDTH; i++) begin
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for(genvar j = 0 ; j < SOURCE_COUNT; j++) begin
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assign trans_data[i][j] = data_i[j][i];
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end
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end
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endgenerate
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generate
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for(genvar i = 0; i < DATA_WIDTH; i++) begin
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assign select_mat[i] = trans_data[i] & sel_i;
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assign data_o[i] = |select_mat[i];
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end
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endgenerate
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endmodule
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`endif |