560 lines
20 KiB
Systemverilog
560 lines
20 KiB
Systemverilog
module tb_single_router
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import rvh_noc_pkg::*;
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import v_noc_pkg::*;
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#(
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// router parameters
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parameter INPUT_PORT_NUM = INPUT_PORT_NUMBER,
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parameter OUTPUT_PORT_NUM = OUTPUT_PORT_NUMBER,
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parameter LOCAL_PORT_NUM = INPUT_PORT_NUM-4,
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parameter type flit_payload_t = logic[FLIT_LENGTH-1:0],
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parameter VC_NUM_INPUT_N = 1+LOCAL_PORT_NUM,
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parameter VC_NUM_INPUT_S = 1+LOCAL_PORT_NUM,
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parameter VC_NUM_INPUT_E = 3+LOCAL_PORT_NUM,
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parameter VC_NUM_INPUT_W = 3+LOCAL_PORT_NUM,
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`ifdef ALLOW_SAME_ROUTER_L2L_TRANSFER
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parameter VC_NUM_INPUT_L = 4+LOCAL_PORT_NUM-1,
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`else
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parameter VC_NUM_INPUT_L = 4,
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`endif
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parameter SA_GLOBAL_INPUT_NUM_N = 3+LOCAL_PORT_NUM,
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parameter SA_GLOBAL_INPUT_NUM_S = 3+LOCAL_PORT_NUM,
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parameter SA_GLOBAL_INPUT_NUM_E = 1+LOCAL_PORT_NUM,
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parameter SA_GLOBAL_INPUT_NUM_W = 1+LOCAL_PORT_NUM,
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`ifdef ALLOW_SAME_ROUTER_L2L_TRANSFER
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parameter SA_GLOBAL_INPUT_NUM_L = 4+LOCAL_PORT_NUM-1,
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`else
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parameter SA_GLOBAL_INPUT_NUM_L = 4,
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`endif
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parameter VC_NUM_OUTPUT_N = 1+LOCAL_PORT_NUM,
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parameter VC_NUM_OUTPUT_S = 1+LOCAL_PORT_NUM,
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parameter VC_NUM_OUTPUT_E = 3+LOCAL_PORT_NUM,
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parameter VC_NUM_OUTPUT_W = 3+LOCAL_PORT_NUM,
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parameter VC_NUM_OUTPUT_L = 1,
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parameter VC_DEPTH_INPUT_N = VC_DEPTH_MAX,
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parameter VC_DEPTH_INPUT_S = VC_DEPTH_MAX,
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parameter VC_DEPTH_INPUT_E = VC_DEPTH_MAX,
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parameter VC_DEPTH_INPUT_W = VC_DEPTH_MAX,
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parameter VC_DEPTH_INPUT_L = VC_DEPTH_MAX,
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// test_generator parameters
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parameter RANDOM_BIT_NUM = 32,
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parameter SCOREBOARD_TIMEOUT_EN = 1,
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parameter SCOREBOARD_TIMEOUT_THRESHOLD = 256,
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parameter TEST_CASE_NUM_PER_CYCLE = 10,
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// scoreboard parameters
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parameter SCOREBOARD_ENTRY_NUM_PER_SENDER = 64,
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// sender parameters
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parameter SENDER_TIMEOUT_EN = 1,
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parameter SENDER_TIMEOUT_THRESHOLD = 256,
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// overall longest test cycle
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parameter LONGEST_TEST_CYCLE = 10000
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)
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(
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);
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genvar i;
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// Ports
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logic [INPUT_PORT_NUM-1:0] rx_flit_pend_i;
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logic [INPUT_PORT_NUM-1:0] rx_flit_v_i;
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flit_payload_t [INPUT_PORT_NUM-1:0] rx_flit_i;
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logic [INPUT_PORT_NUM-1:0] [VC_ID_NUM_MAX_W-1:0] rx_flit_vc_id_i;
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io_port_t [INPUT_PORT_NUM-1:0] rx_flit_look_ahead_routing_i;
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logic [OUTPUT_PORT_NUM-1:0] tx_flit_pend_o;
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logic [OUTPUT_PORT_NUM-1:0] tx_flit_v_o;
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flit_payload_t [OUTPUT_PORT_NUM-1:0] tx_flit_o;
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logic [OUTPUT_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] tx_flit_vc_id_o;
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io_port_t [OUTPUT_PORT_NUM-1:0] tx_flit_look_ahead_routing_o;
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logic [INPUT_PORT_NUM-1:0] rx_lcrd_v_o;
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logic [INPUT_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] rx_lcrd_id_o;
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logic [OUTPUT_PORT_NUM-1:0] tx_lcrd_v_i;
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logic [OUTPUT_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] tx_lcrd_id_i;
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logic [NodeID_X_Width-1:0] node_id_x_ths_hop_i;
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logic [NodeID_Y_Width-1:0] node_id_y_ths_hop_i;
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logic clk;
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logic rstn;
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assign node_id_x_ths_hop_i = 2'b01;
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assign node_id_y_ths_hop_i = 2'b01;
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vnet_router
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#(
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.INPUT_PORT_NUM(INPUT_PORT_NUM ),
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.OUTPUT_PORT_NUM(OUTPUT_PORT_NUM ),
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.flit_payload_t(flit_payload_t),
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.VC_NUM_INPUT_N(VC_NUM_INPUT_N ),
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.VC_NUM_INPUT_S(VC_NUM_INPUT_S ),
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.VC_NUM_INPUT_E(VC_NUM_INPUT_E ),
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.VC_NUM_INPUT_W(VC_NUM_INPUT_W ),
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.VC_NUM_INPUT_L(VC_NUM_INPUT_L ),
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.SA_GLOBAL_INPUT_NUM_N(SA_GLOBAL_INPUT_NUM_N ),
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.SA_GLOBAL_INPUT_NUM_S(SA_GLOBAL_INPUT_NUM_S ),
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.SA_GLOBAL_INPUT_NUM_E(SA_GLOBAL_INPUT_NUM_E ),
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.SA_GLOBAL_INPUT_NUM_W(SA_GLOBAL_INPUT_NUM_W ),
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.SA_GLOBAL_INPUT_NUM_L(SA_GLOBAL_INPUT_NUM_L ),
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.VC_NUM_OUTPUT_N(VC_NUM_OUTPUT_N ),
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.VC_NUM_OUTPUT_S(VC_NUM_OUTPUT_S ),
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.VC_NUM_OUTPUT_E(VC_NUM_OUTPUT_E ),
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.VC_NUM_OUTPUT_W(VC_NUM_OUTPUT_W ),
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.VC_NUM_OUTPUT_L(VC_NUM_OUTPUT_L ),
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.VC_DEPTH_INPUT_N(VC_DEPTH_INPUT_N ),
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.VC_DEPTH_INPUT_S(VC_DEPTH_INPUT_S ),
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.VC_DEPTH_INPUT_E(VC_DEPTH_INPUT_E ),
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.VC_DEPTH_INPUT_W(VC_DEPTH_INPUT_W ),
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.VC_DEPTH_INPUT_L(VC_DEPTH_INPUT_L )
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)
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vnet_router_dut (
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.rx_flit_pend_i (rx_flit_pend_i ),
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.rx_flit_v_i (rx_flit_v_i ),
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.rx_flit_i (rx_flit_i ),
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.rx_flit_vc_id_i (rx_flit_vc_id_i ),
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.rx_flit_look_ahead_routing_i (rx_flit_look_ahead_routing_i ),
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.tx_flit_pend_o (tx_flit_pend_o ),
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.tx_flit_v_o (tx_flit_v_o ),
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.tx_flit_o (tx_flit_o ),
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.tx_flit_vc_id_o (tx_flit_vc_id_o ),
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.tx_flit_look_ahead_routing_o (tx_flit_look_ahead_routing_o ),
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.rx_lcrd_v_o (rx_lcrd_v_o ),
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.rx_lcrd_id_o (rx_lcrd_id_o ),
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.tx_lcrd_v_i (tx_lcrd_v_i ),
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.tx_lcrd_id_i (tx_lcrd_id_i ),
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.node_id_x_ths_hop_i (node_id_x_ths_hop_i ),
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.node_id_y_ths_hop_i (node_id_y_ths_hop_i ),
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.clk (clk ),
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.rstn (rstn)
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);
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// test generate
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logic [64-1:0] mcycle;
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node_id_t target_node;
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int longest_test_cycle = LONGEST_TEST_CYCLE;
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int self_finish = 1;
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initial begin
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$value$plusargs("longest_test_cycle=%d", longest_test_cycle);
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$value$plusargs("self_finish=%d", self_finish);
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end
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always_ff @(posedge clk or negedge rstn) begin
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if(~rstn) begin
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mcycle <= '0;
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end else begin
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mcycle <= mcycle + 1;
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if(self_finish > 0) begin
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if(mcycle == longest_test_cycle) begin
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$finish();
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end
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end
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end
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end
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logic [32-1:0] src_id_lfsr_seed;
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logic [32-1:0] tgt_id_lfsr_seed;
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logic [INPUT_PORT_NUM-1:0] new_test_vld;
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test_case_t [INPUT_PORT_NUM-1:0] new_test;
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logic [INPUT_PORT_NUM-1:0] new_test_rdy;
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assign src_id_lfsr_seed = 32'hdeadbeef;
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assign tgt_id_lfsr_seed = 32'hbaadf00d;
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v_test_generator
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#(
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.SENDER_NUM (INPUT_PORT_NUM ),
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.RANDOM_BIT_NUM (RANDOM_BIT_NUM ),
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.SCOREBOARD_TIMEOUT_EN (SCOREBOARD_TIMEOUT_EN ),
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.SCOREBOARD_TIMEOUT_THRESHOLD (SCOREBOARD_TIMEOUT_THRESHOLD ),
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.TEST_CASE_NUM_PER_CYCLE(TEST_CASE_NUM_PER_CYCLE ),
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.TEST_CASE_SINGLE_ROUTER(1 ),
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.ASSUMED_SYSTEM_FREQUENCY((1<<30) )
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)
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v_test_generator_u (
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.new_test_vld_o (new_test_vld ),
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.new_test_o (new_test ),
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.new_test_rdy_i (new_test_rdy ),
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.src_id_lfsr_seed_i (src_id_lfsr_seed ^ mcycle[16+:32]),
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.tgt_id_lfsr_seed_i (tgt_id_lfsr_seed ^ mcycle[20+:32] ),
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.lfsr_update_en_i (&mcycle[16-1:0]),
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.mcycle_i (mcycle),
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.clk (clk ),
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.rstn (rstn)
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);
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logic [INPUT_PORT_NUM-1:0] new_scoreboard_entry_vld;
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scoreboard_entry_t [INPUT_PORT_NUM-1:0] new_scoreboard_entry;
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logic [INPUT_PORT_NUM-1:0] new_scoreboard_entry_rdy;
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node_id_t [OUTPUT_PORT_NUM-1:0] sender_node_id;
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// sender0 (1,2)
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// |
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// sender3 (0,1) - (1,1) - (2,1) sender2
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// | \
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// sender1 (1,0) (local) sender4
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assign sender_node_id[0].x_position = 1;
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assign sender_node_id[0].y_position = 2;
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assign sender_node_id[0].device_port = '0;
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assign sender_node_id[0].device_id = '0;
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assign sender_node_id[1].x_position = 1;
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assign sender_node_id[1].y_position = 0;
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assign sender_node_id[1].device_port = '0;
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assign sender_node_id[1].device_id = '0;
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assign sender_node_id[2].x_position = 2;
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assign sender_node_id[2].y_position = 1;
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assign sender_node_id[2].device_port = '0;
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assign sender_node_id[2].device_id = '0;
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assign sender_node_id[3].x_position = 0;
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assign sender_node_id[3].y_position = 1;
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assign sender_node_id[3].device_port = '0;
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assign sender_node_id[3].device_id = '0;
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generate
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if(LOCAL_PORT_NUM > 0) begin: gen_have_local_sender_node_id
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for(i = 0; i < LOCAL_PORT_NUM; i++) begin: gen_local_sender_node_id
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assign sender_node_id[4+i].x_position = 1;
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assign sender_node_id[4+i].y_position = 1;
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assign sender_node_id[4+i].device_port = i;
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assign sender_node_id[4+i].device_id = '0;
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end
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end
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endgenerate
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v_sender
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#(
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.FLIT_BUFFER_DEPTH (8 ),
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.flit_payload_t (flit_payload_t ),
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.VC_NUM_OUTPORT (VC_NUM_INPUT_N),
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.VC_DEPTH_OUTPORT (VC_DEPTH_INPUT_N ),
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.SENDER_TIMEOUT_EN (SENDER_TIMEOUT_EN ),
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.SENDER_TIMEOUT_THRESHOLD (SENDER_TIMEOUT_THRESHOLD),
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.OUTPUT_TO_N (1)
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)
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v_sender_toN_u (
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.tx_flit_pend_o (rx_flit_pend_i [0] ),
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.tx_flit_v_o (rx_flit_v_i [0] ),
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.tx_flit_o (rx_flit_i [0] ),
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.tx_flit_vc_id_o (rx_flit_vc_id_i [0] ),
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.tx_flit_look_ahead_routing_o (rx_flit_look_ahead_routing_i [0] ),
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.tx_lcrd_v_i (rx_lcrd_v_o [0] ),
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.tx_lcrd_id_i (rx_lcrd_id_o [0] ),
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.new_test_vld_i (new_test_vld [0] ),
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.new_test_i (new_test [0] ),
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.new_test_rdy_o (new_test_rdy [0] ),
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.new_scoreboard_entry_vld_o (new_scoreboard_entry_vld [0] ),
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.new_scoreboard_entry_o (new_scoreboard_entry [0] ),
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.new_scoreboard_entry_rdy_i (new_scoreboard_entry_rdy [0] ),
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.node_id_i (sender_node_id [0] ),
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.mcycle_i (mcycle),
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.clk (clk ),
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.rstn (rstn)
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);
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v_sender
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#(
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.FLIT_BUFFER_DEPTH (8 ),
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.flit_payload_t (flit_payload_t ),
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.VC_NUM_OUTPORT (VC_NUM_INPUT_S),
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.VC_DEPTH_OUTPORT (VC_DEPTH_INPUT_S ),
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.SENDER_TIMEOUT_EN (SENDER_TIMEOUT_EN ),
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.SENDER_TIMEOUT_THRESHOLD (SENDER_TIMEOUT_THRESHOLD),
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.OUTPUT_TO_S (1)
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)
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v_sender_toS_u (
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.tx_flit_pend_o (rx_flit_pend_i [1] ),
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.tx_flit_v_o (rx_flit_v_i [1] ),
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.tx_flit_o (rx_flit_i [1] ),
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.tx_flit_vc_id_o (rx_flit_vc_id_i [1] ),
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.tx_flit_look_ahead_routing_o (rx_flit_look_ahead_routing_i [1] ),
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.tx_lcrd_v_i (rx_lcrd_v_o [1] ),
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.tx_lcrd_id_i (rx_lcrd_id_o [1] ),
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.new_test_vld_i (new_test_vld [1] ),
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.new_test_i (new_test [1] ),
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.new_test_rdy_o (new_test_rdy [1] ),
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.new_scoreboard_entry_vld_o (new_scoreboard_entry_vld [1] ),
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.new_scoreboard_entry_o (new_scoreboard_entry [1] ),
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.new_scoreboard_entry_rdy_i (new_scoreboard_entry_rdy [1] ),
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.node_id_i (sender_node_id [1] ),
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.mcycle_i (mcycle),
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.clk (clk ),
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.rstn (rstn)
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);
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v_sender
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#(
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.FLIT_BUFFER_DEPTH (8 ),
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.flit_payload_t (flit_payload_t ),
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.VC_NUM_OUTPORT (VC_NUM_INPUT_E),
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.VC_DEPTH_OUTPORT (VC_DEPTH_INPUT_E ),
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.SENDER_TIMEOUT_EN (SENDER_TIMEOUT_EN ),
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.SENDER_TIMEOUT_THRESHOLD (SENDER_TIMEOUT_THRESHOLD),
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.OUTPUT_TO_E (1)
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)
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v_sender_toE_u (
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.tx_flit_pend_o (rx_flit_pend_i [2] ),
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.tx_flit_v_o (rx_flit_v_i [2] ),
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.tx_flit_o (rx_flit_i [2] ),
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.tx_flit_vc_id_o (rx_flit_vc_id_i [2] ),
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.tx_flit_look_ahead_routing_o (rx_flit_look_ahead_routing_i [2] ),
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.tx_lcrd_v_i (rx_lcrd_v_o [2] ),
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.tx_lcrd_id_i (rx_lcrd_id_o [2] ),
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.new_test_vld_i (new_test_vld [2] ),
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.new_test_i (new_test [2] ),
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.new_test_rdy_o (new_test_rdy [2] ),
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.new_scoreboard_entry_vld_o (new_scoreboard_entry_vld [2] ),
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.new_scoreboard_entry_o (new_scoreboard_entry [2] ),
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.new_scoreboard_entry_rdy_i (new_scoreboard_entry_rdy [2] ),
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.node_id_i (sender_node_id [2] ),
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.mcycle_i (mcycle),
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.clk (clk ),
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.rstn (rstn)
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);
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v_sender
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#(
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.FLIT_BUFFER_DEPTH (8 ),
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.flit_payload_t (flit_payload_t ),
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.VC_NUM_OUTPORT (VC_NUM_INPUT_W),
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.VC_DEPTH_OUTPORT (VC_DEPTH_INPUT_W ),
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.SENDER_TIMEOUT_EN (SENDER_TIMEOUT_EN ),
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.SENDER_TIMEOUT_THRESHOLD (SENDER_TIMEOUT_THRESHOLD),
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.OUTPUT_TO_W (1)
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)
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v_sender_toW_u (
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.tx_flit_pend_o (rx_flit_pend_i [3] ),
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.tx_flit_v_o (rx_flit_v_i [3] ),
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.tx_flit_o (rx_flit_i [3] ),
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.tx_flit_vc_id_o (rx_flit_vc_id_i [3] ),
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.tx_flit_look_ahead_routing_o (rx_flit_look_ahead_routing_i [3] ),
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.tx_lcrd_v_i (rx_lcrd_v_o [3] ),
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.tx_lcrd_id_i (rx_lcrd_id_o [3] ),
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.new_test_vld_i (new_test_vld [3] ),
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.new_test_i (new_test [3] ),
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.new_test_rdy_o (new_test_rdy [3] ),
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.new_scoreboard_entry_vld_o (new_scoreboard_entry_vld [3] ),
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.new_scoreboard_entry_o (new_scoreboard_entry [3] ),
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.new_scoreboard_entry_rdy_i (new_scoreboard_entry_rdy [3] ),
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.node_id_i (sender_node_id [3] ),
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.mcycle_i (mcycle),
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.clk (clk ),
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.rstn (rstn)
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);
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generate
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for(i = 0; i < LOCAL_PORT_NUM; i++) begin
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v_sender
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#(
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.FLIT_BUFFER_DEPTH (8 ),
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.flit_payload_t (flit_payload_t ),
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.VC_NUM_OUTPORT (VC_NUM_INPUT_L),
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.VC_DEPTH_OUTPORT (VC_DEPTH_INPUT_L ),
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.SENDER_TIMEOUT_EN (SENDER_TIMEOUT_EN ),
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.SENDER_TIMEOUT_THRESHOLD (SENDER_TIMEOUT_THRESHOLD),
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.OUTPUT_TO_L (1)
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)
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v_sender_toL_u (
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.tx_flit_pend_o (rx_flit_pend_i [4+i] ),
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.tx_flit_v_o (rx_flit_v_i [4+i] ),
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.tx_flit_o (rx_flit_i [4+i] ),
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.tx_flit_vc_id_o (rx_flit_vc_id_i [4+i] ),
|
|
.tx_flit_look_ahead_routing_o (rx_flit_look_ahead_routing_i [4+i] ),
|
|
|
|
.tx_lcrd_v_i (rx_lcrd_v_o [4+i] ),
|
|
.tx_lcrd_id_i (rx_lcrd_id_o [4+i] ),
|
|
|
|
.new_test_vld_i (new_test_vld [4+i] ),
|
|
.new_test_i (new_test [4+i] ),
|
|
.new_test_rdy_o (new_test_rdy [4+i] ),
|
|
|
|
.new_scoreboard_entry_vld_o (new_scoreboard_entry_vld [4+i] ),
|
|
.new_scoreboard_entry_o (new_scoreboard_entry [4+i] ),
|
|
.new_scoreboard_entry_rdy_i (new_scoreboard_entry_rdy [4+i] ),
|
|
|
|
.node_id_i (sender_node_id [4+i] ),
|
|
|
|
.mcycle_i (mcycle),
|
|
|
|
.clk (clk ),
|
|
.rstn (rstn)
|
|
);
|
|
end
|
|
endgenerate
|
|
|
|
|
|
logic [OUTPUT_PORT_NUM-1:0] check_scoreboard_vld;
|
|
receiver_info_t [OUTPUT_PORT_NUM-1:0] check_scoreboard;
|
|
logic [OUTPUT_PORT_NUM-1:0] check_scoreboard_rdy;
|
|
node_id_t [OUTPUT_PORT_NUM-1:0] receiver_node_id;
|
|
|
|
// receiver0 (1,2)
|
|
// |
|
|
// receiver3 (0,1) - (1,1) - (2,1) receiver2
|
|
// | \
|
|
// receiver1 (1,0) (local) receiver4
|
|
|
|
assign receiver_node_id[0].x_position = 1;
|
|
assign receiver_node_id[0].y_position = 2;
|
|
assign receiver_node_id[0].device_port = '0;
|
|
assign receiver_node_id[0].device_id = '0;
|
|
assign receiver_node_id[1].x_position = 1;
|
|
assign receiver_node_id[1].y_position = 0;
|
|
assign receiver_node_id[1].device_port = '0;
|
|
assign receiver_node_id[1].device_id = '0;
|
|
assign receiver_node_id[2].x_position = 2;
|
|
assign receiver_node_id[2].y_position = 1;
|
|
assign receiver_node_id[2].device_port = '0;
|
|
assign receiver_node_id[2].device_id = '0;
|
|
assign receiver_node_id[3].x_position = 0;
|
|
assign receiver_node_id[3].y_position = 1;
|
|
assign receiver_node_id[3].device_port = '0;
|
|
assign receiver_node_id[3].device_id = '0;
|
|
generate
|
|
if(LOCAL_PORT_NUM > 0) begin: gen_have_local_receiver_node_id
|
|
for(i = 0; i < LOCAL_PORT_NUM; i++) begin: gen_local_receiver_node_id
|
|
assign receiver_node_id[4+i].x_position = 1;
|
|
assign receiver_node_id[4+i].y_position = 1;
|
|
assign receiver_node_id[4+i].device_port = i;
|
|
assign receiver_node_id[4+i].device_id = '0;
|
|
end
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
for(i = 0; i < OUTPUT_PORT_NUM; i++) begin: gen_v_receiver
|
|
v_receiver
|
|
#(
|
|
.flit_payload_t (flit_payload_t )
|
|
)
|
|
v_receiver_u (
|
|
.rx_flit_pend_i (tx_flit_pend_o [i] ),
|
|
.rx_flit_v_i (tx_flit_v_o [i] ),
|
|
.rx_flit_i (tx_flit_o [i] ),
|
|
.rx_flit_vc_id_i (tx_flit_vc_id_o [i] ),
|
|
.rx_flit_look_ahead_routing_i (tx_flit_look_ahead_routing_o [i] ),
|
|
|
|
.rx_lcrd_v_o (tx_lcrd_v_i [i] ),
|
|
.rx_lcrd_id_o (tx_lcrd_id_i [i] ),
|
|
|
|
.check_scoreboard_vld_o (check_scoreboard_vld [i] ),
|
|
.check_scoreboard_o (check_scoreboard [i] ),
|
|
.check_scoreboard_rdy_i (check_scoreboard_rdy [i] ),
|
|
|
|
.node_id_i (receiver_node_id [i] ),
|
|
|
|
.clk (clk ),
|
|
.rstn (rstn)
|
|
);
|
|
end
|
|
endgenerate
|
|
|
|
|
|
v_scoreboard
|
|
#(
|
|
.SCOREBOARD_ENTRY_NUM_PER_SENDER (SCOREBOARD_ENTRY_NUM_PER_SENDER ),
|
|
.SENDER_NUM (INPUT_PORT_NUM ),
|
|
.RECEIVER_NUM (OUTPUT_PORT_NUM ),
|
|
|
|
.NODE_NUM_X_DIMESION (NODE_NUM_X_DIMESION ),
|
|
.NODE_NUM_Y_DIMESION (NODE_NUM_Y_DIMESION ),
|
|
.LOCAL_PORT_NUM (LOCAL_PORT_NUM ),
|
|
|
|
.TEST_CASE_SINGLE_ROUTER (1),
|
|
|
|
.ASSUMED_SYSTEM_FREQUENCY ((1<<30) )
|
|
)
|
|
v_scoreboard_u (
|
|
.new_scoreboard_entry_vld_i (new_scoreboard_entry_vld ),
|
|
.new_scoreboard_entry_i (new_scoreboard_entry ),
|
|
.new_scoreboard_entry_rdy_o (new_scoreboard_entry_rdy ),
|
|
|
|
.check_scoreboard_vld_i (check_scoreboard_vld ),
|
|
.check_scoreboard_i (check_scoreboard ),
|
|
.check_scoreboard_rdy_o (check_scoreboard_rdy ),
|
|
|
|
.mcycle_i (mcycle ),
|
|
|
|
.clk (clk ),
|
|
.rstn (rstn)
|
|
);
|
|
|
|
|
|
|
|
|
|
|
|
//clock generate
|
|
initial begin
|
|
clk = 1'b0;
|
|
forever #5 clk = ~clk;
|
|
end
|
|
|
|
//reset generate
|
|
initial begin
|
|
rstn = 1'b0;
|
|
#30;
|
|
rstn = 1'b1;
|
|
end
|
|
|
|
initial begin
|
|
int dumpon = 1;
|
|
int vcdplus = 0;
|
|
$value$plusargs("dumpon=%d", dumpon);
|
|
$value$plusargs("vcdplus=%d", vcdplus);
|
|
|
|
if (dumpon > 0) begin
|
|
$fsdbDumpvars(0, tb_single_router);
|
|
$fsdbDumpvars("+struct");
|
|
$fsdbDumpvars("+mda");
|
|
$fsdbDumpvars("+all");
|
|
$fsdbDumpon;
|
|
end
|
|
if (vcdplus > 0) begin
|
|
$vcdpluson();
|
|
end
|
|
end
|
|
|
|
endmodule
|