175 lines
5.4 KiB
Systemverilog
175 lines
5.4 KiB
Systemverilog
module testbench
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import rvh_noc_pkg::*;
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#(
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// Parameters
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parameter INPUT_PORT_NUM = 5,
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parameter OUTPUT_PORT_NUM = 5,
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parameter type flit_payload_t = logic[FLIT_LENGTH-1:0],
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parameter VC_NUM_INPUT_N = 2,
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parameter VC_NUM_INPUT_S = 2,
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parameter VC_NUM_INPUT_E = 4,
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parameter VC_NUM_INPUT_W = 4,
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parameter VC_NUM_INPUT_L = 4,
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parameter SA_GLOBAL_INPUT_NUM_N = 4,
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parameter SA_GLOBAL_INPUT_NUM_S = 4,
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parameter SA_GLOBAL_INPUT_NUM_E = 2,
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parameter SA_GLOBAL_INPUT_NUM_W = 2,
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parameter SA_GLOBAL_INPUT_NUM_L = 4,
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parameter VC_NUM_OUTPUT_N = 2,
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parameter VC_NUM_OUTPUT_S = 2,
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parameter VC_NUM_OUTPUT_E = 4,
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parameter VC_NUM_OUTPUT_W = 4,
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parameter VC_NUM_OUTPUT_L = 1,
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parameter VC_DEPTH_INPUT_N = 2,
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parameter VC_DEPTH_INPUT_S = 2,
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parameter VC_DEPTH_INPUT_E = 2,
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parameter VC_DEPTH_INPUT_W = 2,
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parameter VC_DEPTH_INPUT_L = 2
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)
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(
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);
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// Ports
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logic [INPUT_PORT_NUM-1:0] rx_flit_pend_i;
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logic [INPUT_PORT_NUM-1:0] rx_flit_v_i;
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flit_payload_t [INPUT_PORT_NUM-1:0] rx_flit_i;
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io_port_t [INPUT_PORT_NUM-1:0] rx_flit_vc_id_i;
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io_port_t [INPUT_PORT_NUM-1:0] rx_flit_look_ahead_routing_i;
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logic [OUTPUT_PORT_NUM-1:0] tx_flit_pend_o;
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logic [OUTPUT_PORT_NUM-1:0] tx_flit_v_o;
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flit_payload_t [OUTPUT_PORT_NUM-1:0] tx_flit_o;
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io_port_t [OUTPUT_PORT_NUM-1:0] tx_flit_vc_id_o;
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io_port_t [OUTPUT_PORT_NUM-1:0] tx_flit_look_ahead_routing_o;
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logic [INPUT_PORT_NUM-1:0] rx_lcrd_v_o;
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logic [INPUT_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] rx_lcrd_id_o;
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logic [OUTPUT_PORT_NUM-1:0] tx_lcrd_v_i;
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logic [OUTPUT_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] tx_lcrd_id_i;
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logic [NodeID_X_Width-1:0] node_id_x_ths_hop_i;
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logic [NodeID_Y_Width-1:0] node_id_y_ths_hop_i;
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logic clk;
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logic rstn;
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vnet_router
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#(
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.INPUT_PORT_NUM(INPUT_PORT_NUM ),
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.OUTPUT_PORT_NUM(OUTPUT_PORT_NUM ),
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.flit_payload_t(flit_payload_t),
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.VC_NUM_INPUT_N(VC_NUM_INPUT_N ),
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.VC_NUM_INPUT_S(VC_NUM_INPUT_S ),
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.VC_NUM_INPUT_E(VC_NUM_INPUT_E ),
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.VC_NUM_INPUT_W(VC_NUM_INPUT_W ),
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.VC_NUM_INPUT_L(VC_NUM_INPUT_L ),
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.SA_GLOBAL_INPUT_NUM_N(SA_GLOBAL_INPUT_NUM_N ),
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.SA_GLOBAL_INPUT_NUM_S(SA_GLOBAL_INPUT_NUM_S ),
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.SA_GLOBAL_INPUT_NUM_E(SA_GLOBAL_INPUT_NUM_E ),
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.SA_GLOBAL_INPUT_NUM_W(SA_GLOBAL_INPUT_NUM_W ),
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.SA_GLOBAL_INPUT_NUM_L(SA_GLOBAL_INPUT_NUM_L ),
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.VC_NUM_OUTPUT_N(VC_NUM_OUTPUT_N ),
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.VC_NUM_OUTPUT_S(VC_NUM_OUTPUT_S ),
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.VC_NUM_OUTPUT_E(VC_NUM_OUTPUT_E ),
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.VC_NUM_OUTPUT_W(VC_NUM_OUTPUT_W ),
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.VC_NUM_OUTPUT_L(VC_NUM_OUTPUT_L ),
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.VC_DEPTH_INPUT_N(VC_DEPTH_INPUT_N ),
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.VC_DEPTH_INPUT_S(VC_DEPTH_INPUT_S ),
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.VC_DEPTH_INPUT_E(VC_DEPTH_INPUT_E ),
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.VC_DEPTH_INPUT_W(VC_DEPTH_INPUT_W ),
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.VC_DEPTH_INPUT_L(VC_DEPTH_INPUT_L )
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)
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vnet_router_dut (
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.rx_flit_pend_i (rx_flit_pend_i ),
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.rx_flit_v_i (rx_flit_v_i ),
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.rx_flit_i (rx_flit_i ),
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.rx_flit_vc_id_i (rx_flit_vc_id_i ),
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.rx_flit_look_ahead_routing_i (rx_flit_look_ahead_routing_i ),
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.tx_flit_pend_o (tx_flit_pend_o ),
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.tx_flit_v_o (tx_flit_v_o ),
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.tx_flit_o (tx_flit_o ),
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.tx_flit_vc_id_o (tx_flit_vc_id_o ),
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.tx_flit_look_ahead_routing_o (tx_flit_look_ahead_routing_o ),
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.rx_lcrd_v_o (rx_lcrd_v_o ),
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.rx_lcrd_id_o (rx_lcrd_id_o ),
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.tx_lcrd_v_i (tx_lcrd_v_i ),
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.tx_lcrd_id_i (tx_lcrd_id_i ),
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.node_id_x_ths_hop_i (node_id_x_ths_hop_i ),
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.node_id_y_ths_hop_i (node_id_y_ths_hop_i ),
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.clk (clk ),
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.rstn (rstn)
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);
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// test generate
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flit_payload_t counter;
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node_id_t target_node;
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always_ff @(posedge clk or negedge rstn) begin
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if(~rstn) begin
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counter <= '0;
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end else begin
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counter <= counter + 1;
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if(counter == 'd1000) begin
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$finish();
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end
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end
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end
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assign node_id_x_ths_hop_i = 2'b01;
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assign node_id_y_ths_hop_i = 2'b01;
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assign target_node.x_position = 1;
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assign target_node.y_position = 2;
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assign target_node.device_port = 0;
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assign target_node.device_id = 0;
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always_comb begin
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rx_flit_pend_i = '1;
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rx_flit_v_i = '0;
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rx_flit_i = '0;
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rx_flit_vc_id_i = '0;
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rx_flit_look_ahead_routing_i = '0;
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if(counter[5:0] == '1) begin
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rx_flit_v_i [2] = 1'b1;
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rx_flit_i [2] = {{(128-7-4){1'b0}}, target_node, {4'b0}}; // x=1,y=2
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rx_flit_vc_id_i [2][1:0] = counter[7:6] ^ counter[9:8];
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rx_flit_look_ahead_routing_i[2] = N;
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end
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end
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//clock generate
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initial begin
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clk = 1'b0;
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forever #5 clk = ~clk;
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end
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//reset generate
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initial begin
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rstn = 1'b0;
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#30;
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rstn = 1'b1;
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end
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initial begin
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int dumpon = 1;
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int vcdplus = 0;
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$value$plusargs("dumpon=%d", dumpon);
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$value$plusargs("vcdplus=%d", vcdplus);
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if (dumpon > 0) begin
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$fsdbDumpvars(0, testbench);
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$fsdbDumpvars("+struct");
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$fsdbDumpvars("+mda");
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$fsdbDumpvars("+all");
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$fsdbDumpon;
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end
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if (vcdplus > 0) begin
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$vcdpluson();
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end
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end
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endmodule
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