308 lines
16 KiB
Systemverilog
308 lines
16 KiB
Systemverilog
module top_mesh_syn
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import rvh_noc_pkg::*;
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// import v_noc_pkg::*;
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#(
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// mesh parameters
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parameter NODE_NUM_X_DIMESION = 3,
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parameter NODE_NUM_Y_DIMESION = 3,
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// router parameters
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parameter INPUT_PORT_NUM = INPUT_PORT_NUMBER,
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parameter OUTPUT_PORT_NUM = OUTPUT_PORT_NUMBER,
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parameter LOCAL_PORT_NUM = INPUT_PORT_NUM-4,
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parameter type flit_payload_t = logic[FLIT_LENGTH-1:0],
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parameter VC_NUM_INPUT_N = 1+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT,
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parameter VC_NUM_INPUT_S = 1+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT,
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parameter VC_NUM_INPUT_E = 3+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT,
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parameter VC_NUM_INPUT_W = 3+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT,
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`ifdef ALLOW_SAME_ROUTER_L2L_TRANSFER
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parameter VC_NUM_INPUT_L = 4+LOCAL_PORT_NUM-1+QOS_VC_NUM_PER_INPUT,
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`else
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parameter VC_NUM_INPUT_L = 4+QOS_VC_NUM_PER_INPUT,
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`endif
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parameter SA_GLOBAL_INPUT_NUM_N = 3+LOCAL_PORT_NUM,
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parameter SA_GLOBAL_INPUT_NUM_S = 3+LOCAL_PORT_NUM,
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parameter SA_GLOBAL_INPUT_NUM_E = 1+LOCAL_PORT_NUM,
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parameter SA_GLOBAL_INPUT_NUM_W = 1+LOCAL_PORT_NUM,
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`ifdef ALLOW_SAME_ROUTER_L2L_TRANSFER
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parameter SA_GLOBAL_INPUT_NUM_L = 4+LOCAL_PORT_NUM-1,
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`else
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parameter SA_GLOBAL_INPUT_NUM_L = 4,
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`endif
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parameter VC_NUM_OUTPUT_N = 1+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT,
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parameter VC_NUM_OUTPUT_S = 1+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT,
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parameter VC_NUM_OUTPUT_E = 3+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT,
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parameter VC_NUM_OUTPUT_W = 3+LOCAL_PORT_NUM+QOS_VC_NUM_PER_INPUT,
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parameter VC_NUM_OUTPUT_L = 1,
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parameter VC_DEPTH_INPUT_N = VC_DEPTH_MAX,
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parameter VC_DEPTH_INPUT_S = VC_DEPTH_MAX,
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parameter VC_DEPTH_INPUT_E = VC_DEPTH_MAX,
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parameter VC_DEPTH_INPUT_W = VC_DEPTH_MAX,
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parameter VC_DEPTH_INPUT_L = VC_DEPTH_MAX
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)
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(
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output logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][LOCAL_PORT_NUM-1:0] tx_flit_pend_o,
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output logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][LOCAL_PORT_NUM-1:0] tx_flit_v_o,
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output flit_payload_t [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][LOCAL_PORT_NUM-1:0] tx_flit_o,
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output logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][LOCAL_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] tx_flit_vc_id_o,
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output io_port_t [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][LOCAL_PORT_NUM-1:0] tx_flit_look_ahead_routing_o,
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input logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][LOCAL_PORT_NUM-1:0] rx_flit_pend_i,
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input logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][LOCAL_PORT_NUM-1:0] rx_flit_v_i,
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input flit_payload_t [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][LOCAL_PORT_NUM-1:0] rx_flit_i,
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input logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][LOCAL_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] rx_flit_vc_id_i,
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input io_port_t [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][LOCAL_PORT_NUM-1:0] rx_flit_look_ahead_routing_i,
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input logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][LOCAL_PORT_NUM-1:0] tx_lcrd_v_i,
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input logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][LOCAL_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] tx_lcrd_id_i,
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output logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][LOCAL_PORT_NUM-1:0] rx_lcrd_v_o,
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output logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][LOCAL_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] rx_lcrd_id_o,
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input logic clk,
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input logic rst
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);
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genvar i, j, k;
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// Ports
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logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][OUTPUT_PORT_NUM-1:0] tx_flit_pend;
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logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][OUTPUT_PORT_NUM-1:0] tx_flit_v;
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flit_payload_t [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][OUTPUT_PORT_NUM-1:0] tx_flit;
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logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][OUTPUT_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] tx_flit_vc_id;
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io_port_t [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][OUTPUT_PORT_NUM-1:0] tx_flit_look_ahead_routing;
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logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][OUTPUT_PORT_NUM-1:0] rx_flit_pend;
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logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][OUTPUT_PORT_NUM-1:0] rx_flit_v;
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flit_payload_t [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][OUTPUT_PORT_NUM-1:0] rx_flit;
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logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][OUTPUT_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] rx_flit_vc_id;
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io_port_t [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][OUTPUT_PORT_NUM-1:0] rx_flit_look_ahead_routing;
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logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][INPUT_PORT_NUM-1:0] tx_lcrd_v;
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logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][INPUT_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] tx_lcrd_id;
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logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][INPUT_PORT_NUM-1:0] rx_lcrd_v;
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logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][INPUT_PORT_NUM-1:0][VC_ID_NUM_MAX_W-1:0] rx_lcrd_id;
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logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][NodeID_X_Width-1:0] node_id_x;
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logic [NODE_NUM_X_DIMESION-1:0][NODE_NUM_Y_DIMESION-1:0][NodeID_Y_Width-1:0] node_id_y;
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// generate mesh routers
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generate
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for(i = 0; i < NODE_NUM_X_DIMESION; i++) begin: gen_mesh_routers_x_dimesion
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for(j = 0; j < NODE_NUM_Y_DIMESION; j++) begin: gen_mesh_routers_y_dimesion
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vnet_router
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#(
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.INPUT_PORT_NUM(INPUT_PORT_NUM ),
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.OUTPUT_PORT_NUM(OUTPUT_PORT_NUM ),
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.flit_payload_t(flit_payload_t),
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.QOS_VC_NUM_PER_INPUT(QOS_VC_NUM_PER_INPUT),
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.VC_NUM_INPUT_N(VC_NUM_INPUT_N ),
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.VC_NUM_INPUT_S(VC_NUM_INPUT_S ),
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.VC_NUM_INPUT_E(VC_NUM_INPUT_E ),
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.VC_NUM_INPUT_W(VC_NUM_INPUT_W ),
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.VC_NUM_INPUT_L(VC_NUM_INPUT_L ),
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.SA_GLOBAL_INPUT_NUM_N(SA_GLOBAL_INPUT_NUM_N ),
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.SA_GLOBAL_INPUT_NUM_S(SA_GLOBAL_INPUT_NUM_S ),
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.SA_GLOBAL_INPUT_NUM_E(SA_GLOBAL_INPUT_NUM_E ),
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.SA_GLOBAL_INPUT_NUM_W(SA_GLOBAL_INPUT_NUM_W ),
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.SA_GLOBAL_INPUT_NUM_L(SA_GLOBAL_INPUT_NUM_L ),
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.VC_NUM_OUTPUT_N(VC_NUM_OUTPUT_N ),
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.VC_NUM_OUTPUT_S(VC_NUM_OUTPUT_S ),
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.VC_NUM_OUTPUT_E(VC_NUM_OUTPUT_E ),
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.VC_NUM_OUTPUT_W(VC_NUM_OUTPUT_W ),
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.VC_NUM_OUTPUT_L(VC_NUM_OUTPUT_L ),
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.VC_DEPTH_INPUT_N(VC_DEPTH_INPUT_N ),
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.VC_DEPTH_INPUT_S(VC_DEPTH_INPUT_S ),
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.VC_DEPTH_INPUT_E(VC_DEPTH_INPUT_E ),
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.VC_DEPTH_INPUT_W(VC_DEPTH_INPUT_W ),
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.VC_DEPTH_INPUT_L(VC_DEPTH_INPUT_L )
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)
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vnet_router_dut (
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.rx_flit_pend_i (rx_flit_pend [i][j] ),
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.rx_flit_v_i (rx_flit_v [i][j] ),
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.rx_flit_i (rx_flit [i][j] ),
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.rx_flit_vc_id_i (rx_flit_vc_id [i][j] ),
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.rx_flit_look_ahead_routing_i (rx_flit_look_ahead_routing [i][j] ),
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.tx_flit_pend_o (tx_flit_pend [i][j] ),
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.tx_flit_v_o (tx_flit_v [i][j] ),
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.tx_flit_o (tx_flit [i][j] ),
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.tx_flit_vc_id_o (tx_flit_vc_id [i][j] ),
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.tx_flit_look_ahead_routing_o (tx_flit_look_ahead_routing [i][j] ),
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.rx_lcrd_v_o (rx_lcrd_v [i][j] ),
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.rx_lcrd_id_o (rx_lcrd_id [i][j] ),
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.tx_lcrd_v_i (tx_lcrd_v [i][j] ),
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.tx_lcrd_id_i (tx_lcrd_id [i][j] ),
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.node_id_x_ths_hop_i (node_id_x [i][j] ),
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.node_id_y_ths_hop_i (node_id_y [i][j] ),
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.clk (clk ),
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.rstn (rst)
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);
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end
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end
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endgenerate
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// assign node id to each router
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generate
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for(i = 0; i < NODE_NUM_X_DIMESION; i++) begin: gen_node_id_x_x_dimesion
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for(j = 0; j < NODE_NUM_Y_DIMESION; j++) begin: gen_node_id_x_y_dimesion
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assign node_id_x [i][j] = i;
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end
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end
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for(i = 0; i < NODE_NUM_Y_DIMESION; i++) begin: gen_node_id_y_y_dimesion
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for(j = 0; j < NODE_NUM_X_DIMESION; j++) begin: gen_node_id_y_x_dimesion
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assign node_id_y [j][i] = i;
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end
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end
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endgenerate
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// connect each router together
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generate
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for(i = 0; i < NODE_NUM_X_DIMESION; i++) begin: gen_connect_routers_ns_x_dimesion
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for(j = 0; j < NODE_NUM_Y_DIMESION-1; j++) begin: gen_connect_routers_ns_y_dimesion
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// connect N inport to S outport
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assign rx_flit_pend [i][j][0] = tx_flit_pend [i][j+1][1];
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assign rx_flit_v [i][j][0] = tx_flit_v [i][j+1][1];
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assign rx_flit [i][j][0] = tx_flit [i][j+1][1];
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assign rx_flit_vc_id [i][j][0] = tx_flit_vc_id [i][j+1][1];
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assign rx_flit_look_ahead_routing [i][j][0] = tx_flit_look_ahead_routing [i][j+1][1];
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assign tx_lcrd_v [i][j][0] = rx_lcrd_v [i][j+1][1];
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assign tx_lcrd_id [i][j][0] = rx_lcrd_id [i][j+1][1];
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// connect S inport to N outport
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assign rx_flit_pend [i][j+1][1] = tx_flit_pend [i][j][0];
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assign rx_flit_v [i][j+1][1] = tx_flit_v [i][j][0];
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assign rx_flit [i][j+1][1] = tx_flit [i][j][0];
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assign rx_flit_vc_id [i][j+1][1] = tx_flit_vc_id [i][j][0];
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assign rx_flit_look_ahead_routing [i][j+1][1] = tx_flit_look_ahead_routing [i][j][0];
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assign tx_lcrd_v [i][j+1][1] = rx_lcrd_v [i][j][0];
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assign tx_lcrd_id [i][j+1][1] = rx_lcrd_id [i][j][0];
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end
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end
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endgenerate
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generate
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for(i = 0; i < NODE_NUM_Y_DIMESION; i++) begin: gen_connect_routers_ew_x_dimesion
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for(j = 0; j < NODE_NUM_X_DIMESION-1; j++) begin: gen_connect_routers_ew_y_dimesion
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// connect E inport to W outport
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assign rx_flit_pend [j][i][2] = tx_flit_pend [j+1][i][3];
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assign rx_flit_v [j][i][2] = tx_flit_v [j+1][i][3];
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assign rx_flit [j][i][2] = tx_flit [j+1][i][3];
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assign rx_flit_vc_id [j][i][2] = tx_flit_vc_id [j+1][i][3];
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assign rx_flit_look_ahead_routing [j][i][2] = tx_flit_look_ahead_routing [j+1][i][3];
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assign tx_lcrd_v [j][i][2] = rx_lcrd_v [j+1][i][3];
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assign tx_lcrd_id [j][i][2] = rx_lcrd_id [j+1][i][3];
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// connect W inport to E outport
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assign rx_flit_pend [j+1][i][3] = tx_flit_pend [j][i][2];
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assign rx_flit_v [j+1][i][3] = tx_flit_v [j][i][2];
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assign rx_flit [j+1][i][3] = tx_flit [j][i][2];
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assign rx_flit_vc_id [j+1][i][3] = tx_flit_vc_id [j][i][2];
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assign rx_flit_look_ahead_routing [j+1][i][3] = tx_flit_look_ahead_routing [j][i][2];
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assign tx_lcrd_v [j+1][i][3] = rx_lcrd_v [j][i][2];
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assign tx_lcrd_id [j+1][i][3] = rx_lcrd_id [j][i][2];
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end
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end
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endgenerate
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// other unused non-local ports, assign router rx to 0
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generate
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for(i = 0; i < NODE_NUM_X_DIMESION; i++) begin: gen_unused_non_local_ports_x_dimesion
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assign rx_flit_pend [i][NODE_NUM_Y_DIMESION-1][0] = '0;
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assign rx_flit_v [i][NODE_NUM_Y_DIMESION-1][0] = '0;
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assign rx_flit [i][NODE_NUM_Y_DIMESION-1][0] = '0;
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assign rx_flit_vc_id [i][NODE_NUM_Y_DIMESION-1][0] = '0;
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assign rx_flit_look_ahead_routing [i][NODE_NUM_Y_DIMESION-1][0] = '0;
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assign tx_lcrd_v [i][NODE_NUM_Y_DIMESION-1][0] = '0;
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assign tx_lcrd_id [i][NODE_NUM_Y_DIMESION-1][0] = '0;
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assign rx_flit_pend [i][0][1] = '0;
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assign rx_flit_v [i][0][1] = '0;
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assign rx_flit [i][0][1] = '0;
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assign rx_flit_vc_id [i][0][1] = '0;
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assign rx_flit_look_ahead_routing [i][0][1] = '0;
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assign tx_lcrd_v [i][0][1] = '0;
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assign tx_lcrd_id [i][0][1] = '0;
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end
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for(i = 0; i < NODE_NUM_Y_DIMESION; i++) begin: gen_unused_non_local_ports_y_dimesion
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// connect E inport to W outport
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assign rx_flit_pend [NODE_NUM_X_DIMESION-1][i][2] = '0;
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assign rx_flit_v [NODE_NUM_X_DIMESION-1][i][2] = '0;
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assign rx_flit [NODE_NUM_X_DIMESION-1][i][2] = '0;
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assign rx_flit_vc_id [NODE_NUM_X_DIMESION-1][i][2] = '0;
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assign rx_flit_look_ahead_routing [NODE_NUM_X_DIMESION-1][i][2] = '0;
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assign tx_lcrd_v [NODE_NUM_X_DIMESION-1][i][2] = '0;
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assign tx_lcrd_id [NODE_NUM_X_DIMESION-1][i][2] = '0;
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// connect W inport to E outport
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assign rx_flit_pend [0][i][3] = '0;
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assign rx_flit_v [0][i][3] = '0;
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assign rx_flit [0][i][3] = '0;
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assign rx_flit_vc_id [0][i][3] = '0;
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assign rx_flit_look_ahead_routing [0][i][3] = '0;
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assign tx_lcrd_v [0][i][3] = '0;
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assign tx_lcrd_id [0][i][3] = '0;
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end
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endgenerate
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generate
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for(i = 0; i < NODE_NUM_X_DIMESION; i++) begin: gen_v_sender_x_dimesion
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for(j = 0; j < NODE_NUM_Y_DIMESION; j++) begin: gen_v_sender_y_dimesion
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for(k = 0; k < LOCAL_PORT_NUM; k++) begin: gen_v_sender_device_port
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assign rx_flit_pend [i][j][4+k] = rx_flit_pend_i [i][j][k];
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assign rx_flit_v [i][j][4+k] = rx_flit_v_i [i][j][k];
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assign rx_flit [i][j][4+k] = rx_flit_i [i][j][k];
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assign rx_flit_vc_id [i][j][4+k] = rx_flit_vc_id_i [i][j][k];
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assign rx_flit_look_ahead_routing [i][j][4+k] = rx_flit_look_ahead_routing_i [i][j][k];
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assign rx_lcrd_v_o [i][j][k] = rx_lcrd_v [i][j][4+k];
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assign rx_lcrd_id_o [i][j][k] = rx_lcrd_id [i][j][4+k];
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end
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end
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end
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endgenerate
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generate
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for(i = 0; i < NODE_NUM_X_DIMESION; i++) begin: gen_v_receiver_x_dimesion
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for(j = 0; j < NODE_NUM_Y_DIMESION; j++) begin: gen_v_receiver_y_dimesion
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for(k = 0; k < LOCAL_PORT_NUM; k++) begin: gen_v_sender_device_port
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assign tx_flit_pend_o [i][j][k] = tx_flit_pend [i][j][4+k];
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assign tx_flit_v_o [i][j][k] = tx_flit_v [i][j][4+k];
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assign tx_flit_o [i][j][k] = tx_flit [i][j][4+k];
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assign tx_flit_vc_id_o [i][j][k] = tx_flit_vc_id [i][j][4+k];
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assign tx_flit_look_ahead_routing_o [i][j][k] = tx_flit_look_ahead_routing [i][j][4+k];
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assign tx_lcrd_v [i][j][4+k] = tx_lcrd_v_i [i][j][k];
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assign tx_lcrd_id [i][j][4+k] = tx_lcrd_id_i [i][j][k];
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end
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end
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end
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endgenerate
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endmodule
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