61 lines
2.1 KiB
Systemverilog
61 lines
2.1 KiB
Systemverilog
module hn_router_sam
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import rvh_noc_pkg::*;
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#(
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parameter type flit_payload_t = logic[256-1:0],
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parameter int sliced_llc = 0
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// parameter VC_NUM_IDX_W = 1
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)
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(
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input logic flit_v_i,
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input flit_payload_t flit_i,
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input io_port_t flit_look_ahead_routing_i,
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input logic [NodeID_X_Width-1:0] node_id_x_i,
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input logic [NodeID_Y_Width-1:0] node_id_y_i,
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output flit_dec_t flit_dec_o,
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output flit_payload_t flit_o
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);
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`ifdef USE_QOS_VALUE
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assign flit_dec_o.qos_value = flit_i.qos_value;
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`endif
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always_comb begin
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flit_o = flit_i;
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if(sliced_llc) begin
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flit_o.tgt_id.x_position = flit_i.id.cid % NODE_NUM_X_DIMESION;
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flit_o.tgt_id.y_position = flit_i.id.cid / NODE_NUM_Y_DIMESION;
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end else begin // when the hn is at (1,0)
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flit_o.tgt_id.x_position = flit_i.id.cid ? (flit_i.id.cid + 1) % NODE_NUM_X_DIMESION : '0;
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flit_o.tgt_id.y_position = flit_i.id.cid ? (flit_i.id.cid + 1) / NODE_NUM_Y_DIMESION : '0;
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end
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flit_o.tgt_id.device_port = 0;
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flit_o.tgt_id.device_id = 0;
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flit_o.src_id.x_position = node_id_x_i;
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flit_o.src_id.y_position = node_id_y_i;
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flit_o.src_id.device_port = 0;
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flit_o.src_id.device_id = 0;
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flit_o.id.sid = node_id_y_i * NODE_NUM_Y_DIMESION + node_id_x_i;
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end
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generate
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if(sliced_llc) begin: gen_sliced_llc
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assign flit_dec_o.tgt_id.x_position = flit_i.id.cid % NODE_NUM_X_DIMESION;
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assign flit_dec_o.tgt_id.y_position = flit_i.id.cid / NODE_NUM_Y_DIMESION;
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end else begin: gen_whole_llc // when the hn is at (1,0)
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assign flit_dec_o.tgt_id.x_position = flit_i.id.cid ? (flit_i.id.cid + 1) % NODE_NUM_X_DIMESION : '0;
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assign flit_dec_o.tgt_id.y_position = flit_i.id.cid ? (flit_i.id.cid + 1) / NODE_NUM_Y_DIMESION : '0;
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end
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endgenerate
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assign flit_dec_o.tgt_id.device_port = 0;
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assign flit_dec_o.tgt_id.device_id = 0;
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assign flit_dec_o.src_id.x_position = node_id_x_i;
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assign flit_dec_o.src_id.y_position = node_id_y_i;
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assign flit_dec_o.src_id.device_port = 0;
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assign flit_dec_o.src_id.device_id = 0;
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assign flit_dec_o.look_ahead_routing = flit_look_ahead_routing_i;
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endmodule |