24 lines
816 B
Systemverilog
24 lines
816 B
Systemverilog
module input_port_flit_decoder
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import rvh_noc_pkg::*;
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#(
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parameter type flit_payload_t = logic[256-1:0]
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// parameter VC_NUM_IDX_W = 1
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)
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(
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input logic flit_v_i,
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input flit_payload_t flit_i,
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input io_port_t flit_look_ahead_routing_i,
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output flit_dec_t flit_dec_o
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);
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`ifdef USE_QOS_VALUE
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assign flit_dec_o.qos_value = flit_i[QoS_Value_Width-1:0];
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`endif
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assign flit_dec_o.tgt_id = flit_i[QoS_Value_Width+NodeID_Width-1:QoS_Value_Width];
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assign flit_dec_o.src_id = flit_i[QoS_Value_Width+NodeID_Width+NodeID_Width-1:QoS_Value_Width+NodeID_Width];
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assign flit_dec_o.txn_id = flit_i[QoS_Value_Width+NodeID_Width+NodeID_Width+TxnID_Width-1:QoS_Value_Width+NodeID_Width+NodeID_Width];
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assign flit_dec_o.look_ahead_routing = flit_look_ahead_routing_i;
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endmodule |