60 lines
1.2 KiB
Verilog
60 lines
1.2 KiB
Verilog
module CountOne_tb;
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// Parameters
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localparam int unsigned InputWidth = 8;
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localparam int unsigned CountWidth = $clog2(InputWidth + 1);
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// Ports
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reg [InputWidth-1:0] bits_i;
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wire [CountWidth-1:0] cnt_o;
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CountOne #(
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.InputWidth(InputWidth)
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) u_CountOne (
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.bits_i(bits_i),
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.cnt_o (cnt_o)
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);
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function automatic [CountWidth-1:0] GlodenModel;
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input bit [InputWidth-1:0] in;
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bit [CountWidth-1:0] sum;
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begin
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sum = 0;
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for (int i = 0; i < InputWidth; i++) begin
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sum = sum + in[i];
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end
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GlodenModel = sum;
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end
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endfunction
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`ifdef DUMPON
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initial begin : GEN_WAVEFORM
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$fsdbDumpfile("CountOne_tb.fsdb");
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$fsdbDumpvars(0, CountOne_tb);
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$fsdbDumpvars("+mda");
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$fsdbDumpvars("+all");
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$fsdbDumpon();
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end
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`endif
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initial begin : RANDOM_TEST
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begin
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repeat (10000) begin : GEN_CASE
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bits_i = $urandom_range(0, InputWidth - 1);
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#100;
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NOT_EQUAL :
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assert (cnt_o == GlodenModel(bits_i))
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else begin
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$error("Input[%b], Output[%d], Gloden[%d]\n", bits_i, cnt_o, GlodenModel(bits_i));
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break;
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end
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end
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#100;
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$fatal("PASS\n");
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$finish;
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end
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end
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endmodule
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