84 lines
1.9 KiB
Verilog
84 lines
1.9 KiB
Verilog
module StreamFIFO_tb;
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// Parameters
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localparam int unsigned Depth = 8;
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localparam int unsigned WordWidth = 64;
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// Ports
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reg enq_vld_i = 0;
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reg [WordWidth-1:0] enq_payload_i;
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wire enq_rdy_o;
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wire deq_vld_o;
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wire [WordWidth-1:0] deq_payload_o;
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reg deq_rdy_i = 0;
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reg flush_i = 0;
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reg clk = 0;
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reg rstn = 0;
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bit [WordWidth-1:0] golden_fifo[$];
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bit [WordWidth-1:0] random_payload;
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bit [WordWidth-1:0] golden_fifo_front;
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int iter = 1000000;
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initial begin
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begin
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#10 rstn = 1'b1;
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repeat (iter) begin : random_test
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@(negedge clk);
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enq_vld_i = 1'b0;
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deq_rdy_i = 1'b0;
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if ($urandom_range(0, 1) && deq_vld_o) begin : test_deq
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deq_rdy_i = 1'b1;
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golden_fifo_front = golden_fifo.pop_front();
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CHECK_EQUALATION :
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assert (deq_payload_o == golden_fifo_front)
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else begin
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$fatal("\n Error: Fail when check equalation, ours[%x] -- gloden[%x]", deq_payload_o,
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golden_fifo_front);
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end
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;
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end
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if ($urandom_range(0, 1) && enq_rdy_o) begin : test_push
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random_payload = $urandom();
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enq_vld_i = 1'b1;
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enq_payload_i = random_payload;
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golden_fifo.push_back(random_payload);
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end
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end
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$info("\n PASS after %d iter \n", iter);
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$finish;
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end
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end
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StreamFIFO #(
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.Depth(Depth),
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.WordWidth(WordWidth)
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) StreamFIFO_dut (
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.enq_vld_i(enq_vld_i),
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.enq_payload_i(enq_payload_i),
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.enq_rdy_o(enq_rdy_o),
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.deq_vld_o(deq_vld_o),
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.deq_payload_o(deq_payload_o),
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.deq_rdy_i(deq_rdy_i),
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.flush_i(flush_i),
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.clk(clk),
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.rstn(rstn)
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);
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`ifdef DUMPON
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initial begin : GEN_WAVEFORM
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$fsdbDumpfile("StreamFIFO_tb.fsdb");
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$fsdbDumpvars(0, StreamFIFO_tb);
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$fsdbDumpvars("+mda");
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$fsdbDumpvars("+all");
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$fsdbDumpon();
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end
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`endif
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always #20 clk = !clk;
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endmodule
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