34 lines
1.1 KiB
Makefile
34 lines
1.1 KiB
Makefile
## prefered path: proj_root/syn/dc/
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export TIMESTAMP=$(shell date +%Y%m%d%H%M%S)
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export DESIGN_NAME=rvh_noc
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# T12/GF22
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export SYN_PDK=T12
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# SINGLE_ROUTER/MESH
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export SYN_TOP=SINGLE_ROUTER
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all:
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export TIMESTAMP=$(shell date +%Y%m%d%H%M%S)
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export DESIGN_NAME=rvh_noc
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export SYN_PDK=T12
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export SYN_TOP=SINGLE_ROUTER
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mkdir ./$(TIMESTAMP)_$(SYN_PDK)_$(SYN_TOP)_run && cd ./$(TIMESTAMP)_$(SYN_PDK)_$(SYN_TOP)_run && mkdir rpt && mkdir output
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/opt/cad/synopsys/installs/syn/Q-2019.12-SP5-1/bin/dc_shell-t -checkout DesignWare -f tcl_scripts/synth.tcl | tee $(TIMESTAMP)_$(SYN_PDK)_$(SYN_TOP)_run/$(SYN_PDK)_$(SYN_TOP).log
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PHONY:
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clean:
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rm -rf *_run
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rm *.log
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# -topographical_mode means using physical constraints on your design, this will allow you to
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# accurately predict post-layout timing, area, and power during synthesis without the need for
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# timing approximations based on wire load models. It uses placement and optimization
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# technologies to drive accurate timing prediction within synthesis and automatically performs
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# leakage power optimization, ensuring better correlation with the final physical design.
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