61 lines
1.1 KiB
Systemverilog
Executable File
61 lines
1.1 KiB
Systemverilog
Executable File
`ifndef __PSEUDO_RAM_SV__
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`define __PSEUDO_RAM_SV__
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module pseudo_ram
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#(
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parameter int unsigned WIDTH = 8,
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parameter int unsigned DEPTH = 8
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)
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(
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input logic we,
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input logic [$clog2(DEPTH)-1:0] a,
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input logic [WIDTH-1:0] d,
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output logic [WIDTH-1:0] q,
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input logic rst,
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input logic clk
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);
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logic [DEPTH-1:0][WIDTH-1:0] ram;
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logic [$clog2(DEPTH)-1:0] a_ff;
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logic we_ff;
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logic [WIDTH-1:0] d_ff;
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//sync
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always_ff@(posedge clk) begin
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if (rst) begin
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a_ff <= 0;
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d_ff <= 0;
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we_ff <= 0;
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end
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else begin
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a_ff <= a;
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d_ff <= d;
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we_ff <= we;
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end
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end
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// read
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always_comb begin
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q = 0;
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if (!we_ff) begin
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q = ram[a_ff];
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end
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end
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// write
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always_ff@(posedge clk) begin
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if (rst) begin
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for (int i=0; i<DEPTH; i++) begin
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ram[i] <= 0;
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end
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end
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else if (we_ff) begin
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ram[a_ff] <= d_ff;
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end
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end
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endmodule
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`endif |