diff --git a/tests/eth_mac/test_eth_mac.py b/tests/eth_mac/test_eth_mac.py
index 40fd5be..63b09dc 100644
--- a/tests/eth_mac/test_eth_mac.py
+++ b/tests/eth_mac/test_eth_mac.py
@@ -81,12 +81,12 @@ class TB:
         self.dut.rx_rst.setimmediatevalue(0)
         await RisingEdge(self.dut.tx_clk)
         await RisingEdge(self.dut.tx_clk)
-        self.dut.tx_rst <= 1
-        self.dut.rx_rst <= 1
+        self.dut.tx_rst.value = 1
+        self.dut.rx_rst.value = 1
         await RisingEdge(self.dut.tx_clk)
         await RisingEdge(self.dut.tx_clk)
-        self.dut.tx_rst <= 0
-        self.dut.rx_rst <= 0
+        self.dut.tx_rst.value = 0
+        self.dut.rx_rst.value = 0
         await RisingEdge(self.dut.tx_clk)
         await RisingEdge(self.dut.tx_clk)
 
diff --git a/tests/gmii/test_gmii.py b/tests/gmii/test_gmii.py
index 219e5a5..df7abfe 100644
--- a/tests/gmii/test_gmii.py
+++ b/tests/gmii/test_gmii.py
@@ -61,10 +61,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
 
@@ -85,7 +85,7 @@ class TB:
         clock_edge_event = RisingEdge(self.dut.clk)
 
         for val in self._enable_generator:
-            self.dut.gmii_clk_en <= val
+            self.dut.gmii_clk_en.value = val
             await clock_edge_event
 
 
@@ -94,7 +94,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_
     tb = TB(dut)
 
     tb.source.ifg = ifg
-    tb.dut.gmii_mii_sel <= mii_sel
+    tb.dut.gmii_mii_sel.value = mii_sel
 
     if enable_gen is not None:
         tb.set_enable_generator(enable_gen())
diff --git a/tests/gmii_phy/test_gmii_phy.py b/tests/gmii_phy/test_gmii_phy.py
index 04f5ad7..f622d43 100644
--- a/tests/gmii_phy/test_gmii_phy.py
+++ b/tests/gmii_phy/test_gmii_phy.py
@@ -64,10 +64,10 @@ class TB:
         self.dut.phy_rst.setimmediatevalue(0)
         await RisingEdge(self.dut.phy_tx_clk)
         await RisingEdge(self.dut.phy_tx_clk)
-        self.dut.phy_rst <= 1
+        self.dut.phy_rst.value = 1
         await RisingEdge(self.dut.phy_tx_clk)
         await RisingEdge(self.dut.phy_tx_clk)
-        self.dut.phy_rst <= 0
+        self.dut.phy_rst.value = 0
         await RisingEdge(self.dut.phy_tx_clk)
         await RisingEdge(self.dut.phy_tx_clk)
 
diff --git a/tests/mii/test_mii.py b/tests/mii/test_mii.py
index ba177f9..ddb77ae 100644
--- a/tests/mii/test_mii.py
+++ b/tests/mii/test_mii.py
@@ -60,10 +60,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
 
@@ -84,7 +84,7 @@ class TB:
         clock_edge_event = RisingEdge(self.dut.clk)
 
         for val in self._enable_generator:
-            self.dut.mii_clk_en <= val
+            self.dut.mii_clk_en.value = val
             await clock_edge_event
 
 
diff --git a/tests/mii_phy/test_mii_phy.py b/tests/mii_phy/test_mii_phy.py
index 17500cd..b363833 100644
--- a/tests/mii_phy/test_mii_phy.py
+++ b/tests/mii_phy/test_mii_phy.py
@@ -55,10 +55,10 @@ class TB:
         self.dut.phy_rst.setimmediatevalue(0)
         await RisingEdge(self.dut.phy_tx_clk)
         await RisingEdge(self.dut.phy_tx_clk)
-        self.dut.phy_rst <= 1
+        self.dut.phy_rst.value = 1
         await RisingEdge(self.dut.phy_tx_clk)
         await RisingEdge(self.dut.phy_tx_clk)
-        self.dut.phy_rst <= 0
+        self.dut.phy_rst.value = 0
         await RisingEdge(self.dut.phy_tx_clk)
         await RisingEdge(self.dut.phy_tx_clk)
 
diff --git a/tests/ptp_clock/test_ptp_clock.py b/tests/ptp_clock/test_ptp_clock.py
index ca468e5..7ced8ba 100644
--- a/tests/ptp_clock/test_ptp_clock.py
+++ b/tests/ptp_clock/test_ptp_clock.py
@@ -59,10 +59,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
 
diff --git a/tests/rgmii/test_rgmii.py b/tests/rgmii/test_rgmii.py
index 1705904..9ece403 100644
--- a/tests/rgmii/test_rgmii.py
+++ b/tests/rgmii/test_rgmii.py
@@ -59,10 +59,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
 
@@ -83,7 +83,7 @@ class TB:
         clock_edge_event = RisingEdge(self.dut.clk)
 
         for val in self._enable_generator:
-            self.dut.rgmii_clk_en <= val
+            self.dut.rgmii_clk_en.value = val
             await clock_edge_event
 
 
@@ -92,7 +92,7 @@ async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12, enable_
     tb = TB(dut)
 
     tb.source.ifg = ifg
-    tb.dut.rgmii_mii_sel <= mii_sel
+    tb.dut.rgmii_mii_sel.value = mii_sel
 
     if enable_gen is not None:
         tb.set_enable_generator(enable_gen())
diff --git a/tests/rgmii_phy/test_rgmii_phy.py b/tests/rgmii_phy/test_rgmii_phy.py
index bc281f7..62b2d3a 100644
--- a/tests/rgmii_phy/test_rgmii_phy.py
+++ b/tests/rgmii_phy/test_rgmii_phy.py
@@ -68,10 +68,10 @@ class TB:
         self.dut.phy_rst.setimmediatevalue(0)
         await RisingEdge(self.dut.phy_tx_clk)
         await RisingEdge(self.dut.phy_tx_clk)
-        self.dut.phy_rst <= 1
+        self.dut.phy_rst.value = 1
         await RisingEdge(self.dut.phy_tx_clk)
         await RisingEdge(self.dut.phy_tx_clk)
-        self.dut.phy_rst <= 0
+        self.dut.phy_rst.value = 0
         await RisingEdge(self.dut.phy_tx_clk)
         await RisingEdge(self.dut.phy_tx_clk)
 
diff --git a/tests/xgmii/test_xgmii.py b/tests/xgmii/test_xgmii.py
index 5cfb625..5b3eeb6 100644
--- a/tests/xgmii/test_xgmii.py
+++ b/tests/xgmii/test_xgmii.py
@@ -59,10 +59,10 @@ class TB:
         self.dut.rst.setimmediatevalue(0)
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 1
+        self.dut.rst.value = 1
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
-        self.dut.rst <= 0
+        self.dut.rst.value = 0
         await RisingEdge(self.dut.clk)
         await RisingEdge(self.dut.clk)
 
@@ -83,7 +83,7 @@ class TB:
         clock_edge_event = RisingEdge(self.dut.clk)
 
         for val in self._enable_generator:
-            self.dut.xgmii_clk_en <= val
+            self.dut.xgmii_clk_en.value = val
             await clock_edge_event